JP6121831B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board used for mounting a semiconductor element.

  2. Description of the Related Art Conventionally, there is known a wiring board on which a semiconductor element having electrode terminals arranged peripherally on the outer periphery of a lower surface is mounted by flip chip connection. The main part in such a wiring board is shown in FIG. As shown in FIG. 5, the conventional wiring board has a plurality of strip-like wiring conductors 26 for connecting semiconductor elements and a solder resist layer 23 on an insulating substrate 21. The strip-shaped wiring conductors 26 each have a thickness of about 10 to 20 μm and a width of about 10 to 20 μm, and are arranged in parallel at an interval of about 10 to 20 μm. The solder resist layer 23 has openings 29 for individually exposing a part of each strip-shaped wiring conductor 26 as semiconductor element connection pad portions 27 in a staggered arrangement with respect to the adjacent strip-shaped wiring conductors 26. . A part of each strip-shaped wiring conductor 26 has a parallel portion 28 parallel to the semiconductor element connection pad portion 27 of the strip-shaped wiring conductor 26 adjacent to each other in a state of being covered with the solder resist layer 23. Then, the electrode terminal T of the semiconductor element S is brought into contact with the semiconductor element connection pad 27, and the two are joined via a conductive bonding material such as solder, for example, so that the electrode terminal T of the semiconductor element S and the strip-shaped wiring conductor are joined. 26 is electrically connected.

  Here, a method of forming the solder resist layer 23 in such a wiring board will be described. First, as shown in FIG. 6A, a strip-shaped wiring conductor 26 is formed on the upper surface of the insulating substrate 21. Next, as shown in FIG. 6B, a photosensitive resin layer 23 </ b> P for the solder resist layer 23 is formed on the insulating substrate 21 and the strip-shaped wiring conductor 26. Next, as shown in FIG. 6C, an exposure mask M having a light-shielding pattern at a portion corresponding to the opening 29 is disposed on the photosensitive resin layer 23P, and exposure is performed by irradiating ultraviolet rays as exposure light from above. To do. Finally, as shown in FIG. 6D, the solder resist layer 23 is formed by removing the unexposed portion by development and thermally curing the remaining photosensitive resin layer 23P.

  However, in the conventional wiring board, the parallel part 28 of the strip-shaped wiring conductor 26 exists between the openings 29 arranged side by side. Therefore, when the interval between the opening 29 and the parallel portion 28 adjacent thereto becomes narrow, as shown in FIG. 7A, when exposing the photosensitive resin layer 23P, a part of the exposure light of the parallel portion 28 is obtained. The light is reflected from the side surface and enters the opening 29 and is exposed to light. As a result, as shown in FIG. 6B, the opening 29 cannot be formed in an accurate shape, and the electrode terminal T of the semiconductor element S and the semiconductor element connection pad portion 27 can be satisfactorily connected. It had the problem of becoming difficult.

JP-A-8-139438

  An object of the present invention is that a part of a plurality of strip-like wiring conductors arranged in parallel can be satisfactorily exposed individually as a semiconductor element connection pad portion in an opening of a solder resist layer, whereby an electrode terminal of a semiconductor element and a semiconductor An object of the present invention is to provide a wiring board capable of satisfactorily connecting an element connection pad portion.

In the wiring board of the present invention, a plurality of strip-shaped wiring conductors for connecting semiconductor elements are arranged in parallel on an insulating substrate, and a part of each of the strip-shaped wiring conductors is disposed on the insulating substrate and the strip-shaped wiring conductor. A wiring board formed by depositing a solder resist layer having openings which are individually exposed as semiconductor element connection pad portions in a staggered arrangement with respect to the adjacent band-shaped wiring conductors, At least a part has a parallel part parallel to the semiconductor element connection pad part of the strip-shaped wiring conductor adjacent to each other adjacent to the opening in a state covered with the solder resist layer, and is adjacent to the parallel part. wherein and the thickness of the solder resist layer to an opening is the width of the parallel portion is narrowed so that the above 10 [mu] m, and the direction of crossing the strip line conductors of said opening Surface shape is characterized in that it is a drum-shaped side wall is less swollen 3μm inside of the opening.

According to the wiring board of the present invention, each strip-shaped wiring conductor has a solder resist layer thickness of 10 μm or more from the side surface of the parallel portion parallel to the semiconductor element connection pad portion in the adjacent strip-shaped wiring conductor to the adjacent opening. Since the width of the parallel portion is narrowed so that the cross-sectional shape of the opening crossing the strip-shaped wiring conductor is a drum shape in which the side wall bulges 3 μm or less inside the opening , When exposing the photosensitive resin layer for solder resist, exposure light is reflected on the side surface of the parallel part and enters the part that becomes the opening part. Since the distance is increased, the influence of reflection can be reduced, thereby making it possible to form an accurately shaped opening. Therefore, it is possible to provide a wiring substrate capable of satisfactorily connecting the electrode terminal of the semiconductor element and the semiconductor element connection pad portion.

Fig.1 (a) is a schematic sectional drawing which shows an example of embodiment in the wiring board of this invention, FIG.1 (b) is the schematic top view. 2A is an enlarged top view of the main part of the wiring board shown in FIG. 1, and FIG. 2B is an enlarged sectional view of the main part of the wiring board shown in FIG. FIGS. 3A to 3D are enlarged schematic perspective views of main parts for each process for explaining the method of manufacturing the wiring board shown in FIG. FIG. 4 is an enlarged schematic cross-sectional view of a main part for explaining a method of manufacturing the wiring board shown in FIG. FIG. 5 is an enlarged perspective view of a main part of a conventional wiring board. 6 (a) to 6 (d) are enlarged schematic perspective views of main parts by process for explaining a conventional method of manufacturing a wiring board. FIG. 7 is an enlarged cross-sectional view of a main part for explaining a conventional method for manufacturing a wiring board.

  Next, the wiring board of the present invention will be described with reference to FIGS. 1A and 1B show an example of an embodiment of a wiring board 100 of the present invention. The wiring substrate 100 of this example is mainly composed of an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3. A central portion of the upper surface of the wiring substrate 100 is a mounting portion A on which the semiconductor element S is mounted. In FIG. 1B, a portion of the wiring conductor 2 on the upper surface of the insulating substrate 1 that is covered with the solder resist layer 3 is indicated by a broken line.

  The insulating substrate 1 is formed by stacking build-up insulating layers 1b on and under a core insulating layer 1a. The core insulating layer 1a is made of, for example, an electrically insulating material having a thickness of about 30 to 200 μm obtained by impregnating a glass cloth base material with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. A plurality of through holes 4 having a diameter of about 50 to 250 μm are formed in the insulating layer 1a from the upper surface to the lower surface. A part of the wiring conductor 2 is attached to the upper and lower surfaces of the insulating layer 1 a and the inner wall of the through hole 4. On the other hand, the build-up insulating layer 1b is made of an electrically insulating material having a thickness of about 10 to 50 μm in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. A plurality of via holes 5 having a diameter of about 30 to 100 μm are formed in the insulating layer 1b from the upper surface to the lower surface. A part of the wiring conductor 2 is deposited on the surface of the insulating layer 1 b and the inside of the via hole 5.

  The wiring conductor 2 is made of a highly conductive material such as a copper foil or a copper plating layer, and is led out from the upper surface of the insulating substrate 1 to the lower surface of the insulating substrate 1 through the via hole 5 and the through hole 4. The thickness of the wiring conductor 2 is about 10 to 20 μm. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a are composed of a copper foil and a copper plating layer thereon, and are formed in a predetermined pattern by a well-known subtractive method. The wiring conductor 2 in the through hole 4 is made of a copper plating layer, and is attached to the entire inner wall of the through hole 4. The inside of the through hole 4 to which the wiring conductor 2 is attached is filled with a thermosetting resin. The surface of the insulating layer 1b and the wiring conductor 2 in the via hole 4 are made of a copper plating layer, and are formed in a predetermined pattern by a known semi-additive method.

  A part of the wiring conductor 2 deposited on the upper surface of the insulating substrate 1 forms a number of strip-shaped wiring conductors 6 for connection to the semiconductor element S. The strip-shaped wiring conductors 6 are juxtaposed so as to extend from the central portion side of the mounting portion A to the outer side of the mounting portion A so as to cross each outer periphery of the mounting portion A in a perpendicular direction. The strip-shaped wiring conductors 6 each have a thickness of about 10 to 20 μm and a width of about 10 to 20 μm, and are arranged in parallel so as to be close to each other at a portion crossing the outer peripheral portion of the mounting portion A.

  The solder resist layer 3 is made of an electrically insulating material in which an inorganic insulating filler such as silicon oxide is dispersed in a photosensitive thermosetting resin such as an acrylic-modified epoxy resin, and is attached to the upper and lower surfaces of the insulating substrate 1. .

  The solder resist layer 3 deposited on the upper surface side of the insulating substrate 1 has an opening 9 that individually exposes a part of each strip-like wiring conductor 6 as a semiconductor element connection pad portion 7 in the strip-like wiring conductors 6 adjacent to each other. On the other hand, it has a staggered arrangement. The thickness of the solder resist layer 3 is about 3 to 10 μm on the strip-shaped wiring conductor 6. The size of the opening 9 is about 35 to 40 μm in the direction crossing the strip-shaped wiring conductor 6 and about 40 to 150 μm in the direction along the strip-shaped wiring conductor 6.

  According to the wiring board 100 of this example, the electrode terminal T of the semiconductor element S is brought into contact with the semiconductor element connection pad portion 7 and the two are bonded together via a conductive bonding material such as solder. The electrode terminal T of the element S and the strip-shaped wiring conductor 6 are electrically connected.

  By the way, in the wiring board 100 of the present invention, each strip-shaped wiring conductor 6 has a parallel portion 8 parallel to the semiconductor element connection pad portion 7 of the strip-shaped wiring conductor 6 adjacent to each other in a state covered with the solder resist layer 3. doing. By providing such parallel portions 8, when the strip-shaped wiring conductor 6 is formed by the semi-additive method, the etching for forming the strip-shaped wiring conductor 6 becomes uniform, and the strip-shaped wiring conductor 6 having a stable width is formed. It becomes possible.

  Further, as shown in FIGS. 2A and 2B, the strip-shaped wiring conductor 6 is connected to the adjacent semiconductor element from the side surface of the parallel portion 8 parallel to the semiconductor element connection pad portion 7 in the adjacent strip-shaped wiring conductor 6. The width of the parallel portion 8 is narrowed so that the thickness t of the solder resist layer 3 up to the opening 9 exposing the pad portion 7 is 10 μm or more. The width of the parallel portion 8 is set so that the thickness t of the solder resist layer 3 from the side surface of the parallel portion 8 parallel to the semiconductor element connection pad portion 7 in the adjacent strip-shaped wiring conductors 6 to the adjacent opening 9 becomes 10 μm or more. As described later, when the solder resist layer 3 having the opening 9 is formed, the opening 9 can be formed in an accurate shape. Therefore, it is possible to provide the wiring substrate 100 capable of satisfactorily connecting the electrode terminal T of the semiconductor element S and the semiconductor element connection pad portion 7. Note that the cross-sectional shape of the opening 9 across the strip-shaped wiring conductor 6 has a drum shape in which the side wall bulges 3 μm or less inside the opening 9.

  Next, a method for forming the solder resist layer 3 in the wiring substrate 100 described above will be described with reference to FIG. First, as shown in FIG. 3A, the strip-shaped wiring conductor 6 is formed on the upper surface of the insulating substrate 1. The strip-shaped wiring conductor 6 is formed by a known semi-additive method. At this time, the width from the portion that becomes the semiconductor element connection pad portion 7 to the portion that becomes the parallel portion 8 in the adjacent strip-shaped wiring conductors 6 is narrowed.

  Next, as shown in FIG. 3B, a photosensitive resin layer 3 </ b> P for the solder resist layer 3 is formed on the insulating substrate 1 and the strip-shaped wiring conductor 6. Such a photosensitive resin layer 3P is formed by, for example, a method of thermocompression bonding a photosensitive resin film or a method of applying a photosensitive resin paste. The photosensitive resin layer 3P is formed so that the thickness on the strip-shaped wiring conductor 6 is about 3 to 10 μm.

  Next, as shown in FIG. 3C, an exposure mask M having a light shielding pattern in a portion corresponding to the opening 9 is disposed on the photosensitive resin layer 3P, and ultraviolet rays are irradiated from above as exposure light. Exposure. Finally, as shown in FIG. 3D, the unexposed portion is removed by development and the remaining photosensitive resin layer 3P is thermally cured to form the solder resist layer 3.

  At this time, each strip-shaped wiring conductor 6 is soldered from the side surface of the parallel portion 8 parallel to the semiconductor element connection pad portion 7 in the adjacent strip-shaped wiring conductor 6 to the opening portion 9 exposing the adjacent semiconductor element connection pad portion 7. Since the width of the parallel portion 8 is narrowed so that the thickness t of the resist layer 3 is 10 μm or more, when the photosensitive resin layer 3P for the solder resist 3 is exposed, the side surface of the parallel portion 8 is exposed to exposure light. Even if the light is reflected and enters the part that becomes the opening 9, the distance between the side surface of the parallel part 8 and the side wall of the opening 9 adjacent to the parallel part 8 is increased, so that the influence of reflection can be reduced. Thus, it is possible to form the opening 9 having an accurate shape. When the thickness t is less than 10 μm, the cross-sectional shape in the direction across the strip-shaped wiring conductor 6 in the opening 9 becomes an extreme drum shape in which the side wall bulges by 3 μm or more inside the opening 9. There is a greater risk that it is difficult to connect the electrode terminal T and the semiconductor element connection pad portion 7 satisfactorily.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Wiring conductor 3 Solder resist layer 6 Band-shaped wiring conductor 7 Semiconductor element connection pad part 8 Parallel part 9 Opening of solder resist layer S Semiconductor element T Electrode terminal of semiconductor element

Claims (1)

A plurality of strip-shaped wiring conductors for connecting semiconductor elements are arranged in parallel on the insulating substrate, and a part of each of the strip-shaped wiring conductors is individually provided as a semiconductor element connection pad portion on the insulating substrate and the strip-shaped wiring conductor. A wiring board formed by depositing a solder resist layer having openings exposed to each other in a staggered arrangement with respect to the adjacent band-shaped wiring conductors, wherein at least some of the band-shaped wiring conductors are adjacent to each other A parallel portion parallel to the semiconductor element connection pad portion of the strip-shaped wiring conductor is covered with the solder resist layer adjacent to the opening, and the parallel portion to the adjacent opening the thickness of the solder resist layer has a width of the parallel portion is narrowed so that the above 10 [mu] m, and the cross-sectional shape in a direction transverse to the strip conductor of said opening, the side wall is the Wiring board, characterized by that the drum shape that follows bulging 3μm inside of the mouth.

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