JP6123510B2 - Semiconductor device and method for controlling semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for controlling the semiconductor device.

  One method for mounting a processor data memory is a bank interleave method. In the bank interleaving method, generally, data memories corresponding to a plurality of power banks of 2 (memory banks) are connected to a processor. In the bank interleave method, addresses are not allocated so as to be continuous in the depth direction of each bank as shown in FIG. 8 (A), but are continuous in the horizontal direction across banks as shown in FIG. 8 (B). Allocate to In the bank interleaving method, for example, the bank corresponding to the address is uniquely determined by the lower bits of the address (lower 2 bits for 4 banks and lower 3 bits for 8 banks).

  FIG. 8A and FIG. 8B are diagrams illustrating an example of a data memory mounting method. 8A and 8B show an example having four banks, 810 is a processor, 820-p is a data memory (bank p) (p = 0, 1, 2,. 3). The processor 810 has interfaces 811-p including registers for inputting / outputting data to / from the data memory (bank p) 820-p corresponding to each of the data memories (bank p) 820-p. The data memory (bank p) 820-p can be accessed independently.

  The bank interleave method has an advantage that continuous access (sequential access) for sequentially accessing data arranged in a row such as an array is fast. For example, as shown in FIG. 8C, the data (elements) of the array data stored in the continuous address area are represented by data [0], data [1], data [2],. [15] Assume that a process for obtaining the sum sum is performed by sequentially reading and adding.

  In the data memory mounting method shown in FIG. 8A, for example, data [0] and data [1] are present on the same data memory (bank 0) 820-0 and cannot be read simultaneously. . That is, in the data memory mounting method shown in FIG. 8A, only one data can be read out in one cycle in most of the processes shown in FIG. 8C, so data [0] to data [15 ] Takes 13 cycles to read all the data.

  On the other hand, in the bank interleave method shown in FIG. 8B, for example, data [0], data [1], data [2], and data [3] are different data memories (bank p) 820-p. Since they exist above, they can be read simultaneously. That is, in the bank interleaving method illustrated in FIG. 8B, four data can be read in one cycle when performing the processing illustrated in FIG. 8C, and thus data [0] to data [ 15] requires only 4 cycles to read all.

  For example, in sequential access in which array data is sequentially written, the mounting method shown in FIG. 8A can only write one data per cycle. On the other hand, in the bank interleave method shown in FIG. 8B, four data can be written in one cycle.

  Based on the access address in the memory access instruction, the memory area accessed by the processor that performs the access instruction is allocated in a stack type when the access address has locality. A device has been proposed in which the access address is assigned in an interleaved manner when there is no locality (see, for example, Patent Document 1). In addition, a multi-bank memory type memory system having a plurality of memory banks having interleaved addresses has been proposed (see, for example, Patent Documents 2 and 3). In order to improve concurrency in a memory system, a technique for reordering a plurality of memory access requests has been proposed (see, for example, Patent Document 3).

JP 2008-234156 A Special table 2003-520368 gazette Japanese Patent Laid-Open No. 10-228417

  As described above, the bank interleave method has an advantage that sequential access for sequentially accessing data in an array is fast. However, depending on the application, not only the sequential access but also the sequence may be accessed in a non-consecutive order. For example, in a signal processing application or an encryption application for wireless communication, access may be performed not only with sequential access but also with a special order access pattern. In access in a special order other than sequential access, the advantage of the bank interleave method may not be utilized, and it may be possible that only one data can be read from or written to the data memory per cycle.

  An object of the present invention is to make it possible to control the bank arrangement of data in an array in a data memory in accordance with an access pattern for the array.

One embodiment of a semiconductor device includes a data memory having a plurality of banks and a processor that performs access according to an access command to the data memory. In the case where the input access instruction is an access instruction including designation information for designating the allocation of the bank of the data memory in which the array data is arranged, according to the bank allocation specified by the designation information , The index corresponding to the bank in which the data to be accessed by the access instruction is arranged is converted, the bank is selected according to the converted index , and the data memory related to the array is accessed.

  The disclosed semiconductor device enables bank arrangement of array data according to the access pattern for the array by modifying the application by selecting the bank in which the array data is arranged according to the specified bank allocation. Therefore, appropriate memory access can be realized, and performance can be improved.

It is the schematic which shows the structural example of the semiconductor device in embodiment of this invention. It is a figure which shows the example of the memory map in this embodiment. It is a figure which shows the structural example of the semiconductor device in this embodiment. It is a figure which shows the structural example of the index converter in this embodiment. It is a figure which shows the example of the selector setting table | surface in this embodiment. It is a figure which shows an example of the source code and access instruction in this embodiment. It is a figure which shows the example of the memory access in this embodiment. It is a figure for demonstrating the mounting method of a data memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention. The semiconductor device in the present embodiment includes a processor 10 and a data memory (bank p) 20-p. Note that p is a subscript, and p = 0, 1, 2, and 3 (the same applies to the following). Although FIG. 1 shows an example having four banks, the number of banks is arbitrary as long as it is plural, and is preferably a power of two.

  The processor 10 has an interface 11-p for inputting / outputting data to / from the data memory (bank p) 20-p, corresponding to each of the data memories (bank p) 20-p. The processor 10 can access each data memory (bank p) 20-p independently by each interface 11-p. The interface 11-p includes a register that holds input / output data for the data memory (bank p) 20-p.

  The semiconductor device according to the present embodiment can control the allocation of the banks of the data memory to the arrays, that is, which bank the array data (elements) is arranged in the data memory. For example, for an array in which data is to be accessed in a special order, the array data is arranged in each bank in a bank pattern designated by the user, as shown in an area 201 in FIG. Further, for example, in an array in which sequential access for sequentially accessing data is performed, the array data is arranged in each bank in a normal bank pattern as shown in an area 202 in FIG. Here, the normal bank pattern is a bank interleave type bank pattern in which the bank is uniquely determined by the value of the lower bits of the address (array index). For example, the bank pattern is arranged as shown in FIG. A pattern having a certain rule.

  FIG. 2 is a diagram illustrating an example of a memory map in the present embodiment. In FIG. 2, the fill pattern indicates the bank difference in the data memory. For example, a block in which a right-down diagonal line and a left-down diagonal line intersect corresponds to bank 0 of the data memory, a dot-filled block corresponds to bank 1 of the data memory, and a block of right lower diagonal line corresponds to the bank of the data memory 2 corresponds to bank 3 of the data memory. In the example shown in FIG. 2, in the area 201, banks are arbitrarily assigned in the address direction, and in the area 202, banks are assigned in order (regularly) in the address direction.

  In FIG. 2, BAD 1 is the base address of the area 201, and BAD 2 is the base address of the area 202. Even when the array data is arranged in the bank pattern designated by the user, the size of the area is the same as the area size in the arrangement with the normal bank pattern. In other words, the area in which the array data is arranged is an area having a size that is sufficient for storing the array data.

  As described above, in the present embodiment, by controlling the bank arrangement in the data memory of the array data (elements) in a user-designable manner, the arrangement of the array data according to the data access pattern of the application with respect to the array becomes possible. . Therefore, even for applications that access array data in a special order, appropriate memory access can be achieved by arranging data according to the application without modifying (changing) the application. Improvements can be made.

  FIG. 3 is a diagram illustrating a configuration example of the semiconductor device according to the present embodiment. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals. FIG. 3 shows the configuration related to access control to the data memory in the semiconductor device of the present embodiment, but the processor 10 has a configuration related to data input / output to the data memory and a general processor. It also has a configuration related to other processing such as arithmetic processing (not shown).

  The processor 10 includes an instruction control unit 12, an index converter 13, a selector 14, an adder 15, an address holding unit 16, and a bank selection decoder 17. The instruction control unit 12 receives an instruction ins read from an instruction memory (not shown), decodes the instruction ins, and performs processing according to the decoding result. For example, when the instruction ins is an access instruction to the data memory (bank p) 20-p, the instruction control unit 12 accesses the data memory (bank p) 20-p.

  If the instruction ins is an access instruction to the data memory (bank p) 20-p related to the array, the instruction control unit 12 outputs the base address base and the index index1 specified by the access instruction. Here, the base address specified by the access instruction is the base address of the memory area related to the array to be accessed, and the index specified by the access instruction is an index for identifying the data of the array to be accessed.

  Further, the instruction control unit 12 is an instruction to access the data memory (bank p) 20-p in which the instruction ins is an array, and further displays a bank pattern indicating bank allocation (bank arrangement) in the data memory of the array data. When the access instruction includes the designation information to be designated, the designation information bankpt is output. The instruction control unit 12 outputs a signal S1 indicating whether or not the instruction ins is an access instruction including bank pattern designation information for designating bank allocation.

  The index converter 13 receives the index index1 output from the instruction control unit 12 and the bank pattern designation information bankpt, and outputs the index index2. The index converter 13 converts the input index index1 into the index index2 based on the bank assignment (bank pattern) specified by the specification information bankpt and outputs the index.

Based on the signal S1 output from the instruction control unit 12, the selector 14 selects one of the index index1 output from the instruction control unit 12 or the index index2 output from the index converter 13 and outputs it as an index index3. . When the signal S1 indicates that the instruction ins is an access instruction including bank pattern designation information, the selector 14 outputs the index index 2 as the index index3. On the other hand, when the signal S1 indicates that the instruction ins is not an access instruction including bank pattern designation information, the selector 14 outputs the index index 1 as the index index3.

  The adder 15 adds the index index3 output from the selector 14 to the base address base output from the instruction control unit 12, and generates a memory address for accessing the data memory (bank p) 20-p. . The memory address generated by the adder 15 is held in the address holding unit 16. The bank selection decoder 17 decodes the memory address held in the address holding unit 16, selects a bank based on the decoding result, and performs access. That is, the bank selection decoder 17 selects a bank according to the index index 3 output from the selector 14.

  In the data memory (bank p) 20-p, for example, the data datA [0] to datA [31] of the array datA are stored in the bank according to the bank pattern table of setting 0 in the selector setting table illustrated in FIG. When arranged by arrangement, the arrangement is performed as shown in the region 21. The selector setting table illustrated in FIG. 5 will be described later. Further, for example, when the data datB [0] to datB [31] of the array datB are arranged in a bank arrangement according to a normal bank pattern, they are arranged as shown in the region 22.

  FIG. 4 is a diagram illustrating a configuration example of the index converter 13. As shown in FIG. 4, the index converter 13 includes a selector 31, a selector setting table 32, and registers 33 and 34. The register 33 is a register that holds an input index index 1, and the register 34 is a register that holds an index index 2 that is an output of the selector 31. FIG. 4 shows an example in which the indexes index1 and index2 are 6 bits, but the number of bits of the indexes index1 and index2 is not limited to this.

  The selector 31 refers to the bank pattern table selected according to the bank pattern designation information bankpt from the table of the selector setting table 32, converts the index index1 into the index index2, and outputs the index. The selector setting table 32 has a table indicating the correspondence (bank pattern) between the array index and the bank in which the array data is arranged, as shown in FIG. 5 according to the bank pattern designation information bankpt. One table is selected.

  FIG. 5 is a diagram illustrating an example of the selector setting table 32. The selector setting table has a table for allocating banks in which array data is arranged with respect to the array index. One table is selected according to the bank pattern designation information bankpt, and data in an array corresponding to the index is arranged in the bank designated by the selected table. FIG. 5 shows an example having a table of setting 0 and setting 1 in which fixed values are set by hardware (HW) and a table of setting 2 in which arbitrary values can be set by software (SW). Yes.

  Here, as for the selector setting table, all the tables may be realized by hardware, or all the tables may be realized by software. Further, a part of the selector setting table may be realized by hardware, and the remaining tables may be realized by software. When the selector setting table is realized by hardware, the table cannot be changed later according to the application, but the application developer can increase the access efficiency by simulation etc. from the existing table. By selecting such a table, it is possible to develop an application that can realize appropriate memory access. Further, when the selector setting table is realized by software, the application developer must input the table, but the table suitable for the application can be freely set.

  FIG. 6A is a diagram illustrating an example of source code of an application that is operated on the semiconductor device according to the present embodiment. The code 601 is a code for instructing the data of the array proposal to be arranged in each bank according to the bank pattern 3, and the codes 602 and 603 are codes that define the arrays proposal and normal, respectively. The array normal is an array in which array data is arranged in a normal bank pattern in which the bank is uniquely determined by the value of the lower bits of the address (array index).

  The code 604 is a code for reading data proposal [0] having an index value 0 in the array proposal from the data memory and assigning it to the variable a. The code 605 is a code for reading the data proposal [4] of the index value 4 in the array proposal from the data memory and assigning it to the variable b. Similarly, the code 606 is a code for reading the data normal [0] of the index value 0 in the array normal from the data memory and assigning it to the variable x. The code 607 is a code for reading the data normal [4] of the index value 4 in the array normal from the data memory and assigning it to the variable y.

  A special instruction different from a normal instruction is used for accessing the data memory related to the array proposal that distributes banks arranged in the bank pattern 3. For example, the compiler compiles the source code by determining whether to use a normal instruction or a special instruction based on the type of the variable.

  FIG. 6B shows an example of a load instruction for reading the data of the array proposal that distributes the banks to be arranged according to the bank pattern. In the instruction loadProposal for reading data of the array proposal from the data memory, Register indicates a register for storing the read data, base indicates a base address of the array, and index indicates an index in the array. BankPattern is designation information for designating a bank pattern indicating the bank arrangement of the array.

  When the input instruction ins is the instruction loadProposal, the instruction control unit 12 illustrated in FIG. 3 outputs the base and index in the instruction loadProposal as the base address base and the index index1. Further, the instruction control unit 12 outputs bankPattern in the instruction loadProposal as bank pattern designation information bankpt, and indicates that the inputted instruction ins is an access instruction including bank pattern designation information by a signal S1.

  FIG. 6C shows an example of a load instruction for reading data of an array normal for distributing banks arranged in a normal bank pattern. In an instruction load for reading data of the array normal from the data memory, Register indicates a register for storing the read data, base indicates a base address of the array, and index indicates an index in the array.

  When the input instruction ins is an instruction load, the instruction control unit 12 illustrated in FIG. 3 outputs the base and index in the instruction load as the base address base and the index index1. Further, the instruction control unit 12 indicates by a signal S1 that the input instruction ins is not an access instruction including bank pattern designation information.

  According to the present embodiment, it is possible to arbitrarily allocate the banks of the data memory with respect to the array, and by selecting the bank according to the specified bank allocation, the data of the array can be determined according to the access pattern for the application array. The bank arrangement in the data memory can be controlled. Therefore, even for applications that access array data in a special order, appropriate memory access can be achieved by arranging data according to the application without modifying (changing) the application. Improvements can be made.

  For example, suppose that an array having 32 data (elements) with an index of 0 to 31 is incremented by 1 such that the index is 0, 1, 2,. After that, the index is 0, 4, 8, 12, 16, 20, 24, 28, 1, 5, 9, 13, 17, 21, 25, 29, 2, 6, 10, 14, 18, 22, 26, Assume that data is read in the order of 30, 3, 7, 11, 15, 19, 23, 27, and 31.

  Each bank stores array data in a normal bank interleaved bank pattern (bank interleaved bank pattern in which the bank is uniquely determined by the lower bits of the address), with the bank uniquely determined by the lower bits of the address (array index) 7A, as shown in FIG. 7A, 8 cycles are required to write data, 29 cycles are required to read data, and 37 cycles are required as a whole. On the other hand, when the array data is arranged in each bank with the bank pattern set to 0 in the selector setting table shown in FIG. 5, as shown in FIG. In other words, 13 cycles are required to read data, and 28 cycles are required in total. As described above, in this embodiment, by controlling the bank arrangement of the array data according to the array data access pattern, appropriate memory access can be realized, and the number of cycles required for memory access can be reduced. be able to.

  In the above-described embodiment, a normal access instruction is used for the arrangement of banks in the normal bank pattern, and a special access instruction is used for the arrangement of banks in the bank pattern of the table included in the selector setting table. Are distinguished. The present embodiment is not limited to this. For example, in the selector setting table, the value of the lower bit of the address (array index) and the bank in which the data is allocated uniquely correspond to a bank interleaved normal bank A pattern table may be provided, and a memory pattern may be realized by one type of access instruction so that a bank pattern is always designated.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

10 processor 11-0 to 11-3 interface 20-0 to 20-4 data memory 12 instruction control unit 13 index converter 14 selector 15 adder 16 address holding unit 17 bank selection decoder 31 selector 32 selector setting table 33, 34 register

Claims (7)

A data memory having a plurality of banks;
A processor that performs access in response to an access instruction to the data memory,
The processor is
In the case where the input access instruction is an access instruction including designation information for designating allocation of banks of the data memory in which the array data is arranged, according to the bank allocation specified by the designation information , A semiconductor device, wherein an index corresponding to a bank in which data accessed by the access instruction is arranged is converted, the bank is selected according to the converted index , and the data memory according to the array is accessed . The processor is
An index conversion unit that converts an index corresponding to a bank in which data to be accessed by the access instruction that is input is converted according to the distribution of the bank designated by the designation information;
2. If the access instruction is an access instruction including the designation information, the bank is selected based on the converted index, and the data memory related to the array is accessed. The semiconductor device described. The index conversion unit
A table showing a correspondence relationship between an index of the array and the bank in which the data of the array is arranged;
The semiconductor device according to claim 2, further comprising: a conversion unit that converts an index corresponding to a bank in which data to be accessed by the access instruction is referenced with reference to the table selected according to the designation information. .   4. The semiconductor device according to claim 3, wherein the table included in the index conversion unit includes a table in which a value of a lower-order bit of an array index uniquely corresponds to the bank in which the array data is arranged. . The processor is
When the access instruction is an access instruction including the designation information, the converted index is selected. When the access instruction is not an access instruction including the designation information, the access instruction corresponds to a bank in which data to be accessed is arranged. A selection unit for selecting an index to be
The semiconductor device according to claim 2, wherein the bank is selected based on the index selected by the selection unit, and the data memory related to the array is accessed. A method for controlling a semiconductor device, comprising: a data memory having a plurality of banks; and a processor that performs access in response to an access instruction to the data memory,
When the input access instruction is an access instruction including designation information for designating allocation of banks of the data memory in which data of an array is arranged, according to the allocation of banks specified by the designation information, Converting an index corresponding to a bank in which data to be accessed by an access instruction is placed ;
And a step of selecting the bank based on the converted index and accessing the data memory related to the array. Transforming the array index comprises:
Selecting a table indicating a correspondence relationship between an array index and the bank in which the array data is arranged according to the designation information;
7. The method of controlling a semiconductor device according to claim 6, further comprising: converting an index corresponding to a bank in which data accessed by the access instruction is arranged with reference to the selected table.

Images