JP6124615B2 - MEMORY CONTROL DEVICE, MEMORY CONTROL METHOD, AND IMAGING DEVICE HAVING MEMORY CONTROL DEVICE - Google Patents

Description

  The present invention relates to a memory control device, and more particularly to a memory control device that controls access by a plurality of masters to a common memory.

  In recent years, higher resolution has been advanced in imaging apparatuses such as digital still cameras and video cameras. For this reason, a volatile memory such as SDRAM (Synchronous Dynamic Access Memory) is often used as a large-scale storage unit for storing intermediate images for image processing. In addition, with the diversification of photographing assist functions such as face detection and camera shake correction, functions for accessing the SDRAM are increasing, and it is required to increase the access efficiency of the memory bus.

  Also, in SDRAM, when switching between read access and write access, it is necessary to open a certain period in order to avoid data collision, resulting in a decrease in access efficiency. Therefore, techniques for improving access efficiency have been proposed. For example, Patent Document 1 discloses a method for arbitrating transfer requests so as to improve access efficiency in consideration of the contents of transfer requests from a plurality of bus masters and the current access state to the SDRAM.

JP 2001-356916 A

  However, in this method, it is necessary to select which of the priority setting between the masters and the access efficiency is to be prioritized. For example, an imaging apparatus has a function that requires real-time processing such as data input from an imaging sensor and display output to a liquid crystal panel, and there is a problem that real-time performance cannot be guaranteed if priority is given to access efficiency.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device that enhances memory access efficiency while guaranteeing real-time performance.

According to one aspect of the embodiment, the memory control device controls data transfer between a plurality of bus masters and a memory, and includes the plurality of bus masters including a predetermined bus master that repeatedly issues a data transfer request every predetermined period. Queue means for storing a data transfer request from the bus master, means for outputting a command corresponding to the data transfer request stored in the queue means to the memory, and data transfer according to the data transfer request from the predetermined bus master When a time obtained by subtracting time from the predetermined period is set as a threshold , and the data transfer request is newly output, the time required for data transfer by the data transfer request stored in the queue means and the threshold Control means for controlling whether or not to store the newly output data transfer request in the queue means based on Memory controller is provided to obtain.

  According to the present invention, it is possible to guarantee real-time processing and to prevent a condition for newly storing a transfer request for a queue (queue) from becoming more severe than necessary. Efficiency can be improved.

It is a figure which shows the structure of the imaging device to which the memory control apparatus which concerns on 1st Example of this invention is applied. It is a figure for demonstrating control operation | movement of the queue in the memory control apparatus which concerns on 1st Example of this invention. It is a figure which shows the structure of the imaging device to which the memory control apparatus which concerns on 2nd Example of this invention is applied. It is a figure for demonstrating threshold value control in the memory control apparatus which concerns on 2nd Example of this invention. It is a figure for demonstrating the control operation of the queue in the memory control apparatus which concerns on 2nd Example of this invention.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of an imaging apparatus to which a memory control apparatus according to a first embodiment of the present invention is applied. Each unit of the imaging apparatus is controlled by a control unit (CPU) (not shown). Hereinafter, FIG. 1 will be described.

  In FIG. 1, the timing generator 101 generates horizontal and vertical synchronization signals in accordance with the operation mode at the time of shooting, and outputs them to the sensor drive control unit 102. The sensor drive control unit 102 generates a control pulse for controlling charge accumulation and data output of the image sensor 103 based on the synchronization signal, and outputs the control pulse to the image sensor 103. The imaging sensor 103 is driven according to the control pulse, photoelectrically converts the subject image, and outputs moving image data. The imaging processing unit 104 is an image processing unit that appropriately performs defective pixel correction, shading correction, and the like on each frame of the moving image data output from the imaging sensor 103 in real time. The processed data is recorded in the SDRAM 107 via the memory bus 105 and the memory controller 106.

  The face detection unit 108 reads out image data after imaging processing recorded in the SDRAM 107 via the memory bus 105 and the memory controller 106, and detects a person's face. The development processing unit 109 reads the image data after the imaging process recorded in the SDRAM 107 via the memory bus 105 and the memory controller 106, and performs the development process. For example, resize processing such as pixel interpolation, filter processing, reduction, and color conversion processing, for example, processing for conversion to a format of Y, Cb, Cr format, which is an optimal format for saving in compressed image data, is performed. The development processing unit 109 records the processed image in the SDRAM 107 via the memory bus 105 and the memory controller 106. The display control unit 110 reads out the image data after the development processing via the memory bus 105 and the memory controller 106 and outputs the read image data to the display unit 111. The encoding unit 112 reads an image after development processing from the SDRAM 107 via the memory bus 105 and the memory controller 106, and H.264 or the like is compressed and encoded, and recorded on the recording medium 113. The control unit 121 has a CPU and controls the operation of each unit of the imaging apparatus.

  Next, the internal configuration of the memory controller 106 will be described. In response to data transfer requests from a plurality of bus masters, the arbitration unit 114 selects one bus master according to a preset priority and outputs the selected bus master to the queue 115 and the queue control unit 116. When the data transfer request is stored in the queue 115, the bus master is notified of acceptance of the transfer request.

  The transfer request from each master includes the address of the access destination in the SDRAM 107, the data length of the data for which transfer is requested (data amount, hereinafter referred to as burst length), and a write or read instruction. When the arbitration unit 114 does not accept the transfer request, the arbitration unit 114 does not transmit a request acceptance response (acknowledgement) to the master. Therefore, each master continues to output the same transfer request repeatedly at a predetermined timing until the transfer request acceptance response output by itself is received from the arbitration unit 114 (first bus master).

  The queue 115 stores a transfer request in response to an instruction from the queue control unit 116. The queue processing time calculation unit 117 calculates the time required to complete the data transfer for all transfer requests stored in the queue 115 based on the burst length included in the transfer request stored in the queue 115. To the queue control unit 116. The queue control unit 116 compares the transfer processing time from the queue processing time calculation unit 117 with the queue input threshold value from the threshold setting unit 118, and stores a transfer request in the queue 115 based on the result. Control to determine whether or not. In this embodiment, it is assumed that the time required for data transfer is determined based on the burst length, and there is no difference in transfer time between the bus masters. The queue 115 holds the transfer request (command) output from the arbitration unit 114. The queue 115 includes a plurality (a predetermined number) of holding units each holding one transfer request with different priorities.

  The threshold setting unit 118 sets a queue threshold according to the control from the control unit 121 and outputs the queue threshold to the queue control unit 116. In response to the transfer request output from the queue 115, the command control unit 119 issues a memory access command such as an active command for accessing the SDRAM 107 and an address such as a bank or page to the SDRAM 107. The data control unit 120 controls data transfer between the memory bus 105 and the SDRAM 107.

  The SDRAM 107 is composed of a plurality of banks, and each bank is composed of a plurality of pages. Access to the SDRAM 107 is realized by activating a page to be accessed by designating a bank and page and issuing an active command, and issuing a memory command such as designating a column address and reading / writing.

  When the same page of the SDRAM 107 is accessed continuously by two commands, a column address and a memory access command can be issued without issuing an active command between these two commands. Also, in SDRAM 107, when accessing a different page in the same bank as the access destination by the previous command, after issuing a precharge command for deactivating the previously accessed page, the page to be accessed next is accessed. Issue an active command.

  FIG. 2 is a diagram for explaining the control operation of the queue 115 of the memory control device according to the present embodiment. In FIG. 2, the transfer request from each bus master may be either a data read command or a data write command.

  In the figure, (1) is a time axis for explaining the passage of time of processing. (2) is a horizontal synchronization signal generated by the timing generator, and image data is read from the image sensor 103 at this cycle. (3) to (7) are transfer requests from the development processing unit 104, the face detection unit 108, the development processing unit 109, the display control unit 110, and the encoding unit 112. (8) shows the state of the queue 115. Here, the queue 115 has three holding units indicated by 1-3. The lower the number, the higher the priority. (9) shows the processing time until the transfer of data by all the transfer requests stored in the queue calculated by the queue processing time calculation unit is completed. (10) is a threshold set in the threshold setting unit 118. (11) indicates a command issued to the SDRAM 107 by the address bus. A command such as an active command or an address for designating an address such as a bank position is issued by the address bus. (12) indicates data transferred between the SDRAM 107 and each bus master by the data bus.

  The queue control operation of the memory control device according to this embodiment will be described with reference to FIGS. In this embodiment, the transfer of the imaging processing unit 104 is a real-time process (first process) that is required to be processed in accordance with the cycle of the horizontal synchronization signal. Further, since the other transfer is performed by reading an image from the SDRAM, it will be described as a non-real-time process (second process). Here, the priority in the arbitration unit 114 is set in the order of imaging processing unit> face detection unit> development processing unit> display control unit> encoding unit.

  In FIG. 2, since the cycle of the horizontal synchronization signal, which is the processing cycle of the imaging processing unit, is 21 microseconds (μs) and the transfer time of the imaging processing unit is 6 μs, the transfer request is output from the imaging processing unit 104. It is necessary to start data transfer to the SDRAM 107 within 15 (21-6) μs. Therefore, the threshold setting unit 118 sets the threshold to 15 μs. This guarantees execution of real-time processing. As described above, the queue control unit 116 controls the storage of the transfer request in the queue 115.

  The queue processing time calculation unit 117 calculates the total value of the time required for data transfer by all transfer requests stored in the queue 115 and the processing time until the transfer of data currently being transferred to the SDRAM 107 is completed. As the data transfer to the SDRAM 107 proceeds, the processing time changes. However, in order to simplify the description, the description will be made using the maximum value of the transfer time for data transfer according to the transfer request. At time T0, there is no transfer request from the bus master, and no transfer with the SDRAM 107 is performed. When a transfer request is issued from the face detection unit 108 at time T1, transfer to the SDRAM 107 is not performed. Therefore, the transfer request is output to the command control unit 119 without being stored in the queue 115, and the command C2 is issued by the command control unit 119. Also, data D2 between the face detection unit 108 and the face detection unit 108 is started. Further, the queue processing time calculation unit 117 sets 5 μs, which is the processing time required for data transfer in response to the transfer request from the face detection unit 108, as the queue processing time.

  When a transfer request from the development processing unit 109 is issued at time T2, the queue transfer processing time is 5 μs, and even if the transfer processing time of 5 μs of the development processing unit 109 is added, the threshold value of 15 μs is not exceeded. Therefore, the queue control unit 116 stores the transfer request from the development processing unit 109 in the queue 115. Further, the queue processing time calculation unit 117 adds the transfer processing time of the development processing unit 109 to 10 μs.

  At the time when a transfer request from the display control unit 110 is issued at time T3, the queue processing time is 10, and even if the transfer processing time of 5 μs of the display control unit 110 is added, the threshold value of 15 μs is not exceeded. Therefore, the queue control unit 116 stores the transfer request from the development processing unit 109 in the queue 115.

  Next, the transfer processing time of the display control unit 110 is added by the queue processing time calculation unit 117, and the queue processing time becomes 15 μs. When a transfer request from the encoding unit 112 is issued at time T4, the queue processing time is 15 μs, and when the time required for data transfer by the transfer request from the encoding unit 112 is added, the threshold value exceeds 15 μs. . Therefore, the queue control unit 116 prohibits a new transfer request from being stored in the queue 115 even if the queue 115 is empty.

  When the data transfer of the face detection unit 108 is completed at time T5, the transfer request 3 from the development processing unit 109 having the highest priority among the transfer requests stored in the queue 115 is output to the command control unit 119, and the data Transfer starts. Then, the queue processing time calculation unit 117 recalculates the data transfer time according to the transfer request stored in the queue 115, excluding the processing time due to the transfer request from the face detection unit 108 that has been transferred. Here, it is 10 μs. The queue control unit 116 determines whether or not to store the transfer request 5 from the encoding unit 112 waiting for storage in the queue 115 based on the queue processing time calculated again. Here, since the sum of the queue processing time of 10 μs and the processing time of 6 μs due to the transfer request from the encoding unit 112 waiting for storage exceeds the threshold of 15 μs, the queue control unit 116 transfers the data from the encoding unit 112. Request 5 is not stored in queue 115.

  Since the imaging processing unit 104 has a higher priority than the encoding unit 112, when the transfer request 1 is issued from the imaging processing unit 104 at time T6, the transfer request selected by the arbitration unit 114 is the imaging processing unit. Transfer request 1 from 104. Then, the queue control unit 116 determines whether or not to store the transfer request 1 in the queue 115. Here, since the queue processing time 10 μs and the transfer processing time 6 μs of the imaging processing unit 104 exceed the threshold value 15 μs, the queue control unit 116 does not store the transfer request 1 from the imaging processing unit 104 in the queue 115.

  When the data transfer of the development processing unit 109 is completed at time T7, the transfer request from the display control unit 110 having the highest priority among the transfer requests stored in the queue 115 is output to the command control unit 119, and the data transfer is performed. Be started. Then, the queue control unit 116 determines whether or not the transfer request 1 from the development processing unit 104 waiting to be stored in the queue 115 is stored in the queue 115. Here, the sum of the queue processing time 5 μs based on the transfer request 4 from the display control unit 110 and the processing time 6 μs based on the transfer request from the imaging processing unit 104 does not exceed the threshold value 15 μs. Therefore, the queue control unit 116 stores the transfer request 1 from the imaging processing unit 104 in the queue 115.

  When the data transfer of the display control unit 110 is completed at time T8, the queue control unit 116 stores the transfer request 5 from the encoding unit 112 waiting for queue storage in the queue 115. In addition, a transfer request from the imaging processing unit 104 having the highest priority among the transfer requests stored in the queue 115 is output to the command control unit 119, data transfer is started, and is completed at time T9. Since the first transfer is completed when a second transfer request is issued from the imaging processing unit 104 at time T10, real-time processing is guaranteed.

  Note that the operation shown in FIG. 2 is merely an example, and the same operation is performed according to the technical idea of the present invention described above even when, for example, transfer requests for each process are given in a different order from the figure. In the memory control of a processing device other than the imaging device, a similar memory control configuration can be achieved for the processing performed by the processing device.

  As described above, according to the first embodiment of the present invention, the queue can be effectively used up to the limit at which the real-time processing fails, and the efficiency of memory access can be increased.

  Next, a second embodiment of the present invention will be described. In the first embodiment, the access efficiency is improved while guaranteeing real-time processing by setting a threshold value that does not cause the real-time processing unit to fail as a threshold value. For this reason, the storage of new transfer requests in the queue 115 may be limited by the threshold even during periods other than the period for which real-time processing is required. In this embodiment, therefore, the threshold is adaptively changed according to the operation state (mode) of the device to which the memory control device is applied, thereby increasing the probability that a transfer request is newly stored in the queue 115. , Make the configuration to improve the access efficiency.

  FIG. 3 is a diagram illustrating a configuration of an imaging apparatus to which the memory control apparatus according to the present embodiment is applied. In FIG. 3, the same components as those in the first embodiment are denoted by the same reference numerals, and description of the operation thereof is omitted.

  The timing generator 101 generates horizontal and vertical synchronization signals in accordance with the operation mode at the time of shooting, and outputs them to the image sensor control unit 102. In addition, a flag for distinguishing a period during which an effective image is output from the vertical period and a period other than the period during the vertical period is generated in accordance with the output specification at the time of shooting, and is output to the threshold setting unit 301.

  The threshold value setting unit 301 sets a first threshold value for a period during which an effective image is output and a second threshold value for other periods, and outputs the first threshold value to the queue control unit 116 according to the flag from the timing generator 101. Switch the threshold.

  FIG. 4 is a diagram for explaining the queue control operation of the memory control device according to the present embodiment, in particular, the threshold control operation in the cycle of reading one image.

  In the figure, (1) is a vertical synchronizing signal, and in this cycle, one frame of moving image data is read out by the operation of the imaging processing unit. (2) shows the contents of data output from the image sensor 103. The output of the image sensor 103 is divided into an effective image data period in which image data of a subject image formed on the image sensor 103 is output, and a reference data output period such as an OB (optical black) level. Here, the reference data is data used for the correction process in the imaging process, and only data in the effective image period is recorded in the SDRAM.

  (3) is a flag for switching a threshold value for determining whether or not a transfer request is stored in the queue 115, and is switched between an effective image period and a reference data period. (4) is a horizontal synchronizing signal, and image data of the horizontal line is read from the image sensor 103 at this cycle. Here, in the effective image period indicated by the broken line 401, it is necessary to continue processing the input image periodically according to the horizontal synchronization signal, and the real-time processing described in the first embodiment is necessary.

  However, since the output of the image sensor is not recorded in the SDRAM during the reference data period indicated by the broken line 402, real-time processing is not necessary.

  FIG. 5 is a diagram for explaining the queue control operation during the period of the broken line 402 shown in FIG. In the figure, the same components as those in FIG. 2 for explaining the queue control operation of the first embodiment are denoted by the same reference numerals, and the description of the operation is omitted.

  In FIG. 5, reference numeral (11) denotes an address bus for issuing a command such as an active command to the SDRAM and designating an address such as a bank position. Command issuance to the SDRAM is executed in units of banks and indicates commands in units of banks. In this embodiment, the transfer processing time to the SDRAM is indicated by each command processing and data transfer processing. Here, it is assumed that various command issuance times are 1 μs, and that data transfer is 1 μs in processing time per burst. In FIG. 5, the first threshold for a period during which an effective image is output (period in which real-time processing is required) is 20 μs, and the second threshold for other periods (period in which real-time processing is not required) is 50 μs.

  FIG. 5A is a diagram for explaining the queue control operation when the first threshold value corresponding to the effective image period is set. The queue control operation in the case of the first threshold will be described with reference to FIG.

  At time T0, there is no transfer request from the bus master, and no transfer with the SDRAM is performed. Data transfer between the SDRAM and each bus master is not performed when a transfer request is issued from the face detection unit 108 at time T1. Therefore, the transfer request is not stored in the queue, but the command control unit 119 issues an active command (hereinafter abbreviated as ACT) that activates the page to be accessed.

  Since the transfer request of the face detection unit 108 is read access to bank 0 and page 0, ACT is issued to bank 0. Further, the queue processing time calculation unit 117 determines the number of command issuances and the burst width from the transfer contents, and calculates the queue processing time. At time T1, the processing time is 5 μs from the number of command issuance times: 2 and the burst width: 3. At time T2, a read command (hereinafter abbreviated as RD) that is a memory access command is issued. When a transfer request is issued from the development processing unit 109 at time T2, the number of command issuances and the burst width are determined from the transfer contents. The transfer request of the development processing unit 109 is a write access to bank 0 and page 1 and an access to another page in the same bank. Therefore, it is necessary to deactivate the current page with a precharge command (hereinafter abbreviated as PRE), activate the next page with ACT, and issue a memory access command.

  Therefore, the processing time is 6 μs based on the number of command issuance times: 3 and the burst width: 3. Since the queue transfer processing time at this point is 5 μs, and the transfer processing time 5 μs of the development processing unit 109 is added, the queue control unit 116 does not exceed the first threshold 20 μs. Store in the queue 115. Further, the queue processing time is 11 μs by adding the transfer processing time of the development processing unit 109. When a transfer request is issued from the display control unit 110 at time T3, the queue processing time calculation unit 117 calculates the maximum processing time for this transfer request alone. Since the number of command issuances is the maximum of 3 for the same page in the same bank, the number of command issuances is 3 times, which is 6 μs from the burst width.

The queue transfer processing time at this point is 11 μs, and even if the transfer processing time 6 μs of the display control unit 110 is added, the threshold value 20 μs is not exceeded. Therefore, the queue control unit 116
The transfer request from the display control unit 110 is stored in the queue 115. Next, the queue control unit 116 compares each transfer request stored in the queue 115 at this time with the data transfer state of the transfer request being executed, and determines the order of the transfer requests stored in the queue 115. It is determined whether the time required for the transfer process is shortened by changing the sales. If the queue control unit 116 determines that the processing time is shortened by changing the execution order of the transfer requests stored in the queue 115, the queue control unit 116 executes reorder processing for changing the execution order of the transfer requests stored in the queue 115. To do.

  For example, in FIG. 5, the transfer request 4 from the display control unit 110 issued at time T3 is a read access to the bank 0 and page 2, and is the same as the bank according to the transfer request from the currently executing face detection unit 108. is there. The transfer request 3 stored in the queue 115 is also an access request to the bank 0. Since the next command cannot be issued until the data transfer by the previously executed command to the same bank is completed, the processing can be performed even if the order of the transfer request 3 and the transfer request 4 stored in the queue 115 is changed. Time does not change. Therefore, in this case, the transfer request stored in the queue 115 is not reordered. When the reorder processing is executed by the queue control unit 116, the queue control unit 116 causes the queue processing time calculation unit 117 to calculate the actual transfer processing time.

  The transfer request 4 from the display control unit 110 is an access request to the same bank and the same page as the transfer request 3 from the development processing unit 109. Therefore, the processing time does not change to 6 μs, and is added to the transfer processing time 11 μs at time T3 to be 17 μs. When the transfer request 5 is issued from the encoding unit 112 at time T4, the maximum processing time for the transfer request alone is calculated by the queue processing time calculation unit 117, similarly to the time T3. When the transfer request 5 is issued from the encoding unit 112 at time T4, the queue transfer processing time is 17 μs, and when the processing time 6 μs from the transfer request 5 from the encoding unit 112 is added, the threshold exceeds 20 μs. For this reason, the queue control unit 116 prohibits the transfer request from the encoding unit 112 from being stored in the queue even if the queue is empty.

  When the data transfer from the face detection unit 108 is completed at time T5, the transfer request 3 from the development processing unit 109 having the highest priority among the transfer requests stored in the queue 115 is output to the command control unit 119. Data transfer from the development processing unit 109 to the SDRAM 107 is started. Then, the queue processing time calculation unit 117 recalculates the queue processing time excluding the transfer time of the face detection unit 108 that has been transferred. The queue control unit 116 determines whether or not to store a new transfer request to the queue 115 based on this queue processing time. Here, since the queue processing time 11 μs and the processing time 6 μs due to the transfer request 5 from the encoding unit 112 do not exceed the threshold 20 μs, they are stored in the queue. Here, reorder determination is performed as in T3.

  The transfer request 5 from the encoding unit 112 is an access to bank 1 and page 0, and is an access to a bank different from the bank 0 to which data transfer is being performed from the development processing unit 109. Therefore, before the data transfer from the development processing unit 109 to the bank 0 is completed, it is possible to issue a command according to the transfer request 5 from the encoding unit 112 to the bank 1, and accordingly, until the processing is completed. The time required is shortened. Therefore, in this case, the queue control unit 116 changes the order of the transfer request 4 and the transfer request 5 stored in the queue 115, and stores the transfer request 5 from the encoding unit 112 in a position with the highest priority. To do. The command control unit 119 issues a PRE for page inactivation for transfer processing from the development processing unit 109. At time T6, an ACT for activating a page accessed by the development processing unit 109 is issued.

  At time T7, the command control unit 119 issues a write command (hereinafter abbreviated as WR) which is a memory access command for writing. At time T8, data transfer of the development processing unit 109 is started. Since the bank 1 to be accessed by the transfer request 5 from the encoding unit 112 to be transferred next is different from the bank 0 to be accessed by the transfer request 3 from the development processing unit 109, the development processing unit 109 to the SDRAM 107 During a data transfer process to bank 0, a command according to transfer request 5 can be issued to bank 1. Therefore, the command control unit 119 issues an ACT command to the bank 1 at time T9 and issues an RD at time T10 to the bank 1 based on the transfer request 5 stored at the highest priority position in the queue 115.

  When the data transfer from the development processing unit 109 is completed at time T11, a PRE is issued by the command control unit 119 for accessing the next bank 0. Further, among the transfer requests stored in the queue 115, the transfer request 5 from the encoding unit 112 having the highest priority is output to the command control unit 119, and the transfer process is started. In order to avoid the collision, the command control unit 119 stops issuing the ACT command by the transfer request 5 until time T12.

  At times T13 to T14, the next transfer is in a different bank, similar to times T9 to T10, so that the command control unit 119 issues ACT and WR. When data transfer to the encoding unit 112 is completed at time T15, a PRE is issued by the command control unit 119 to access the next bank 1. In addition, data transfer from the SDRAM 107 to the display control unit 110 is started. When the transfer of data to the display control unit 110 is completed at time T16, a PRE is issued by the command control unit 119 to access the next bank 0.

  FIG. 5B is a diagram for explaining the queue control operation when the threshold value is switched between the effective image period and the reference data period. Here, the description of the same operation as that in FIG.

  In FIG. 5B, the threshold value for determining whether or not to store the transfer request in the queue 115 is changed from the first threshold value to the second threshold value in accordance with the threshold control flag indicated by (3) in FIG. The queue control operation when switching to the threshold is shown for the case where there is a transfer request similar to that in FIG.

  When the transfer request 5 from the encoding unit 112 is issued at time T4, the queue processing time calculation unit 117 calculates the maximum processing time for this transfer request alone, similarly to time T3. When the transfer request 5 from the encoding unit 112 is issued at time T4, the queue transfer processing time is 17 μs, and even if the processing time 6 μs according to the transfer request from the encoding unit 112 is added, the second threshold 50 μs. Not exceed. Therefore, the queue control unit 116 stores the transfer request 5 from the encoding unit 112 in the queue 115. Here, similarly to time T3, the queue control unit 116 determines reordering of each transfer request stored in the queue 115. The transfer request 5 from the encoding unit 112 is a read access to bank 1 and page 0, and is an access to a bank different from bank 0 being accessed at time T3. Therefore, the queue control unit 116 stores the newly stored transfer request 5 at the highest priority position in the queue 115.

  Here, both the transfer request 3 from the development processing unit 109 and the transfer request 4 from the display control unit 110 that are stored in the queue 115 at the time T 4 are both accessed by the transfer request 5 from the encoding unit 112. This is an access request to bank 0 different from bank 1 that is the destination. However, the transfer request 4 from the display control unit 110 and the transfer request 5 from the encoding unit 112 are both read commands (read commands). On the other hand, the transfer request 3 from the development processing unit 109 is a write command (write command). When issuing a write command following a read command, it is necessary to issue a next command after a certain time after the completion of the read command in order to prevent a collision on the data bus. On the other hand, when issuing read commands continuously, the next command can be issued without waiting for a certain time after the processing by the previous command is completed, so the read command and the write command are issued alternately. Less processing time loss. Therefore, the queue control unit 116 stores the transfer request 4 from the display control unit 110 at the second priority position in the queue 115 so that the read commands are continuous.

  The transfer request from the encoding unit 112 is bank 1 different from bank 0 during data transfer to the face detection unit 108 at time T4. Therefore, the command control unit 119 issues ACT and RD in advance to the bank 1 before the data transfer to the face detection unit 108 by the transfer request 2 is completed. When the data transfer to the face detection unit 108 is completed at time T6, the data transfer process according to the transfer request 5 from the encoding unit 112 is started. For the next transfer request 4 from the display control unit 110, the command control unit 119 issues PRE, ACT, and RD to the bank 0 at times T6 to T8.

  When the data transfer by the transfer request 5 from the encoding unit 112 is completed at time T9, the command control unit 119 issues a PRE for the next transfer of the bank 1. In addition, the data transfer process in response to the transfer request 4 from the display control unit 110 is started. When data transfer to the display control unit 110 is completed at time T11, the command control unit 119 issues PRE, ACT, and WR for data transfer according to the transfer request 4 from the next development processing unit 109 at time T11 to T14. Is done. When the data transfer from the development processing unit 109 is completed at time T16, the command control unit 119 issues a PRE for the next bank 0 transfer. In FIG. 5B, the threshold for determining whether or not to newly store a transfer request in the queue 115 is increased during a period when the real-time processing is not required, so that the transfer request from each bus master enters the queue 115. The probability of storage increases, and the number of reorder occurrences for improving access efficiency increases.

  Note that the operations shown in FIGS. 5A and 5B are only one example. For example, even when transfer requests for each process are given in an order different from that shown in FIG. The same operation is performed. In the memory control of a processing device other than the imaging device, a similar memory control configuration can be achieved for the processing performed by the processing device.

As described above, according to the second embodiment of the present invention, during a period when real-time processing is not necessary, the transfer request is increased by increasing the threshold value for determining whether or not to newly store the queue. The probability of being stored in the queue can be increased. As a result, the probability that the order of transfer requests stored in the queue is changed by the reorder process is increased, and the time required for the transfer process is shortened.
In the first and second embodiments, the value obtained by adding the time required to complete the data transfer in progress to the total time required for the data transfer by the transfer request stored in the queue 115 exceeds the threshold. In such a case, a new transfer request is not stored in the queue 115.
In addition to this, for example, the total time required for data transfer by the transfer request stored in the queue 115 is compared with the threshold, and the total time required for data transfer by the transfer request stored in the queue 115 exceeds the threshold. In this case, a new transfer request may not be stored in the queue 115.

  Although the present invention has been described in detail based on preferred embodiments thereof, the present invention is not limited to these specific embodiments, and various forms within the scope of the present invention are also included in the present invention. included. Further, each of the above-described examples is merely an example of the present invention, and the embodiments can be appropriately combined.

  For example, in the above-described embodiment, the case where the present invention is applied to an imaging apparatus such as a digital camera has been described as an example. However, this is not limited to this example. That is, the present invention can be applied to an information processing apparatus using a memory. For example, the present invention can be applied to digital data processing devices using a memory, such as an image editing device, a print data processing device of a printer device, and a data processing device for data communication.

  In addition, the function of each unit configuring the memory control device according to the above-described embodiment of the present invention is that a program stored in a RAM or ROM of a computer included in the control unit of the device to which the memory control device is applied operates. Can also be realized. This program and a computer-readable storage medium storing the program are included in the present invention.

  Examples of the storage medium for supplying the program include a flexible disk, a hard disk, an optical disk, and a magneto-optical disk. Furthermore, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD-R), and the like.

Claims (7)

A memory control device for controlling data transfer between a plurality of bus masters and a memory,
Queue means for storing data transfer requests from the plurality of bus masters including a predetermined bus master that repeatedly issues a data transfer request every predetermined period;
Means for outputting a command corresponding to the data transfer request stored in the queue means to the memory;
When the time required for data transfer in response to a data transfer request from the predetermined bus master is subtracted from the predetermined period as a threshold value , the data is stored in the queue means when the data transfer request is newly output. A memory control device comprising: control means for controlling whether or not to store the newly output data transfer request in the queue means based on a time required for data transfer by the data transfer request and the threshold value.   The control means includes a time required for data transfer according to a data transfer request stored in the queue means, a time required for transfer of data being executed, and a time required for data transfer according to the newly output data transfer request. 2. The memory control device according to claim 1, wherein the newly output data transfer request is not stored in the queue means when the sum of the two exceeds the threshold value. The queue means is capable of storing a predetermined number of data transfer requests,
2. The control unit according to claim 1, wherein when the total exceeds the threshold value, the newly output data transfer request is not stored in the queue unit even when the queue unit has an empty space. 3. The memory control device according to 2. It said predetermined bus master outputs a data transfer request for a given real-time processing, the control means, the time required for data transfer by the data transfer request from the previous SL predetermined bus master cycle of the predetermined real-time processing 2. The memory control device according to claim 1, wherein a time subtracted from the corresponding predetermined period is set as the threshold value.   The said control means determines the time required for the data transfer by the data transfer request stored in the said queue means based on the data length requested | required by the said data transfer request. Memory controller. A memory control method for controlling data transfer between a plurality of bus masters and a memory,
A queue step of storing in the queue means data transfer requests from the plurality of bus masters including a predetermined bus master that repeatedly issues a data transfer request every predetermined period;
Outputting a command corresponding to the data transfer request stored in the queue means to the memory;
When the time required for data transfer due to a transfer request from the predetermined bus master is subtracted from the predetermined period as a threshold , the data is stored in the queue means when the data transfer request is newly output. A memory control method comprising: a control step for controlling whether or not to store the newly output data transfer request in the queue means based on a time required for data transfer by the data transfer request and the threshold value. Memory,
Imaging means;
First processing means for processing the image data from the imaging means at a predetermined cycle, and repeatedly outputting a data transfer request to the memory at each predetermined cycle;
A plurality of processing means each performing processing using the image data stored in the memory;
Queue means for storing a data transfer request from the first processing means and a data transfer request to the memory from the plurality of processing means;
Means for outputting a command corresponding to the data transfer request stored in the queue means to the memory;
A time obtained by subtracting the time required for data transfer by the data transfer request from the first processing means from the predetermined period is set as a threshold value , and stored in the queue means when the data transfer request is newly output. An image pickup apparatus comprising: control means for controlling whether or not to store the newly output data transfer request in the queue means based on the time required for data transfer by the data transfer request being made and the threshold value.

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