JP6130175B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and the like.

  Patent Document 1 lists various types of memories (SRAM, DRAM, etc.).

JP 2005-196949 A

  When the power source of the semiconductor device is stopped, the data in the volatile memory is lost.

  By electrically connecting the first circuit having the volatile memory to the second circuit having the nonvolatile memory, data of the first circuit can be backed up to the second circuit.

  Even if the power of the semiconductor device is stopped, the data of the second circuit is not lost, so that the problem of data loss can be solved.

  Note that the second circuit preferably includes a transistor including a channel formation region including an oxide semiconductor and a capacitor.

  The semiconductor device preferably has a function of comparing data of the first circuit and data of the second circuit.

  For example, the backup data can be verified by comparing the data of the first circuit and the data of the second circuit.

  For example, when the semiconductor device includes a processor, it is possible to determine whether or not the branch instruction is executed by comparing the data of the first circuit and the data of the second circuit.

  When comparing the data of the first circuit and the data of the second circuit, a circuit having a function capable of comparing the data of the first circuit and the data of the second circuit (a circuit having a comparison function) Is preferably provided.

  In addition, switching between feedback loop formation and data reading can be performed using the third circuit having the first terminal, the second terminal, and the third terminal.

  For example, the third circuit has a structure in which the third terminal can be electrically connected to one of the first terminal and the second terminal.

  Further, the first terminal is electrically connected to the first circuit.

  Further, the second terminal is electrically connected to the second circuit.

  And it is set as the structure which can form a feedback loop by electrically connecting the 3rd terminal with the 1st terminal.

  The third terminal is electrically connected to the second terminal, whereby data of the second circuit can be read out to the first circuit.

  For example, the semiconductor device includes a first circuit having a volatile memory, a second circuit having a nonvolatile memory, and the first circuit is electrically connected to the second circuit. It is possible to provide a semiconductor device having a function capable of determining whether or not a branch instruction is executed by comparing the data of the second circuit and the data of the second circuit.

  For example, the semiconductor device includes a first circuit having a volatile memory, a second circuit having a memory having a transistor and a capacitor, and the transistor includes a channel formation region having an oxide semiconductor, One of a source and a drain of the transistor is electrically connected to the first circuit, and the other of the source and the drain of the transistor is electrically connected to the capacitor, and the first circuit It is possible to provide a semiconductor device having a function of determining whether or not a branch instruction is executed by comparing the data of the second circuit and the data of the second circuit.

  For example, a first circuit having a volatile memory, a second circuit having a nonvolatile memory, a third circuit having a first terminal, a second terminal, and a third terminal are provided. And the third circuit has a function of electrically connecting the third terminal to the first terminal, and the third circuit has the third terminal connected to the first terminal. The first terminal is electrically connected to the first circuit, and the second terminal is connected to the second circuit. And the third terminal is electrically connected to the first circuit and the second circuit, and in the first period, the third terminal is connected to the third circuit. By having a function of forming a feedback loop by being electrically connected to the first terminal, in the second period, The serial third terminal by connecting the second terminal and electrically, it is possible to provide a semiconductor device which is characterized in that data can be read in the second circuit to the first circuit.

  For example, the semiconductor device includes a first circuit having a volatile memory, a second circuit having a memory having a transistor and a capacitor, and has a first terminal, a second terminal, and a third terminal. The transistor includes a channel formation region including an oxide semiconductor, and one of a source and a drain of the transistor is electrically connected to the first circuit, and the transistor The other of the source and the drain is electrically connected to the capacitor, and the third circuit has a function of electrically connecting the third terminal to the first terminal. And the third circuit has a function of electrically connecting the third terminal to the second terminal, and the transistor has a channel formation region including an oxide semiconductor. And the transition One of a source and a drain of the transistor is electrically connected to the first circuit, and the other of the source and the drain of the transistor is electrically connected to the capacitor, and the first terminal Is electrically connected to the first circuit, the second terminal is electrically connected to the second circuit, and the third terminal is connected to the first circuit. A function that is electrically connected to the second circuit and that can form a feedback loop by electrically connecting the third terminal to the first terminal in the first period. And the data of the second circuit can be read out to the first circuit by electrically connecting the third terminal to the second terminal in the second period. A semiconductor device can be provided.

  By electrically connecting the first circuit having the volatile memory to the second circuit having the nonvolatile memory, the problem of data loss can be solved.

An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a semiconductor device. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit. An example of a truth table of a logic circuit.

  Embodiments will be described in detail with reference to the drawings.

  However, it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit of the invention.

  Therefore, the scope of the invention should not be construed as being limited to the description of the embodiments below.

  The same reference numerals, the same circuit symbols, the same reference numerals, the same circuit symbols, and the like may be used in common in different drawings for portions having the same function, and repeated description thereof may be omitted.

  The same reference numerals, the same circuit symbols, the same reference numerals, the same circuit symbols, and the like may be used in common in different drawings for parts having similar functions, and repeated description thereof may be omitted.

  In addition, the following embodiments can be implemented by appropriately combining several.

  Note that the circuit has a reference potential (or reference voltage).

  The reference potential (or reference voltage) may be 0V or other than 0V.

  A potential (or voltage) higher than the reference potential (or reference voltage) is set to “1 (High)”.

  A potential (or voltage) lower than the reference potential (or reference voltage) is set to “0 (Low)”.

  The opposite polarity of “0 (Low)” is “1 (High)”.

  The opposite polarity of “1 (High)” is “0 (Low)”.

  An “electrical state” is any one of a signal, voltage, potential, current, and the like.

(Embodiment 1)
The semiconductor device illustrated in FIG. 1 includes a storage unit REGx (x is a natural number).

  The storage unit REGx includes at least a circuit 10001 and a circuit 10002.

  The circuit 10001 has a volatile memory.

  The circuit 10002 includes a nonvolatile memory.

  Data can be written to the circuit 10002, data can be held, and data can be read.

  Then, by electrically connecting the circuit 10001 to the circuit 10002, for example, data of the circuit 10001 can be backed up to the circuit 10002.

  Here, it is preferable to provide a circuit 10003 as shown in FIG.

  The circuit 10003 is electrically connected to the circuit 10001.

  The circuit 10003 is electrically connected to the circuit 10002.

  The circuit 10003 has a function of comparing the data in the circuit 10001 and the data in the circuit 10002.

  By including the circuit 10003, for example, backup data can be verified.

  By including the circuit 10003, for example, it can be determined whether or not a branch instruction is executed.

  The circuit 10001 can output DATAx (x is a natural number).

  DATAx is data stored in the circuit 10001.

  The circuit 10003 can output Px (x is a natural number).

  Px is a comparison result between the data of the circuit 10001 and the data of the circuit 10002.

  Here, determination of whether or not a branch instruction is executed will be described.

  2 and 3 are examples of register files.

  2 and 3 each have a register file 11000.

  Each of the register files 11000 includes storage units REG1 to REGn (n is a natural number).

  As the storage unit REG1 to the storage unit REGn, for example, the configuration of the storage unit REGx in FIG. 1 or the like can be applied.

  The circuit 12000 has a function of determining the output of the register file 11000 and outputting a BRANCH (branch instruction (branch control signal)).

  FIG. 2 is an example in which DATAj output from the storage unit REGj and DATAk output from the storage unit REGk are compared using the circuit 12000, and then BRANCH is output (j and k are natural numbers).

  DATAj and DATAk correspond to, for example, DATAx in FIG.

  FIG. 3 shows an example in which Pj output from the storage unit REGj is processed in the circuit 12000 and BRANCH is output.

  Note that Pj corresponds to, for example, Px in FIG.

  In the case of FIG. 2, two storage units (a storage unit REGj and a storage unit REGk) are used when determining whether or not a branch instruction is executed.

  In the case of FIG. 3, one storage unit (storage unit REGj) is used when determining whether or not a branch instruction is executed.

  In the case of FIG. 2, it is necessary to use the storage unit REGk as a comparison target of the storage unit REGj.

  On the other hand, in the case of FIG. 3, the storage unit REGk can be used for another purpose.

  Therefore, it can be said that FIG. 3 has a configuration in which the register file 11000 can be used more efficiently than FIG.

  In other words, the register file 11000 can be used efficiently by using the circuit 10002 that can be used for backup also in determining whether or not a branch instruction is executed.

  Note that when backup is performed, the data in the circuit 10001 and the data in the circuit 10002 are set to be the same.

  Further, as a result of verifying the backup data, when the data of the circuit 10001 and the data of the circuit 10002 are different, processing is performed so that the data of the circuit 10001 and the data of the circuit 10002 are the same.

  At this time, the data of the circuit 10001 may be written into the circuit 10002, or the data of the circuit 10002 may be read into the circuit 10001.

  When determining whether or not a branch instruction is executed, the data in the circuit 10001 and the data in the circuit 10002 are in the same state (first state), or the data in the circuit 10001 and the data in the circuit 10002 are different. It is in a state (second state).

  Note that the branch instruction is executed in one of the first state and the second state, and the branch instruction is not executed in the other of the first state and the second state.

  That is, it is possible to execute a branch instruction in the first state and not execute a branch instruction in the second state.

  It is also possible to execute a branch instruction in the second state and not execute a branch instruction in the first state.

  Note that although FIG. 1 illustrates an example in which Px is output from the circuit 10003, a configuration in which Px is output from the circuit 10001 may be used (for example, FIGS. 21 to 28).

  Here, any volatile memory may be used.

  For example, a feedback loop memory, a volatile charge storage type memory, or the like can be used.

  The feedback loop memory is a memory that can form a feedback loop by combining a plurality of logic circuits.

  For example, one output terminal of two inverters and the other input terminal of two inverters are electrically connected, and one input terminal of two inverters and the other output terminal of two inverters are electrically connected However, the feedback loop memory is not limited.

  A volatile charge storage type memory is a volatile memory that stores charges in a capacitor element or the like.

  For example, a volatile charge storage memory in which a capacitor is electrically connected to one of a source and a drain of a transistor can be used, but the invention is not limited to this.

  Any nonvolatile memory may be used.

  The volatile memory preferably has both a practical N-channel transistor and a practical P-channel transistor.

  Therefore, the transistor included in the volatile memory preferably includes a silicon semiconductor.

  Any nonvolatile memory may be used.

  For example, a nonvolatile charge storage memory in which a capacitor is electrically connected to one of a source and a drain of a transistor including a channel formation region including an oxide semiconductor can be used, but the invention is not limited to this.

  Here, a transistor including a channel formation region including an oxide semiconductor has extremely low off-state current as compared to a transistor including a channel formation region including a silicon semiconductor.

  Therefore, a charge storage memory including a transistor having a channel formation region including a silicon semiconductor is volatile, and a charge storage memory including a transistor including a channel formation region including an oxide semiconductor is nonvolatile.

  Other nonvolatile memories include, but are not limited to, a floating gate memory, a magnetoresistive memory, a resistance change type memory, and a ferroelectric memory.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 2)

  An example of the storage unit will be described with reference to FIGS.

  FIG. 11 shows an example in which (B) of FIGS. 5 to 10 is applied.

  If necessary, the reader can read the contents of the present embodiment while referring to FIG. 11 to deepen understanding.

  FIG. 4 illustrates an example of a semiconductor device including the circuits 1001 to 1006 and the like.

  The circuit 1001 and the circuit 1002 correspond to, for example, the circuit 10001 in FIG.

  The circuit 1004 and the circuit 1005 correspond to, for example, the circuit 10002 in FIG.

  The circuit 1006 corresponds to, for example, the circuit 10003 in FIG.

  Hereinafter, the connection relationship will be described, each terminal will be described, and the circuits 1001 to 1006 will be described.

<Connections>
The circuit 1001 includes a terminal N1, a terminal N2, a terminal N3, and the like.

  The circuit 1002 includes a terminal N5, a terminal N6, a terminal N23, and the like.

  The circuit 1003 includes a terminal N8, a terminal N9, a terminal N10, a terminal N11, and the like.

  The circuit 1004 includes a terminal N17, a terminal N18, a terminal N19, and the like.

  The circuit 1005 includes a terminal N20, a terminal N21, a terminal N22, and the like.

  The circuit 1006 includes a terminal N13, a terminal N14, a terminal N15, and the like.

  The terminal IN and the terminal N1 are electrically connected.

  The terminal N3, the node N4, the terminal N5, the terminal N11, the node N12, and the terminal N17 are electrically connected.

  The terminal OUT, the terminal N6, the node N7, and the terminal N13 are electrically connected.

  The terminal OUTB and the terminal N23 are electrically connected.

  The terminal S1 and the terminal N8 are electrically connected.

  Terminal P and terminal N15 are electrically connected.

  The terminal N10, the terminal N14, the node N16, and the terminal N20 are electrically connected.

  Terminal W and terminal N18 are electrically connected.

  Terminal N19 and terminal N21 are electrically connected.

  The terminal S2 and the terminal N22 are electrically connected.

<Each terminal>
The terminal IN can function as an input terminal.

  The terminal OUT can function as an output terminal.

  The terminal OUTB can function as an output terminal.

  The terminal OUTB outputs a signal having a polarity opposite to that of the terminal OUT.

  For example, DATAx in FIG. 1 can be output from the terminal OUT or the terminal OUTB.

  When only one of the terminal OUT and the terminal OUTB is used, the other of the terminal OUT and the terminal OUTB is not necessarily provided.

  The terminal S1 can function as a control terminal.

  For example, by setting the terminal S1 to a predetermined electrical state, the terminal N11 can be electrically connected to one of the terminal N9 or the terminal N10.

  The terminal P can function as an output terminal.

  For example, Px in FIG. 1 can be output from the terminal P.

  The terminal W can function as a control terminal.

  For example, the electrical state of the node N4 can be written to the circuit 1004 by setting the terminal W to a predetermined electrical state.

  The terminal S2 can function as a control terminal.

  For example, the electrical state written in the circuit 1004 can be read by setting the terminal S2 to a predetermined electrical state.

<Circuit 1001>
FIG. 5A illustrates an example of the circuit 1001.

  FIG. 5B is an example of FIG.

  FIG. 5A includes a circuit element 101, a circuit element 102, and a circuit element 103.

  The terminal IN and the input terminal IN1 (terminal N1) of the circuit element 101 are electrically connected.

  The output terminal OUT1 of the circuit element 101, the input terminal IN2 of the circuit element 102, and the output terminal OUT3 of the circuit element 103 are electrically connected.

  The output terminal OUT2 (terminal N2) of the circuit element 102 and the terminal N9 are electrically connected.

  The input terminal IN3 (terminal N3), the node N4, the terminal N5, and the node N12 of the circuit element 103 are electrically connected.

  For example, the circuit element 101 has a function of outputting a signal or the like input to the input terminal IN1 from the output terminal OUT1 without inverting the polarity.

  The circuit element 101 has a function capable of interrupting transmission of a signal or the like between the input terminal IN1 and the output terminal OUT1, for example.

  Examples of the circuit element 101 include, but are not limited to, a transistor and a transmission gate.

  FIG. 5B shows an example in which a transmission gate is applied as the circuit element 101.

  A terminal C2 is electrically connected to the first control terminal of the transmission gate.

  A terminal C1 is electrically connected to the second control terminal of the transmission gate.

  The polarity of the terminal C2 is opposite to that of the terminal C1.

  When the terminal C2 is “1 (High)”, the transmission gate can output the signal or the like input to the input terminal from the output terminal without inverting the polarity.

  Further, when the terminal C2 is “0 (Low)”, the input terminal and the output terminal of the transmission gate become non-conductive.

  The circuit element 102 has a function of, for example, outputting a signal or the like input to the input terminal IN2 from the output terminal OUT2 by inverting the polarity.

  For example, an inverter, NAND, NOR, a clocked inverter, a clocked NAND, a clocked NOR, or the like can be used as the circuit element 102, but is not limited thereto.

  Note that a reset function can be added by using NAND, NOR, clocked NAND, clocked NOR, or the like.

  For example, when a 2-input NAND is used, by setting one of the two input terminals of the NAND to “1 (High)”, the polarity of the signal or the like input to the other of the two input terminals of the NAND is reversed. Can be output from the output terminal.

  Then, by setting one of the two input terminals of the NAND to “0 (Low)”, the signal output from the output terminal becomes “1 (High)”.

  In other words, the signal or the like can be reset by setting one of the two input terminals of the NAND to “0 (Low)”.

  For example, when 2-input NOR is used, the polarity of the signal or the like input to the other of the two input terminals of NOR is reversed by setting one of the two input terminals of NOR to “0 (Low)”. Can be output from the output terminal.

  Then, by setting one of the two NOR input terminals to “1 (High)”, the signal output from the output terminal becomes “0 (Low)”.

  That is, by setting one of the two NOR input terminals to “1 (High)”, it is possible to reset a signal or the like.

  Therefore, when it is desired to set the output to “1 (High)” after resetting, for example, NAND or the like may be used.

  Further, when resetting the output to be “0 (Low)”, for example, NOR may be used.

  FIG. 5B shows an example in which NAND is applied as the circuit element 102.

  The terminal R and one of the two terminals of NAND are electrically connected.

  The other of the two terminals of the NAND corresponds to the input terminal IN2 in FIG.

  The terminal R can function as a control terminal.

  For example, the terminal R is normally set to “1 (High)”.

  Then, by setting the terminal R to “0 (Low)”, the signal or the like can be reset.

  For example, the circuit element 103 has a function of inverting the polarity of a signal input to the input terminal IN3 and outputting the signal from the output terminal OUT3.

  The circuit element 103 has a function capable of blocking transmission of a signal or the like between the input terminal IN3 and the output terminal OUT3, for example.

  As the circuit element 103, for example, a clocked inverter, a clocked NAND, a clocked NOR, or the like can be used, but the circuit element 103 is not limited.

  Note that a signal or the like can be reset by using a clocked NAND, a clocked NOR, or the like.

  FIG. 5B shows an example in which a clocked inverter is applied as the circuit element 103.

  A terminal C1 is electrically connected to the first control terminal of the clocked inverter.

  A terminal C2 is electrically connected to the second control terminal of the clocked inverter.

  The polarity of the terminal C2 is opposite to that of the terminal C1.

  When the terminal C1 is “1 (High)”, the clocked inverter can invert the polarity of the signal or the like input to the input terminal and output it from the output terminal.

  When the terminal C1 is “0 (Low)”, the output terminal of the clocked inverter becomes high impedance.

  An example of operation of the circuit 1001 will be described.

  A state other than high impedance is defined as “active” and will be described below.

  As a premise, it is assumed that the terminal N9 and the node N12 are electrically connected.

  For example, in the period A, the circuit element 101 is activated and the output terminal of the circuit element 103 is set to high impedance.

  Since the circuit element 101 and the circuit element 102 are active, the polarity of the terminal IN is inverted and transmitted to the terminal N9.

  Since the terminal N9 and the node N12 are electrically connected, as a result, a polarity opposite to the polarity of the terminal IN is transmitted to the node N4.

  Next, for example, in the period B, when the circuit element 103 is activated and the output terminal of the circuit element 101 is set to high impedance, a feedback loop including the circuit element 102 and the circuit element 103 is formed.

  Accordingly, as a result, the signal or the like (data) input to the terminal IN in the period A is stored in the feedback loop in the period B.

<Circuit 1002>
FIG. 6A illustrates an example of the circuit 1002.

  FIG. 6B is an example of FIG.

  FIG. 6A includes a circuit element 104, a circuit element 105, and a circuit element 106.

  The input terminal IN4 (terminal N5), the terminal N3, the node N4, and the node N12 of the circuit element 104 are electrically connected.

  The output terminal OUT4 of the circuit element 104, the input terminal IN5 of the circuit element 105, the output terminal OUT6 of the circuit element 106, the terminal N23, and the terminal OUTB are electrically connected.

  The output terminal OUT5 (terminal N6) of the circuit element 105, the input terminal IN6 of the circuit element 106, the node N7, the terminal N13, and the terminal OUT are electrically connected.

  The circuit element 104 has a function of outputting, for example, a signal input to the input terminal IN4 from the output terminal OUT4 without inverting the polarity.

  The circuit element 104 has a function capable of interrupting transmission of a signal or the like between the input terminal IN4 and the output terminal OUT4, for example.

  Examples of the circuit element 104 include, but are not limited to, a transistor and a transmission gate.

  FIG. 6B shows an example in which a transmission gate is applied as the circuit element 104.

  A terminal C1 is electrically connected to the first control terminal of the transmission gate.

  A terminal C2 is electrically connected to the second control terminal of the transmission gate.

  The polarity of the terminal C2 is opposite to that of the terminal C1.

  When the terminal C1 is “1 (High)”, the transmission gate can output the signal or the like input to the input terminal from the output terminal without inverting the polarity.

  Further, when the terminal C1 is “0 (Low)”, the transmission gate is non-conductive between the input terminal and the output terminal.

  For example, the circuit element 105 has a function of inverting the polarity of a signal or the like input to the input terminal IN5 and outputting it from the output terminal OUT5.

  For example, an inverter, NAND, NOR, a clocked inverter, a clocked NAND, a clocked NOR, or the like can be used as the circuit element 105, but is not limited thereto.

  Note that a reset function can be added by using NAND, NOR, clocked NAND, clocked NOR, or the like.

  FIG. 6B shows an example in which an inverter is applied as the circuit element 105.

  The circuit element 106 has a function of, for example, outputting a signal or the like input to the input terminal IN6 from the output terminal OUT6 by inverting the polarity.

  The circuit element 106 has a function capable of interrupting transmission of a signal or the like between the input terminal IN6 and the output terminal OUT6, for example.

  As the circuit element 106, for example, a clocked inverter, a clocked NAND, a clocked NOR, or the like can be used, but the circuit element 106 is not limited.

  Note that a signal or the like can be reset by using a clocked NAND, a clocked NOR, or the like.

  FIG. 6B shows an example in which a clocked NAND is applied as the circuit element 106.

  A terminal C2 is electrically connected to the first control terminal of the clocked NAND.

  The terminal C1 is electrically connected to the second control terminal of the clocked NAND.

  The polarity of the terminal C2 is opposite to that of the terminal C1.

  When the terminal C2 is “1 (High)”, the clocked NAND can invert the polarity of the signal or the like input to the input terminal and output the signal from the output terminal.

  When the terminal C2 is “0 (Low)”, the output terminal of the clocked NAND becomes high impedance.

  An example of operation of the circuit 1002 will be described.

  A state other than high impedance is defined as “active” and will be described below.

  First, for example, in the period C, the circuit element 104 is activated and the output terminal of the circuit element 106 is set to high impedance.

  Since the circuit element 104 and the circuit element 105 are active, the polarity of the node N4 is inverted and transmitted to the terminal N6.

  As a result, the polarity opposite to that of the node N4 is transmitted to the terminal N6.

  Next, for example, in the period D, when the circuit element 105 is activated and the output terminal of the circuit element 104 is set to high impedance, a feedback loop including the circuit element 105 and the circuit element 106 is formed.

  Therefore, as a result, the signal or the like (data) input to the node N4 in the period C is stored in the feedback loop in the period D.

  By the way, for convenience, the period C is described as a period different from the period B.

  For convenience, the period D is described as a period different from the period A.

  On the other hand, by alternately repeating the period A and the period B, the circuit 10001 including the circuit 1001 and the circuit 1002 can operate, so that the period C is the same as the period B and the period D is the period A. The same period can be used.

<Circuit 1003>
FIG. 7A illustrates an example of the circuit 1003.

  FIG. 7B is an example of FIG.

  FIG. 7A includes a circuit element 107.

  The input terminal IN7A (terminal N9) of the circuit element 107 and the terminal N2 are electrically connected.

  The input terminal IN7B (terminal N10) of the circuit element 107 and the node N16 are electrically connected.

  The control terminal IN7S (terminal N8) of the circuit element 107 and the terminal S1 are electrically connected.

  The output terminal OUT7 (terminal N11) of the circuit element 107 and the node N12 are electrically connected.

  The circuit element 107 has a function capable of electrically connecting the terminal N11 to one of the terminal N9 or the terminal N10, for example, by setting the terminal S1 to a predetermined electrical state.

  For example, when the terminal S1 is “1 (High)” or “0 (Low)”, the terminal N10 and the terminal N11 can be electrically connected, and the terminal S1 is “1 (High)” or At the other time of “0 (Low)”, the terminal N9 and the terminal N11 can be electrically connected.

  Examples of the circuit element 107 include, but are not limited to, a plurality of transistors and a multiplexer.

  FIG. 7B shows an example in which a multiplexer is applied as the circuit element 107.

  An example of operation of the circuit 1003 is described.

  For example, when data written in the circuit 1004 is read, the terminal S1 is set to one of “1 (High)” and “0 (Low)”, and the terminal N10 and the terminal N11 are electrically connected.

  For example, except when reading data written in the circuit 1004, the terminal S1 is set to the other of “1 (High)” or “0 (Low)”, and the terminal N9 and the terminal N11 are electrically connected.

<Circuit 1004>
FIG. 8A illustrates an example of the circuit 1004.

  FIG. 8B is an example of FIG.

  FIG. 8A includes a circuit element 108, a circuit element 109, and a circuit element 110.

  The input terminal IN8A (terminal N17) of the circuit element 108 and the node N12 are electrically connected.

  The input terminal IN8B (terminal N18) of the circuit element 108 and the terminal W are electrically connected.

  The output terminal OUT8 of the circuit element 108, the input terminal IN9 of the circuit element 109, the input terminal IN10 of the circuit element 110, and the node N26 are electrically connected.

  For example, the electrical state of the node N26 corresponds to the data of the circuit 1004.

  The output terminal OUT10 (terminal N19) of the circuit element 110 and the terminal N21 are electrically connected.

  The circuit element 108 has a function of outputting, for example, a signal input to the input terminal IN8A from the output terminal OUT8 without inverting the polarity.

  The circuit element 108 has a function capable of blocking transmission of a signal or the like between the input terminal IN8A and the output terminal OUT8, for example.

  Note that the terminal W can control conduction between the input terminal IN8A and the output terminal OUT8.

  If the off-state current of the circuit element 108 (for example, a transistor) is extremely small, leakage between the input terminal IN8A and the output terminal OUT8 can be prevented with the power supply of the semiconductor device stopped.

  Therefore, the circuit element 108 is preferably a transistor (OS-FET) including a channel formation region including an oxide semiconductor.

  The OS-FET is preferably a normally-off type.

  Note that when the circuit element 109 is a floating gate memory, a magnetoresistive memory, a resistance change memory, a ferroelectric memory, or the like, for example, a transistor, a transmission gate, or the like can be applied as the circuit element 108. Not.

  FIG. 8B shows an example in which an N-channel OS-FET is applied as the circuit element 108.

  One of the source or the drain of the OS-FET and the node N12 are electrically connected.

  The other of the source and the drain of the OS-FET, the input terminal IN9 of the circuit element 109, the input terminal IN10 of the circuit element 110, and the node N26 are electrically connected.

  By having the OS-FET, it can be said that the electrical state of the node N26 can be maintained even when the power supply is stopped.

  The gate of the OS-FET and the terminal W are electrically connected.

  The circuit element 109 has a function capable of storing the electrical state of the output terminal OUT8, for example.

  As the circuit element 109, for example, a capacitor, a floating gate memory, a magnetoresistive memory, a resistance change memory, a ferroelectric memory, or the like can be used, but the circuit element 109 is not limited.

  When a capacitor is used as the circuit element 109, it is preferable to use an OS-FET as the circuit element 108.

  FIG. 8B illustrates an example in which a capacitor is applied as the circuit element 109.

  The output terminal OUT8 of the circuit element 108, one electrode of the capacitor, the input terminal IN10 of the circuit element 110, and the node N26 are electrically connected.

  The other electrode of the capacitor and the terminal Vss are electrically connected.

  The terminal Vss has a function of transmitting (or fixing) “0 (Low)”.

  For example, the circuit element 110 has a function of changing the electrical state of the terminal N21 in accordance with the electrical state of the node N26.

  For example, when the node N26 is “1 (High)”, the terminal N21 is in the first electrical state, and when the node N26 is “0 (Low)”, the terminal N21 is in the second electrical state. be able to.

  The first electrical state and the second electrical state are different.

  The first electrical state and the second electrical state can be selected from “1 (High)”, “0 (Low)”, a floating state, and the like, but are not limited thereto.

  As the circuit element 110, for example, a transistor, a transmission gate, an inverter, a NAND, a NOR, a clocked inverter, a clocked NAND, a clocked NOR, a multiplexer, or the like can be used, but is not limited.

  FIG. 8B illustrates an example in which an N-channel transistor is used as the circuit element 110.

  One of a source and a drain of the N-channel transistor and the terminal N21 are electrically connected.

  The other of the source and the drain of the N-channel transistor and the terminal Vss are electrically connected.

  The node N26 and the gate of the N-channel transistor are electrically connected.

  Again, in FIG. 8, for example, when the node N26 is “1 (High)”, the terminal N21 is set to the first electrical state, and when the node N26 is “0 (Low)”, the terminal N21 is set. Can be in the second electrical state.

  In FIG. 8B, the terminal N21 is “0 (Low)” (conductive with the terminal Vss) in the first electrical state, and the terminal N21 is in the floating state (terminal Vss) in the second electrical state. And non-conduction).

  In FIG. 8B, an N-channel transistor may be replaced with a P-channel transistor.

  In the case of using a P-channel transistor, the other of the source and the drain is electrically connected to the terminal Vdd instead of the terminal Vss.

  Further, the N-channel transistor in FIG. 9 is replaced with a P-channel transistor, the P-channel transistor in FIG. 9 is replaced with an N-channel transistor, and the terminal Vdd in FIG. 9 is replaced with a terminal Vss.

  Note that as the N-channel transistor or the P-channel transistor, a transistor including a channel formation region including a silicon semiconductor can be used.

  An example of operation of the circuit 1004 will be described.

  A state other than high impedance is defined as “active” and will be described below.

  When a write operation to the circuit element 109 is performed, the circuit element 108 is activated by setting the terminal W to a predetermined electrical state.

  Then, the electrical state of the node N12 is written to the circuit element 109, and the node N26 enters a predetermined electrical state.

  Note that the writing operation to the circuit element 109 may be performed during the period A or during the period B.

  That is, a period E that is a writing period may exist during the period A, and a period E that is a writing period may exist during the period B.

  Except when writing operation to the circuit element 109 is performed, the terminal W is set to a predetermined electrical state, and the output terminal of the circuit element 108 is set to high impedance.

  By performing the operation as described above, the electrical state of the terminal N21 is determined according to the electrical state of the node N26.

<Circuit 1005>
FIG. 9A illustrates an example of the circuit 1005.

  FIG. 9B is an example of FIG.

  FIG. 9A includes a circuit element 111, a circuit element 112, and a circuit element 113.

  The terminal S2 and the input terminal IN11A (terminal N22) of the circuit element 111 are electrically connected.

  The output terminal OUT11 of the circuit element 111, the input terminal IN12 of the circuit element 112, the input terminal IN13 of the circuit element 113, and the node N27 are electrically connected.

  The output terminal OUT12 (terminal N20) of the circuit element 112, the node N16, and the terminal N14 are electrically connected.

  The circuit element 111 has a function capable of changing the electrical state of the output terminal OUT11 by, for example, setting the terminal S2 to a predetermined electrical state.

  For example, the output terminal OUT11 can be fixed to a predetermined electrical state according to the electrical state of the terminal S2.

  That is, when the terminal S2 is one of “1 (High)” and “0 (Low)”, the output terminal OUT11 can be precharged.

  For example, when the terminal S1 is the other of “1 (High)” or “0 (Low)”, the input terminal IN11B and the output terminal OUT11 can be electrically connected.

  Examples of the circuit element 111 include, but are not limited to, a plurality of transistors and a multiplexer.

  FIG. 9B illustrates an example in which a plurality of transistors (an N-channel transistor and a P-channel transistor) are applied as the circuit element 111.

  One of a source and a drain of the N-channel transistor, one of a source and a drain of the P-channel transistor, the input terminal IN12 of the circuit element 112, the input terminal IN13 of the circuit element 113, and the node N27 are electrically It is connected.

  The other of the source and the drain of the N-channel transistor and the terminal N19 are electrically connected.

  The gate of the N-channel transistor, the gate of the P-channel transistor, and the terminal S2 are electrically connected.

  The other of the source and the drain of the P-channel transistor is electrically connected to the terminal Vdd.

  Note that the terminal Vdd has a function of transmitting (or fixing) “1 (High)”.

  In FIG. 9B, when the terminal S2 is “0 (Low)”, the node N27 can be precharged by electrically connecting the terminal Vdd and the node N27.

  In FIG. 9B, when the terminal S2 is “1 (High)”, the terminal N19 and the node N27 can be electrically connected.

  Here, the terminal N19 can be set to “0 (Low)” or in a floating state.

  First, the node N27 is precharged in advance (fixed to “1 (High)”).

  For example, when the terminal S2 is set to “1 (High)” and the terminal N19 and the node N27 are electrically connected, if the terminal N19 is “0 (Low)”, the node N27 is “0 (Low)”. To be rewritten.

  For example, when the terminal S2 is set to “1 (High)” and the terminal N19 and the node N27 are electrically connected and the terminal N19 is in a floating state, the polarity of the node N27 does not change and “1 (High)”. Will remain.

  The circuit element 112 has a function of, for example, inverting the polarity and outputting the signal input to the input terminal IN12 from the output terminal OUT12.

  For example, an inverter, NAND, NOR, a clocked inverter, a clocked NAND, a clocked NOR, or the like can be used as the circuit element 112, but is not limited thereto.

  Note that a reset function can be added by using NAND, NOR, clocked NAND, clocked NOR, or the like.

  In addition, by using a clocked inverter, a clocked NAND, a clocked NOR, etc., the output terminal of the circuit element 112 is set to high impedance in a state in which a read operation (a backup data restoration operation, data comparison operation, etc.) is not performed can do.

  Therefore, the output of the circuit 1005 can be stopped in a state where the reading operation is not performed.

  FIG. 9B shows an example in which an inverter is applied as the circuit element 112.

  The input terminal of the inverter and the node N27 are electrically connected.

  The output terminal of the inverter, the node N16, and the terminal N14 are electrically connected.

  For example, a capacitor element or the like can be used as the circuit element 113, but the circuit element 113 is not limited thereto.

  Note that the circuit element 113 is not an essential component, but it is preferable to provide the circuit element 113 in order to increase the holding time.

  FIG. 9B illustrates an example in which a capacitor is applied as the circuit element 113.

  One electrode of the capacitor and the node N27 are electrically connected.

  The other electrode of the capacitor and the terminal Vss are electrically connected.

  The terminal Vss has a function of transmitting (or fixing) “0 (Low)”.

  An example of operation of the circuit 1005 will be described.

  With the circuit 1005, data written to the circuit 1004 can be read.

  First, the terminal S2 is set to the first electrical state, the terminal Vdd and the node N27 are electrically connected, and the node N27 is precharged.

  Next, the terminal S2 is set to the second electrical state, and the terminal N19 and the node N27 are electrically connected.

  For example, if the terminal N19 is in a floating state or “1 (High)”, the electrical state of the node N27 does not change.

  For example, if the terminal N19 is “0 (Low)”, the node N27 is rewritten to “0 (Low)”.

  The polarity of the node N16 is opposite to that of the node N27.

  Further, the polarity of the node N27 is opposite to the polarity of the node N26 in FIG.

  Therefore, as a result, the polarity of the node N16 is the same as the polarity of the node N26 in FIG.

<Circuit 1006>
FIG. 10A illustrates an example of the circuit 1006.

  FIG. 10B is an example of FIG.

  FIG. 10A includes a circuit element 114 and a circuit element 115.

  The input terminal IN14 (terminal N14) of the circuit element 114, the node N16, and the terminal N20 are electrically connected.

  The output terminal OUT14 of the circuit element 114 and the input terminal IN15B of the circuit element 115 are electrically connected.

  The input terminal IN15A (terminal N13), the terminal N6, the node N7, and the terminal OUT of the circuit element 115 are electrically connected.

  The output terminal OUT15 (terminal N15) of the circuit element 115 and the terminal P are electrically connected.

  The circuit element 114 has a function of, for example, outputting a signal or the like input to the input terminal IN14 from the output terminal OUT14 by inverting the polarity.

  For example, an inverter, NAND, NOR, a clocked inverter, a clocked NAND, a clocked NOR, or the like can be used as the circuit element 114, but is not limited thereto.

  Note that a reset function can be added by using NAND, NOR, clocked NAND, clocked NOR, or the like.

  FIG. 10B shows an example in which an inverter is applied as the circuit element 114.

  The input terminal of the inverter, the node N16, and the terminal N20 are electrically connected.

  The output terminal of the inverter and the input terminal IN15B of the circuit element 115 are electrically connected.

  The circuit element 115 has a function of, for example, comparing the electrical state of the terminal OUT with the electrical state of the output terminal OUT14 of the circuit element 114.

  Note that the polarity of the terminal OUT is opposite to that of the node N4 in FIG.

  Further, the polarity of the output terminal OUT14 of the circuit element 114 is opposite to the polarity of the node N26 in FIG.

  Therefore, in the case of the state like the period B described above, it can be said that the electrical state of the node N4 is compared with the electrical state of the node N26.

  For example, the circuit element 115 may have a function of fixing the electrical state of the terminal P when the comparison operation is not performed.

  For example, the circuit element 115 may have a function capable of setting the output terminal to high impedance when the comparison operation is not performed.

  First, the comparison circuit in the circuit element 115 preferably has, for example, XOR, XNOR, clocked XOR, clocked XNOR, etc., but is not limited thereto.

  Note that by using clocked XOR, clocked XNOR, or the like, it is possible to have a function of making the output terminal high impedance.

  Further, in order to add a function of fixing the electrical state of the terminal P, for example, AND, OR, NAND, NOR, clocked AND, clocked OR, clocked NAND, clocked NOR are connected to the output terminal of the comparison circuit. Etc. are preferably connected, but not limited thereto.

  By using a clocked AND, a clocked OR, a clocked NAND, a clocked NOR, or the like, it is possible to have a function capable of setting the output terminal to high impedance.

  For example, a transistor, a transmission gate, a clocked inverter, or the like can be electrically connected to the output terminal of the comparison circuit.

  FIG. 10B illustrates an example in which XOR and AND are used as the circuit element 115.

  XOR is a comparison circuit.

  Further, when XNOR, clocked XOR, clocked XNOR, or the like is used as the comparison circuit, the connection relationship can be the same as that in FIG.

  AND is a circuit for fixing the electrical state of the terminal P.

  In addition, when OR, NAND, NOR, clocked AND, clocked OR, clocked NAND, clocked NOR, or the like is used instead of AND, the connection relationship can be the same as in FIG.

  The first XOR input terminal (terminal N13), the terminal N6, the node N7, and the terminal OUT are electrically connected.

  The second input terminal of XOR and the output terminal OUT14 of the circuit element 114 are electrically connected.

  The output terminal of XOR and the first input terminal of AND are electrically connected.

  The terminal P and the AND output terminal (terminal N15) are electrically connected.

  The second input terminal of the AND and the terminal COMP are electrically connected.

  The terminal COMP is a control terminal, for example.

  By setting the terminal COMP to one of “1 (High)” or “0 (Low)”, the output of the terminal P can be fixed.

  Comparison can be performed by setting the terminal COMP to the other of “1 (High)” or “0 (Low)”.

  In the case of FIG. 10B, since the terminal COMP is electrically connected to the second input terminal of the AND, the output of the terminal P can be fixed when the terminal COMP is “0 (Low)”. .

  In the case of FIG. 10B, since the terminal COMP is electrically connected to the second input terminal of the AND, the comparison can be performed when the terminal COMP is “1 (High)”.

  An example of operation of the circuit 1006 will be described.

  For example, when the terminal COMP is not provided, the electrical state of the terminal P can be changed according to the electrical state of the terminal OUT.

  For example, when the terminal COMP is provided, the electrical state of the terminal P can be changed according to the electrical state of the terminal OUT by setting the terminal COMP to the first electrical state.

  For example, when the terminal COMP is provided, the electrical state of the terminal P can be fixed regardless of the electrical state of the terminal OUT by setting the terminal COMP to the second electrical state.

  For example, when the output terminal of the circuit element 115 is set to high impedance, the terminal P can be in a floating state.

  Although the circuit 1006 is not an essential component, it can be said that the circuit 1006 is preferable because various functions can be added to the semiconductor device.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 3)
4 to 11, the data comparison operation is performed using the electrical state of the terminal OUTB. However, the data comparison operation may be performed using the electrical state of the terminal OUTB.

  For example, FIG. 12 is an example in which the terminal N13 and the terminal OUTB are electrically connected in FIG.

  In FIG. 12, the terminal OUTB, the terminal N13, the terminal N23, and the terminal N24 are electrically connected.

  FIG. 13 is an example of the circuit 1006 in FIG.

  FIG. 13 corresponds to, for example, a configuration in which the circuit element 114 is deleted from FIG.

  The polarity of the terminal OUTB is opposite to that of the terminal OUT.

  Therefore, since it is not necessary to reverse the polarity using the circuit element 114, the circuit element 114 is deleted.

  An example of FIG. 12 is shown in FIG.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 4)
Although FIG. 4 illustrates an example in which the output of the circuit 1005 is input to the circuit 1006, data of the circuit 1004 can be input to the circuit 1006.

  For example, FIG. 15 is an example in which the terminal N14 in FIG. 4 is electrically connected to the node N26 in the circuit 1004 instead of the node N16.

  Further, by adopting the configuration as shown in FIG. 15, the terminal S1 and the terminal S2 in FIG.

  In FIG. 15, as shown in FIG. 4, the terminal S1 and the terminal S2 may be provided separately.

  FIG. 16 is an example of the circuit 1003 in FIG.

  Although FIG. 16 is basically the same as FIG. 7 and the like, the control terminal IN7S is electrically connected to the terminal S and the terminal N25 as the terminal S1 and the terminal S2 are made common and used as the terminal S. Yes.

  FIG. 17 is an example of the circuit 1004 in FIG.

  FIG. 17 is basically the same as FIG. 8 or the like, but the node N26 and the terminal N14 are electrically connected.

  FIG. 18 is an example of the circuit 1005 in FIG.

  Although FIG. 18 is basically the same as FIG. 9 and the like, the input terminal IN11A is electrically connected to the terminal S as the terminal S1 and the terminal S2 are commonly used as the terminal S.

  In FIG. 9, the output terminal OUT12 is electrically connected to the terminal N14. However, in FIG. 18, the output terminal OUT12 is electrically separated from the terminal N14.

  FIG. 19 is an example of the circuit 1006 in FIG.

  The circuit element 115 in FIG. 19 is basically the same as that in FIG.

  19 is different from FIG. 10 in that a circuit element 116 and a circuit element 117 are provided instead of the circuit element 114.

  The circuit element 116 is a circuit element similar to a circuit element in which the circuit element 110 in FIG. 8 and the circuit element 111 in FIG. 9 are combined.

  That is, the input terminal IN16A of the circuit element 116 and the terminal PRE are electrically connected.

  The terminal PRE is, for example, a control terminal.

  When the terminal PRE is in the first electrical state, OUT16 of the circuit element 116 is precharged.

  When the terminal PRE is in the second electrical state, the electrical state of OUT16 of the circuit element 116 is maintained or rewritten.

  When the terminal PRE is in the second electrical state, the data comparison operation is performed in the circuit element 115.

  Therefore, it can be said that the terminal PRE is a terminal for controlling the data comparison operation.

  Further, the node N26 and the input terminal IN16B (terminal N14) of the circuit element 116 are electrically connected.

  When the terminal PRE is in the second electrical state, the electrical state of OUT16 of the circuit element 116 is maintained or rewritten depending on the electrical state of the node N26.

  The circuit element 117 is a circuit element similar to the circuit element 113 of FIG.

  The circuit element 117 has a function capable of storing the electrical state of the output terminal OUT16, for example.

  As the circuit element 117, for example, a capacitor, a volatile memory, a floating gate memory, a magnetoresistive memory, a resistance change memory, a ferroelectric memory, or the like can be used, but the circuit element 117 is not limited.

  However, from the viewpoint of maintaining the precharged state, the circuit element 117 is preferably a capacitor element, a volatile memory, or the like that can be easily rewritten.

  Further, when the precharge state can be maintained using the capacitance (parasitic capacitance) of the circuit element 115, the circuit element 117 is not necessary.

  FIG. 19B is the same as FIG. 19A, in which a first N-channel transistor, a second N-channel transistor, and a P-channel transistor are used as the circuit element 116 and a capacitor is used as the circuit element 117. It is an example.

  One of the source and the drain of the first N-channel transistor and the terminal Vss are electrically connected.

  The other of the source and drain of the first N-channel transistor and one of the source and drain of the second N-channel transistor are electrically connected.

  The other of the source or the drain of the second N-channel transistor, the source or the drain of the P-channel transistor, the input terminal IN17 of the circuit element 117, the input terminal IN15B of the circuit element 115, and the node N28 are Electrically connected.

  The other of the source and the drain of the P-channel transistor and the terminal Vdd are electrically connected.

  The gate (terminal N14) of the first N-channel transistor and the node N26 are electrically connected.

  The gate of the second N-channel transistor, the gate of the P-channel transistor, and the terminal PRE are electrically connected.

  An example of FIG. 15 is shown in FIG.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 5)
4 to 11, the terminal S1 and the terminal P can be omitted by electrically connecting the terminal N8 and the terminal N15.

  For example, FIG. 21 is an example in which the terminal N8 and the terminal N15 are electrically connected in FIG.

  FIG. 22 is an example of the circuit 1003 in FIG.

  FIG. 22 corresponds to, for example, a configuration in which the terminal N8 is electrically connected to the terminal N15 instead of the terminal S1 in FIG.

  FIG. 23 is an example of the circuit 1006 in FIG.

  FIG. 23 corresponds to, for example, a configuration in which the terminal N15 is electrically connected to the terminal N8 instead of the terminal P in FIG.

  An example of FIG. 21 is shown in FIG.

  An example of the operation will be described with reference to FIGS.

<Basic operation>
When predetermined operations (such as backup data restoration operation, backup data verification operation, and branch control signal output operation) are not performed, the terminals N9 and N11 are electrically connected.

  For example, in the case of FIG. 24, the terminal COMP is fixed to “0 (Low)”.

  Then, since the terminal N15 is fixed to “0 (Low)”, the terminal N9 and the terminal N11 are electrically connected.

  In the following, it is considered that the contents are easily understood when the explanation can be read with reference to FIG.

  The transmission gate (circuit element 104) in the circuit 1002 is activated.

  When performing predetermined operations (such as backup data restoration operation, backup data verification operation, and branch instruction (branch control signal) output operation), the polarity of the node N4 and the polarity of the node N26 match (same). In this case, the polarity of the node N4 does not change.

  When performing predetermined operations (backup data restoration operation, backup data verification operation, branch instruction (branch control signal) output operation, etc.), the polarity of the node N4 and the polarity of the node N26 do not match (different). In this case, the polarity of the node N4 is inverted.

  For example, in the case of FIG. 24, the terminal COMP is fixed to “1 (High)”.

  When the polarity of the node N4 and the polarity of the node N26 match (same), the output of the XOR becomes “0 (Low)”, so that the terminal N15 becomes “0 (Low)”.

  When the terminal N15 is “0 (Low)”, the terminal N9 and the terminal N11 are electrically connected, so the polarity of the node N4 does not change.

  On the other hand, when the polarity of the node N4 and the polarity of the node N26 do not match (different), the output of the XOR becomes “1 (High)”, and therefore the terminal N15 becomes “1 (High)”.

  When the terminal N15 is “1 (High)”, the terminal N10 and the terminal N11 are in an electrically connected state, and thus the terminal N10 and the terminal N11 are electrically connected.

  Therefore, the terminal N20 and the node N4 are electrically connected.

  Since the polarity of the terminal N20 is the same as that of the node N26, as a result, the polarity of the node N4 is inverted.

  Since the transmission gate (circuit element 104) in the circuit 1002 is active, the polarity opposite to that of the node N4 is output from the terminal OUT.

<Data backup>
Since the data backup is the same as in the other embodiments, repeated description is omitted.

<Restoration operation of backup data>
When the backup data is restored, for example, when the polarity of the node N4 matches the polarity of the node N26 in the circuit 1004, the circuit 1006 operates so that the polarity of N15 becomes the first polarity.

  When the backup data is restored, for example, when the polarity of the node N4 does not match the polarity of the node N26 in the circuit 1004, the circuit 1006 operates so that the terminal N15 has the second polarity.

  The first polarity is opposite to the second polarity.

  When the polarity of the terminal N15 is the first polarity (the comparison result is the same), the circuit 1003 operates so that the terminal N9 and the terminal N11 are electrically connected.

  When the polarity of the terminal N15 is the second polarity (the comparison result does not match), the circuit 1003 operates so that the terminal N10 and the terminal N11 are electrically connected.

  As a result, the polarity of the node N4 and the polarity of the node N26 can be matched as a result, so that the backup data can be restored.

  For example, in the case of FIG. 24, the terminal COMP is set to “1 (High)”.

  When the polarity of the node N4 and the polarity of the node N26 match (same), the polarity of the node N4 does not change.

  When the polarity of the node N4 and the polarity of the node N26 do not match (different), the polarity of the node N4 is inverted.

  That is, regardless of whether the node N4 is “1 (High)” or “0 (Low)”, the polarity of the node N4 matches the polarity of the node N26 in the circuit 1004.

  Therefore, the node N4 may be “1 (High)” or “0 (Low)”.

<Verification of backup data>
The basic operation is the same as the backup data restoration operation.

  The node N4 is set to either “1 (High)” or “0 (Low)”.

  When the polarity of the node N4 does not change, that is, when the polarity of the terminal OUT does not change, it can be determined that the node N26 in the circuit 1004 is one of “1 (High)” or “0 (Low)”. .

  When the polarity of the node N4 changes, that is, when the polarity of the terminal OUT changes, it can be determined that the node N26 in the circuit 1004 is the other of “1 (High)” or “0 (Low)”. .

<Branch instruction (branch control signal) output operation>
The basic operation is the same as the backup data restoration operation.

  The node N4 is set to either “1 (High)” or “0 (Low)”.

  When the polarity of the node N4 does not change, that is, when the polarity of the terminal OUT does not change, one of the presence / absence of the output operation of the branch instruction (branch control signal) can be selected.

  When the polarity of the node N4 changes, that is, when the polarity of the terminal OUT changes, it is possible to select the other of the presence / absence of a branch instruction (branch control signal) output operation.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 6)
In FIG. 12, the terminal N8 and the terminal N15 may be electrically connected.

  FIG. 25 shows an example in which the terminal N8 and the terminal N15 in FIG. 12 are electrically connected.

  FIG. 25 can be said to be an example in which the terminal N13 in FIG. 21 is electrically connected to the terminal OUTB instead of the terminal OUT.

  FIG. 26A illustrates an example of the circuit 1003 in FIG.

  FIG. 26B is an example of FIG.

  FIG. 27A illustrates an example of the circuit 1006 in FIG.

  FIG. 27B is an example of FIG.

  FIG. 28 is an example of FIG.

  The operation of FIG. 25 is the same as the operation of FIG.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 7)
FIG. 29 illustrates an example of a semiconductor device.

  An insulating layer 992 is provided over the substrate 991.

  A semiconductor layer 201 is provided over the insulating layer 992.

  A semiconductor layer 202 is provided over the insulating layer 992.

  An insulating layer 300 is provided over the semiconductor layer 201 and the semiconductor layer 202.

  A conductive layer 401 is provided over the insulating layer 300.

  A conductive layer 402 is provided over the insulating layer 300.

  An insulating layer 500 is provided over the conductive layer 401 and the conductive layer 402.

  A semiconductor layer 550 is provided over the insulating layer 500.

  A conductive layer 601 is provided over the insulating layer 500.

  A conductive layer 602 is provided over the insulating layer 500.

  A conductive layer 603 is provided over the insulating layer 500.

  A conductive layer 604 is provided over the insulating layer 500.

  A conductive layer 605 is provided over the semiconductor layer 550 and the insulating layer 500.

  A conductive layer 606 is provided over the semiconductor layer 550 and the insulating layer 500.

  The insulating layer 700 is provided over the semiconductor layer 550, the conductive layer 601, the conductive layer 602, the conductive layer 603, the conductive layer 604, the conductive layer 605, and the conductive layer 606.

  A conductive layer 801 is provided over the insulating layer 700.

  An insulating layer 900 is provided over the conductive layer 801.

  At least a part of the insulating layer 992 can function as a base insulating film, for example.

  At least a part of the semiconductor layer 201 can function as a semiconductor layer of an N-type transistor, for example.

  The semiconductor layer 201 includes at least a channel formation region, a source region, and a drain region.

  The semiconductor layer 201 is preferably a semiconductor layer containing silicon.

  A source region and a drain region included in the semiconductor layer 201 contain a donor element (eg, phosphorus, arsenic, or the like).

  The semiconductor layer 201 may have an LDD region containing a donor element.

  At least a part of the semiconductor layer 202 can function as a semiconductor layer of a P-type transistor, for example.

  The semiconductor layer 202 includes at least a channel formation region, a source region, and a drain region.

  The semiconductor layer 202 is preferably a semiconductor layer including a silicon semiconductor.

  The source region and the drain region of the semiconductor layer 202 contain an acceptor element (eg, boron).

  The semiconductor layer 202 may have an LDD region containing an acceptor element.

  Note that the channel formation region is provided between the source region and the drain region.

  The LDD region can be disposed between the channel formation region and the source region.

  The LDD region can be disposed between the channel formation region and the drain region.

  At least a part of the insulating layer 300 can function as a gate insulating film of an N-type transistor, for example.

  At least a part of the insulating layer 300 can function as a gate insulating film of a P-type transistor, for example.

  At least a part of the conductive layer 401 can function as a gate electrode of an N-type transistor, for example.

  At least part of the conductive layer 401 overlaps with a channel formation region included in the semiconductor layer 201.

  At least a part of the conductive layer 402 can function as a gate electrode of a P-type transistor, for example.

  At least part of the conductive layer 402 overlaps with a channel formation region included in the semiconductor layer 202.

  At least a part of the insulating layer 500 can function as an interlayer insulating film, for example.

  At least a part of the semiconductor layer 550 can function as a semiconductor layer of an N-type transistor, for example.

  The semiconductor layer 550 preferably includes an oxide semiconductor.

  That is, the semiconductor layer 550 is preferably an oxide semiconductor layer.

  The conductive layer 601 is electrically connected to a source region included in the semiconductor layer 201 through a contact hole included in the insulating layer 500.

  The conductive layer 602 is electrically connected to the drain region of the semiconductor layer 201 through the contact hole of the insulating layer 500.

  The conductive layer 603 is electrically connected to a source region included in the semiconductor layer 202 through a contact hole included in the insulating layer 500.

  The conductive layer 604 is electrically connected to the drain region of the semiconductor layer 202 through the contact hole of the insulating layer 500.

  At least part of the conductive layer 605 can function as a source electrode of a transistor including a channel formation region including an oxide semiconductor, for example.

  At least part of the conductive layer 606 can function as a drain electrode of a transistor including a channel formation region including an oxide semiconductor, for example.

  At least part of the insulating layer 700 can function as a gate insulating film of a transistor including a channel formation region including an oxide semiconductor, for example.

  At least part of the conductive layer 801 can function as a gate electrode of a transistor including a channel formation region including an oxide semiconductor, for example.

  At least part of the conductive layer 801 overlaps with a channel formation region included in the semiconductor layer 550.

  At least a part of the insulating layer 900 can function as an interlayer insulating film.

  As described above, an N-type transistor having a channel formation region having a silicon semiconductor, a P-type transistor having a channel formation region having silicon, and a transistor having a channel formation region having an oxide semiconductor may be formed over the same substrate. it can.

  Although an example of a top gate type transistor is shown, a bottom gate type transistor may be used. A double-gate transistor having gate electrodes above and below the semiconductor layer may be used.

  Although an example in which an N-type transistor having a channel formation region including a silicon semiconductor and a P-type transistor having a channel formation region including silicon is a thin film transistor, a transistor using a semiconductor substrate or an SOI substrate may be used.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 8)
The materials of the substrate, the insulating layer, the conductive layer, and the semiconductor layer will be described.

  As the substrate, a glass substrate, a quartz substrate, a metal substrate, a semiconductor substrate, a resin substrate (plastic substrate), or the like can be used, but is not limited thereto.

  Any material can be used for the insulating layer as long as it has insulating properties.

  Examples of the insulating layer include, but are not limited to, an insulating film having an inorganic substance and an insulating film having an organic substance. The insulating layer may have a single layer structure or a laminated structure.

  Examples of the inorganic substance include, but are not limited to, silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, and hafnium oxide.

  Examples of the organic substance include, but are not limited to, polyimide, acrylic, siloxane, and epoxy.

  Any material can be used for the conductive layer as long as it has conductivity.

  The conductive layer may have a single layer structure or a laminated structure.

  Examples of the conductive layer include, but are not limited to, a conductive film having a metal and a conductive film having a transparent conductor.

  Examples of the metal include, but are not limited to, aluminum, titanium, molybdenum, tungsten, chromium, gold, silver, copper, alkali metal, and alkaline earth metal.

  Examples of the transparent conductor include, but are not limited to, indium tin oxide and indium zinc oxide.

  As the semiconductor layer, any material having semiconductor characteristics can be used.

  The semiconductor layer may have a single layer structure or a stacked structure.

  A silicon semiconductor, an oxide semiconductor, or the like can be used for the semiconductor layer, but it is not limited.

  Examples of the silicon semiconductor include, but are not limited to, silicon, silicon germanium, and silicon carbide.

  The oxide semiconductor layer is not limited as long as it is a film containing a metal and oxygen.

  For example, a film containing indium and oxygen, a film containing zinc and oxygen, a film containing tin and oxygen, or the like can function as an oxide semiconductor layer.

  For example, the oxide semiconductor layer includes, but is not limited to, an indium oxide film, a tin oxide film, and a zinc oxide film.

  For example, as the oxide semiconductor layer, an In—Zn-based oxide film, a Sn—Zn-based oxide film, an Al—Zn-based oxide film, a Zn—Mg-based oxide film, a Sn—Mg-based oxide film, an In— Examples include, but are not limited to, an Mg-based oxide film and an In—Ga-based oxide film.

  The AB-based oxide film (A and B are elements) means a film containing A, B, and oxygen.

  For example, as the oxide semiconductor layer, for example, an In—Ga—Zn-based oxide film, an In—Sn—Zn-based oxide film, a Sn—Ga—Zn-based oxide film, an In—Al—Zn-based oxide film, In-Hf-Zn-based oxide film, In-La-Zn-based oxide film, In-Ce-Zn-based oxide film, In-Pr-Zn-based oxide film, In-Nd-Zn-based oxide film, In-Sm-Zn-based oxide film, In-Eu-Zn-based oxide film, In-Gd-Zn-based oxide film, In-Tb-Zn-based oxide film, In-Dy-Zn-based oxide film, In-Ho-Zn-based oxide film, In-Er-Zn-based oxide film, In-Tm-Zn-based oxide film, In-Yb-Zn-based oxide film, In-Lu-Zn-based oxide film, An Al—Ga—Zn-based oxide film, a Sn—Al—Zn-based oxide film, or the like is used without limitation.

  The A-B-C-based oxide film (A, B, and C are elements) means a film containing A, B, C, and oxygen.

  For example, as the oxide semiconductor layer, an In—Sn—Ga—Zn-based oxide film, an In—Hf—Ga—Zn-based oxide film, an In—Al—Ga—Zn-based oxide film, an In—Sn—Al— A Zn-based oxide film, an In-Sn-Hf-Zn-based oxide film, an In-Hf-Al-Zn-based oxide film, or the like is used, but not limited thereto.

  The A-B-C-D oxide film (A, B, C, and D are elements) means a film having A, B, C, D, and oxygen.

  As the oxide semiconductor layer, a film containing indium, gallium, zinc, and oxygen is particularly preferable.

  The oxide semiconductor layer preferably includes a crystal.

  The crystals are preferably oriented so that the c-axis direction is perpendicular to the surface of the oxide semiconductor layer or substrate.

  A crystal that is c-axis aligned so as to be perpendicular to the surface of the oxide semiconductor layer or the substrate is referred to as CAAC (C-Axis Aligned Crystal).

  The angle formed between the c-axis of the crystal and the surface of the oxide semiconductor layer or the substrate is preferably 90 degrees, but may be 80 degrees or more and 100 degrees or less.

  As an example of a method for manufacturing the CAAC, there is a first method in which a substrate temperature during film formation is 200 ° C. or higher and 450 ° C. or lower when an oxide semiconductor layer is formed by a sputtering method.

  In the first method, CAAC is formed in a lower layer and an upper layer of an oxide semiconductor layer.

  As an example of a method for manufacturing CAAC, there is a second method in which after an oxide semiconductor layer is formed, heat treatment is performed on the oxide semiconductor layer at 650 ° C. or more for 3 minutes or more.

  In the second method, CAAC is formed on at least the upper layer of the oxide semiconductor layer (pattern A of the second method).

  In the second method, CAAC can be formed in the lower layer and the upper layer by reducing the thickness of the oxide semiconductor layer (pattern B of the second method).

  As an example of a method for manufacturing the CAAC, there is a third method in which a second oxide semiconductor layer is formed over the first oxide semiconductor layer formed using the pattern B of the second method.

  The formation method of the oxide semiconductor layer in the second method and the third method is not limited to the sputtering method.

  By the first to third methods, a crystal whose angle between the c-axis and the surface of the oxide semiconductor layer or the substrate is greater than or equal to 80 degrees and less than or equal to 100 degrees can be formed.

  In any of the first to third methods, an oxide semiconductor layer having CAAC can be formed at least on the upper layer (surface).

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

(Embodiment 9)
A semiconductor device is a device having an element including a semiconductor.

  Examples of the element having a semiconductor include a transistor, a resistance element, a capacitor element, and a diode.

  The transistor is preferably a field effect transistor, but is not limited.

  The transistor is preferably a thin film transistor, but is not limited thereto.

  A transistor may be formed using a silicon wafer, an SOI substrate, or the like.

  Examples of the semiconductor device include, but are not limited to, a display device having a display element, a memory device having a memory element, an RFID, and a processor.

At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.
(Embodiment 10)
30 to 37 show examples of the truth table of the logic circuit.

  In the figure, “0” is “0 (Low)”.

  In the figure, “1” is “1 (High)”.

  In the figure, “CLK”, “CLKB”, and “S” are control signals.

  “CLKB” has the opposite polarity of “CLK”.

  In the figure, “IN”, “A”, and “B” are inputs.

  In the figure, “OUT” is an output.

  In the figure, “X: Don't Care” means that the state of the corresponding terminal is not related to the output.

  In the figure, “Z: High Impedance” means high impedance.

  FIG. 30A is an example of the truth table of the inverter.

  FIG. 30B is an example of a truth table of a clocked inverter.

  FIG. 30C is an example of a truth table of the transmission gate.

  FIG. 31A is an example of an AND truth table.

  FIG. 31B is an example of a truth table of NAND.

  FIG. 32A is an example of a truth table of clocked AND.

  FIG. 32B is an example of a truth table of clocked NAND.

  FIG. 33A is an example of an OR truth table.

  FIG. 33B is an example of a NOR truth table.

  FIG. 34A is an example of a truth table of clocked OR.

  FIG. 34B is an example of a truth table of clocked NOR.

  FIG. 35A is an example of the truth table of XOR.

  FIG. 35B is an example of an XNOR truth table.

  FIG. 36A is an example of a truth table of clocked XOR.

  FIG. 36B is an example of a truth table of clocked XNOR.

  FIG. 37 is an example of the truth table of the multiplexer.

  At least some of the aspects disclosed in this embodiment can be implemented in combination with at least some of the aspects disclosed in all other embodiments.

101 circuit element 102 circuit element 103 circuit element 104 circuit element 105 circuit element 106 circuit element 107 circuit element 108 circuit element 109 circuit element 110 circuit element 111 circuit element 112 circuit element 113 circuit element 114 circuit element 115 circuit element 116 circuit element 117 circuit Element 201 Semiconductor layer 202 Semiconductor layer 300 Insulating layer 401 Conductive layer 402 Conductive layer 500 Insulating layer 550 Semiconductor layer 601 Conductive layer 602 Conductive layer 603 Conductive layer 604 Conductive layer 605 Conductive layer 606 Conductive layer 700 Insulating layer 801 Conductive layer 900 Insulating layer 991 Substrate 992 Insulating layer 1001 Circuit 1002 Circuit 1003 Circuit 1004 Circuit 1005 Circuit 1006 Circuit 10001 Circuit 10002 Circuit 10003 Circuit 11000 Register file 12000 Circuit C1 Terminal C2 Terminal COM Terminal IN Terminal IN1 Input Terminal IN2 Input Terminal IN3 Input Terminal IN4 Input Terminal IN5 Input Terminal IN6 Input Terminal IN7A Input Terminal IN7B Input Terminal IN7S Control Terminal IN8A Input Terminal IN8B Input Terminal IN9 Input Terminal IN10 Input Terminal IN11A Input Terminal IN11B Input Terminal IN12 Input Terminal IN13 input terminal IN14 input terminal IN15A input terminal IN15B input terminal IN16A input terminal IN16B input terminal IN17 input terminal N1 terminal N2 terminal N3 terminal N4 node N5 terminal N6 terminal N7 node N8 terminal N9 terminal N10 terminal N11 terminal N12 node N13 terminal N14 terminal N15 terminal N16 node N17 terminal N18 terminal N19 terminal N20 terminal N21 terminal N22 terminal N23 terminal N24 terminal N25 terminal N26 node 27 node N28 node OUT terminal OUTB terminal OUT1 output terminal OUT2 output terminal OUT3 output terminal OUT4 output terminal OUT5 output terminal OUT6 output terminal OUT7 output terminal OUT8 output terminal OUT10 output terminal OUT11 output terminal OUT12 output terminal OUT14 output terminal OUT15 output terminal OUT16 output terminal P terminal PRE terminal R terminal REG1 storage unit REGj storage unit REGk storage unit REGn storage unit REGx storage unit S terminal S1 terminal S2 terminal Vdd terminal Vss terminal W terminal

Claims (4)

A first circuit having a volatile memory;
A second circuit having a memory having first to fourth transistors and a capacitor;
The first transistor has a channel formation region including an oxide semiconductor,
One of a source and a drain of the first transistor is electrically connected to the first circuit;
The other of the source and the drain of the first transistor is electrically connected to the capacitor;
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
The second to fourth transistors are electrically connected in series between two terminals,
A semiconductor device having a function of determining whether or not a branch instruction is executed by comparing data of the first circuit and data of the second circuit. A first circuit having a volatile memory;
A second circuit having a memory having first to fourth transistors and a capacitor;
A third circuit having a first terminal, a second terminal, and a third terminal;
The first circuit is electrically connected to the second circuit;
A function capable of determining whether or not a branch instruction is executed by comparing the data of the first circuit and the data of the second circuit;
The first transistor has a channel formation region including an oxide semiconductor,
One of a source and a drain of the first transistor is electrically connected to the first circuit;
The other of the source and the drain of the first transistor is electrically connected to the capacitor;
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
The second to fourth transistors are electrically connected in series between two terminals,
The third circuit has a function of electrically connecting the third terminal to the first terminal;
The third circuit has a function of electrically connecting the third terminal to the second terminal ;
The first terminal prior Symbol is electrically connected to said first circuit,
The second terminal is electrically connected to the second circuit;
The third terminal is electrically connected to the first circuit and the second circuit;
A function of forming a feedback loop by electrically connecting the third terminal to the first terminal in the first period;
In the second period, the by third terminals for connecting the second terminal and electrically, characterized by having a function capable of reading data of the second circuit to the first circuit A semiconductor device. In claim 2,
The gate of the third transistor and the gate of the fourth transistor are electrically connected to the third circuit. In any one of Claims 1 thru | or 3,
The second circuit includes fifth to seventh transistors,
The other of the source and the drain of the first transistor is electrically connected to the gate of the fifth transistor;
The semiconductor device, wherein the fifth to seventh transistors are electrically connected in series between the two terminals.

Images