JP6131591B2 - D / A converter circuit - Google Patents

Description

  The present invention relates to a D / A conversion circuit using a resistance variable element.

  FIG. 17 is a circuit diagram showing a configuration example of a comparison circuit using a conventional simple D / A conversion circuit 200. In FIG. 17, the D / A conversion circuit 200 includes a load resistor Rr2 interposed between the analog voltage output node for generating the analog voltage VIN and the power supply VDD, and an analog voltage output node and the ground. And an inserted switch transistor SWk (k = 0 to n). Here, a selection signal Sk (k = 0 to n) is supplied to each gate of the switch transistor SWk (k = 0 to n) based on a digital signal to be converted. The voltage VIN generated at the analog voltage output node is supplied to the comparator 100. A bias voltage BIAS is applied to the gate of the transistor T1. The voltage generation circuit including the transistor T1 and the resistor Rr1 supplies the reference voltage VREF to the comparator 100. The comparator 100 compares the analog voltage VIN and the reference voltage VREF, and outputs a digital signal Out indicating the comparison result.

  FIG. 18 is a diagram illustrating a relationship between ON / OFF of the switch transistor SWk (k = 0 to n) and the output voltage VIN of the D / A conversion circuit 200. In this example, as the selection signal Sk (k = 0 to n) when the switch transistor SWn (k = 0 to n) is turned on, a gate voltage for operating each switch transistor in the saturation region is given. FIG. 18 illustrates output voltages when the switch transistor SW0 is turned on, when SW0 and SW1 are turned on, when SW0 to SW2 are turned on, and when SW0 to SW3 are turned on. In this example, since the saturation currents of the switch transistors SWk (k = 0 to n) are equal, a voltage drop proportional to the number of switching transistors that are turned on is generated in the resistor Rr2. Therefore, the analog voltage VIN corresponding to the digital signal to be converted is output from the D / A conversion circuit 200.

JP 2009-187631 A

ISSCC Digest of Technical Papers, pp. 258, Feb. 2010. Non-Patent Literature IEICE IEICE Technical Report ICD Technical Report ICD2010-7 p35-p40

  By the way, in the conventional D / A conversion circuit, a polysilicon layer is usually used as the fixed resistor Rr2. However, in order to make the fixed resistor Rr2 high resistance suitable for the D / A converter circuit, a very large area is required. Polysilicon layer is required. Here, a well (low-concentration impurity diffusion region) resistor may be used as the fixed resistor Rr2. However, the resistance of the well (low-concentration impurity diffusion region) has a large variation in the resistance itself, and it is difficult to construct a highly accurate D / A conversion circuit using this resistance. Further, as illustrated in FIG. 18, the conventional D / A converter circuit can output only the output voltages corresponding to the number of the switch transistors, so that a highly accurate D / A converter circuit can be configured. It is necessary to increase the number of switch transistors. For this reason, when a highly accurate D / A conversion circuit is configured, there is a problem that the required area becomes large.

  The present invention has been made in view of the circumstances described above, and an object thereof is to provide a D / A conversion circuit with high accuracy and a small area.

  The present invention includes a plurality of resistance change elements, and selects one or a plurality of resistance change elements in the plurality of resistance change elements based on a digital signal to be converted, and sets a write voltage to each of the resistance change elements. An analog signal corresponding to the digital signal is generated by applying and connecting in parallel. A D / A conversion circuit is provided.

  According to this invention, by changing the resistance change type elements connected in parallel and the write voltage for each of them, various types of combined resistance values of the resistance change type elements connected in parallel are realized, Many types of analog signals can be generated by the variable resistance elements connected in parallel. Therefore, it is possible to realize a D / A conversion circuit with high accuracy and a small area.

  In a preferred aspect, the D / A conversion circuit is a voltage dividing circuit that divides the voltage between the first and second power supply nodes and outputs the divided voltage to the analog voltage output node, and each of the switch and the resistance variable element is connected in series. A first variable resistance switch circuit formed by connecting a plurality of connected circuits to each other in parallel is provided between the first power supply node and the analog voltage output node, and each switch and a resistance variable element are connected in series. A voltage dividing circuit having a second variable resistance switch circuit formed by connecting the plurality of circuits connected in parallel to each other between the second power supply node and the analog voltage output node; and a resistance change type in the voltage dividing circuit And a control circuit that performs control for applying a write voltage to the element and ON / OFF control of a plurality of switches in the voltage dividing circuit.

  In this aspect, since the resistance value of the resistance variable element can be changed by applying a write voltage, many types of voltage dividing ratios can be realized by a voltage dividing circuit including a small number of resistance variable elements. it can. Therefore, it is possible to realize a D / A conversion circuit with high accuracy and a small area.

  In another preferred aspect, the D / A conversion circuit includes a write switch interposed between the analog voltage output node and a third power supply node, and the control circuit includes the write switch and the first switch Alternatively, by turning on a switch in the second variable resistance switch circuit and applying a write voltage between the first and third power supply nodes or between the second and third power supply nodes, A write voltage is applied to the resistance variable element in the second variable resistance switch circuit.

  In another preferred embodiment, the control circuit applies control to apply a write voltage to one or a plurality of resistance variable elements in the first or second variable resistance switch circuit based on a digital signal to be converted. Then, one or a plurality of switches in the first or second variable resistance switch circuit is turned on to control the voltage dividing circuit to output an analog signal corresponding to the digital signal.

  In another preferable aspect, the D / A conversion circuit is a voltage dividing circuit that divides a voltage between the first and second power supply nodes and outputs the divided voltage to an analog voltage output node, and the fixed resistor is connected to the first resistor. And a variable resistance switch circuit formed by connecting a plurality of circuits each having a switch and a resistance variable element connected in series with each other between the power supply node and the analog voltage output node, and the second power supply node. A voltage dividing circuit between the analog voltage output node, a control for applying a write voltage to a resistance variable element in the voltage dividing circuit, and a control for performing ON / OFF control of a plurality of switches in the voltage dividing circuit Circuit.

  In this aspect, the variable resistance switch circuit is provided only between the second power supply node and the analog voltage output node. Therefore, the D / A conversion circuit can be made small.

  In a preferred aspect, when the analog signal is output to the voltage dividing circuit, the D / A conversion circuit sets the first power supply node as a high potential power supply node and the second power supply node as a low potential power supply node. .

  In another preferred aspect, when the D / A conversion circuit outputs the analog signal to the voltage dividing circuit, the second power supply node is a high potential power supply node, and the first power supply node is a low potential power supply node. And

  In the above aspects, the resistance variable element may be a magnetic tunnel junction element or a resistance element in which an electric field induced giant resistance change occurs.

1 is a circuit diagram showing a configuration of a successive approximation A / D conversion circuit including a D / A conversion circuit according to a first embodiment of the present invention. FIG. It is a figure explaining the structure and operation | movement of an MTJ element used in the embodiment. It is sectional drawing which shows the example of a layout of the memory cell using the same MTJ element. It is a figure which shows the operating condition of the memory cell using the MTJ element. It is a time chart which shows operation | movement of the same D / A conversion circuit. It is a figure which shows operation | movement of the D / A converter circuit which is a comparative example. It is a figure which illustrates the relationship between the digital signal value of the same D / A conversion circuit, and a voltage dividing ratio. It is a figure which shows the operation | movement of the embodiment. It is a figure which shows the relationship between the digital signal value of the D / A converter circuit by the same embodiment, and a voltage dividing ratio. It is a circuit diagram which shows the structure of the successive approximation type A / D conversion circuit containing the D / A conversion circuit which is 2nd Embodiment of this invention. It is a figure which shows operation | movement of the D / A converter circuit which is a comparative example. It is a figure which illustrates the relationship between the digital signal value of the same D / A conversion circuit, and a voltage dividing ratio. It is a figure which shows the operation | movement of the embodiment. It is a figure which shows the relationship between the digital signal value of the D / A converter circuit by the same embodiment, and a voltage dividing ratio. It is a circuit diagram which shows the structure of the successive approximation type A / D conversion circuit containing the D / A conversion circuit which is other Embodiment of this invention. It is a circuit diagram which shows the structure of the successive approximation type A / D conversion circuit containing the D / A conversion circuit which is other Embodiment of this invention. It is a circuit diagram which shows the structure of the comparison circuit using the conventional D / A conversion circuit. It is a figure which shows operation | movement of the same D / A conversion circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of an A / D conversion circuit including a D / A conversion circuit according to the first embodiment of the present invention. As shown in FIG. 1, the A / D conversion circuit includes a voltage dividing circuit 301, a control circuit 302, and a comparator 100. In this A / D conversion circuit, the voltage dividing circuit 301 and the control circuit 302 (more strictly, a part of the control circuit 302) constitute the D / A conversion circuit according to the present embodiment. The comparator 100 is a circuit that compares the reference voltage VREF output as a D / A conversion result by the D / A conversion circuit with the input voltage VIN and outputs a signal Out indicating the comparison result. Then, the control circuit 302 causes the voltage dividing circuit 301 to perform D / A conversion while changing the digital signal that is the D / A conversion target in a certain direction, and the voltage VREF that is the D / A conversion result becomes the input voltage VIN. Control is performed to obtain matching digital signal values.

  Here, the voltage dividing circuit 301 which is one of the components of the D / A conversion circuit will be described. The voltage dividing circuit 301 is a circuit that outputs the reference voltage VREF to the analog voltage output node N0 by dividing the voltage between the power supplies VP1 and VP2. The voltage dividing circuit 301 is configured to be able to control the voltage dividing ratio. The feature of the present embodiment lies in the variety of voltage division ratios realized by the voltage dividing circuit 301. A voltage dividing circuit 301 capable of voltage division at various voltage division ratios enables D / A conversion with high resolution.

  In order to enable voltage division at various voltage division ratios, the voltage dividing circuit 301 includes variable resistance elements R0k (k = 0 to n) and R1k (k = 0 to n), and MOSFETs (Metal Oxide Semiconductor Fields). The transistor includes switch transistors SW0k (k = 0 to n), SW1k (k = 0 to n), and a write transistor T1, which are effect transistors (field-effect transistors having a metal-oxide-semiconductor structure).

  Here, one end of each resistance variable element R0k (k = 0 to n) is connected to the power source VP1. Further, the switch transistor SW0k (k = 0 to n) is inserted between each other end of the resistance variable element R0k (k = 0 to n) and the analog voltage output node N0. The switch transistor SW0k (k = 0 to n) plays a role of switching whether or not the resistance variable element R0k (k = 0 to n) is connected between the power supply VP1 and the analog voltage output node N0. These variable resistance elements R0k (k = 0 to n) and switch transistors SW0k (k = 0 to n) constitute a variable resistance switch circuit interposed between the power supply VP1 and the analog voltage output node N0. .

  In addition, one end of each variable resistance element R1k (k = 0 to n) is connected to the analog voltage output node N0. In addition, switch transistors SW1k (k = 0 to n) are respectively inserted between the other ends of the resistance variable elements R1k (k = 0 to n) and the power supply VP2. The switch transistor SW1k (k = 0 to n) plays a role of switching whether or not the resistance variable element R1k (k = 0 to n) is connected between the analog voltage output node N0 and the power source VP2. These variable resistance element R1k (k = 0 to n) and switch transistor SW1k (k = 0 to n) constitute a variable resistance switch circuit interposed between power supply VP2 and analog voltage output node N0. .

  As described above, the voltage dividing circuit 301 has the switch transistors SW0k (k = 0 to n) and SW1k (k = 0 to n) for selecting the resistance variable element connected to the analog voltage output node N0. . Therefore, in this embodiment, many types of voltage division ratios can be realized by ON / OFF control of the switch transistors SW0k (k = 0 to n) and SW1k (k = 0 to n).

  Furthermore, in the present embodiment, resistance variable elements R0k (k = 0 to n) and R1k (k = 0 to n) are used as resistance elements for configuring the voltage dividing circuit 301, instead of fixed resistors. . This resistance variable element is an element that can be made to have a high resistance by flowing a current in a certain direction and can have a low resistance by flowing a current in the opposite direction. Then, the voltage dividing circuit 301 according to the present embodiment selects any one of the resistance variable elements R0k (k = 0 to n) and R1k (k = 0 to n), and allows a current in a desired direction to flow. Is possible. Therefore, in the voltage dividing circuit 301 in the present embodiment, it is possible to realize a remarkably many types of voltage dividing ratios compared to the case where a fixed resistor is used, and to dramatically improve the resolution of D / A conversion. This is the greatest feature of this embodiment.

  In addition to the power sources VP1 and VP2, the voltage dividing circuit 301 is supplied with a power source VP3. The power source VP3 is a power source used for setting a desired resistance value among the resistance variable elements R0k (k = 0 to n) and R1k (k = 0 to n). The write transistor T1 is interposed between the power supply VP3 and the analog voltage output node N0. The write transistor T1 plays a role of switching whether or not the power supply VP3 is connected to the analog voltage output node N0. The write transistor T1 is turned on, the power source VP3 is connected to the analog voltage output node N0, and the resistance variable elements connected to the analog voltage output node N0 are switched transistors SW0k (k = 0 to n) and SW1k (k = 0). N), and by generating an appropriate write voltage between the power supplies VP1 and VP3 or between the power supplies VP3 and VP2, the resistance value of any resistance variable element can be set high / low.

Next, a specific example of the resistance variable element constituting the voltage dividing circuit 301 will be described. The variable resistance elements R0k (k = 0 to n) and R1k (k = 0 to n) in this embodiment are, for example, MTJ (Magnetic Tunnel Junction) elements. 2A and 2B are diagrams showing the configuration and operation of this MTJ element. As shown in FIGS. 2A and 2B, the MTJ element is composed of a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer whose magnetic direction changes. As shown in FIG. 2A, when a current in the direction from the free layer toward the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element becomes low resistance, and data “0” is stored. It becomes a state. Conversely, as shown in FIG. 2B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored.
This MTJ element is used for a memory cell of a non-volatile memory such as an MRAM (Magnetic Resistive Random Access Memory) (see Patent Document 1 and Non-Patent Document 1). When a memory cell is configured with an MTJ element, a transistor Ts is connected in series with the MTJ element as a switch for selecting the MTJ element, as illustrated in FIGS.

  FIG. 3 is a diagram illustrating a cross-sectional structure of a memory array including memory cells as shown in FIGS. 2 (a) and 2 (b). In the example shown in FIG. 3, the selection transistor Ts shown in FIGS. 2A and 2B is formed on the semiconductor substrate. A selection voltage WL is applied to the gate of each transistor Ts. The source of the transistor Ts is connected to the second layer metal wiring 2M for supplying the source voltage SL through the through hole and the first layer metal wiring 1M. The drain of the transistor Ts is connected to the pin layer of the MTJ element through the through hole CS, and the free layer of this MTJ element is the second layer metal wiring 2M for supplying the write voltage BL through the through hole V1. It is connected to the. This memory cell is disclosed in Non-Patent Document 2, for example. FIG. 4 is a diagram showing the operating conditions of this memory cell. First, data writing to the resistance variable element R1 will be described. When “0” is written to the resistance variable element R1, the bit line BL is set to 1.2V, the source line SL is set to 0V, and the selection voltage WL is set to 1.2V. In this state, a voltage of about 0.6 V is applied to both ends of the resistance variable element R1, and a current of about 49 μA flows from the bit line BL to the source line SL. As a result, the resistance variable element R1 has a low resistance and stores data “0”. When “1” is written to the resistance variable element R1, the bit line BL is set to 0V, the source line SL is set to 1.2V, and the selection voltage WL is set to 1.2V. As a result, a current of about 49 μA flows from the source line SL to the bit line BL. As a result, the resistance variable element R1 changes to a high resistance and stores data “1”. In data reading, the bit line BL is set to 0.15V, the source line SL is set to 0V, and the selection voltage WL is set to 1.2V. Here, when the resistance variable element R1 stores data “0” and has a low resistance, a current of 15 μA flows from the bit line BL to the source line SL. On the other hand, when the resistance variable element R1 stores data “1” and has a high resistance, a current of 10 μA flows from the bit line BL to the source line SL. Therefore, a threshold value (for example, 12.5 μA) is generated between the current 15 μA flowing when reading data “0” and the current 10 μA flowing when reading data “1”, and the bit line BL is switched to the source line SL when reading data. By comparing the current flowing in the direction with this threshold value, it is possible to determine whether the data stored in the resistance variable element R1 is “0” or “1”.

  The above is the outline of the MTJ element used as the resistance variable element R0k (k = 0 to n) and R1k (k = 0 to n) in the present embodiment. In the example shown in FIG. 1, the variable resistance element R0k (k = 0 to n) has a free layer on the power supply VP1 side and a pinned layer on the opposite side, and the variable resistance element R1k (k = 0 to n) The node N0 side is a free layer and the opposite side is a pinned layer.

  As the resistance change elements R0k (k = 0 to n) and R1k (k = 0 to n), in addition to the MTJ elements, CER used for memory cells of ReRAM (Resistance Random Access Memory). (Collective Electro-Resistance; electric field induced giant resistance change) A resistive element may be used.

  In FIG. 1, a control circuit 302 that constitutes a D / A conversion circuit together with a voltage dividing circuit 301 includes a counter for updating a digital signal that is a D / A conversion target. The control circuit 302 controls the voltage dividing circuit 301 to perform D / A conversion of the digital signal while counting the digital signal to be D / A converted by the counter, and the output signal Out of the comparator 100 is inverted. Is detected to obtain a digital signal value at which the D / A conversion result VREF becomes the input voltage VIN.

  In the present embodiment, the control of the voltage dividing ratio of the voltage dividing circuit 301 performed by the control circuit 302 includes two controls. The first control selects a resistance variable element used to perform voltage division at a desired voltage dividing ratio (that is, a voltage dividing ratio corresponding to the updated digital signal), and selects an appropriate resistance variable element. This is data write control for setting a high / low resistance value by applying a write voltage. In the present embodiment, the control for setting the resistance value high / low for the resistance variable element is referred to as data writing. The flow of current from the pinned layer to the free layer through the resistance variable element to increase the resistance value of the resistance variable element is the writing of data “1”. In addition, the flow of current from the free layer to the pinned layer through the resistance variable element to lower the resistance value of the resistance variable element is the writing of data “0”. The second control is data read control in which a resistance variable element used for voltage division at a desired voltage division ratio is connected to the analog voltage output node N0 and the voltage dividing circuit 301 performs D / A conversion. is there.

In the present embodiment, the control circuit 302 sets each of the resistance variable elements R0k (k = 0 to n) and R1k (k = 0 to n) to a high resistance, a low resistance, or an analog voltage. A table 302T that defines whether to disconnect from the output node N0 in association with the digital signal value is stored. In the data write control, the control circuit 302 refers to the table 302T to obtain a resistance variable element to be made high resistance and a resistance variable element to be made low resistance from the digital signal value to be converted. Control to set the high / low resistance value of the resistance variable element is performed. In this data writing control, data writing may be performed not on all of the resistance variable elements R0k and R1k (k = 0 to n), but only on a part of the resistance variable elements. For example, in the table 302T shown in FIG. 1, when the digital signal value to be converted changes from “1” to “2”, the resistance variable element R1n is changed from low resistance (“0”) to high resistance (“1”). You only need to rewrite it. Therefore, only data writing to the resistance variable element R1n that needs to be rewritten is performed. That is, at the time of D / A conversion, information associated with the digital signal value to be subjected to the previous D / A conversion and information associated with the digital signal value to be subjected to the current D / A conversion are obtained. By reading from the table 302T and comparing both pieces of information, the variable resistance element for writing data in the current D / A conversion is determined. Further, the control circuit 302 refers to the table 302T in the data read control, obtains a resistance variable element to be separated from the analog voltage output node N0 based on the digital signal value to be converted, and determines the resistance variable type thereof. Control is performed to disconnect the element from the analog voltage output node N0. Note that details of the control of the voltage division ratio will be made clear in the description of the operation of the present embodiment in order to avoid duplication of explanation.
The above is the configuration of the present embodiment.

Next, the operation of this embodiment will be described.
FIG. 5 is a time chart illustrating the operation of an A / D conversion circuit that repeats D / A conversion while updating a digital signal. As already described, in this embodiment, data writing and D / A conversion are executed based on the updated digital signal while updating the digital signal to be converted. Data writing is performed for each resistance variable element used for voltage division processing at a voltage division ratio corresponding to the updated digital signal. Here, when a plurality of resistance change elements are used in the voltage dividing process, the plurality of resistance change elements are sequentially selected, and data writing is performed on these resistance change elements. However, in FIG. 5, in order to prevent the drawing from becoming complicated, as data writing performed before each D / A conversion, data writing operation for one resistance variable element, that is, resistance change type is performed. Operation of writing data “0” to the element R00, writing data “1” to the resistance variable element R01, writing data “0” to the resistance variable element R10, and writing data “1” to the resistance variable element R11 It is shown.

  When writing data “0” to the resistance variable element R00, the control circuit 302 sets the write enable signal WE to the active level (H level), turns on the write transistor T1, and connects the power supply VP3 to the analog voltage output node N0. . Further, the control circuit 302 turns on only the switch transistor SW00, turns off the other switch transistors, outputs 1V to the power supply VP1, and outputs 0V to the power supply VP3. In this case, the voltage VP1-VP3 = 1V is the write voltage. In this case, a write voltage of 1 V is applied between the free layer and the pin layer of the resistance variable element R00, and a current from the free layer to the pin layer flows through the resistance variable element R00. As a result, the resistance variable element R00 is in a state in which the resistance value decreases and data “0” is written. Note that the power supply VP2 may be an arbitrary voltage value because it does not participate in the data writing (Don't Care).

In the subsequent D / A conversion, the control circuit 302 sets the write permission signal WE to the L level, turns the write transistor T1 OFF, disconnects the power supply VP3 from the analog voltage output node N0, and sets the power supply VP1 to 0.6 V and the power supply VP3. 0V (the write transistor T1 is OFF and Don't
Since it is Care, another voltage is acceptable), and 0 V is output to the power source VP2. In this case, the voltage VP1−VP2 = 0.6V is the read voltage. Then, the control circuit 302 turns on switch transistors connected to the resistance variable element used for voltage division processing, such as the switch transistor SW00 connected to the resistance variable element R00, and turns off the other switch transistors. Selection signals S0k (k = 0 to n) and S1k (k = 0 to n) are output. Here, the resistance variable element R00 is a resistance variable element used for D / A conversion since the previous data writing is performed. Therefore, the selection signal S00 corresponding to the resistance variable element R00 becomes H level. The level of the selection signal other than the selection signal S00 (the hatched selection signal in FIG. 5) is determined by the digital signal to be converted.

  In this state, a current flows through the resistance variable element group connected to the analog voltage output node N0, and the analog voltage VREF obtained by dividing the read voltage VP1-VP2 = 0.6V by the voltage dividing ratio corresponding to the digital signal is the analog voltage. Output to output node N0.

  Here, the reason why the reading voltage is set to 0.6 V, which is lower than the writing voltage, is to prevent erroneous writing. More specifically, when data is written, a maximum voltage of 1 V is applied to one resistance variable element. This voltage is a voltage necessary for performing stable data writing. On the other hand, at the time of reading, in order to prevent erroneous writing, it is necessary to reduce the current flowing through the resistance variable element (that is, to reduce the applied voltage). Here, the maximum value of the voltage applied to one resistance variable element at the time of reading is a voltage value obtained by multiplying the read voltage by the maximum voltage dividing ratio in D / A conversion. For example, when the read voltage is 0.6 V and the maximum value of the voltage division ratio is 0.8, the maximum value of the voltage applied to one resistance change element is 0.48 V. Thus, by setting the read voltage to 0.6 V, the maximum value of the applied voltage to the resistance variable element is 0.48 V, which is lower than the applied voltage at which data can be written (that is, the voltage at which erroneous writing occurs). Can be. Therefore, the read voltage is set to 0.6V.

  When the D / A conversion is performed in this way and the signal Out indicating the determination result regarding the D / A conversion result is output, the control circuit 302, based on the signal Out, outputs the digital signal that is the target of the D / A conversion. It is determined whether to update the signal. Then, the control circuit 302 performs data writing for enabling voltage division at a voltage division ratio corresponding to the updated digital signal.

  As shown in FIG. 5, when data “1” is written to the resistance variable element R01, the write permission signal WE is set to the H level, the power supply VP1 is 0V, the power supply VP3 is 1V, and the power supply VP2 is 0V (Don ' t Care) is output, only the selection signal S01 is set to H level, only the switch transistor SW01 is turned on, and the other switch transistors are turned off. As a result, a current from the pinned layer to the free layer flows through the resistance variable element R01, and the resistance variable element R01 has a high resistance.

  When the data writing is completed, a D / A conversion operation is performed. This D / A conversion operation is the same as described above.

Similarly to the above, a signal Out indicating the determination result regarding the D / A conversion result is output. Based on this signal, it is determined whether or not to continue the update of the digital signal. Data writing and D / A conversion based on the above are performed.
Hereinafter, the same operation is repeated.

Next, the resolution of the D / A conversion circuit according to the present embodiment will be described.
First, for comparison, in the D / A conversion circuit as shown in FIG. 1, the D / A when the resistance variable elements R0k (k = 0 to n) and R1k (k = 0 to n) are replaced with fixed resistors. The resolution of A conversion will be described. For simplicity, consider the case of n = 1.

  In this case, four different voltage division ratios can be realized by variously changing one of the upper resistors R00 and R01 and the lower resistors R10 and R11 connected to the analog voltage output node N0. In FIG. 6, the voltage division ratio number is a number associated with various configurations of the voltage dividing circuit in which the resistance connected to the analog voltage output node N0 is variously changed. In FIG. 6, for example, in the column of the voltage division ratio number 1, “R” is described in each column corresponding to the resistors R00, R01, and R10, and the column corresponding to the resistor R11 is blank. This indicates that, in the configuration of the voltage dividing circuit corresponding to the voltage dividing ratio number 1, the resistors R00, R01, and R10 are connected to the analog voltage output port, and the resistor R11 is disconnected from the analog voltage output port. In this case, in the voltage dividing circuit, the combined resistance of the upper resistor group is R / 2, and the combined resistance of the lower resistor group is R, so that the voltage dividing ratio is R / ((R / 2) + R) ≈0. .67. The same applies to configurations corresponding to other voltage division ratio numbers.

  When n = 1, there are four configurations of the voltage dividing circuit, but each of the voltage dividing ratios corresponding to the voltage dividing ratio numbers 2 and 3 is 0.50. Therefore, there are three types of partial pressure ratios to be realized.

  FIG. 7 is a graph in which three voltage division ratios realized by a voltage dividing circuit with n = 1 are arranged in ascending order and their digital signal values 1 to 3 are associated with each other. In this way, when n = 1, three digital signal values can be expressed by analog voltages. The resolution in this case is 3.

  On the other hand, in the present embodiment, the voltage dividing circuit is configured by a resistance variable element, and the resistance value of the resistance variable element used for the voltage dividing process can be changed in two ways. Therefore, the types of voltage dividing ratios that can be realized can be remarkably increased as compared with the voltage dividing circuit constituted by fixed resistors.

  FIG. 8 shows various resistances connected to the analog voltage output node N0 among the upper resistances R00 and R01 and the lower resistances R10 and R11 of the voltage dividing circuit, and the resistance of the resistance variable element connected to the analog voltage output node. The figure shows various voltage divider circuit configurations realized by variously changing the high / low values and the voltage division ratios obtained by them. In FIG. 8, in the column corresponding to the voltage division ratio number 1, “R” is described in each column corresponding to the resistance variable elements R00 and R01, and “2R” is described in the column corresponding to the resistance variable element R10. ", And the column corresponding to the resistance variable element R11 is blank. In this case, data “0” is written in the resistance change elements R00 and R01 in which “R” is written in the column corresponding to the voltage division ratio number 1, and the resistance value is estimated based on Non-Patent Document 1. 5 kΩ. In addition, data “1” is written in the variable resistance element R10 in which “2R” is written in the column corresponding to the voltage division ratio number 1, and when estimated based on Non-Patent Document 1, the resistance value is 10 kΩ. . The variable resistance element R11 that is blank in the column corresponding to the voltage division ratio number 1 is disconnected from the analog voltage output node N0. In the voltage dividing circuit configuration corresponding to the voltage dividing ratio number 1, the upper combined resistance is R / 2 and the lower combined resistance is 2R, so the dividing ratio is 2R / ((R / 2) + 2R) = 0.80. .

  In FIG. 8, the configurations corresponding to the voltage division ratio numbers 1 to 4 are combinations in which the upper combined resistance is minimum, that is, the resistance variable elements R00 and R01 have low resistance, and both of them are analog voltage output nodes N0. It is the structure connected to. In this case, the upper combined resistance is R / 2.

  Each of the configurations corresponding to the voltage division ratio numbers 5 to 8 is a combination in which the upper combined resistance is the next smallest, the resistance variable element R00 is the high resistance 2R, the resistance variable element R01 is the low resistance R, and the upper combined resistance. The resistance is 2R / 3.

The voltage dividing ratio numbers 9 to 12 are combinations in which the upper combined resistance is R. Here, when R00 = R01 = 2R is set and both R00 and R01 are connected to the analog voltage output node, the upper combined resistance is R, which is the same as the upper combined resistance of the voltage dividing ratio numbers 9 to 12. Therefore, it is not used as a configuration of a voltage dividing circuit for D / A conversion.
The voltage dividing ratio numbers 13 to 16 are combinations in which the upper combined resistance is the maximum 2R.

  In the various voltage divider circuit configurations shown in FIG. 8, the resistance values of the lower resistance change elements R10 and R11 are variously changed in each type of the upper combined resistance.

Then, except for overlapping ones obtained from the respective voltage dividing circuit configurations corresponding to the voltage dividing ratio numbers 1 to 16 shown in FIG. 8, the remaining voltage dividing ratios are arranged in ascending order, and various digital signal values are arranged in them. FIG. 9 is a graph in which these are associated with each other. As shown in FIG. 9, in the present embodiment, when n = 1, the resolution 11 can be realized, and the resolution can be made approximately four times as accurate as the voltage dividing circuit configured by the fixed resistor. it can.
Thus, according to the present embodiment, a highly accurate D / A conversion circuit can be configured with a small area.

Second Embodiment
FIG. 10 is a circuit diagram showing a configuration of an A / D conversion circuit including a D / A conversion circuit according to the second embodiment of the present invention. In the present embodiment, the voltage dividing circuit 301 and the control circuit 302 in the first embodiment (FIG. 1) are replaced with a voltage dividing circuit 311 and a control circuit 312. In the voltage dividing circuit 311, the fixed resistance element Rr and the write transistor T2 are interposed between the power supply VP1 and the analog voltage output node N0. A write inhibit signal WEB is input to the gate of the write transistor T2. The write inhibit signal WEB is a signal obtained by inverting the write enable signal WE. The analog voltage output node N0 is connected to a free layer of the resistance variable element Rk (k = 0 to n), and between the pin layer of the resistance variable element Rk (k = 0 to n) and the power source VP2. Are respectively provided with switch transistors SWk (k = 0 to n). A selection signal Sk (k = 0 to n) is applied to the gate of the switch transistor SWk (k = 0 to n). The write transistor T1 is the same as that in the first embodiment.

  The control circuit 312 includes a write enable signal WE for the write transistor T1, a write inhibit signal WEB for the write transistor T2, and a selection signal Sk (k = 0 to 0) for controlling ON / OFF of the switch transistor SWk (k = 0 to n). n) is output. As a result, the control circuit 312 writes data to each resistance variable element of the voltage dividing circuit 311 and causes the voltage dividing circuit 311 to perform D / A conversion.

  The operation at the time of data writing in this embodiment is as follows. First, at the time of data writing, the control circuit 312 sets the write enable signal WE to the H level, the write prohibit signal WEB to the L level, and the resistance change element Rk (k) to be written by the selection signal Sk (k = 0 to n). = 0 to n). When data “0” is written to the selected variable resistance element, 1 V is output to the power source VP3, 0 V is output to the power source VP2, and when data “1” is written, 0 V is supplied to the power source VP3. 1V is output to VP2.

  11 and 12 show a comparative example of this embodiment. More specifically, FIG. 11 shows various types realized by replacing the variable resistance elements R0 to R3 of the voltage dividing circuit with fixed resistors and changing various ones of those fixed resistors connected to the analog voltage output node N0. The voltage dividing circuit configuration and the voltage dividing ratio obtained thereby are shown. FIG. 12 rearranges the voltage division ratios realized in FIG. 11 in ascending order and associates them with digital signal values. In this example, when each fixed resistance is R, the upper resistance Rr of the voltage dividing circuit is R / 2. In this case, since there are four voltage division ratios, the resolution is 4.

  13 and 14 show the effects of this embodiment. More specifically, FIG. 13 shows various voltage divider circuit configurations realized by changing various ones of the resistance variable elements R0 to R3 connected to the analog voltage output node N0 in the present embodiment, and the obtained voltage dividing circuit configurations. The partial pressure ratio is shown.

  FIG. 14 rearranges the voltage division ratios realized in FIG. 13 in ascending order and associates them with digital signal values. In this case, since there are 8 voltage division ratios, the resolution is 8. If the voltage dividing circuit is configured by a resistance variable element in this way, it is possible to obtain twice the resolution of the comparative example configured by a fixed resistor.

  In the present embodiment (FIG. 10), the resistor Rr is provided in the upper stage of the voltage dividing circuit and the resistance variable element group is provided in the lower stage, but conversely, the resistance variable element group is provided in the upper stage and the fixed resistance is provided. Even if it is provided in the lower stage, the same effect can be obtained.

  As described above, according to each embodiment of the present invention, a highly accurate and highly sensitive D / A converter circuit can be realized with a small area.

<Other embodiments>
Although the first and second embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:
(1) The embodiment shown in FIG. 15 is a modification of the first embodiment (FIG. 1). In FIG. 15, the illustration corresponding to the control circuit 302 in FIG. 1 is omitted. In the embodiment shown in FIG. 15, the resistance variable element R2k (k = 0 to n) corresponds to the resistance variable element R1k (k = 0 to n) in FIG. In the embodiment shown in FIG. 15, the positional relationship between the resistance variable element R2k (k = 0 to n) and the switch transistor SW1k (k = 0 to n) is opposite to that in FIG. The other points are the same as the configuration shown in FIG.

  According to the embodiment shown in FIG. 15, when the switch transistors SW0k (k = 0 to n) and SW1k (k = 0 to n) are laid out (arranged), the source of the switch transistor SW1k is the source of the switch transistor SW0k. Since the common diffusion region can be used, the layout area can be reduced.

  The data write operation in this embodiment is exactly the same as that in the first embodiment. However, in this embodiment, as shown in FIG. 15, the drain of the switch transistor S1k (k = 0 to n) and the free layer of the resistance variable element R2k (k = 0 to n) are connected. The layout connection shape of the resistance variable element R2k (k = 0 to n) is different from that of the resistance variable element R1k (k = 0 to n) of the first embodiment.

(2) The embodiment shown in FIG. 16 is an example in which the embodiment of FIG. 15 is further modified. In FIG. 16, the resistance variable element R3k (k = 0 to n) corresponds to the resistance variable element R2k (k = 0 to n) in FIG. However, the resistance variable element R2k (k = 0 to n) in FIG. 15 has the pin layer connected to the power supply VP2, whereas the resistance variable element R3k (k = 0 to n) in FIG. Is connected to the drain of the switch transistor SW1k (k = 0 to n).

  This variable resistance element R3k (k = 0 to n) has the pin layer connected to the drain of the switch transistor SW1k (k = 0 to n), so that the variable resistance element R1k (k) of the first embodiment is used. = 0 to n).

  Therefore, according to the present embodiment, the layout connection shape of the resistance variable element R3k (k = 0 to n) is made the same as that of the resistance variable element R1k (k = 0 to n) of the first embodiment. In addition, the source of the switch transistor SW0k (k = 0 to n) and the switch transistor SW1k (k = 0 to n) can be shared to reduce the layout area.

  In this embodiment, the direction of the resistance variable element R3k (k = 0 to n) between the power supplies VP3 and VP2 is opposite to that of the resistance variable element R1k (k = 0 to n) of the first embodiment. It is facing. Therefore, in this embodiment, when writing data to the resistance variable element R3k (k = 0 to n), a write voltage having a polarity opposite to that of the first embodiment is generated between the power supplies VP3 and VP2.

(3) In each of the above embodiments, the voltage dividing circuit formed of the resistance variable element is a D / A conversion circuit. However, the configuration of the D / A conversion circuit is not limited to the voltage dividing circuit. For example, a combined resistor in which a plurality of variable resistance elements are connected in series and a constant current source for supplying current to the variable resistance elements are provided. Depending on the digital signal value, the resistance value of each variable resistance element is high / low and whether there is a short circuit. And the voltage drop of the combined resistor at that time may be output as an analog signal corresponding to the digital signal value.

301, 311, 321, 331... Voltage divider circuit, 302, 312... Control circuit, R0k (k = 0 to n), R1k (k = 0 to n), Rk (k = 0 to n). Variable element, SW0k (k = 0 to n), SW1k (k = 0 to n), SWk (k = 0 to n)... Switch transistor, T1 .. write transistor, Rr... Fixed resistor, VP1, VP2 , VP3 …… Power supply.

Claims (9)

  A voltage dividing circuit for dividing a voltage between first and second power supply nodes and outputting the divided voltage to an analog voltage output node, wherein a plurality of circuits each having a switch and a resistance variable element connected in series are connected in parallel to each other. The first variable resistance switch circuit is provided between the first power supply node and the analog voltage output node, and a plurality of circuits each having a switch and a resistance variable element connected in series are connected in parallel to each other. A voltage dividing circuit having a second variable resistance switch circuit between the second power supply node and the analog voltage output node;
  A control circuit that performs control to apply a write voltage to the variable resistance element in the voltage dividing circuit and ON / OFF control of a plurality of switches in the voltage dividing circuit;
  A D / A conversion circuit comprising:   A write switch interposed between the analog voltage output node and a third power supply node;
  The control circuit turns on the write switch and the switch in the first or second variable resistance switch circuit, and between the first and third power supply nodes or between the second and third power supply nodes. 2. The D / A converter circuit according to claim 1, wherein a write voltage is applied to the resistance variable element in the first or second variable resistance switch circuit by applying a write voltage.   The control circuit applies a write voltage to one or a plurality of resistance variable elements in the first or second variable resistance switch circuit based on a digital signal to be converted; 3. The control according to claim 1, wherein one or a plurality of switches in the variable resistance switch circuit of 2 is turned on to control the voltage dividing circuit to output an analog signal corresponding to the digital signal. D / A conversion circuit.   A voltage dividing circuit for dividing a voltage between a first power supply node and a second power supply node and outputting the divided voltage to an analog voltage output node, having a fixed resistor between the first power supply node and the analog voltage output node. A voltage dividing circuit having a variable resistance switch circuit formed by connecting a plurality of circuits each having a switch and a resistance variable element connected in series with each other in parallel between the second power supply node and the analog voltage output node;
  A control circuit that performs control to apply a write voltage to the variable resistance element in the voltage dividing circuit and ON / OFF control of a plurality of switches in the voltage dividing circuit;
  A D / A conversion circuit comprising:   5. The output circuit according to claim 4, wherein when the analog signal is output to the voltage dividing circuit, the first power supply node is a high potential power supply node and the second power supply node is a low potential power supply node. D / A conversion circuit.   5. The method according to claim 4, wherein when the analog signal is output to the voltage dividing circuit, the second power supply node is a high potential power supply node, and the first power supply node is a low potential power supply node. D / A conversion circuit.   A write switch interposed between the analog voltage output node and a third power supply node;
  The control circuit turns on the write switch and the switch in the variable resistance switch circuit and applies a write voltage between the second and third power supply nodes to change the resistance in the variable resistance switch circuit. The D / A conversion circuit according to claim 4, wherein a write voltage is applied to the mold element.   The control circuit controls the application of a write voltage to one or more variable resistance elements in the variable resistance switch circuit based on a digital signal to be converted, and one or more in the variable resistance switch circuit The D / A conversion according to any one of claims 4 to 7, characterized in that a switch is turned on to control the voltage dividing circuit to output an analog signal corresponding to the digital signal. circuit.   9. The D / A conversion circuit according to claim 1, wherein the resistance variable element is a magnetic tunnel junction element or a resistance element in which an electric field induced giant resistance change occurs.

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