JP6132475B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device such as a liquid crystal display or a plasma display.

  In the image display apparatus as described above, the frame image corresponding to the input video signal is displayed on the display device (display element) sequentially at a period corresponding to the timing synchronization signal such as the horizontal synchronization signal and the vertical synchronization signal, thereby smoothly. The correct video. When the timing synchronization signal is output at a constant cycle suitable for the display device, it seems that the image is normally displayed to the human eye. However, when the timing synchronization signal is output in a cycle that does not match the display device, or when the timing synchronization signal deviates from the normal cycle due to a special operation, image disturbance that can be perceived by human eyes occurs.

  Patent Document 1 discloses a method of suppressing reverse transition of liquid crystal using a black insertion driving method when disturbance of a video signal input to a liquid crystal display device is detected. The disturbance of the video signal is a state in which the video signal becomes unstable, such as the moment when the frequency of the video signal changes from 50 Hz to 60 Hz. Further, the reverse transition of the liquid crystal is prevented by the black insertion driving method, thereby preventing the deterioration of the display image quality.

JP 2009-42659 A

  However, the liquid crystal display device disclosed in Patent Document 1 copes with disturbance of the video signal input from the outside, but does not cope with disturbance of the timing synchronization signal. Moreover, since the signal generation source applied to the data line in the liquid crystal device is switched in response to disturbance of the input video signal, the circuit scale tends to increase.

  The present invention provides an image display device that can suppress the disturbance of a display video when a disturbance of a timing synchronization signal occurs while suppressing an increase in circuit scale.

An image display apparatus according to an aspect of the present invention includes an image input unit that receives an input of an image signal from the outside, a display device that can display an image, and a plurality of pixels of the display device in a cycle of a timing synchronization signal. A display device drive unit that displays an image according to the image signal on the display device by applying a pixel voltage generated by sampling a lamp voltage that changes in a predetermined voltage range at a timing according to the image signal ; A control unit for fixing the lamp voltage to the predetermined voltage so that the predetermined voltage in the predetermined voltage range is sampled regardless of the timing for a predetermined period when disturbance of the timing synchronization signal occurs ; It is characterized by having .

  According to the present invention, it is possible to suppress the deterioration of the image quality of the display video when the timing synchronization signal is disturbed without increasing the circuit scale.

1 is a block diagram illustrating a configuration of an image display apparatus that is Embodiment 1 of the present invention. FIG. 3 is a diagram illustrating a configuration of a pixel in the image display device according to the first embodiment. FIG. 6 is a diagram illustrating sampling of the ramp voltage based on the CCLK count in the first embodiment. FIG. 3 is a diagram illustrating a relationship between a vertical synchronization signal and a horizontal synchronization signal in the first embodiment. The figure which shows the normal synchronizing signal and disordered synchronizing signal in Example 1. FIG. FIG. 3 is a diagram showing a lamp voltage in Example 1. FIG. 3 is a block diagram illustrating an application example of the image display apparatus according to the first embodiment to a projector. 3 is a control flowchart according to the first embodiment. FIG. 5 is a diagram illustrating a DA conversion unit of an image display apparatus that is Embodiment 2 of the present invention. The figure which shows operation | movement of the DA converter shown in FIG. FIG. 6 is a block diagram illustrating a configuration of an image display device according to a second embodiment. The figure which shows the relationship between the vertical synchronizing signal in Example 2, a horizontal synchronizing signal, and data. FIG. 6 is a diagram illustrating a pixel configuration in an image display apparatus according to a second embodiment. FIG. 6 is a diagram showing pixel voltages in Example 2. 7 is a control flowchart according to the second embodiment. The figure which shows CRST signal and CCLK output from a sampling control circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a configuration of a liquid crystal panel display unit included in an image display apparatus that is Embodiment 1 of the present invention. The liquid crystal panel display unit includes a liquid crystal display panel 100 as a display device capable of displaying an image, a panel drive unit 200 for driving the liquid crystal display panel 100, and a lamp voltage generation circuit 300 as a voltage generation unit. Yes. The panel drive unit 200 and the lamp voltage generation circuit 300 constitute a display device drive unit. Further, the liquid crystal display panel 100 displays an image in a display region 130 including a plurality of pixels (here, horizontal 1024 pixels × vertical 768 pixels corresponding to XGA resolution).

  The display device driving unit described here includes various optical devices and electronic devices such as a liquid crystal projector, a liquid crystal television, a mobile phone, a notebook computer, a digital still camera, and a car navigation device.

  A panel control circuit 210 in the panel drive unit 200 receives a digitized video input (input of an image signal) from a scaler (not shown) or the like and generates a drive control signal to the liquid crystal display panel 100. The same data sampling number detection circuit 230 detects the number of pixels in which the same gradation data (hereinafter referred to as the same data) is set from the video data subjected to various corrections such as gamma correction and color unevenness correction by the panel control circuit 210. To do. In the following description, the number of pixels for which the same data is set is referred to as the same data sampling number.

  The sampling control circuit 220 generates the voltage of the ramp voltage generation circuit 300, the voltage of the common electrode voltage generation circuit 301, and the liquid crystal display panel 100 according to the same data sampling number detected by the same data sampling number detection circuit 230. Control the drive.

  In the liquid crystal display panel 100, a display area 130, an H driving circuit 110, and a V shift register 120 as a scanning line driving circuit are provided. The H drive circuit 110 receives a drive control signal and video data from the panel control circuit 210 and a drive control signal from the sampling control circuit 220 and receives each horizontal pixel column (hereinafter referred to as a line) included in the display area 130. Drive the pixels.

  As shown in FIG. 2, the input data register 111 in the H drive circuit 110 sequentially receives video data subjected to various corrections such as gamma correction and color unevenness correction by the panel control circuit 210, and video data for N + 1 lines. Remember.

  The data memory 112 in the H drive circuit 110 stores the Nth line video data received by the input data register 111. The data comparator 113 compares the video data stored in the data memory 112 with the count value of CCLK which is a counter clock (sampling clock) input to the data comparator 113.

  Based on the output from the data comparator 113, the SW controller 114 converts the SW signal 132 for switching the analog SW 133 as a data line switch into a voltage that can turn the analog SW 133 ON / OFF, and outputs it.

  The ramp voltage generation circuit 300 generates a ramp voltage (RV) 131 as a sampling voltage that can be supplied to a plurality of video lines 134. Then, the analog SW 133 turns on / off the supply of the ramp voltage (RV) 131 to the video line 134 as a plurality of data lines wired so as to extend in the vertical direction to the display area 130. In XGA, 1024 video lines 134 are included in the display area 130, and an analog SW 133 is provided for each video line 134.

  The V shift register 120 receives the VS signal and the VCLK signal from the panel control circuit 210, and receives a V scanning signal (selection voltage) to a plurality of horizontal scanning lines 135 wired in the display area 130 so as to extend in the horizontal direction. Control the output of. In XGA, 768 horizontal scanning lines 135 are included in the display area 130. As will be described in detail later, the ramp voltage (RV) 131 is generated so as to monotonously change (monotonically increase) during a period in which the V scanning signal is applied to one horizontal scanning line 135.

  At a location where each horizontal scanning line (one scanning line) 135 and each video line (one data line) 134 intersect, a pixel transistor 136 as a pixel switching element, a pixel capacitor 137, and a liquid crystal (LC) 138 are provided. Is provided. These pixel transistor 136, pixel capacitor 137, and liquid crystal (LC) 138 constitute one pixel.

  A ramp voltage (RV) 131 supplied to the video line 134 via the analog SW 133 is connected to the drain of the pixel transistor 136. Thereby, the gate of the pixel transistor 136 is connected to the horizontal scanning line 135, and the on / off control of the pixel transistor 136 is performed by the V scanning signal from the horizontal scanning line 135.

  The pixel capacitor 137 is connected to the source of the pixel transistor 136, receives the ramp voltage applied to the video line 134, and charges the ramp voltage as a liquid crystal drive voltage (pixel voltage). The video line 134 is connected to the source of the pixel transistor 136, and the video line 134 itself as a wiring functions as a capacitor capacity, and forms a capacity (several hundred to several tens of thousands times) larger than the capacity of the pixel capacitor 137. The other end of the pixel capacitor 137 is connected to VcomC, which is a predetermined voltage.

  The liquid crystal (LC) 138 is charged to the pixel capacitor 137 and applied to a liquid crystal driving voltage (pixel voltage) (not shown) and a predetermined voltage VcomL applied to a transparent electrode (common electrode) (not shown). It is driven according to the potential difference that is the difference between The value of VcomL is set by the common electrode voltage generation circuit 301. The above-mentioned “same data” meaning the same gradation data can also be referred to as the same liquid crystal driving voltage.

  In this embodiment, when the liquid crystal driving voltage is close to zero, the light transmittance of the liquid crystal 138 is minimized and black is displayed, and the light transmittance increases as the liquid crystal driving voltage increases, so-called normally black mode. A case where the liquid crystal driving method is employed will be described.

  Subsequently, operations of the liquid crystal display panel 100 and the lamp voltage generation circuit 300 will be described in detail with reference to FIGS. 1 and 2.

  As described above, the panel control circuit 210 in the panel drive unit 200 receives video input and generates video data on which various corrections such as gamma correction and color unevenness correction have been performed. The generated video data is input to the H drive circuit 110 of the liquid crystal display panel 100 via the DATA line, and is also input to the same data sampling number detection circuit 230 in the panel drive unit 200.

  The video data input to the H drive circuit 110 is stored in the input data register 111 in the H drive circuit 110. The state at this time is shown in FIG. The input data register 111 stores video data as data D <b> 1 to D <b> 1024 in synchronization with HCLK starting from the HS signal that is a horizontal start signal from the panel control circuit 210. In the XGA resolution, 1024 pieces of data are stored as horizontal video data.

  The data memory 112 stores the Nth line video data received by the input data register 111. At this time, the video data of the (N + 1) th line which is the next line is input to the input data register 111.

  As shown in FIG. 16, the data comparator 113 includes a counter that counts CCLK starting from the CRST signal output from the sampling control circuit 220. Then, the data comparator 113 compares the video data stored in the data memory 112 with the count value by the counter.

  For example, if the video data has a 10-bit gradation and the data of D1 is 100, the data comparator 113 outputs a comparator to the SW controller 114 at CK100. For example, if the data of D2 is 4, the data comparator 113 outputs a comparator to the SW controller 114 at CK4. In this way, the data comparator 113 can perform 1024 comparator outputs in the horizontal direction.

  The SW controller 114 converts the voltage of the 1024 comparator outputs from the data comparator 113 and outputs a control signal to the 1024 analog SWs 133. By turning on / off the analog SW 133, the lamp voltage (RV) 131 output from the lamp voltage generation circuit 300 is controlled to be applied to or cut off from the video line 134.

  The 1024 analog SWs 133 are all turned on by the CRST signal and the lamp voltage (RV) 131 is applied to the video line 134. When the analog SW 133 receives the comparator output, the analog SW 133 is turned off, and the lamp voltage (RV) 131 is not applied to the video line 134 (blocking state).

  Next, generation of the ramp voltage in the ramp voltage generation circuit 300 will be described. In this embodiment, the case where the ramp voltage generation circuit 300 is a D / A converter that converts digital data into analog will be described. The sampling control circuit 220 is a clock for causing the D / A converter, which is the ramp voltage generation circuit 300, to update the data of the D / A converter, and D / ADATA, which is data instructing to increment the ramp voltage. Enter. D / ACLK and D / ADATA are output from the sampling control circuit 220 in synchronization with CCLK starting from the above-described CRST signal.

  Further, D / ADATA is output as data that is incremented according to the number of clocks of D / ACLK. For example, when the gradation of the ramp voltage generation circuit 300 is 10 bits, the ramp voltage generation circuit 300 generates a ramp waveform with a resolution of 1024. As a result, the D / A converter generates a ramp voltage that monotonously increases (monotonically changes) as shown in FIG.

That is, the ramp voltage (RV) 131 output from the ramp voltage generation circuit 300 becomes a predetermined start voltage at the time of inputting the CRST signal. 134 is applied. As described above, when the gradation of the ramp voltage generation circuit 300 is 10 bits and 1024 resolution, and the maximum voltage (Δ voltage) of the ramp voltage is 4V, the voltage represented by “D1: 100” is
{(100-1) / 1024} × 4V = 0.3867V
Thus, +0.3867 V is applied to the video line 134 with respect to the start voltage of the lamp voltage. The ramp voltage (RV) 131 is applied to the video line 134 as a voltage indicated by “D2: 4” in FIG. The voltage indicated by “D2: 4” is
{(4-1) / 1024} × 4 = 0.0117V
Thus, +0.0117 V is applied to the video line 134 with respect to the start voltage of the lamp voltage.

  Sampling from such a ramp voltage is performed, and a sampled voltage (liquid crystal driving voltage) is applied to 1024 video lines 134. The voltage applied to the video line 134 is connected to the gates of 1024 (H1 to H1024) pixel transistors 136 in one line by a V scanning signal output from the V shift register 120. Thereby, 1024 pixel transistors 136 are turned on.

  When the pixel transistor 136 is turned on, the video line 134 and the pixel capacitor 137 are connected via the pixel transistor 136, and the pixel transistor 136 is charged with a liquid crystal driving voltage sampled from the ramp voltage. In this way, the liquid crystal 138 is driven by the liquid crystal driving voltage charged in the pixel capacitors 137 of H1 to H1024.

  Upon receiving the vertical scanning start signal VS and the vertical scanning clock signal VCLK from the panel control circuit 210, the V shift register 120 sequentially outputs the V scanning signal output to the horizontal scanning line 135 from V1 to V768 in the vertical direction for each clock VCLK. Scan (select sequentially). By this scanning, it is possible to perform writing (charge) control of the liquid crystal driving voltage for all the pixels in the display region 130 of the liquid crystal display panel 100. Then, the liquid crystal 138 is driven according to the difference between VcomL applied to the transparent electrode and the liquid crystal drive voltage applied to the pixel electrode, and an image is displayed in the display area 130.

  Next, the operation when disturbance occurs in the timing synchronization signal (Vsync, Hsync: hereinafter also simply referred to as a synchronization signal) in the present embodiment will be described. FIG. 4 shows the relationship between the vertical synchronization signal Vsync corresponding to the above-described vertical scanning start signal VS and the horizontal synchronization signal Hsync corresponding to the horizontal scanning start signal.

  The liquid crystal driving voltage described above is applied to all pixels in the first line in the period from the first Hsync rise to the second Hsync rise, and two lines are applied from the second Hsync rise to the third Hsync rise. A liquid crystal driving voltage is applied to all the pixels of the eye. Thereafter, the liquid crystal driving voltage is applied to all the pixels up to the 768th line in the same manner. The period from the application of the liquid crystal drive voltage to the first pixel on the first line to the application of the liquid crystal drive voltage to the last pixel on the 768th line corresponds to one cycle (period) of Vsync, and 1 within the 1Vsync period. A frame image of the frame is displayed. Further, the frame image of the second frame is displayed within the next 1Vsync period.

  At this time, when Vsync and Hsync are output constantly, that is, at a constant cycle, the display on the liquid crystal display panel is normal and the image quality is good.

  However, there is a case where at least one of Vsync and Hsync is not constantly output and disturbance occurs. FIG. 5 shows an example of Vsync when it is not constantly output. A solid line indicates Vsync output at the original timing, and a broken line indicates Vsync whose timing is disturbed. The solid line Vsync rises at a timing of “1” and originally rises at a timing of “2”. However, when it rises at the timing “3” after the rise of the timing “1”, the liquid crystal driving voltage applied to each pixel is different from the original voltage. As a result, the video is disturbed during one frame up to the timing of “4” when Hsync is changed by PLL (Phase Locked Loop), and good image quality cannot be obtained.

Such disturbance of the synchronization signal often occurs due to a user operation in the image display apparatus. Examples of user operations include operations for performing keystone (trapezoidal distortion) correction, operations for performing frame lock when changing an input image signal, and the like. Of course, user operations other than these operations include operations that cause disturbances in Vsync and Hsync. Further, the cause of the disturbance of Vsync and Hsync may be an event other than the timing relationship as shown in FIG.

  In this way, when the synchronization signal is disturbed, in this embodiment, the operation of the display device drive unit is made different from the case where the disturbance is not generated for a predetermined period. Specifically, the following operation is performed.

  As described above, the ramp voltage is originally variable within a predetermined voltage range (a range of Δ4.0 V from the start voltage shown in FIG. 3) for each period of the synchronization signal, and the ramp voltage at the voltage sampling timing is the image voltage ( Applied to the pixel as a liquid crystal driving voltage).

  However, when the synchronization signal is disturbed, as shown in FIG. 6, the ramp voltage is set to the lower limit voltage value (in the predetermined voltage range) for a predetermined period (one cycle of the synchronization signal in FIG. 6). It is fixed to (Δ0 V) corresponding to the predetermined start voltage described above. As a result, a voltage higher than Δ0 V is not applied to the video line 134 in FIG. 2 at any timing of the predetermined period, and the liquid crystal display panel 100 driven in the normally black mode is not applied. The display area 130 which is a screen becomes black. Therefore, it is possible to prevent the image from being disturbed.

  Note that the value of the lamp voltage to be fixed when the synchronization signal is disturbed may not be Δ0V, but may be a value close to Δ0V (a voltage value on the lower limit side of the predetermined voltage range), for example, Δ0.2V. . In other words, the display area 130 may not be black, but may be gray if the image is not disturbed.

  The predetermined period for fixing the lamp voltage is not limited to one cycle of the synchronization signal, but may be any cycle until the disturbance of the synchronization signal is eliminated. The specific time may be calculated or measured in advance, and an operation that causes disturbance in the synchronization signal may be associated with a predetermined time and stored as table data.

  Next, the configuration of the image display apparatus according to the present embodiment will be described with reference to FIG. The image display apparatus includes an input unit 700, a control unit 710, a drive unit 720, and a projection unit 730.

  The input unit 700 includes an operation unit 701 that receives a user operation and an input IF (VGA, DVI, HDMI, etc.) 702 as an image input unit to which an image signal from the outside is input. The input unit 700 is provided with switches and remote control light receiving units for various user operations such as power ON / OFF operation, keystone correction command operation, and input image signal switching operation.

  The control unit 710 includes a CPU 711, an image processing unit 712, and a memory 713. The CPU 711 performs control of operations of each unit in the image display device, power management, error detection, and the like.

  The image processing unit 712 processes the image signal input from the input unit 700 (input IF 702). For example, when the resolution of the liquid crystal display panel 100 is XGA (1024 × 768) and the input image signal is WXGA (1280 × 800), the pixel of the liquid crystal display panel 100 is used to display the input image signal as it is. There are not enough numbers. For this reason, it is necessary to change (scaling) the format of the image signal. In addition, when the projection direction and the projection surface are not orthogonal, the image that should be projected as a rectangle originally becomes a trapezoid, which reduces visibility. For this reason, the keystone correction is performed according to the keystone correction command operation in the operation unit 701 so that the rectangular image can be displayed even in such a case.

  The memory 713 is used to temporarily store data when the CPU 711 or the image processing unit 712 performs processing.

  The drive unit 720 as the display device drive unit includes the panel drive unit 200 and the lamp voltage generation circuit 300 shown in FIG. The projection unit 730 includes the light source 731 and the liquid crystal display panel 100 shown in FIG. The light source 731 includes a cold cathode tube, a white LED, a high-pressure mercury lamp, and the like.

  FIG. 8 shows a flowchart of operation control executed by the control unit 710 (mainly the CPU 711) in the image display apparatus of the present embodiment. Here, as an example in which the synchronization signal is disturbed, a case where a keystone correction operation as a predetermined user operation is performed will be described as an example, but the predetermined operation may be performed by other operations such as an operation for performing frame lock. User operation may be sufficient.

  First, in step S100, the CPU 711 starts the following process in response to the power switch being turned on.

  Next, in step S101, the CPU 711 determines whether an input operation other than the operation of the power switch has been performed on the operation unit 701. If there is no input operation, the CPU 711 repeats this step and waits for the input operation. On the other hand, if there is an input operation, the CPU 711 proceeds to step S102, and whether or not the input operation performed in step S101 is an operation that causes the above-described disturbance in the synchronization signal, that is, whether or not it is a keystone correction operation. Determine whether. In other words, the disturbance of the synchronization signal is detected when a keystone correction operation (predetermined operation) is performed by the operation unit 701. In this step, the synchronization signal may be directly monitored to detect disturbance of the synchronization signal.

  If the keystone correction operation has been performed, the CPU 711 proceeds to step S103, and if the keystone correction operation has not been performed, the process proceeds to step S107.

  In step S103, the CPU 711 sends a lamp fixing instruction signal to the panel driving unit 200, and fixes the lamp voltage generated by the lamp voltage generating circuit 300 to the lower limit value Δ0V (or the lower limit side voltage value) as described above.

  In step S104, the CPU 711 performs an operation for keystone correction. Specifically, a trapezoidal image whose direction is opposite to that of the trapezoid of the image projected on the projection surface is displayed on the liquid crystal display panel 100. However, since the lamp voltage is still fixed to the lower limit value Δ0 V (or the lower limit voltage value) here, the keystone correction image is not displayed on the liquid crystal display panel 100.

  Next, in step S105, the CPU 711 stands by for the predetermined time until the disturbance of the synchronization signal is resolved. Then, after the synchronization signal is stabilized, in step S106, the CPU 711 sends a lamp fixing release instruction signal to the panel driving unit 200, and causes the lamp voltage generation circuit 300 to resume normal generation of the ramp voltage that increases monotonously. For the first time, the keystone correction image is displayed on the liquid crystal display panel 100.

  On the other hand, in step S107, the CPU 711 causes the lamp voltage generation circuit 300 to generate a normal lamp voltage through the panel driving unit 200. As a result, a normal rectangular image is displayed on the liquid crystal display panel 100, and the rectangular image is also projected on the projection surface.

  As described above, in this embodiment, when the occurrence of the disturbance of the synchronization signal is detected, the operation of the drive unit 720 is made different for a predetermined period from the normal case where the disturbance is not detected. Specifically, the lamp voltage is fixed to the lower limit voltage value (or the lower limit voltage value) of a predetermined voltage range that is the variable range. As a result, it is possible to suppress the deterioration of the image quality of the display video when the synchronization signal is disturbed without increasing the circuit scale.

  Next, a second embodiment of the present invention will be described. The basic configuration of the image display apparatus of the present embodiment is as shown in FIG. However, in this embodiment, instead of the lamp voltage generation circuit 300 included in the driving unit 720 and the liquid crystal display panel 100 included in the projection unit 730 of the first embodiment, a DA converter (voltage) shown in FIG. Generator) 900 and liquid crystal display panel 1100 are used. Further, part of the signal output from the panel drive unit 200 included in the drive unit 720 is also different from that in the first embodiment (however, the panel drive unit is denoted by the same reference numeral 200 as in the first embodiment).

  The DA conversion unit 900 receives the CLK, DATA, Latch signal, and INV signal from the panel drive unit 200 and generates Video0 to Video7 that are liquid crystal drive signals (pixel voltages). Input / output timings of the input CLK, DATA, and Latch signals and the output Video0 to Video7 are shown in FIGS.

  The panel driving unit 200 transfers DATA for Video output to a register (not shown) in the DA conversion unit 900 at the rising edge of CLK. In addition, the panel driving unit 200 causes the DA conversion unit 900 to invert +/− of the video output, which is an analog voltage, with respect to a predetermined center voltage in accordance with the input DATA in accordance with the INV signal. Here, it is assumed that the video output is 8 channels. The DA converter 900 latches DATA at the rising edge of the Latch signal after transferring DATA for 8 clocks. The DA converter 900 updates the Video signal to the DATA Video signal before the Latch signal rises at the rising edge of CLK after the Latch signal falls. By repeating this, the DA converter 900 generates and outputs a liquid crystal drive signal to the liquid crystal display panel 1100.

  As shown in FIG. 11, the liquid crystal display panel 1100 includes an H shift register 1110, a V shift register 1120, and a display area 1130. The liquid crystal display panel 1100 performs the H scanning operation shown in the upper diagram of FIG. Specifically, the H shift register 1110 uses the HS signal as the reset signal and start signal for the H shift register. Then, while updating the liquid crystal drive signals of Video0 to Video7 every HCLK clock, the eight signal lines arranged in the vertical direction are turned on to perform H scanning. HCLK and the Latch signal shown in FIGS. 10A to 10C have the same frequency.

  For example, when the resolution of the liquid crystal display panel 1100 is XGA (1024 × 768), the H scan of the liquid crystal display panel 1100 is performed with 128 clocks of HCLK. Then, H scanning of the next line is performed using the next HS signal as a reset signal and start signal for the H shift register 1110. Actually, the H scan is performed with the number of clocks obtained by adding so-called blanking of several clocks to 128 clocks of HCLK necessary for the H scan.

  The V scan is performed using the VS signal as a reset signal and a start signal for the V shift register 1120, as shown in the lower diagram of FIG. The V shift register 1120 shifts the H line for each clock of VCLK, and performs V scanning with 768 clocks of VCLK. Actually, similarly to the H scan, the V scan is performed with the number of clocks obtained by adding blanking of several clocks to the 768 clocks of VCLK necessary for the V scan. Note that the number of blanking clocks is arbitrary.

  A pixel voltage as a liquid crystal drive signal Video0 to Video7 (hereinafter referred to as Video voltage) is applied to the pixels in the display area 1130 of the liquid crystal display panel 1100 by each of the H scan and the V scan.

  The display area 1130 is configured as shown in FIG. As described above, the H shift register 1110 operates according to HCLK, turns on the transfer SW 1345 by the H shift register output 1348, and applies the Video voltage 1349 input from the DA converter 900 to the signal line 1347. The V shift register output 1346 from the V shift register 1120 drives the gate of the NMOS 1341 and accumulates the Video voltage in the pixel capacitor 1342. At this time, the voltage Vcom is applied to the counter electrode of the pixel capacitor 1342 and the LC 1343.

  FIG. 14 shows the relationship between the voltage Vcom and the video voltage from the DA converter 900. Video voltages ΔV1 and ΔV2 are voltages applied to the actual pixel capacitors 1342 and LC 1343 with reference to Vcom. The reason why ΔV1 and ΔV2 are in the vertical direction with respect to Vcom is that there is a voltage when the INV signal is input to the DA converter 900 and inverted. At this time, the peak of ΔV is determined by the reference voltage Vref input to the DA converter 900 as shown in FIG. The LC 1343 that is a liquid crystal changes the transmittance of light polarized by a polarizing plate (not shown) according to the accumulated voltage of the pixel capacitor 1342.

  Also in this embodiment, when the occurrence of the disturbance of the synchronization signal is detected, the operation of the drive unit 720 is made different for a predetermined period from the normal case where the disturbance is not detected. Specifically, the reference voltage Vref input from the panel drive unit 200 to the DA conversion unit 900 is set to a voltage with a gain of 0 based on the specifications of the DA conversion unit 900. By setting the gain to 0, the Video voltage output from the DA conversion unit 900 matches Vcom no matter what DATA is input to the DA conversion unit 900. In other words, during a predetermined period (for example, one cycle of the synchronization signal), the pixel voltage is fixed to Video0 that is the lower limit value of the predetermined voltage range (Video0 to Video7) that is the variable range and matches Vcom. As a result, the display area 1130 which is the screen of the liquid crystal display panel 1100 driven in the normally black mode becomes black. Therefore, it is possible to prevent the image from being disturbed.

  Note that the gain of the DA converter 900 that is set when the synchronization signal is disturbed does not have to be 0, and is a value close to 0, where the pixel voltage is a voltage value on the lower limit side of the predetermined voltage range (for example, Video1). It may be. In other words, the display area 130 may not be black, but may be gray if the image is not disturbed.

  FIG. 15 shows a flowchart of operation control executed by the control unit 710 (mainly the CPU 711) in the image display apparatus of the present embodiment. Here, a case where a keystone correction operation is performed as a predetermined user operation that causes a disturbance in the synchronization signal will be described as an example, but other user operations such as an operation for performing a frame lock may be used. .

  First, in step S1500, the CPU 711 starts the following process in response to the power switch being turned on.

  Next, in step S1501, the CPU 711 determines whether an input operation other than the operation of the power switch has been performed on the operation unit 701. If there is no input operation, the CPU 711 repeats this step and waits for the input operation. On the other hand, if there is an input operation, the CPU 711 proceeds to step S1502 and determines whether or not the input operation performed in step S1501 is an operation that causes the above-described disturbance in the synchronization signal, that is, whether or not it is a keystone correction operation. Determine whether. In other words, the disturbance of the synchronization signal is detected when the keystone correction operation is performed by the operation unit 701. In this step, the synchronization signal may be directly monitored to detect disturbance of the synchronization signal.

  If the keystone correction operation has been performed, the CPU 711 proceeds to step S1503, and if the keystone correction operation has not been performed, the process proceeds to step S1507.

  In step S1503, the CPU 711 sends a 0 gain setting instruction signal to the panel drive unit 200 to set the gain of the DA conversion unit 900 to 0 (or a value close to 0).

  In step S1504, the CPU 711 performs an operation for keystone correction described in the first embodiment. However, since the gain of the DA converter 900 is still set to 0 (or a value close to 0) here, the keystone correction image is not displayed on the liquid crystal display panel 100.

  Next, in step S1505, the CPU 711 stands by for the predetermined time until the disturbance of the synchronization signal is resolved. The predetermined period is not limited to one period of the synchronization signal, but may be any period until the disturbance of the synchronization signal is eliminated. The specific time may be calculated or measured in advance, and an operation that causes disturbance in the synchronization signal may be associated with a predetermined time and stored as table data.

  After the synchronization signal is stabilized, in step S1506, the CPU 711 sends a 0 gain setting release signal to the panel drive unit 200, and performs a normal gain setting operation for generating the liquid crystal drive signals Video0 to Video7 to the DA conversion unit 900. Let it resume. For the first time, the keystone correction image is displayed on the liquid crystal display panel 1100.

  On the other hand, in step S <b> 1507, the CPU 711 causes the DA converter 900 to perform a normal gain setting operation through the panel driver 200. As a result, a normal rectangular image is displayed on the liquid crystal display panel 100, and the rectangular image is also projected on the projection surface.

  In each of the above embodiments, the liquid crystal display driven in the normally black mode is fixed by fixing the pixel voltage to the lower limit value or the lower limit voltage value of the predetermined voltage range in response to detecting the disturbance of the synchronization signal. The case where the panel screen is black (or gray) has been described. However, the screen of the liquid crystal display panel may be blackened by other methods. For example, the voltage VcomL applied to the common electrode of the liquid crystal display panel may be changed so that the difference from the pixel voltage is zero or small.

  Also, when the screen of the liquid crystal display panel is blackened, the light amount of the light source of the image display device is reduced, the light emission of the light source is stopped, or the light path from the light source to the liquid crystal display panel is blocked. Good.

  Each embodiment described above is only a representative example, and various modifications and changes can be made to each embodiment in carrying out the present invention.

  An image display device such as a projector that can display a high-quality image can be provided.

DESCRIPTION OF SYMBOLS 100 Liquid crystal display panel 200 Panel drive part 300 Lamp voltage generation circuit 702 Input IF
711 CPU

Claims (3)

An image input unit for receiving an input of an image signal from the outside;
A display device capable of displaying images;
In each of a plurality of pixels of said display device in a period of timing synchronization signals, by applying the picture element voltage generated by sampling at a timing corresponding to the lamp voltage varying in a predetermined voltage range to the image signal, A display device driving unit for displaying an image according to the image signal on the display device;
When the timing synchronization signal is disturbed, the lamp voltage is supplied to the display device driver for a predetermined period so that the predetermined voltage in the predetermined voltage range is sampled regardless of the timing. An image display device comprising: a control unit to be fixed.   The image display apparatus according to claim 1, wherein the predetermined voltage is a lower limit value of the predetermined voltage range.   The control unit causes the display device driving unit to fix the lamp voltage to the predetermined voltage during the predetermined period in response to a predetermined operation that causes the disturbance as a user operation. The image display device according to claim 1 or 2.