JP6132655B2 - Signal processing circuit and capsule endoscope - Google Patents

Description

  The present invention relates to a signal processing circuit and a capsule endoscope having the signal processing circuit.

  FIG. 16 shows the configuration of the GmC filter circuit described in Patent Document 1. The GmC filter circuit 1 shown in FIG. 16 includes an OTA (Operational Transducer Amplifier) circuit 2 and a capacitor C. When the input signal to the GmC filter circuit 1 is Vin, the output signal of the GmC filter circuit 1 is Vout, the capacitance of the capacitor C is C, and the transconductance value of the OTA circuit 2 is Gm, the output signal Vout is Vout = (Gm · Vin) / jωC. The cutoff frequency Fc of the GmC filter circuit 1 is determined by Fc = Gm · Vin / C.

JP 2009-33323 A

  In general, the transconductance Gm of the OTA circuit is approximately proportional to the circuit current or approximately proportional to the square root of the circuit current. Therefore, in order to reduce the current consumption of the conventional GmC filter while maintaining the same cut-off frequency Fc, the capacitance of the capacitor C may be reduced. However, since there is a limit in reducing the capacitance of the capacitor C due to the limit of the manufacturing process, there is a limit in reducing the current consumption.

  A sample and hold circuit having a switch that can be switched on and off may be inserted between the OTA circuit 2 and the capacitor C. The above problem also suggests the limitation of reducing the power consumption of the OTA circuit that exists as a means for realizing a driver circuit for driving the sample and hold circuit. This is because an OTA circuit 2 and a capacitor C are used to drive a sample-and-hold circuit that periodically performs a sample operation and a hold operation so that an error that occurs during the sample operation is a predetermined value or less. This is because the cutoff frequency (Fc = Gm · Vin / C) of the GmC filter needs to be larger than a predetermined value.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a signal processing circuit and a capsule endoscope that can reduce power consumption of a driver circuit that drives a sample-and-hold circuit. To do.

The present invention has been made to solve the above-described problem, and a plurality of voltage signals are time-divided and sequentially output as a first signal sequence, and the plurality of voltage signals are simultaneously parallelized as a second signal sequence. Output signal sequence generating circuit, the second signal sequence is input, the maximum signal corresponding to the substantially maximum value of the plurality of voltage signals, and the minimum signal corresponding to the approximately minimum value of the plurality of voltage signals And a bias control circuit that receives the maximum signal and the minimum signal and outputs a bias control signal that changes in accordance with the difference between the maximum signal and the minimum signal; A driver circuit that receives the first signal string and the bias control signal and outputs a driver output voltage obtained by converting the first signal string with a transconductance according to the bias control signal; and the driver Power voltage is input, possess behavior and for sampling the driver output voltage at a sample period, the sample and hold circuit to repeat the operation and for holding the driver output voltage in a holding period, wherein the transconductance of the driver circuit Is a signal processing circuit controlled by the bias control signal so that the value increases when the difference between the maximum signal and the minimum signal increases and decreases when the difference decreases. .

  In addition, the signal processing circuit of the present invention includes an AD converter that has the sample and hold circuit in an input stage and outputs an analog signal held in the sample and hold circuit to the outside as an AD conversion signal that is a digital signal. It is characterized by having.

In the present invention, a signal string generation circuit that outputs a first signal string by repeatedly time-dividing a plurality of voltage signals at a predetermined frame period, the first signal string and a bias control signal are input. A driver circuit that outputs a driver output voltage obtained by converting the first signal sequence with a transconductance according to the bias control signal; and an operation that inputs the driver output voltage and samples the driver output voltage in a sample period; An AD converter having a sample-and-hold circuit that repeats the operation of holding the driver output voltage in a holding period in an input stage, and outputting an analog signal held in the sample-and-hold circuit as an AD conversion signal that is a digital signal A maximum signal corresponding to a substantially maximum value of the AD conversion signal, and a minimum of the AD conversion signal And a second value after the first frame based on the difference between the maximum signal and the minimum signal output to the first frame. A bias control circuit for predicting a difference between the maximum signal and the minimum signal output in a frame of the first frame and outputting the bias control signal corresponding to the first signal sequence output in the second frame; have a, the transconductance of the driver circuit, the maximum signal and the difference between the minimum signal increases the value increases, as the value when the difference is decreased to decrease, controlled by the bias control signal a signal processing circuit, characterized in that that.

  In the signal processing circuit of the present invention, the transconductance of the driver circuit is controlled by a function that increases when the difference between the maximum signal and the minimum signal increases and decreases when the difference decreases. It is characterized by that.

In the signal processing circuit of the present invention, the sample and hold circuit includes a sampling switch that is controlled to be turned on and off by a sampling clock, and a sampling capacitor having a capacitance value of _CSH , and the sampling switch Is set to ts, the sampling error allowed in the sample and hold circuit is ε, and the voltage difference between the maximum signal and the minimum signal is V _{CONT_MAX} ,
The bias control circuit controls the bias control signal so that the driver circuit operates with a transconductance gm satisfying

  In the signal processing circuit of the present invention, the signal string generation circuit is arranged on a plane of a semiconductor substrate, and includes a pixel string having a plurality of light receiving elements that generate the voltage signal according to the amount of received light, and a first terminal And a second terminal, the first terminal is connected to each of the light receiving elements, the second terminal is connected to each other, and a plurality of switches that can be switched on and off, and The voltage signals generated by the plurality of light receiving elements are sequentially output as the first signal sequence by sequentially switching the switches, and the voltages generated by the plurality of light receiving elements. A signal is output as a second signal sequence in parallel to signal lines provided corresponding to each of the plurality of light receiving elements.

  In the signal processing circuit of the present invention, the maximum value / minimum value detection circuit includes a plurality of NMOS transistors and a first current source having a first terminal and a second terminal, and the plurality of NMOS transistors. Each of the plurality of light receiving elements is connected to all or part of the plurality of light receiving elements, each drain terminal of the plurality of NMOS transistors is connected to a first power supply, and each source terminal of the plurality of NMOS transistors is connected Are connected to each other, the first terminal of the first current source is connected to all source terminals of the plurality of NMOS transistors, and the second terminal of the first current source is connected to a second power source. A maximum value detection circuit for outputting the maximum signal from a portion where the source terminal of the NMOS transistor and the first terminal of the first current source are connected; A plurality of PMOS transistors and a second current source having a first terminal and a second terminal, each gate terminal of the plurality of PMOS transistors being connected to all or a part of the plurality of light receiving elements. Each drain terminal of the plurality of PMOS transistors is connected to the second power source, each source terminal of the plurality of PMOS transistors is connected to each other, and the first terminal of the second current source is the PMOS Connected to all source terminals of the transistor, the second terminal of the second current source is connected to the first power source, the source terminal of the PMOS transistor, and the first terminal of the second current source And a minimum value detection circuit that outputs the minimum signal from a portion connected to.

  In the signal processing circuit of the present invention, the driver circuit includes a tail current source whose output current is controlled by the bias control signal, and a predetermined transformer corresponding to the value of the output current input from the tail current source. A differential pair circuit that outputs a current corresponding to a difference between voltages input to an inverting input terminal and a non-inverting input terminal, and a load that outputs a voltage corresponding to the current input from the differential pair circuit. And a circuit.

  The present invention also includes a pixel column having a plurality of light receiving elements arranged on a plane of a semiconductor substrate and generating the voltage signal corresponding to the amount of received light, in the signal column generation circuit, and corresponding to the voltage signal. An image for performing image processing based on the AD conversion signal input from the signal processing circuit that outputs an AD conversion signal, an objective lens that forms an image of a light beam input from a subject on the pixel array, and the signal processing circuit A capsule endoscope comprising: a processing circuit; and a power supply circuit that supplies power to the signal processing circuit and the image processing circuit.

  According to the present invention, the bias control circuit outputs a bias control signal that changes according to the difference between the maximum signal and the minimum signal output from the maximum value / minimum value detection circuit. Alternatively, the bias control circuit predicts the difference between the maximum signal and the minimum signal output in the next frame based on the difference between the maximum signal and the minimum signal output in the previous frame and outputs the difference in the next frame. A bias control signal corresponding to the output first signal sequence is output. Then, the driver circuit outputs a driver output voltage obtained by converting the first signal sequence with transconductance according to the bias control signal. Thereby, the power consumption of the driver circuit can be reduced.

1 is a block diagram showing a configuration of a signal processing circuit according to a first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a signal string generation circuit according to a first embodiment of the present invention. It is a timing chart which shows operation | movement of the light receiving element which concerns on the 1st Embodiment of this invention. 3 is a timing chart illustrating a signal read operation according to the first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a maximum / minimum value detection circuit according to a first embodiment of the present invention. 1 is a block diagram showing a configuration of a bias control circuit, a driver circuit, and a sample and hold circuit according to a first embodiment of the present invention. 3 is a timing chart illustrating an operation of the sample and hold circuit according to the first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a driver circuit according to a first embodiment of the present invention. It is a graph which shows the relationship between the electric current which flows into the differential pair which concerns on the 1st Embodiment of this invention, and transconductance. 1 is a circuit diagram showing a configuration of a tail current source according to a first embodiment of the present invention. It is a block diagram which shows the structure of the capsule endoscope which concerns on the 2nd Embodiment of this invention. It is a reference figure showing the stomach wall of a human body which is a subject of a capsule endoscope concerning a 2nd embodiment of the present invention. It is a block diagram which shows the structure of the signal processing circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the signal sequence generation circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the transconductance amplifier in the driver circuit based on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the conventional GmC filter circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
<Configuration of signal processing circuit>
The configuration of the signal processing circuit SIG_PROC_CIR according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows the configuration of the signal processing circuit SIG_PROC_CIR. The signal processing circuit SIG_PROC_CIR includes a signal string generation circuit SIG_ARY_GEN, a maximum / minimum value detection circuit MAX_MIN_DETECT, a bias control circuit BIAS_GEN, a driver circuit DRV_CIR, and an AD converter ADC. These structures are formed on the same semiconductor chip.

  The signal string generation circuit SIG_ARY_GEN time-divides a voltage signal group composed of a plurality of voltage signals (DC voltage signals) and sequentially outputs the voltage signal group to the driver circuit DRV_CIR as a first signal string SIG_ARY1, while the second voltage signal group Are simultaneously output in parallel to the maximum value / minimum value detection circuit MAX_MIN_DETECT as the signal sequence SIG_ARY2. The maximum value / minimum value detection circuit MAX_MIN_DETECT receives the second signal sequence SIG_ARY2, receives the maximum signal Vmax corresponding to the maximum value of the voltage signal group constituting the second signal sequence SIG_ARY2, and the minimum value of the voltage signal group. A corresponding minimum signal Vmin is generated and output to the bias control circuit BIAS_GEN.

  The bias control circuit BIAS_GEN receives the maximum signal Vmax and the minimum signal Vmin, generates a bias control signal gm_ctrl that changes according to the difference between the maximum signal Vmax and the minimum signal Vmin, and outputs it to the driver circuit DRV_CIR. The driver circuit DRV_CIR receives the first signal sequence SIG_ARY1 and the bias control signal gm_ctrl, and converts the first signal sequence SIG_ARY1 into the driver output voltage V_DRVOUT with a driving force (transconductance) corresponding to the bias control signal gm_ctrl. And output to the AD converter ADC.

  The AD converter ADC receives the driver output voltage V_DRVOUT, and inputs a sample-and-hold circuit SHC that repeats the operation of sampling the driver output voltage V_DRVOUT in the sample period and the operation of holding the driver output voltage V_DRVOUT in the holding period. Have. The AD converter ADC converts the analog signal held in the sample and hold circuit SHC into an AD conversion signal AD_SIG that is a digital signal and outputs the AD signal to the outside of the signal processing circuit SIG_PROC_CIR. Details of the internal configuration of each block and each signal will be described later.

<Signal string generation circuit>
[Constitution]
Hereinafter, the configuration of the signal string generation circuit SIG_ARY_GEN will be described in more detail with reference to FIG. FIG. 2 shows a configuration of the signal string generation circuit SIG_ARY_GEN. The signal column generation circuit SIG_ARY_GEN includes a pixel column PD_ARY and a switch column SW_ARY.

  The pixel column PD_ARY is arranged on the plane of the semiconductor substrate and generates n (n: integer of 2 or more) light receiving elements PD [1] to PD [n] that generate pixel signals that are voltage signals according to the amount of received light. Have The switch row SW_ARY can be switched on and off by a control signal (not shown), and has n switches SW [1] to SW [n] having a first terminal and a second terminal.

  The n light receiving elements PD [1] to PD [n] are respectively connected to the first terminals of the corresponding numbered switches SW [1] to SW [n], and the pixel signals VPD [1] to VPD. [N] is output to the first terminals of the switches SW [1] to SW [n]. Further, the n light receiving elements PD [1] to PD [n] are connected to the maximum value / minimum value detection circuit MAX_MIN_DETECT described with reference to FIG. The pixel signals VPD [1] to VPD [n] are output to the maximum value / minimum value detection circuit MAX_MIN_DETECT. n signal lines connecting the n light receiving elements PD [1] to PD [n] and the maximum / minimum value detection circuit MAX_MIN_DETECT are arranged, and the pixel signal VPD [1 is connected to each of these n signal lines. ] To VPD [n] are output.

  The second terminals of the switches SW [1] to SW [n] are connected to each other. For example, the second terminals of the switches SW [1] to SW [n] are commonly connected to the output signal line connected to the output terminal of the signal string generation circuit SIG_ARY_GEN.

  The signal string generation circuit SIG_ARY_GEN having the above-described configuration generates pixel signals VPD [1] to VPD [n] generated by the light receiving elements PD [1] to PD [n] by sequentially switching the switches that are turned on. The signals are sequentially switched and sequentially output as the first signal sequence SIG_ARY1. The signal string generation circuit SIG_ARY_GEN uses the pixel signals VPD [1] to VPD [n] generated by the light receiving elements PD [1] to PD [n] as the second signal string SIG_ARY2, and receives the light receiving element PD [1]. Are simultaneously output in parallel via signal lines arranged corresponding to each of PD [n].

[Operation sequence]
Hereinafter, the operation of the signal string generation circuit SIG_ARY_GEN will be described in more detail with reference to FIGS. First, the operation of the light receiving element PD [k] (k: an arbitrary integer satisfying 1 ≦ k ≦ n) will be described with reference to FIG. FIG. 3 is a timing chart for explaining the exposure operation of the light receiving element PD [k]. The horizontal axis of this timing chart is time, and the vertical axis is voltage level.

  The light receiving element PD [k] is reset to the OB level Vob by a control signal (not shown) in the reset period RESET_T. The OB level Vob is a voltage signal generated when the light receiving element PD [k] is reset and the accumulated charge amount becomes zero. When the reset period RESET_T ends, the accumulation period INTEG_T starts. During the accumulation period INTEG_T, the light receiving element PD [k] generates a charge corresponding to the amount of light incident from the outside, and outputs a voltage signal corresponding to the generated charge. When the amount of incident light is large, the slope of the slope indicating the change in the pixel signal VPD [k] during the accumulation period INTEG_T becomes steep, and the pixel signal VPD [k] approaches the saturation level Vsat in a shorter time. The saturation level Vsat is a voltage signal corresponding to the maximum amount of charge that can be accumulated in the light receiving element PD [k]. When the amount of light incident on the light receiving element PD [k] and the accumulation period are appropriately controlled, the pixel signal VPD [k] is kept between the saturation level Vsat and the OB level Vob. When the accumulation period INTEG_T ends, the transfer period TRAN_T starts, and the pixel signal VPD [k] at this time is read out.

  Hereinafter, a signal read operation for reading the pixel signals VPD [1] to VPD [n] from the light receiving elements PD [1] to PD [n] during the transfer period TRAN_T will be described with reference to FIG. FIG. 4 is a timing chart for explaining a signal read operation during the transfer period TRAN_T. The horizontal axis represents time, and the vertical axis represents voltage level.

  First, a reading sequence of the light receiving element PD [k] in the transfer period TRAN_T will be described. The transfer period TRAN_T starts at time t [1] and ends at time t [n + 1]. During this period, one of the switches SW [1] to SW [n] is turned on, the rest are turned off, and the switches that are turned on are sequentially switched, so that the light receiving element PD [k] constituting the voltage signal group G1. Pixel signals VPD [k] are sequentially read out.

The period in which the pixel signal VPD [k] of the light receiving element PD [k] is read starts at time t [k] and ends at time t [k + 1]. In FIG. 4, the minimum level pixel signal output during the transfer period TRAN_T is VPD [3], and the maximum level pixel signal is VPD [n]. Hereinafter, the difference between the minimum level signal and the maximum level signal is defined as the maximum contrast V _{CONT_MAX} .

The range of voltage that can be taken by the pixel signal VPD [k] is the range from the OB level Vob to the saturation level Vsat. Hereinafter, the difference between the OB level Vob and the saturation level _Vsat is defined as a maximum amplitude V _{SWING_MAX} . The OB level Vob corresponds to a pixel signal output when no light strikes the light receiving element PD [k]. The saturation level Vsat corresponds to a pixel signal output when the charge generated in the light receiving element PD [k] by photoelectric conversion reaches the maximum accumulation amount.

When the transfer period TRAN_T ends, the reset period RESET_T starts. When the reset period RESET_T ends, the accumulation period INTEG_T starts. When the accumulation period INTEG_T ends, a new transfer period TRAN_T ′ starts. The transfer period TRAN_T ′ starts at time t ′ [1] and ends at time t ′ [n + 1]. In this period, the pixel signal VPD [k] of the light receiving element PD [k] constituting the voltage signal group G2 is sequentially read. Hereinafter, the difference between the minimum level signal and the maximum level signal obtained during the transfer period TRAN_T ′ is defined as the maximum contrast V ′ _{CONT_MAX} .

<Maximum / minimum value detection circuit>
[Constitution]
Hereinafter, the maximum value / minimum value detection circuit MAX_MIN_DETECT will be described with reference to FIG. FIG. 5 shows a configuration of the maximum value / minimum value detection circuit MAX_MIN_DETECT. The maximum value / minimum value detection circuit MAX_MIN_DETECT includes a maximum value detection circuit MAX_DETECT and a minimum value detection circuit MIN_DETECT.

  The maximum value detection circuit MAX_DETECT detects the maximum value from the pixel signals VPD [1] to VPD [n] constituting the input second signal sequence SIG_ARY2, and outputs the maximum signal Vmax corresponding to the detected maximum value. Output. The minimum value detection circuit MIN_DETECT detects the minimum value from the pixel signals VPD [1] to VPD [n] constituting the input second signal sequence SIG_ARY2, and outputs the minimum signal Vmin corresponding to the detected minimum value. Output.

  The maximum value detection circuit MAX_DETECT includes n NMOS transistors Tr1 [1] to Tr1 [n] and a first current source Iconst1 having a first terminal and a second terminal. The minimum value detection circuit MIN_DETECT includes n PMOS transistors Tr2 [1] to Tr2 [n] and a second current source Iconst2 having a first terminal and a second terminal.

  The gate terminals of the NMOS transistors Tr1 [1] to Tr1 [n] are connected to the light receiving elements PD [1] to PD [n] shown in FIG. 2, respectively, and the pixel signals VPD [1] to VPD [n] are connected. ] Is entered. The drain terminals of the NMOS transistors Tr1 [1] to Tr1 [n] are connected to the first power supply VDD, respectively, and the source terminals of the NMOS transistors Tr1 [1] to Tr1 [n] are connected to each other, respectively. , Connected to the first terminal of the first current source Iconst1. The maximum signal from the portion where the source terminals of the NMOS transistors Tr1 [1] to Tr1 [n] and the first terminal of the first current source Iconst1 are connected (for example, one node on the signal line connecting them). Vmax is output. The second terminal of the first current source Iconst1 is connected to the second power supply VSS.

  The gate terminals of the PMOS transistors Tr2 [1] to Tr2 [n] are connected to the light receiving elements PD [1] to PD [n] shown in FIG. 2, respectively, and the pixel signals VPD [1] to VPD [n] are connected. ] Is entered. The drain terminals of the PMOS transistors Tr2 [1] to Tr2 [n] are connected to the second power supply VSS, respectively, and the source terminals of the PMOS transistors Tr2 [1] to Tr2 [n] are connected to each other, respectively. Are connected to the first terminal of the second current source Iconst2. The minimum signal from the portion where the source terminals of the PMOS transistors Tr2 [1] to Tr2 [n] and the first terminal of the second current source Iconst2 are connected (for example, one node on the signal line connecting them). Vmin is output. The second terminal of the second current source Iconst2 is connected to the first power supply VDD.

[Operating principle]
Hereinafter, the operation principle of the maximum value detection circuit MAX_DETECT will be described. The NMOS transistors Tr1 [1] to Tr1 [n] and the first current source Iconst1 can be regarded as a kind of source follower array, and only the source follower transistor having the highest voltage input to the gate is turned on. When the maximum value among the pixel signals VPD [1] to VPD [n] is VPDmax, the maximum signal Vmax is given by equation (1).

  Here, k1 is a coefficient representing the substrate effect of the NMOS transistor and is usually a value of about 0.6 to 0.9. Further, Vgsn is a gate-source voltage of the NMOS transistor necessary for supplying a circuit current (constant current) supplied by the first current source Iconst1. The coefficient k1 representing the substrate effect of the NMOS transistor is a substantially constant value depending on the manufacturing process. Further, the approximate value of Vgsn can be predicted in advance by accurately controlling the circuit current flowing through the first current source Iconst1. Therefore, by using the maximum value detection circuit MAX_DETECT according to the present embodiment, the value of the maximum signal Vmax corresponding to the substantially maximum value of the pixel signal VPD [k] can be detected.

  Hereinafter, the operation principle of the minimum value detection circuit MIN_DETECT will be described. The PMOS transistors Tr2 [1] to Tr2 [n] and the second current source Iconst2 can be regarded as a kind of source follower array, and only the source follower transistor having the lowest voltage input to the gate is turned on. When the minimum value among the pixel signals VPD [1] to VPD [n] is VPDmin, the minimum signal Vmin is given by equation (2).

  Here, k2 is a coefficient representing the substrate effect of the PMOS transistor and is usually a value of about 0.6 to 0.9. Further, Vgsp is a gate-source voltage of the PMOS transistor necessary for supplying a circuit current (constant current) supplied by the second current source Iconst2. The coefficient k2 representing the substrate effect of the PMOS transistor is a substantially constant value depending on the manufacturing process. In addition, the approximate value of Vgsp can be predicted in advance by accurately controlling the circuit current flowing through the second current source Iconst2. Therefore, by using the minimum value detection circuit MIN_DETECT according to the present embodiment, the value of the minimum signal Vmin corresponding to the substantially minimum value of the pixel signal VPD [k] can be detected.

<Bias control circuit, driver circuit, and sample and hold circuit>
[Constitution]
Hereinafter, the bias control circuit BIAS_GEN, the driver circuit DRV_CIR, and the sample and hold circuit SHC will be described in more detail with reference to FIGS. FIG. 6 shows the configuration of the bias control circuit BIAS_GEN, the driver circuit DRV_CIR, and the sample and hold circuit SHC. FIG. 7 is a timing chart for explaining the operation when the sample and hold circuit SHC is driven by the driver circuit DRV_CIR.

First, the configuration of the sample and hold circuit SHC will be described with reference to FIG. The sample and hold circuit SHC has an input terminal, an output terminal, and a control terminal, a sampling switch S1 that can be turned on and off by a sampling clock ΦSH, a first terminal and a second terminal, and a capacitance value C A sampling capacitor CSH which is _SH .

  The driver output voltage V_DRVOUT is input from the driver circuit DRV_CIR to the input terminal of the sampling switch S1, and the sampling clock ΦSH is input to the control terminal. The output terminal of the sampling switch S1 is connected to the first terminal of the sampling capacitor CSH. The first terminal of the sampling capacitor CSH is connected to the output terminal of the sampling switch S1, and the second terminal of the sampling capacitor CSH is connected to the second power supply VSS. Hereinafter, the voltage at the output terminal of the sampling switch S1 is defined as the sampling voltage V_SH. The operation of the driver circuit DRV_CIR and the bias control circuit BIAS_GEN described in FIG. 6 and their connection with each other are as already described with reference to FIG. A more detailed description will be described later.

[Operating principle]
Next, the operation of the sample and hold circuit SHC and the operation of the driver circuit DRV_CIR and the bias control circuit BIAS_GEN that drive the sample and hold circuit SHC will be described in detail with reference to FIG. In the timing chart shown in FIG. 7, the horizontal axis represents time, and the vertical axis represents voltage or logic level.

  The upper rectangular wave in FIG. 7 represents the time change of the sampling clock ΦSH. The sampling clock ΦSH is at a high level (hereinafter, H level) during the sampling period, and is at a low level (hereinafter, L level) during the holding period. The sample period continues for ts seconds, the holding period continues for th seconds, and the sample period and the holding period are alternately repeated periodically. After a sample period of ts seconds continues, a hold period of th seconds continues, and subsequently, after a sample period of ts seconds continues again, the hold period of th seconds continues again. Since the sampling clock ΦSH is at the H level in the sample period, the sampling switch S1 is on. In the hold period, the sampling clock ΦSH is at the L level, so the sampling switch S1 is off.

  The lower part of FIG. 7 represents the time change of the sampling voltage V_SH. The timing chart shown in FIG. 7 starts from the holding period of the pixel signal VPD [k−1], and the sampling voltage V_SH is maintained at VPD [k−1] during this holding period. When the sampling period of the pixel signal VPD [k] starts at time t [k], the sampling voltage V_SH at time t [k] 'is given by the following equation (3).

Here, the sampling error ε is a voltage representing a difference between the pixel signal VPD [k] and the actual sampling voltage V_SH, and is given by a relational expression ε = VPD [k] −V_SH. V ₁ is a voltage representing the difference between the pixel signal VPD [k] and the pixel signal VPD [k−1]. Also, ts is a time representing the difference between the time t [k] ′ and the time t [k]. Further, τ is a time constant given by the relational expression of τ = C _SH / gm.

  By transforming the equation (3), the transconductance gm of the driver circuit DRV_CIR required for sampling the driver output voltage V_DRVOUT so that the sampling error is equal to or less than the predetermined sampling error ε is expressed by the following equation (4): It turns out that it is necessary to satisfy.

In the equation (4), the maximum contrast V _{CONT_MAX} is a signal representing the difference between the maximum signal Vmax and the minimum signal Vmin as described with reference to FIG. In the equation (4), ln is a natural logarithm (logarithm with e as the base).

  If the maximum / minimum value detection circuit MAX_MIN_DETECT does not exist in the present embodiment, the driver circuit DRV_CIR drives a signal having an arbitrary amplitude existing between the saturation level Vsat and the OB level Vob during the sample period ts. There is a need to. For this reason, it is necessary to drive the sampling capacitor CSH by operating the driver circuit DRV_CIR with a transconductance gm ′ satisfying the following expression (5).

In the equation (5), the maximum amplitude V _{SWING_MAX} is a difference between the saturation level Vsat and the OB level Vob as described with reference to FIG. In the equation (5), ln is a natural logarithm (logarithm with e as the base). Since V _{CONT_MAX} <V _{SWING_MAX} is clear from FIG. 4, the driver circuit DRV_CIR can be controlled so that the following expression (6) is satisfied.
gm <gm ′ (6)

As will be described later in detail, the transconductance gm is represented by an increasing function of the circuit current (a function that increases as the circuit current increases). For this reason, when the driver circuit DRV_CIR is controlled so that the expression (6) is satisfied, the current consumption of the driver circuit DRV_CIR becomes smaller than when the driver circuit DRV_CIR is operated with the transconductance gm ′ corresponding to the maximum amplitude V _{SWING_MAX} . In other words, the driver circuit DRV_CIR in the present embodiment reduces the driver output voltage V_DRVOUT while suppressing the sampling error to be equal to or less than the allowable sampling error ε within the predetermined sample period ts even if the current consumption is smaller than that of the conventional circuit. The sample and hold circuit SHC can be driven to sample.

  As described above, in the signal processing circuit SIG_PROC_CIR in the first embodiment, the driver circuit DRV_CIR determines the difference between the maximum value and the minimum value of the pixel signal obtained in advance from the maximum value / minimum value detection circuit MAX_MIN_DETECT (the maximum of the subject image). The sample-and-hold circuit SHC is driven with the minimum transconductance gm necessary for sampling within a predetermined sampling time. The driver circuit DRV_CIR operates with a transconductance smaller than the transconductance necessary for the sample and hold circuit SHC to sample the full dynamic range (difference between the black level and the saturation level of the pixel signal) within a predetermined sampling time. Also, the sampling error can be set to a predetermined value or less. For this reason, the power consumption of the driver circuit DRV_CIR can be reduced as compared with the conventional case.

<Configuration and Operation Principle of Driver Circuit DRV_CIR>
[Constitution]
Hereinafter, the configuration of the driver circuit DRV_CIR will be described with reference to FIG. FIG. 8 shows the configuration of the driver circuit DRV_CIR. The driver circuit DRV_CIR includes a tail current source I_TAIL, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

  The tail current source I_TAIL has a first terminal and a second terminal, the first terminal is connected to the first power supply VDD, and the current is supplied by the bias control signal gm_ctrl input from the bias control circuit BIAS_GEN described in FIG. The tail current Itail whose value is controlled is output from the second terminal. The first transistor M1 is a first conductivity type transistor in which the tail current Itail is input from the source terminal and the gate terminal is connected to the non-inverting input terminal V +. The second transistor M2 is a first conductivity type transistor in which the tail current Itail is input from the source terminal and the gate terminal is connected to the inverting input terminal V−. The inverting input terminal V- is connected to the output terminal VOUT and the drain terminal of the fourth transistor M4.

  The third transistor M3 has a drain terminal connected to the drain terminal of the first transistor M1, a source terminal connected to the second power supply VSS, a gate terminal connected to the drain terminal of the first transistor M1 and the fourth transistor. It is a transistor of the second conductivity type connected to the gate terminal of M4. The fourth transistor M4 is a second conductivity type transistor having a drain terminal connected to the drain terminal of the second transistor M2 and the output terminal VOUT, and a source terminal connected to the second power supply VSS.

  In the present embodiment, the first power supply VDD is the power supply voltage, and the second power supply VSS is the ground. The first conductivity type transistor is a PMOS transistor, and the second conductivity type transistor is an NMOS transistor.

  The first transistor M1 and the second transistor M2 form a differential pair DIFF_STAGE (differential pair circuit), and have a predetermined transconductance gmd according to the value of the input tail current Itail, and an inverting input terminal A current lout corresponding to the difference between the voltages input to V− and the non-inverting input terminal V + is output to the output terminal VOUT. The first signal sequence SIG_ARY1 is input to the non-inverting input terminal V +.

  The third transistor M3 and the fourth transistor M4 constitute a load circuit LOAD_STAGE, which converts the current signal input from the differential pair DIFF_STAGE into a voltage signal and outputs the voltage signal to the output terminal VOUT.

[Operating principle]
Hereinafter, the operation principle of the driver circuit DRV_CIR will be described with reference to FIG. 8, FIG. 9, and FIG. FIG. 9 shows the relationship between the current flowing through the differential pair DIFF_STAGE and the transconductance. FIG. 10 shows a modification of the configuration of the tail current source I_TAIL.

First, the basic operation of the driver circuit DRV_CIR will be described with reference to FIG. The driver circuit DRV_CIR only makes the output current of the tail current source I_TAIL that constitutes a general OTA (Operational Transactance Amplifier) variable. Its detailed operation is described in reference p186-190. In the reference, the first power supply VDD is ground, the second power supply VSS is a power supply voltage, the first conductivity type transistor is an NMOS transistor, and the second conductivity type transistor is a PMOS transistor. The same.
Reference: Behzad Razav, “Basic Design of Analog CMOS Integrated Circuits”, Maruzen Co., Ltd., 2003

  As can be seen from the reference, the transconductance gm of the transconductance amplifier is determined by the transconductance gmd of the first transistor M1 and the second transistor M2 constituting the differential pair (gm = gmd).

When the first transistor M1 and the second transistor M2 constituting the differential pair DIFF_STAGE operate in the weak inversion region, the drain current _ID is given by the following equation (7).

Therefore, it can be seen that the transconductance gmd of these transistors is given by the following equation (8) and is proportional to the drain current _ID .

However, W is the gate width of the MOS transistor, L is the gate length of the MOS transistor, _{I t} is technology current of the MOS transistor, n represents slope factor in the weak inversion region of a MOS transistor, _{V T} is the thermal _{voltage, V GS} is a MOS transistor The gate-source voltage _VDS is the drain-source voltage of the MOS transistor. Therefore, it is clear that the value of the transconductance gm of the driver circuit DRV_CIR can be controlled by the magnitude of the value of the tail current Itail.

When the differential pair DIFF_STAGE operates in the weak inversion region, the value of the transconductance gm is proportional to the drain current _ID . Therefore, by controlling the bias control signal gm_ctrl to an appropriate value, it is possible to realize characteristics as shown by the solid line in FIG. The horizontal axis of the graph shown in FIG. 9 represents the drain current _ID , and the vertical axis represents the transconductance gmd.

The operation region of the transistors constituting the differential pair DIFF_STAGE may be a strong inversion region or an intermediate region. When the operation region of the transistors constituting the differential pair DIFF_STAGE is a strong inversion region, the transconductance gm is proportional to the square root of the drain current _ID. Therefore, by controlling the bias control signal gm_ctrl to an appropriate value, FIG. The characteristic shown by the broken line is obtained. When the operation region of the transistors constituting the differential pair DIFF_STAGE is an intermediate region, characteristics intermediate between the weak inversion region and the strong inversion region can be obtained.

As shown in FIG. 10, the transconductance gm may be realized by changing the mirror ratio of the current mirror circuit constituting the tail current source I_TAIL by the bias control signal gm_ctrl. Since the value of the drain current _ID changes discretely by changing the mirror ratio, the characteristic shown by the double circle in FIG. 9 is obtained. In FIG. 9, as the mirror ratio (M) increases, the transconductance gm increases. In all the modifications described above, gm is an increasing function with respect to _ID .

Tail current Itail of the tail current source I_TAIL supplies drain current _{I D} is controlled by a bias control signal Gm_ctrl. As described above, the bias control signal gm_ctrl changes according to the difference between the maximum signal Vmax and the minimum signal Vmin. More specifically, the value of transconductance gm increases as the difference between maximum signal Vmax and minimum signal Vmin increases, and the value of transconductance gm decreases as the difference between maximum signal Vmax and minimum signal Vmin decreases. In addition, the bias control signal gm_ctrl is controlled.

(Second Embodiment)
<Capsule endoscope>
[Constitution]
A capsule endoscope SCOPE according to a second embodiment of the present invention will be described with reference to FIGS. 11 and 12. FIG. 11 shows the configuration of the capsule endoscope SCOPE. FIG. 12 shows the stomach wall of the human body.

  First, the configuration of the capsule endoscope SCOPE will be described with reference to FIG. The capsule endoscope SCOPE includes an objective lens OL, a signal processing circuit SIG_PROC_CIR ', an image processing circuit MPU, and a power supply circuit SUP.

  The objective lens OL forms an image of the light beam LIGHT input from the subject on the pixel column PD_ARY formed on the signal processing circuit SIG_PROC_CIR ′. The signal processing circuit SIG_PROC_CIR ′ outputs an AD conversion signal AD_SIG that is a digital signal corresponding to a voltage signal generated according to the amount of light incident on the pixel column PD_ARY. The image processing circuit MPU performs image processing based on the input AD conversion signal AD_SIG and generates an image related to the subject. The power supply circuit SUP supplies power to the signal processing circuit SIG_PROC_CIR 'and the image processing circuit MPU.

  The light beam LIGHT input from the subject is imaged on the pixel column PD_ARY through the objective lens OL. The signal processing circuit SIG_PROC_CIR ′ is connected to the image processing circuit MPU and outputs an AD conversion signal AD_SIG to the image processing circuit MPU. The power supply circuit SUP is connected to the signal processing circuit SIG_PROC_CIR 'and the image processing circuit MPU, and supplies power necessary for the operation of each circuit.

[Operation]
The capsule endoscope SCOPE is used to take an image of the body until the patient swallows the capsule endoscope SCOPE from the mouth and ejects it from the anus. The main subjects are the stomach, small intestine, and large intestine. By arranging a plurality of pixel columns PD_ARY having a plurality of light receiving elements arranged in a one-dimensional direction, for example, in a direction orthogonal to the direction in which the light receiving elements are arranged, a two-dimensional image can be acquired. For example, when n pixel columns PD_ARY are arranged, each of the n pixel columns PD_ARY is a voltage signal that forms an image of a region through which arrows L1, L2,..., Ln shown in FIG. Is generated.

  The pixel column PD_ARY outputs a voltage signal corresponding to the amount of light input to the pixel column PD_ARY. The voltage signal output from the pixel column PD_ARY is converted into an AD conversion signal AD_SIG by the AD converter ADC. Image processing is performed on the AD conversion signal AD_SIG in the image processing circuit MPU, and finally a video as shown in FIG. 12 is generated. The video is updated at a predetermined frame rate (frame period). In a typical use example, the video is updated about once to about 100 times per second. The detailed operation of the signal processing circuit SIG_PROC_CIR 'will be described below.

<Signal processing circuit SIG_PROC_CIR '>
[Constitution]
Hereinafter, the configuration of the signal processing circuit SIG_PROC_CIR ′ will be described with reference to FIG. FIG. 13 shows the configuration of the signal processing circuit SIG_PROC_CIR ′. The signal processing circuit SIG_PROC_CIR ′ includes a signal string generation circuit SIG_ARY_GEN ′, a driver circuit DRV_CIR, an AD converter ADC, a maximum value / minimum value detection circuit MAX_MIN_DETECT ′, and a bias control circuit BIAS_GEN ′. These structures are formed on the same semiconductor chip.

  The signal string generation circuit SIG_ARY_GEN 'repeatedly time-divides a voltage signal group composed of a plurality of voltage signals (DC voltage signals) at a predetermined frame period, and outputs it to the driver circuit DRV_CIR as a first signal string SIG_ARY1. The driver circuit DRV_CIR receives the first signal sequence SIG_ARY1 and the bias control signal gm_ctrl ′, converts the first signal sequence SIG_ARY1 into the driver output voltage V_DRVOUT with a transconductance according to the bias control signal gm_ctrl ′, and samples it. Output to the hold circuit SHC. The AD converter ADC has a sample and hold circuit SHC at the input stage, converts an analog signal held in the sample and hold circuit SHC into an AD conversion signal AD_SIG that is a digital signal, and displays the image shown in FIG. Output to the processing circuit MPU.

The maximum value / minimum value detection circuit MAX_MIN_DETECT ′ receives the AD conversion signal AD_SIG and receives the maximum signal Vmax ′ corresponding to the maximum value of the AD conversion signal AD_SIG corresponding to the first signal sequence SIG_ARY1 for one frame and the minimum value. Is generated and output to the bias control circuit BIAS_GEN ′. The bias control circuit BIAS_GEN ′ receives the maximum signal Vmax ′ and the minimum signal Vmin ′, and is a difference between the maximum signal Vmax ′ and the minimum signal Vmin ′ output in the previous frame (first frame). Based on the maximum contrast V _{CONT_MAX} , the maximum contrast V ′ _{CONT_MAX} that is the difference between the maximum signal Vmax ′ and the minimum signal Vmin ′ output in the next frame (second frame) is predicted and output in the next frame. A bias control signal gm_ctrl ′ used for processing the first signal sequence SIG_ARY1 is generated and output to the driver circuit DRV_CIR.

[Operation]
The internal configuration and operation of the driver circuit DRV_CIR and the sample-and-hold circuit SHC are the same as the internal configuration and operation of each circuit described in FIG. FIG. 14 shows a configuration of the signal string generation circuit SIG_ARY_GEN ′. The configuration of the signal string generation circuit SIG_ARY_GEN ′ is the same except that the signal line for extracting the second signal string SIG_ARY2 is removed from the signal string generation circuit SIG_ARY_GEN shown in FIG. A detailed description of the configuration will be omitted.

  Hereinafter, the reading sequence in the signal processing circuit SIG_PROC_CIR ′ will be described with reference to FIG. 4 again. The functions of the maximum value / minimum value detection circuit MAX_MIN_DETECT 'and the bias control circuit BIAS_GEN' are different from those described in FIG.

First, the maximum value / minimum value detection circuit MAX_MIN_DETECT ′ will be described with reference to FIG. The maximum value / minimum value detection circuit MAX_MIN_DETECT ′ uses the AD conversion signal AD_SIG corresponding to the voltage signal group G1 AD-converted by the AD converter ADC to read the voltage signal group read in the transfer period TRAN_T one frame before. The maximum contrast V _{CONT_MAX of} G1 is determined, and the maximum contrast of the voltage signal group G2 read in the transfer period TRAN_T ′ of the next frame is predicted. For example, 1.2 × V _{CONT_MAX} that is 20% _{higher than} the maximum contrast V _{CONT_MAX} of the voltage signal group G1 read in the transfer period TRAN_T one frame before is predicted to be the maximum contrast in the next frame. If the following equation (9) is established as a result of performing such a prediction calculation, the sample and hold circuit SHC is driven so as to sample the driver output voltage V_DRVOUT while suppressing the sampling error to a predetermined sampling error ε or less. Can do.
V ′ _{CONT_MAX} ≦ 1.2 × V _{CONT_MAX} (9)

However, V ′ _{CONT_MAX} is the maximum contrast of the voltage signal group G2 actually read out in the next frame. Therefore, as long as both the expression (9) and the following expression (10) are satisfied, the expression (6) is satisfied. Therefore, the signal processing circuit SIG_PROC_CIR ′ according to the present embodiment consumes less current than the related art. Can be reduced.
1.2 × V _{CONT_MAX} <V _{SWING_MAX} (10)

By mounting the signal processing circuit SIG_PROC_CIR ′ on the capsule endoscope SCOPE according to the present embodiment, an effect of further reducing power consumption can be obtained. This is because of the following two points. The first point is that, as shown in FIG. 12, the contrast of the image of the intestinal wall of the stomach wall is generally low and the value of the maximum contrast V _{CONT_MAX} is small. The second point is that the image generated by the capsule endoscope SCOPE periodically taking images is the same image, and therefore the maximum contrast V _{CONT_MAX} of the voltage signal group read out in the previous frame. It is easy to accurately predict the maximum contrast V ′ _{CONT_MAX} in the next frame based on the above.

  As described above, the driver circuit DRV_CIR constituting the signal processing circuit SIG_PROC_CIR ′ mounted on the capsule endoscope SCOPE according to the present embodiment has a contrast (light / dark difference) as indicated by arrows L1 and L2 in FIG. The sample and hold circuit SHC is driven with a small transconductance gm in a portion corresponding to a low subject. Further, the driver circuit DRV_CIR constituting the signal processing circuit SIG_PROC_CIR ′ mounted on the capsule endoscope SCOPE according to the present embodiment is a part corresponding to a subject having a relatively large contrast as indicated by an arrow Ln in FIG. Then, it operates with a large transconductance gm.

  Since the image of the subject (for example, stomach wall or intestinal wall) to be imaged by the capsule endoscope SCOPE is often low contrast, the difference between the maximum value and the minimum value of the signal to be driven by the driver circuit DRV_CIR becomes small. There is a tendency. Therefore, since the driver circuit DRV_CIR operates with a small transconductance for a longer time by mounting the signal processing circuit SIG_PROC_CIR ′ according to the present embodiment in the capsule endoscope SCOPE, the capsule endoscope SCOPE is smaller than the conventional one. It can operate with power consumption.

<Modification>
As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  The configuration of the driver circuit DRV_CIR is not limited to the configuration shown in FIG. For example, the driver circuit DRV_CIR may be configured by the transconductance amplifier shown in FIG. 15, or the driver circuit DRV_CIR may be configured by a transconductance amplifier having a configuration other than this.

  Hereinafter, the transconductance amplifier shown in FIG. 15 will be described. The transconductance amplifier shown in FIG. 15 includes PMOS transistors P1, P2, P3, P4, P1 ′, P3 ′, P4 ′ and NMOS transistors N1, N2, N3, N4, N1 ′, N3 ′, N4 ′. Have.

  The PMOS transistor P2 constitutes a first tail current source I_TAIL1. The NMOS transistor N2 constitutes a second tail current source I_TAIL2. The PMOS transistors P3 and P3 'and the NMOS transistors N3 and N3' constitute a differential pair DIFF_STAGE. The PMOS transistors P1, P4, P1 ', P4' and the NMOS transistors N1, N4, N1 ', N4' constitute a load circuit LOAD_STAGE.

  Although omitted in FIG. 15, the drain terminal of the PMOS transistor P3 is connected to the drain terminal of the NMOS transistor N1 and the source terminal of the NMOS transistor N4, and the drain terminal of the PMOS transistor P3 ′ is connected to the drain terminal of the NMOS transistor N1 ′ and the NMOS transistor. The drain terminal of the NMOS transistor N3 is connected to the drain terminal of the PMOS transistor P1 and the source terminal of the PMOS transistor P4. The drain terminal of the NMOS transistor N3 ′ is connected to the drain terminal of the PMOS transistor P1 ′. It is connected to the source terminal of the PMOS transistor P4 ′.

  In the driver circuit DRV_CIR shown in FIG. 8, the first power supply VDD is the power supply voltage, the second power supply VSS is the ground, the first conductivity type transistor is a PMOS transistor, and the second conductivity type The transistor is an NMOS transistor. For example, the first power supply VDD is the ground, the second power supply VSS is the power supply voltage, the first conductivity type transistor is an NMOS transistor, The second conductivity type transistor may be a PMOS transistor.

  The driver circuit DRV_CIR has been described as being a single-ended type, but may be a fully differential type driver circuit.

In FIG. 2, all the n light receiving elements PD [1] to PD [n] are connected to the maximum value / minimum value detection circuit MAX_MIN_DETECT, but light reception connected to the maximum value / minimum value detection circuit MAX_MIN_DETECT. The number of elements may be less than n. For example, even if the signal lines connecting the light receiving elements PD [1] to PD [n] and the maximum value / minimum value detection circuit MAX_MIN_DETECT are thinned out one by one, an approximate value of the maximum contrast V _{CONT_MAX} can be obtained. It is possible to reduce the area required for the process.

  Further, even when the signal processing circuit SIG_PROC_CIR ′ shown in FIG. 11 is the signal processing circuit SIG_PROC_CIR according to the first embodiment, the same effect can be obtained.

Further, in the second embodiment, the bias control circuit BIAS_GEN ′ performs the next frame based on the maximum contrast V _{CONT_MAX} that is the difference between the maximum signal Vmax ′ and the minimum signal Vmin ′ output in the previous frame. Although the maximum contrast V ′ _{CONT_MAX} that is the difference between the output maximum signal Vmax ′ and the minimum signal Vmin ′ is expected, the following may be used. For example, the bias control circuit BIAS_GEN ′ uses m frames (m: 2) from the first frame based on the maximum contrast V _{CONT_MAX} that is the difference between the maximum signal Vmax ′ and the minimum signal Vmin ′ output in the first frame. The maximum contrast V ′ _{CONT_MAX} that is the difference between the maximum signal Vmax ′ and the minimum signal Vmin ′ output in the second frame after the above is predicted, and the maximum contrast V ′ predicted in advance in the second frame _A bias control signal gm_ctrl ′ based on CONT_MAX is generated and output to the driver circuit DRV_CIR.

  In FIGS. 3 and 4, the upper portion of the vertical axis of the graph has been described as a state in which the accumulated charge is large (saturation level Vsat). Level Vob) may be used.

  SIG_PROC_CIR, SIG_PROC_CIR 'signal processing circuit, SIG_ARY_GEN, SIG_ARY_GEN' signal sequence generation circuit, MAX_MIN_DETECT, MAX_MIN_DETECT 'maximum value / minimum value detection circuit, BIAS_GEN, BIAS_GEN' A / D driver control circuit, BIAS_GEN, BIAS_GEN'A circuit Circuit, PD_ARY pixel row, SW_ARY switch row, MAX_DETECT maximum value detection circuit, MIN_DETECT minimum value detection circuit, S1 sampling switch, CSH sampling capacitor, Iconst1 first current source, Iconst2 second current source, I_TAIL tail current source, M1 1st transistor, M2 2nd transistor M3 third transistor, M4 fourth transistor, DIFF_STASGE differential pair, LOAD_STAGE load circuit, SCOPE capsule endoscope, OL objective lens, MPU image processing circuit, SUP power supply circuit

Claims (8)

A plurality of voltage signals are time-divided and sequentially output as a first signal string, and the plurality of voltage signals are simultaneously output in parallel as a second signal string; and
Maximum value / minimum value detection that receives the second signal sequence and outputs a maximum signal corresponding to a substantially maximum value of the plurality of voltage signals and a minimum signal corresponding to a substantially minimum value of the plurality of voltage signals. Circuit,
A bias control circuit that receives the maximum signal and the minimum signal and outputs a bias control signal that changes according to a difference between the maximum signal and the minimum signal;
A driver circuit that receives the first signal sequence and the bias control signal, and outputs a driver output voltage obtained by converting the first signal sequence with a transconductance according to the bias control signal;
A sample-and-hold circuit that receives the driver output voltage and repeats an operation of sampling the driver output voltage in a sample period and an operation of holding the driver output voltage in a holding period;
I have a,
The transconductance of the driver circuit is controlled by the bias control signal so that the value increases when the difference between the maximum signal and the minimum signal increases, and decreases when the difference decreases. A signal processing circuit.   2. The AD converter having the sample-and-hold circuit in an input stage and outputting an analog signal held in the sample-and-hold circuit to the outside as an AD conversion signal that is a digital signal. The signal processing circuit described. A signal sequence generation circuit for repeatedly time-dividing a plurality of voltage signals at a predetermined frame period and outputting as a first signal sequence;
A driver circuit that receives the first signal sequence and the bias control signal, and outputs a driver output voltage obtained by converting the first signal sequence with transconductance according to the bias control signal;
A sample and hold circuit that receives the driver output voltage and repeats an operation of sampling the driver output voltage in a sample period and an operation of holding the driver output voltage in a holding period is provided in the input stage, and the sample and hold An AD converter that outputs an analog signal held in the circuit as an AD conversion signal that is a digital signal;
A maximum value / minimum value detection circuit for outputting a maximum signal corresponding to a substantially maximum value of the AD conversion signal and a minimum signal corresponding to a substantially minimum value of the AD conversion signal;
Based on the difference between the maximum signal and the minimum signal output in the first frame, the difference between the maximum signal and the minimum signal output in the second frame after the first frame is predicted. A bias control circuit that outputs the bias control signal corresponding to the first signal sequence output to the second frame;
I have a,
The transconductance of the driver circuit is controlled by the bias control signal so that the value increases when the difference between the maximum signal and the minimum signal increases, and decreases when the difference decreases. A signal processing circuit. The sample and hold circuit
A sampling switch that is controlled on and off by a sampling clock;
A sampling capacity with a capacitance value of _CSH ;
Have
When the length of the sample period when the sampling switch is turned on is ts, the sampling error allowed in the sample and hold circuit is ε, and the voltage difference between the maximum signal and the minimum signal is V _{CONT_MAX} ,
The signal processing circuit according to claim 1 or claim 3 wherein the bias control circuit such that the driver circuit transconductance gm start operating and controlling the bias control signal satisfying. The signal string generation circuit includes:
A pixel array having a plurality of light receiving elements arranged on a plane of a semiconductor substrate and generating the voltage signal according to the amount of received light;
A plurality of switches having a first terminal and a second terminal, wherein the first terminal is connected to each of the light receiving elements, the second terminal is connected to each other, and can be switched on and off;
The voltage signals generated by the plurality of light receiving elements are sequentially switched and sequentially output as the first signal sequence by sequentially switching the switches that are turned on, and the plurality of light receiving elements The voltage signal generated in step (2) is simultaneously output in parallel to a signal line provided corresponding to each of the plurality of light receiving elements as the second signal sequence. Signal processing circuit. The maximum value / minimum value detection circuit includes:
A plurality of NMOS transistors; and a first current source having a first terminal and a second terminal; and each gate terminal of the plurality of NMOS transistors is connected to all or a part of the plurality of light receiving elements. Each drain terminal of the plurality of NMOS transistors is connected to a first power source, each source terminal of the plurality of NMOS transistors is connected to each other, and the first terminal of the first current source is the plurality of the plurality of NMOS transistors. Connected to all source terminals of the NMOS transistor, the second terminal of the first current source is connected to a second power source, the source terminal of the NMOS transistor, and the first terminal of the first current source And a maximum value detection circuit that outputs the maximum signal from a portion to which is connected,
A plurality of PMOS transistors; and a second current source having a first terminal and a second terminal; and each gate terminal of the plurality of PMOS transistors is connected to all or a part of the plurality of light receiving elements. Each drain terminal of the plurality of PMOS transistors is connected to the second power source, each source terminal of the plurality of PMOS transistors is connected to each other, and the first terminal of the second current source is the PMOS Connected to all source terminals of the transistor, the second terminal of the second current source is connected to the first power source, the source terminal of the PMOS transistor, and the first terminal of the second current source And a minimum value detection circuit that outputs the minimum signal from a portion connected to
The signal processing circuit according to claim 5 , comprising: The driver circuit is
By the bias control signal,
A tail current source whose output current is controlled;
A differential pair circuit that outputs a current according to a difference between voltages input to an inverting input terminal and a non-inverting input terminal with a predetermined transconductance corresponding to a value of the output current input from the tail current source;
A load circuit that outputs a voltage corresponding to the current input from the differential pair circuit;
The signal processing circuit according to claim 1, further comprising: 4. The signal processing circuit according to claim 2, wherein a pixel column having a plurality of light receiving elements arranged on a plane of a semiconductor substrate and generating the voltage signal according to the amount of received light is generated. A signal processing circuit for preparing the circuit and outputting the AD conversion signal corresponding to the voltage signal;
An objective lens that forms an image of a light beam input from a subject on the pixel row;
An image processing circuit for performing image processing based on the AD conversion signal input from the signal processing circuit;
A power supply circuit for supplying power to the signal processing circuit and the image processing circuit;
A capsule endoscope characterized by comprising: