JP6136097B2 - A / D conversion circuit and electronic device - Google Patents

Description

  The present invention relates to an A / D conversion circuit, an electronic device, and the like.

  Conventionally, a successive approximation type A / D conversion circuit is known as an A / D conversion circuit that converts an analog signal into digital data. This successive approximation type A / D conversion circuit includes a comparison circuit, a successive approximation register, and a D / A conversion circuit, and digitally converts a signal obtained by sampling and holding an input signal by a successive approximation operation. Output data. As a conventional technique of such a successive approximation type A / D conversion circuit, a technique disclosed in Patent Document 1 is known.

JP-A-8-321779

  As a technique for increasing the resolution of the A / D conversion circuit, there is oversampling. When oversampling is performed, there is an advantage that quantization noise can be reduced. However, since a group delay is caused by a subsequent digital filter (for example, a decimation filter), there is a problem that it is not suitable for an application in which sampling is performed once irregularly, for example.

  According to some aspects of the present invention, it is possible to provide an A / D conversion circuit, an electronic device, and the like that enable pseudo oversampling without providing a subsequent digital filter.

  One embodiment of the present invention is based on a comparison circuit that performs a comparison operation in successive approximation, a control unit that stores successive comparison data updated by successive approximation, and a result of the successive comparison, An output unit that outputs output data, and the control unit performs an m / bit (m is a natural number of 2 or more) A / D conversion operation from a sampling operation to a sampling operation next to the sampling operation. A control process is performed a plurality of times, and the output unit outputs m + j bits (j is a natural number) of the output data based on a plurality of m bit data obtained by the plurality of A / D conversion operations. / D conversion circuit.

  According to one embodiment of the present invention, an m-bit A / D conversion operation is performed a plurality of times between a sampling operation and the next sampling operation of the sampling operation, and can be obtained by the plurality of A / D conversion operations. Based on the plurality of m-bit data, m + j-bit output data is output. This makes it possible to perform pseudo oversampling without providing a digital filter at the subsequent stage.

  In one embodiment of the present invention, a D / A conversion circuit connected to a comparison node of the comparison circuit and performing D / A conversion of the successive approximation data is included. The D / A conversion circuit includes: a capacitor array unit; A switch array unit, and the control unit performs control to change the allocation of the capacitor of the capacitor array unit to each bit of the successive approximation data at each of the plurality of A / D conversion operations, You may perform with respect to a switch array part.

  In this way, the allocation of capacitors to the same code of the successive approximation data can be changed each time in the A / D conversion operation. Thereby, a plurality of A / D conversion data having different values can be obtained for one sample and hold.

  In one embodiment of the present invention, a D / A conversion circuit that is connected to a comparison node of the comparison circuit and performs D / A conversion of the successive approximation data, a capacitor array unit and a switch array that are connected to the comparison node A second D / A conversion circuit, and the control unit performs switch control different in each of the plurality of A / D conversion operations, and switches the second D / A conversion circuit. You may perform with respect to an array part.

  In this way, the switch control for the switch array unit of the second D / A conversion circuit can be changed, and a plurality of A / D conversion data having different values can be obtained for one sample and hold. be able to.

  In the aspect of the invention, the control unit may include a code data generation unit that generates different code data at each of the plurality of A / D conversion operations, and the second D is generated based on the code data. The second D / A conversion circuit may perform D / A conversion of the code data by switch control by the control unit.

  In this way, A / D conversion data for one sample and hold can be changed by generating different code data each time of the A / D conversion operation.

  In the aspect of the invention, the control unit may update an upper limit value and a lower limit value that determine a data range in which the successive comparison is performed based on data obtained by the A / D conversion operation.

  In this way, the data range for successive comparison in the next A / D conversion operation can be updated based on the data obtained by the A / D conversion operation. This makes it possible to reduce the data range for successive comparisons.

  In the aspect of the invention, the control unit may set the upper limit value and the lower limit value of a data range including a predicted value of data obtained by the next A / D conversion operation.

  In one embodiment of the present invention, a D / A conversion circuit that is connected to a comparison node of the comparison circuit and performs D / A conversion of the successive approximation data, and is connected to the comparison node, and the plurality of A / A second D / A conversion circuit that performs D / A conversion of different code data at each D conversion operation, wherein the control unit includes a code data generation unit that generates the code data, and the A The predicted value may be obtained based on the data obtained by the / D conversion operation, the code data in the A / D conversion operation, and the code data in the next A / D conversion operation.

  In this way, it is possible to predict the second and subsequent A / D conversion data out of a plurality of A / D conversion data obtained for one sample and hold, and to reduce the data range for successive comparison. Thereby, the time required for the successive approximation can be shortened.

  In one embodiment of the present invention, the output data may be set to a disabled state or a low power consumption mode from the time when the output data is output until the next sampling operation.

  In this way, the A / D conversion circuit can be set to the disabled state or the low power consumption mode from the time when the output data is output until the next sampling operation, so that the A / D conversion circuit can be reduced in power consumption. it can.

  Another aspect of the invention relates to an electronic device including the A / D conversion circuit described in any of the above.

The timing chart showing the oversampling operation which the A / D conversion circuit of a comparative example performs. 2 is a basic configuration example of an A / D conversion circuit according to the present embodiment. 4 is a timing chart illustrating the operation of the A / D conversion circuit according to the embodiment. 2 is a detailed configuration example of an A / D conversion circuit according to the present embodiment. 4 is a timing chart illustrating the operation of the A / D conversion circuit according to the embodiment. FIG. 6A shows a simulation result when normal oversampling is performed. FIG. 6B shows a simulation result when the pseudo oversampling of this embodiment is performed. Explanatory drawing about a conversion prediction process. The flowchart of the A / D conversion operation | movement in the case of performing a conversion prediction process. The timing chart of A / D conversion operation in the case of performing conversion prediction processing. Characteristic of the number of cycles of successive approximation against the width of the conversion prediction range. FIGS. 11A to 11C are explanatory diagrams of the code shift method. 3 is a detailed configuration example of a D / A conversion circuit according to the present embodiment. Operation | movement explanatory drawing of this embodiment. 3 shows a detailed configuration example of a first capacitor array unit, a first switch array unit, and a DEM control unit. FIG. 15A and FIG. 15B are explanatory diagrams of a method for assigning capacitors to each bit of input digital data. FIGS. 16A and 16B are also explanatory diagrams of a method of assigning capacitors to each bit of input digital data. 3 shows a detailed configuration example of a fully differential D / A conversion circuit. 1 is a configuration example of an electronic apparatus according to an embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example of this Embodiment First, an A / D conversion circuit that performs normal oversampling will be described as a comparative example of this embodiment. FIG. 1 is a timing chart schematically showing the 16 times oversampling operation performed by the A / D conversion circuit of the comparative example.

  As shown in FIG. 1, the A / D conversion circuit of the comparative example continuously samples and holds (S / H) the input voltage at regular intervals, and performs one A / D for one sample and hold. / D conversion operation is performed. Data obtained by A / D conversion is 14-bit data. The subsequent digital filter (decimation filter) receives the 14-bit data and outputs final 16-bit output data DFQ1, DFQ2,... At a rate of once per 16 samplings.

  In order for such an A / D conversion circuit to obtain effective output data, it is necessary to continue sampling the input voltage at regular intervals. For example, a time corresponding to the group delay of the digital filter is required from the start of sampling until the first effective data is output. Therefore, in order to obtain at least one valid data, it is necessary to continue sampling the input voltage at regular intervals for the time corresponding to the group delay from the start of sampling. In other words, it is impossible to use one time by sampling the input voltage and obtaining one output data (hereinafter referred to as one-shot A / D conversion as appropriate).

  For example, in a sensor such as a temperature sensor whose change in sensor output is relatively gradual, an application may be considered in which the sensor output may be A / D converted irregularly. In such an application, it is ideal that one output data is obtained by one sampling, and the A / D conversion circuit of the comparative example is not suitable. As a method for realizing one-shot A / D conversion with the A / D conversion circuit of the comparative example, it is conceivable to use 14-bit data after A / D conversion as output data, but compared with the case where oversampling is performed. As a result, the number of bits of the output data is different, and the resolution is naturally reduced due to the decrease in the number of bits.

2. Therefore, in this embodiment, a plurality of A / D conversion operations are performed for one sampling operation, and one m + j bit data (m is a natural number of 2 or more and j is a natural number). Is output to realize one-shot A / D conversion. In the following, m = 14 bits and m + j = 16 bits, and a case where 16 A / D conversion operations are performed per sampling will be described as an example. However, the present embodiment is not limited to this. That is, A / D conversion operation per sampling is arbitrary k times (k is a natural number of 2 or more), and m + j corresponds to the number of bits of output data when k times oversampling is performed. That's fine.

  FIG. 2 shows a basic configuration example of the A / D conversion circuit of the present embodiment. The A / D conversion circuit of FIG. 2 includes a comparison circuit 10, a control unit 20, an S / H (sample and hold) circuit 30, an output unit 40, and a D / A conversion circuit DAC. The A / D conversion circuit according to the present embodiment is not limited to the configuration shown in FIG. 2, and various modifications such as omitting some of the components or adding other components are possible. For example, as in the configuration example described later with reference to FIG. 12, the components of the S / H circuit 30 may be omitted, and the D / A conversion circuit DAC may have a sample and hold function for the input signal VIN.

  The S / H circuit 30 is a circuit that samples and holds an input signal VIN to be subjected to A / D conversion. In the case of the charge redistribution type, the function of the S / H circuit 30 can be realized by a D / A conversion circuit.

  The D / A conversion circuit DAC performs D / A conversion of the successive approximation data RDA from the control unit 20 and outputs an analog signal D / A output signal DQ corresponding to the successive comparison data RDA. For example, the D / A conversion circuit DAC may be a charge redistribution type using a capacitor array, or a part thereof may be a ladder resistance type.

  The comparison circuit 10 is realized by a comparator and performs, for example, a comparison process between the signal SIN and the signal DQ. For example, the comparator is a latch-type comparator. The comparison circuit 10 performs processing for comparing the sampling signal SIN of the input signal VIN with the D / A output signal DQ. Specifically, the comparison circuit 10 compares the sampling signal SIN input to the first input terminal with the D / A output signal DQ input to the second input terminal. In the case of the charge redistribution type (for example, FIG. 12), the comparison circuit 10 performs a process of comparing the difference signal between the sampling signal SIN and the D / A output signal DQ and the reference signal (for example, the ground voltage). You may go. In the case of a differential type (for example, FIG. 17), the comparison circuit 10 may perform a process of comparing a positive signal and a negative signal of a difference signal between SIN and DQ.

  The control unit 20 has a successive approximation register (SAR) and outputs successive comparison data RDA to the D / A conversion circuit DAC. The successive approximation register SAR is a register whose register value is set by the comparison result signal CPQ from the comparison circuit 10. For example, when the comparison circuit 10 performs a sequential comparison process from the MSB bit to the LSB bit, the comparison process result (“1”, “0”) in each bit is stored in each register of the successive approximation register SAR. Stored as a value. When the successive comparison is completed up to the LSB bit of the successive comparison data RDA, the control unit 20 outputs the successive comparison data RDA as 14-bit (m bit in a broad sense) A / D conversion data QDA.

  The control unit 20 performs control processing for each circuit block of the A / D conversion circuit. For example, control processing for performing A / D conversion operations 16 times (k times in a broad sense) per sample and hold is performed for each circuit block. Alternatively, the control unit 20 performs on / off control of switch elements (for example, the switch arrays 51 to 53 in FIG. 12) included in the D / A conversion circuit DAC in the A / D conversion operation.

  Here, the A / D conversion operation is a series of operations from the start of successive approximation to the output of A / D conversion data QDA, and the operation of obtaining one A / D conversion data QDA is one A / D conversion. Is the action.

  The output unit 40 outputs 16-bit (m + j bits in a broad sense) output data DOUT based on 16 A / D conversion data QDA obtained by 16 A / D conversion operations for one sample and hold. Is output. Specifically, the output unit 40 performs a moving average process on 16 pieces of A / D conversion data QDA, and outputs the result of the moving average process as output data DOUT.

  FIG. 3 is a timing chart showing the operation of the A / D conversion circuit of this embodiment. As shown in FIG. 3, the control unit 20 performs 16 A / D conversion operations on the sampling signal SIN1 sampled and held by the S / H circuit 30, and obtains 16 A / D conversion data QDA. Output.

  Since 16 A / D conversion operations are performed for one sample and hold, the expected values of the 16 A / D conversion data QDA should be the same. If the expected values are the same, the values of the 16 A / D conversion data QDA are almost the same, so even if the output data DOUT1 is expanded to 16 bits, A / D conversion accompanying the expansion of the number of bits It is considered that improvement in characteristics (for example, S / N) cannot be obtained.

  Therefore, in the present embodiment, the control unit 20 outputs a control signal SSW for performing switch control of the D / A conversion circuit DAC, and the D / A conversion circuit DAC performs A / D based on the control signal SSW. Different switch control is performed at each conversion operation. That is, even if the same A / D conversion data QDA is obtained at each A / D conversion operation, the on / off operation of the DAC switch in the successive approximation is different at each A / D conversion operation. It will be. For example, in the present embodiment, as described later, switch control is changed by DEM (Dynamic Element Matching) or code shift.

  The output unit 40 sequentially latches the 16 A / D conversion data QDA obtained as described above, obtains the moving average value of the 16 A / D conversion data QDA, and finally obtains the final value. Output data DOUT1 is output.

  In this embodiment, by performing such pseudo oversampling, an A / D conversion characteristic equivalent to that when oversampling is performed can be expected. That is, 16 A / D conversion data QDA having different values can be obtained for one sampling signal SIN1, and it is possible to avoid obtaining the same A / D conversion data QDA. Further, by changing the switch control so that variations occur around the true A / D conversion data QDA, it is possible to obtain a value close to the true value by averaging the 16 A / D conversion data QDA. is there.

  The output data DOUT1 obtained by pseudo oversampling is 16-bit data equivalent to the case where 16-times oversampling is performed by a 14-bit A / D conversion circuit. As a result, it is possible to use the same peripheral circuit as in the case of oversampling. Further, since no subsequent digital filter is required, group delay does not occur, and one-shot A / D conversion becomes possible.

3. Detailed Configuration of A / D Conversion Circuit FIG. 4 shows a detailed configuration example of the A / D conversion circuit of this embodiment. The A / D conversion circuit of FIG. 4 includes a comparison circuit 10, a control unit 20, an S / H circuit 30, an output unit 40, a first D / A conversion circuit DAC1, and a second D / A conversion circuit DAC2. In addition, the same code | symbol is attached | subjected about the component same as the component demonstrated in FIG. 2, and description is abbreviate | omitted suitably.

  Here, a case where the A / D conversion circuit performs DEM control and code shift will be described below as an example. However, the present embodiment is not limited to this, and for example, only one of DEM control and code shift may be performed. Good. When the code shift is not performed, the code data generation unit 90 and the second D / A conversion circuit DAC2 are omitted.

  The control unit 20 includes a successive approximation register SAR, a DEM control unit 80 that performs DEM switch control, and a code data generation unit 90 that generates code data for performing code shift.

  The DEM control unit 80 outputs a control signal DMP to the switch array of the D / A conversion circuit DAC1. Based on the control signal DMP from the DEM control unit 80, the D / A conversion circuit DAC1 dynamically changes the capacitor assignment for each bit of the higher-order bits of the successive approximation data RDA. Details of the DEM control will be described later with reference to FIG.

  When the allocation of the capacitors is dynamically changed in this way, the capacity variations (for example, manufacturing variations) of the unit capacitors are dynamically distributed. This is equivalent to using a separate D / A conversion circuit at each A / D conversion operation, so that a plurality of A / D conversion data QDA having different values can be obtained for the same sampling signal SIN. become. Also, the DEM control can improve the INL (Integral Non Linearity) characteristic and DNL (Differential Non Linearity) characteristic of the A / D conversion circuit.

  The code data generation unit 90 outputs code data CDA having a different value at each A / D conversion operation. The D / A conversion circuit DAC2 performs D / A conversion of the code data CDA. The comparison circuit 10 compares the addition signal SADD of the sampling signal SIN and the D / A conversion signal SCD of the code data CDA with the D / A conversion signal DQ of the successive approximation data RDA. Since the A / D conversion signal QDA has a larger value by the code data CDA, the control unit 20 subtracts the code data CDA from the A / D conversion signal QDA and outputs it as the final A / D conversion signal QC. To do. The output unit 40 outputs an average value DOUT of the 16 A / D conversion signals QC. Details of the code shift will be described later with reference to FIG.

  In the code shift, the offset signal SCD is intentionally added to the sampling signal SIN, and the successive comparison data RDA is changed by the offset signal SCD. By changing the offset signal SCD at each A / D conversion operation, the D / A conversion circuit DAC1 performs D / A conversion of different successive comparison data RDA at each A / D conversion operation. As a result, an effect equivalent to shifting the D / A conversion characteristic for the input data of DAC 1 can be obtained, so that a plurality of A / D conversion data QDA having different values for the same sampling signal SIN can be obtained. become. Further, the INL characteristic and the DNL characteristic of the A / D conversion circuit can be improved by the code shift.

  FIG. 5 is a timing chart showing the operation of the A / D conversion circuit of FIG. As shown in FIG. 5, the sample and hold operation is performed in synchronization with the rising edge of the clock CK3, and 16 A / D conversion operations are performed in synchronization with the rising edge of the 16 clocks CK2. A 14-bit successive approximation is performed in synchronization with the rising edge of CK1. For example, the control unit 20 generates the clocks CK1 to CK3 based on a system clock supplied from the system.

  Specifically, as shown by A1 in FIG. 5, the sampling signal SIN1 is sampled and held at the rising edge of the clock CK3. As shown in A2, the rise of the first clock CK2 is at the same timing as the rise of the clock CK3. The first A / D conversion operation is started at the rising edge of the first clock CK2, and the DEM control signal DEM1 is input to the D / A conversion circuit DAC1 as indicated by A3. Data CDA1 is input to the D / A conversion circuit DAC2.

  As shown in A5, the 14 clocks CK1 are generated between the rising edge of the clock CK2 and the rising edge of the next clock CK2. As shown at A6, the 14-bit successive approximation data RDA is successively compared at the rise of the 14 clocks CK1. During the successive comparison, the D / A conversion circuit DAC1 assigns capacitors based on DEM1, and the D / A conversion circuit DAC2 outputs a signal SCD obtained by D / A converting CDA1. As shown in A7, when the comparison of all the bits of the successive approximation data RDA is completed, the first A / D conversion data QC1 is output. As shown at A8, the A / D conversion data QC1 is latched at the rising edge of the second clock CK2.

  The above operation is performed while changing the DEM control signal and the code data at the rising edge of the second to sixteenth clock CK2, and the second to sixteenth A / D conversion data QC2 to QC16 are output. As indicated by A9, the output data DOUT1 is output at the timing when the 16th A / D conversion data QC16 is latched. As shown at A10, the next A / D conversion operation is started at the rising edge of the clock CK3.

For example, the output unit 40 in FIG. 4 obtains the output data DOUT1 using a moving average filter expressed by the following equation (1). In the following formula (1), “z ⁻ⁱ ” represents A / D conversion data QC obtained i cycles before the clock CK2, and “1” represents the latest A / D conversion data QC. Data represented by “z ⁻ⁱ ” or “1” is stored in a latch circuit or a register (not shown) of the output unit 40. In the following equation (1), when 16 pieces of 14-bit data are added, the data becomes a maximum of 18 bits, and is divided by 4 (shifted by 2 bits), so that 16-bit DOUT is obtained.
DOUT = (1 + z ⁻¹ + z ⁻² +... + Z ⁻¹⁵ ) / 4 (1)

  FIG. 6A shows a simulation result when normal oversampling is performed. In order to compare with the pseudo oversampling of this embodiment, it is assumed that an ideal decimation filter having the same data output rate as that of this embodiment is provided in the subsequent stage, and the band is limited so as to be the same band as this embodiment. A / D conversion characteristics are obtained. FIG. 6B shows a simulation result when the pseudo oversampling of the present embodiment is performed.

  As shown in FIGS. 6A and 6B, compared to normal oversampling, pseudo-oversampling slightly decreases SNR (Signal to Noise Ratio) and effective bit number ENOB, but is much larger. Is not lowered and is at a level that can withstand practical use. In this way, even in applications that cannot be realized by normal oversampling, such as one-shot A / D conversion, practical A / D conversion characteristics can be obtained by performing pseudo oversampling.

  According to the above embodiment, as shown in FIG. 4, the A / D conversion circuit includes the comparison circuit 10 that performs the comparison operation in the successive approximation and the successive approximation that stores the successive comparison data RDA updated by the successive comparison. A control unit 20 having a register SAR and an output unit 40 that outputs output data DOUT based on a result of successive approximation (A / D conversion data QC) are included. As described with reference to FIG. 5, the control unit 20 performs m bits (m is a natural number greater than or equal to 2; for example, m = 14) indicated by A5 to A7 between the sampling operation indicated by A2 and the next sampling operation indicated by A10. ) Is performed a plurality of times (for example, 16 times). The output unit 40 outputs m + j bits (j is a natural number, for example, m + j = 16) of output data DOUT based on a plurality of m-bit data QC1 to QC16 obtained by a plurality of A / D conversion operations.

  In this way, pseudo oversampling can be performed, and the subsequent digital filter can be omitted. That is, output data having the same number of bits as that obtained when normal oversampling is performed can be obtained from a plurality of A / D conversion data obtained for one sample and hold. As a result, the user can handle the output data in the same manner as when performing normal oversampling, and the convenience is not lowered. In addition, one-shot oversampling in which one output data is acquired by only one sample and hold is possible.

  For example, as described with reference to FIG. 3 and the like, the A / D conversion operation is performed a plurality of times while changing the switch control of the D / A conversion circuit according to the control signal SSW (for example, DMP and CDA in FIG. 4). A plurality of A / D conversion data having different values can be obtained for the sampling signal SIN. Thereby, as described with reference to FIG. 6 and the like, an A / D conversion characteristic close to normal oversampling can be achieved.

  In the present embodiment, as shown in FIG. 4, the A / D conversion circuit includes a D / A conversion circuit DAC1 that performs D / A conversion of the successive approximation data RDA. The D / A conversion circuit DAC1 is connected to a comparison node (comparison node NC in FIG. 12 described later) of the comparison circuit 10. The D / A conversion circuit DAC1 includes a capacitor array section (capacitor array section 41 in FIG. 12) and a switch array section (switch array section 51 in FIG. 12). As described with reference to FIG. 4 and the like, the control unit 20 performs each bit of the successive comparison data RDA (bits 5 to 10 in FIGS. 14 to 16B described later) in a plurality of A / D conversion operations. Control (ie, DEM control) for dynamically changing the allocation of the capacitors in the capacitor array unit for each bit) is performed on the switch array unit.

  In this way, the assignment of capacitors (unit capacitors 1C1 to 1C15 and 3C1 to 3C16 in FIG. 14) to the same code of the successive approximation data RDA can be changed at each A / D conversion operation. As described with reference to FIG. 4 and the like, the capacitance value of the unit capacitor varies due to manufacturing errors and the like, and thus a plurality of A / D conversion data having different values can be obtained for the same sampling signal SIN.

  In the present embodiment, as shown in FIG. 4, the A / D conversion circuit includes a second D / A conversion circuit DAC2. The second D / A conversion circuit DAC2 is connected to a comparison node (comparison node NC in FIG. 12 described later) of the comparison circuit 10, and a capacitor array unit (capacitor array unit 43 in FIG. 12) and a switch array unit (FIG. 12). Switch array section 53). As described with reference to FIG. 4 and the like, the control unit 20 performs different switch control on the switch array unit of the second D / A conversion circuit DAC2 at each time of a plurality of A / D conversion operations.

  Specifically, as illustrated in FIG. 4, the control unit 20 includes a code data generation unit 90 that generates different code data CDA at each time of a plurality of A / D conversion operations. The control unit 20 performs switch control of the second switch array unit (switch array unit 53 in FIG. 12) based on the code data CDA. The second D / A conversion circuit DAC2 performs D / A conversion of the code data CDA by switch control by the control unit 20.

  In this way, as described with reference to FIG. 4 and the like, since the D / A conversion signal SCD of the code data CDA changes, the value of the successive approximation data RDA (comparison code) is changed each time in the A / D conversion operation. Can be changed. The analog circuit (D / A conversion circuit DAC1, comparison circuit 10) that performs the comparison operation has static nonlinearity. Therefore, when the comparison code changes, a plurality of A having different values with respect to the same sampling signal SIN. / D conversion data can be obtained.

4). Conversion Prediction Process Next, the conversion prediction process performed by the A / D conversion circuit of this embodiment will be described.

  In a normal successive approximation sequence, successive comparisons are performed at full scale each time. That is, all bits are sequentially compared from the MSB to the LSB of the successive approximation data RDA. On the other hand, in this embodiment, since A / D conversion is performed 16 times for one sampling signal, it is possible to predict the value of A / D conversion data after the second time. Therefore, in the second and subsequent successive comparison sequences, the conversion is not performed at the full scale, but the conversion is performed within the conversion prediction range based on the prediction value.

Specifically, as shown in FIG. 7, the full scale 0 to 16383 (2 ¹⁴ −1) of the A / D conversion data corresponds to the full scale V _FS of the input voltage (input signal). It is assumed that data QD1 (corresponding to QDA in FIG. 4) is obtained as a result of the first successive comparison. Data QD1 is code-shifted by code data CS1, and data shifted by code data CS2 is obtained in the second successive comparison. Therefore, the data obtained by the second successive comparison is predicted as QD2 ′ = QD1 + CS2−CS1. The predicted value QD2 ′ is given a range of ± ESTRNG (for example, ESTRNG = 16), and the second successive comparison is performed in the conversion prediction range of QD2′−ESTRNG to QD2 ′ + ESTRNG. For the 3rd to 16th successive comparisons, the conversion prediction range is set in the same manner and the successive comparison is performed.

  By performing such conversion prediction processing, it is possible to limit the data range in which successive comparisons are performed. Therefore, it is only necessary to compare some bits of successive comparison data RDA, and the successive approximation sequence can be shortened. Thereby, the efficiency of A / D conversion and the speeding up of A / D conversion can be achieved.

  FIG. 8 shows a flowchart of the A / D conversion operation when the conversion prediction process is performed. When the process shown in FIG. 8 is started, a comparison upper limit register that stores the upper limit value of the conversion prediction range and a comparison lower limit value register that stores the lower limit value of the conversion prediction range are initialized (step S1). That is, the upper limit value 14b11_1111_1111_1111 is set in the comparison upper limit value register, and the lower limit value 14b00_0000_0000_0000 is set in the comparison lower limit value register.

  Next, the pseudo oversampling operation is started (step S2), and the successive approximation operation is started (step S3). When the successive approximation operation is started, a comparison code u (successive comparison data) is generated from the upper limit value and the lower limit value (step S4). Specifically, each bit of the upper limit value and the lower limit value is compared from the MSB side, and the data is substituted into the corresponding bits of the comparison code u up to the same data bit. For bits with different data, “1” is assigned to the corresponding bit of the comparison code u, and “0” is assigned to the subsequent bits of the comparison code u. In the case of the upper limit value 14b11_1111_1111_1111 and the lower limit value 14b00_0000_0000_0000, the first bit with different data is the MSB, so the comparison code u = 14b10_0000_0000_0000.

  Next, the comparison code u is input to the D / A conversion circuit (step S5), and an analog circuit composed of the S / H circuit, the D / A conversion circuit, and the comparator performs a comparison operation (step S6). Next, it is determined whether the comparator output is H level or L level (step S7). When the comparator output is at the H level, the sampling signal level is smaller than the signal level obtained by D / A converting the comparison code u, so the upper limit value is updated to u−1 (steps S8 and S9). When the comparison code u = 14b10_0000_0000_0000, the upper limit value 14b01_1111_1111_1111 and the lower limit value 14b00_0000_0000_0000 are obtained. In this case, the next comparison code is u = 14b01_0000_0000_0000. On the other hand, when the comparator output is L level, the level of the sampling signal is larger than the signal level obtained by D / A conversion of the comparison code u, so the lower limit value is updated to u (step S10). When the comparison code u = 14b10_0000_0000_0000, the upper limit value 14b11_1111_1111_1111 and the lower limit value 14b10_0000_0000_0000 are obtained. In this case, the next comparison code is u = 14b11_0000_0000_0000.

Next, it is determined whether or not the upper limit value and the lower limit value match (step S11). If they do not match, the sequential comparison operation of steps S3 to S11 is performed. On the other hand, if they match, the successive approximation operation ends. In the first successive comparison operation, the 14-bit data is sequentially compared for all the bits from the MSB as described above, so steps S3 to S11 are repeated 14 times. When the successive approximation operation ends, u-CS (n) obtained by subtracting the code data CS (n) from the comparison code u is stored in the moving average filter (steps S12 and S13). In the moving average filter, u-CS (n) is stored as data “1”, the moving average of the past 15 conversion data “z ⁻¹ ” to “z ^-15 ” is performed, and output data is output ( Step S14).

  Next, the upper limit value and the lower limit value are updated using the conversion data (comparison code u) (step S15). That is, from the code data CS (n + 1) used for the n + 1th (next) successive approximation operation and the code data CS (1) used for the first successive approximation operation, the upper limit value of the conversion prediction range is set to u + CS (n + 1). −CS (1) + ESTRNG is set (step S16). Also, the lower limit value of the conversion prediction range is set to u + CS (n + 1) −CS (1) −ESTRNG (step S17). Next, it is determined whether or not n = 16 (step S18). If not n = 16, the pseudo oversampling operation in steps S2 to S18 is performed, and if n = 16, the process ends. To do.

  In the successive approximation operation at n = 2 to 16, successive approximation is performed in the conversion prediction range having a width of ± ESTRNG. For example, it is assumed that the upper limit value 14b10_0010_1111_1111 and the lower limit value 14b10_0010_0000_1011 are set in steps S16 and S17. Since the 7th bit is the first data difference from the MSB side, when step S4 is executed next, the 6th bit from the MSB is passed through, and the 8th bit and thereafter from the MSB is set to “0”. The comparison code u = 14b10_0010_1000_0000 is generated. In this case, since it is not necessary to perform sequential comparison for at least the upper 6 bits, it is sufficient to perform sequential comparison of the lower 8 bits at the maximum. Thus, in the successive approximation operation at n = 2 to 16, the number of loops in steps S3 to S11 is smaller than 14, and the successive approximation sequence is shortened.

  FIG. 9 shows a timing chart of the A / D conversion operation when the conversion prediction process is performed. As shown in B1 of FIG. 9, when sample and hold is performed, 16 A / D conversion operations are started. As shown in B2, in the second A / D conversion operation, the sequential comparison is completed only by comparing the number of bits smaller than 14 bits (for example, 8 bits). In this case, the number of clocks of the clock CK1 is the same as the number of bits to be compared (for example, 8). Therefore, in the 2nd to 16th A / D conversion operations, the cycle of the clock CK2 (for example, from the rise of B3 to the rise of B4) is shortened. By this shortening, the output data DOUT1 indicated by B6 can be output before the rising edge of the clock CK3 indicated by B5. In the period TLP from the output of the output data DOUT1 shown in B6 to the rising edge of the clock CK3 shown in B5 (next sampling operation), it is not necessary to perform the A / D conversion operation, so the A / D conversion circuit is disabled. Or set to the low power consumption mode. In this way, low power consumption of the A / D conversion operation can be realized by the conversion prediction process.

  FIG. 10 shows the characteristics of the cycle number of successive approximation with respect to the width ESTRNG of the conversion prediction range. The number of cycles of successive approximation is the number of cycles of successive approximation performed for one sample and hold. The loop of steps S3 to S11 executed in the A / D conversion operation of n = 1 to 16 in FIG. The total number of times. In FIG. 10, D1 shows the maximum number of cycles, and D2 shows the average number of cycles.

  As shown in FIG. 10, as ESTRNG is reduced, the number of cycles is reduced, and the successive approximation sequence is shortened. For example, when ESTRNG = 16 is set, the maximum number of cycles is 110 cycles. When conversion prediction is not performed, 14 bits × 16 times = 224 cycles are necessary, so that the A / D conversion operation can be completed in about half of the time required when conversion prediction is not performed. Note that if ESTRNG is too small, the conversion data may not enter the conversion prediction range. Therefore, an appropriate ESTRNG may be set within the conversion prediction range in consideration of circuit characteristics and the like.

  According to the above embodiment, as described with reference to FIG. 8 and the like, the control unit 20 sets the upper limit value and the lower limit value that determine the data range (conversion prediction range) for successive comparison to the nth A / D conversion operation. Is updated based on the data (comparison code u) obtained by the above (steps S15 to S17). In the (n + 1) th (next) A / D conversion operation (steps S2 to S18), the control unit 20 performs successive comparison (steps S3 to S11) in the updated data range.

  Specifically, as described with reference to FIG. 8 and the like, the control unit 20 has a data range including a predicted value [u + CS (n + 1) −CS (1)] of data obtained by the next A / D conversion operation. An upper limit value [u + CS (n + 1) −CS (1) + ESTRNG] and a lower limit value [u + CS (n + 1) −CS (1) −ESTRNG] are set (steps S16 and S17).

  More specifically, the control unit 20 includes the data (comparison code u) obtained by the A / D conversion operation, the code data CS (n) in the A / D conversion operation, and the next A / D conversion operation. Based on the code data CS (n + 1), a predicted value [u + CS (n + 1) −CS (1)] is obtained.

  Thus, conversion prediction can be performed by pseudo oversampling. That is, since the second and subsequent A / D conversion data obtained with respect to the same sampling signal SIN can be predicted from the first A / D conversion data, the second and subsequent sequential using the predicted value. The data range to be compared can be narrowed. Thereby, the time from the start of the A / D conversion operation until the output data is obtained (from B1 to B6 in FIG. 9) can be shortened.

  In the present embodiment, as described with reference to FIG. 9 and the like, the A / D conversion circuit is in a period from the time when the output data DOUT is output as indicated by B6 to the next sampling operation indicated by B5 (period TLP). The disabled state or the low power consumption mode is set.

  Here, the disabled state is a state in which the components of the A / D conversion circuit are set to a non-operating state, and is set by a disable signal supplied from the system to the control unit 20, for example. Alternatively, the control unit 20 may include a clock generation circuit, and the clock generation circuit may generate the clocks CK1 to CK3 based on a clock supplied from the system. In this case, the clock generation circuit may stop (mask) the supply of the clocks CK1 to CK3, so that the components of the A / D conversion circuit may be set to a non-operating state. The low power consumption mode is a mode in which the power consumption is smaller than the power consumption when the A / D conversion circuit is operating. For example, this is a mode in which power is not supplied (or decreases) to the analog circuits constituting the A / D conversion circuit.

  In this way, it is possible to reduce the power consumption of the A / D conversion circuit during the time that is free due to the reduction of the time from the start of the A / D conversion operation until the output data is obtained. That is, in pseudo oversampling, power consumption can be reduced by conversion prediction processing.

5. Code Shift Method Details of the code shift performed by the present embodiment will be described by taking an example in which the number of bits of A / D conversion is 8 bits. FIG. 11A shows DNL characteristics and INL characteristics when the A / D conversion circuit does not perform code shift as a comparative example of the present embodiment. As shown in FIG. 11A, for example, a missing code is generated with a specific code due to a DNL error or the like. For example, when DNL exceeds 1LSB, a missing code phenomenon occurs in which a code having no output code is generated.

  In this regard, according to the present embodiment, as described with reference to FIG. 4 and the like, the D / A conversion signal SCD of the code data CDA that changes with time is added to the sampling signal SIN, so that FIG. A code shift as shown in FIG. Note that the solid line in FIG. 11B represents the characteristic after code shift, and the broken line represents the characteristic before code shift.

  That is, in this embodiment, the code data CDA is set to a different value for each one or a plurality of A / D conversion timings, so that the location of the code where the missing code is generated is shown in FIG. It changes every one or a plurality of A / D conversion timings. For example, even if a missing code is generated with a code of 1000010000, the location is shifted to a location of 00010001, 00010010, or 00001111. As a result, when viewed over a long time range, as shown in FIG. 11C, DNL and INL are improved, and good characteristics that do not cause the phenomenon of missing codes can be obtained. In other words, the deterioration of the DNL characteristic (missing code) that has occurred in a specific code is diffused to surrounding codes by the code data CDA that changes with time to improve the characteristic.

  That is, consider the case where the offset voltage is intentionally added to the input voltage in the state where the missing code is generated as shown in FIG. The DNL and INL characteristics at that time are shifted as if by a code corresponding to the applied offset voltage, as shown in FIG. In this case, since the code corresponding to the offset voltage is added to the digital data converted by the A / D conversion circuit, the final result can be obtained by subtracting the code corresponding to the offset voltage. The code shift method of this embodiment uses this characteristic and adds a different offset voltage to the input voltage every time. By doing this, the A / D conversion circuit having the characteristics shown in FIG. 11C apparently performs conversion.

  For example, consider a case in which a voltage corresponding to a code in which a missing code is generated is A / D converted. When code shift is not performed, nonlinear conversion is performed around this input voltage. On the other hand, when code shift is performed by a certain value, conversion with good linearity is performed around the input voltage. In other words, by performing code shift with various values, a certain code shift value is non-linear, but most code shift values are linearly converted. Finally, by performing the code shift, a relatively linear conversion is performed even in the input voltage where the missing code is originally generated.

  As described above, according to the present embodiment, by the simple process of generating and adding the code data CDA, the occurrence of the missing code is prevented, and the DNL and INL characteristics of the A / D conversion circuit are improved. Has succeeded.

6). D / A Conversion Circuit FIG. 12 shows a detailed configuration example of the D / A conversion circuit of this embodiment. FIG. 12 shows a configuration example when the number of A / D conversion bits is 8, and shows a detailed configuration example of the DAC1, DAC2, and comparison circuit 10 of FIG. The DAC1 and DAC2 are configured by a charge redistribution type D / A conversion circuit.

  Specifically, the first D / A conversion circuit DAC1 includes a first capacitor array unit 41 and a first switch array unit 51. Also included is a first series capacitor CS1 provided between the comparison node NC and the first node N1. The DAC 1 includes a second capacitor array unit 42 and a second switch array unit 52. In addition, in the sampling period, a switch element SS1 for setting the nodes NC and N1 to GND (AGND) is included.

  The first capacitor array unit 41 of the DAC 1 includes a plurality of capacitors CA1 to CA4. One end of each of the capacitors CA <b> 1 to CA <b> 4 is connected to the comparison node NC of the comparison circuit 10. Here, the comparison node NC (sampling node) is a node connected to the first input terminal (inverting input terminal) of the comparison circuit 10, and the second input terminal (non-inverting input terminal) of the comparison circuit 10 is GND. Set to The capacitors CA1 to CA4 are binary weighted. For example, the capacitance values of CA1, CA2, CA3, and CA4 are C, 2C, 4C, and 8C in the case of 4 bits. The first capacitor array unit 41 also includes a dummy capacitor CDM.

  The first switch array unit 51 of the DAC 1 includes a plurality of switch elements SA1 to SA4. These switch elements SA1 to SA4 are connected to the other ends of the capacitors CA1 to CA4 of the first capacitor array unit 41. The switch elements SA1 to SA4 are switch-controlled based on the higher-order bit data of the successive approximation data RDA (for example, the higher-order 4-bit data when the RDA is 8 bits).

  The second capacitor array unit 42 of the DAC 1 includes a plurality of capacitors CB1 to CB4. One end of each of the capacitors CB1 to CB4 is connected to the first node N1. Here, the first node N1 is a node on the other end side of the series capacitor CS1 whose one end is connected to the comparison node NC. The capacitors CB1 to CB4 are binary weighted. For example, the capacitance values of CB1, CB2, CB3, and CB4 are C, 2C, 4C, and 8C in the case of 4 bits.

  The second switch array unit 52 of the DAC 1 includes a plurality of switch elements SB1 to SB4. The switch elements SB1 to SB4 are connected to the other ends of the capacitors CB1 to CB4 of the second capacitor array unit 42. The switch elements SB1 to SB4 are switch-controlled based on lower-order bit data of the successive approximation data RDA (for example, lower-order 4-bit data when the RDA is 8 bits).

  The second D / A conversion circuit DAC2 includes a second series capacitor CS2 provided between the comparison node NC and the second node N2. A third capacitor array unit 43 and a third switch array unit 53 are also included.

  The third capacitor array unit 43 of the DAC 2 includes a plurality of capacitors CC1 to CC4. One end of each of the capacitors CC1 to CC4 is connected to the second node N2. Here, the second node N2 is a node on the other end side of the series capacitor CS2, one end of which is connected to the comparison node NC. The capacitors CC1 to CC4 are binary weighted. For example, the capacitance values of CC1, CC2, CC3, and CC4 are C, 2C, 4C, and 8C in the case of 4 bits.

  The third switch array unit 53 of the DAC 2 includes a plurality of switch elements SC1 to SC4. These switch elements SC <b> 1 to SC <b> 4 are connected to the other ends of the capacitors CC <b> 1 to CC <b> 4 of the third capacitor array unit 43. The switch elements SC1 to SC4 are switch-controlled based on the code data CDA.

  That is, the code data generation unit 90 in FIG. 4 outputs the code data CDA to the D / A conversion circuit DAC2, and the switch elements SC1 to SC4 are switch-controlled based on the code data CDA. For example, the code data generation unit 90 outputs, as code data CDA, data having a different value for each one or a plurality of A / D conversion timings within the data range of the lower-order bit data of the successive approximation data RDA.

  Specifically, in the case of 8-bit A / D conversion in FIG. 12, the code data CDA is changed within the lower 4-bit data range of the successive approximation data RDA. For example, the code data CDA is randomly changed within the data range of 0000 to 1111 (or within the data range narrower than 0000 to 1111) to switch the switch elements SC1 to SC4 of the switch array unit 53 of the D / A conversion circuit DAC2. Control. At this time, the switch elements SB1 to SB4 of the switch array unit 52 of the D / A conversion circuit DAC1 are also switch-controlled by the lower 4 bits of the successive approximation data RDA. As described above, by setting the range in which the code data CDA is changed within the data range of the successive approximation data RDA for switch-controlling the switching elements SB1 to SB4 of the DAC1, occurrence of missing codes can be effectively prevented.

  It is assumed that the minimum resolution (voltage corresponding to LSB, quantization voltage) of the D / A conversion circuit DAC1 is RS1, and the minimum resolution of the D / A conversion circuit DAC2 is RS2. In this case, RS2 = RS1 in FIG. Specifically, for example, the capacitance values of the series capacitors CS1 and CS2 are the same (almost the same), and the capacitance value of the capacitor CB1 corresponding to the LSB of the DAC1 and the capacitance value of the capacitor CC1 corresponding to the LSB of the DAC2 are also the same. (Almost the same). That is, the DAC 2 outputs a code voltage larger than the noise voltage, not the noise voltage less than the minimum resolution RS1 (LSB) of the DAC 1. In this way, a code shift as shown in FIG. 11B can be realized. In addition, it is not limited to RS2 = RS1, RS2> = RS1 may be sufficient.

  Next, the operation of this embodiment will be described in detail with reference to FIG. As shown in FIG. 13, in the sampling period of the input signal VIN, the switch element SS1 of the main D / A conversion circuit DAC1 is turned on, and the nodes NC and N1 are set to GND. Further, the other ends of the capacitors CA1 to CA4 and CB1 to CB4 are set to the voltage level of VIN via the switch elements SA1 to SA4 and SB1 to SB4 of the D / A conversion circuit DAC1.

  As a result, the input signal VIN is sampled. When the switch elements SA1 to SA4 and SB1 to SB4 are turned off, the voltage of the input signal VIN at that timing is held. In the sampling period, the other end of the dummy capacitor CDM is set to a voltage level of VIN via the dummy capacitor switching element SDM.

  In the sampling period, the other ends of the capacitors CC1 to CC4 are set to GND via the switch elements SC1 to SC4 of the D / A conversion circuit DAC2 for code shift. As a result, both ends of the capacitors CC1 to CC4 are set to GND, and no charge is accumulated.

  Next, in the successive comparison period of A / D conversion, the switch element SS1 of the main D / A conversion circuit DAC1 is turned off. The other end of the dummy capacitor switching element SDM is set to GND.

  Based on each bit of the successive approximation data RDA, the switch elements SA1 to SA4 and SB1 to SB4 of the DAC1 are switch-controlled, and the other ends of the capacitors CA1 to CA4 and CB1 to CB4 are set to VREF or GND.

  For example, when the successive approximation data is RDA = 10000000, the other end of the capacitor CA4 corresponding to the MSB of RDA is set to the reference voltage VREF. The other ends of the other capacitors CA3 to CA1 and CB4 to CB1 are set to GND.

  When the successive approximation data is RDA = 10001000, the other ends of the capacitors CA4 and CB4 are set to VREF. The other ends of the other capacitors CA3 to CA1 and CB3 to CB1 are set to GND.

  In the successive comparison period of A / D conversion, the switch elements SC1 to SC4 of the D / A conversion circuit DAC2 for code shift are switch-controlled based on each bit of the code data CDA, and the other ends of the capacitors CC1 to CC4. Is set to VREF or GND.

  For example, when the code data is CDA = 1000, the other end of the capacitor CC4 is set to VREF, and the other ends of the other capacitors CC3 to CC1 are set to GND. When the code data is CDA = 1100, the other ends of the capacitors CC4 and CC3 are set to VREF, and the other ends of the other capacitors CC2 and CC1 are set to GND.

  In this case, the code data CDA changes at each A / D conversion timing shown in FIG. That is, the code data CDA changes for each A / D conversion period constituted by the sampling period and the successive approximation period. Note that the code data CDA may be changed at every A / D conversion timing.

7). DEM Method Next, details of the DEM (Dynamic Element Matching) method of this embodiment will be described. FIG. 14 shows a detailed configuration example of the first capacitor array unit 41, the first switch array unit 51 on the upper bit side of FIG. 12, and the DEM control unit 80 of FIG.

  The capacitor array unit 41 includes first type capacitors 1C1 to 1C15 and second type capacitors 3C1 to 3C16. The second type capacitors 3C1 to 3C16 have different capacitance values from the first type capacitors 1C1 to 1C15, for example, three times the capacitance value of the first type capacitors 1C1 to 1C15 (integer multiple in a broad sense). . One ends of the first type capacitors 1C1 to 1C15 and the second type capacitors 3C1 to 3C16 are connected to the output node NC.

  The switch array unit 51 includes switch elements SWX1 to SWX15 and SWY1 to SWY16. The switch elements SWX1 to SWX15 and SWY1 to SWY16 are connected to the other ends of the first type capacitors 1C1 to 1C15 and the second type capacitors 3C1 to 3C16. The switch elements SWX1 to SWX15 and SWY1 to SWY16 perform switch control based on the signals DX1 to DX15 and DY1 to DY16 generated by D4 to D9 on the upper bit side (bits 5 to 10) of the input digital data. Is done.

  Specifically, the switch elements SWX1 to SWX15 and SWY1 to SWY16 connect the other ends of the first type capacitors 1C1 to 1C15 and the second type capacitors 3C1 to 3C16 to the input signal VIN in the sampling period.

  The switch elements SWX1 to SWX15 and SWY1 to SWY16 connect the other ends of the first type capacitors 1C1 to 1C15 and the second type capacitors 3C1 to 3C16 to VREF or GND in the successive comparison period (in the conversion period (conversion period)). For example, when the logic levels of the signals DX1 to DX15 and DY1 to DY16 are “1”, they are connected to the reference voltage VREF, and when the logic levels of the signals DX1 to DX15 and DY1 to DY16 are “0”. Connect to GND.

  The DEM control unit 80 includes first and second assignment determination circuits 21 and 22 and first and second counters 23 and 24.

  The first counter 23 performs a count process and outputs the first count value CTX to the first assignment determination circuit 21. Based on the first count value CTX from the first counter 23, the first allocation determination circuit 21 is configured to use the first type capacitors 1C1 to 1C15 for the respective bits (bits 5 to 10) of the input digital data D4 to D9. The process of determining the assignment of.

  The second counter 24 performs a counting process and outputs the second count value CTY to the second allocation determination circuit 22. Based on the second count value CTY from the second counter 24, the second allocation determining circuit 22 is connected to the second type capacitors 3C1 to 3C16 for each bit (bit 5 to bit 10) of the input digital data D4 to D9. The process of determining the assignment of.

  As described above, the first and second assignment determining circuits 21 and 22 perform the assignment determining process of the first type capacitors 1C1 to 1C15 and the second type capacitors 3C1 to 3C16 to each bit of the input digital data, so that the capacitors A DEM of the capacitor of the array unit 41 is realized. The allocation determination processing by the first and second allocation determination circuits 21 and 22 can be realized by, for example, bit rotation processing using the input digital data D4 to D9.

  When the total count number of the first counter 23 is the first total count number and the total count number of the second counter 24 is the second total count number, the first and second counters 23, Reference numeral 24 denotes a counter having different first and second total count numbers. Specifically, the first and second counters 23 and 24 are counters in which the greatest common divisor of the first and second total count numbers is 1. For example, the first total count number of the first counter 23 is 15, and the second total count number of the second counter 24 is 16. The first common count number = 15 and the second total count number = 16 have the greatest common divisor of 1. Note that the first and second total count numbers are not limited to 15 and 16, but may be at least different total count numbers. Desirably, the first and second total count numbers may be total count numbers whose greatest common divisor is 1.

  Next, the DEM method of this embodiment will be described in detail with reference to FIGS. 15 (A) to 16 (B). Hereinafter, the first type capacitors 1C1 to 1C15 are collectively referred to as “1C” as appropriate, and the second type capacitors 3C1 to 3C16 are collectively referred to as “3C” as appropriate.

  FIG. 15A shows an example of the number of allocations of the first type capacitor 1C and the second type capacitor 3C to the respective bits 5 to 10 of the input digital data. As described above, the capacitance value of the second type capacitor 3C is three times the capacitance value of the first type capacitor 1C.

  For example, one first-type capacitor 1C is assigned to bit 5 (D4) of the input digital data. Similarly, two and four first-type capacitors 1C are assigned to bits 6 and 7 (D5 and D6), respectively. As a result, the capacitors CA1, CA2, and CA3 of FIG. 2 weighted in binary such as 1: 2: 4 are realized. That is, the capacitors CA1, CA2, and CA3 correspond to the bits 5, 6, and 7 in FIG. 15A and are realized by one, two, and four first-type capacitors 1C, respectively.

  Two first-type capacitors 1C and two second-type capacitors 3C are assigned to bit 8 (D7) of the input digital data. Similarly, four first-type capacitors 1C and four second-type capacitors 3C are allocated to bit 9 (D8), and two first-type capacitors 1C and 10 are allocated to bit 10 (D9). The second type capacitor 3C is assigned. As a result, capacitors CA4, CA5, and CA6 weighted in binary such as 8:16:32 are realized. That is, the capacitors CA4, CA5, and CA6 correspond to the bits 8, 9, and 10 in FIG. 15A, respectively, and the capacitors CA4, CA5, and CA6 have two, two, four, and four, This is realized by a pair of the first type capacitor 1C and the second type capacitor 3C such as two and ten.

  Although FIG. 15A shows the case where the second type capacitor 3C is a capacitor having a capacitance value three times that of the first type capacitor 1C, the present embodiment is not limited to this. For example, in FIG. 9B, the second type capacitor 6C is a capacitor having a capacitance value six times that of the first type capacitor 1C. FIG. 15B shows each bit of the input digital data in this case. An example of the number of allocations of the first type capacitor 1C and the second type capacitor 6C to 5 to 10 is shown. Also by the assignment in FIG. 15B, the capacitors CA1, CA2, CA3, CA4, CA5, and CA6 of the capacitor array unit 41 weighted in a binary manner such as 1: 2: 4: 8: 16: 32 can be realized.

  FIG. 16A is a diagram for explaining the operation of the first assignment determination circuit 21 in FIG. The first assignment determination circuit 21 generates signals DX1 to DX15 based on the count value CTX from the first counter 23 that is sequentially incremented as 0, 1, 2,. To the unit 51.

  For example, when the count value CTX = 0, the signal DX1 assigns the first type capacitor 1C1 of FIG. 14 to bit 5 (D4) of the input digital data as shown in FIG. Specifically, the switch element SWX1 controlled by the signal DX1 connects the reference voltage VREF to the other end of the first-type capacitor 1C1 when the bit 5 of the input digital data is “1”, and “0”. In this case, GND is connected to the other end of 1C1.

  When the count value CTX = 0, the signals DX2 and DX3 assign the first type capacitors 1C2 and 1C3 in FIG. 14 to bit 6 (D5) of the input digital data as shown in FIG. Specifically, the switch elements SWX2 and SWX3 controlled by the signals DX2 and DX3 connect VREF to the other ends of 1C2 and 1C3 when the bit 6 of the input digital data is “1”, and “0”. In this case, GND is connected to the other end of 1C2 and 1C3.

  Similarly, when the count value CTX = 0, the signals DX4 to DX7, DX8 to DX9, DX10 to DX13, and DX14 to DX15 cause the first type capacitors 1C4 to 1C7, 1C8 to 1C9, 1C10 to 1C13, 1C14 to 1C15 to be , Respectively, are assigned to bits 7, 8, 9, 10 of the input digital data.

  As described above, the first type capacitor 1C is assigned to the bits 5 to 10 as shown in FIG.

  When the count value CTX is incremented, the allocation state of the first type capacitor 1C for each bit of the input digital data changes. That is, as shown in FIG. 16A, every time the count value CTX is incremented, the assignment state of the first type capacitor 1C to each bit by DX1 to DX15 (signal state of DX1 to DX15) is sequentially leftward. As a result, the assignment of the first type capacitor 1C to each bit of the input digital data changes dynamically.

  For example, as shown in FIG. 16A, when the count value CTX = 1, the first type capacitors 1C1 and 1C2 are assigned to the bit 6 of the input digital data by the signals DX1 and DX2. In other words, when the count value CTX = 0, 1C1 is assigned to bit 5, but when the count value is incremented to CTX = 1, 1C1 is assigned to bit 6.

  When the count value CTX = 1, the first type capacitors 1C3 to 1C6 are assigned to bit 7 of the input digital data by the signals DX3 to DX6. That is, when the count value CTX = 0, 1C3 is assigned to bit 6, but when the count value is incremented to CTX = 1, 1C3 is assigned to bit 7.

  When the count value is incremented from CTX = 1 to CTX1 = 2, 1C1 is assigned to bit 6 by the signal DX1, and 1C2 to 1C5 are assigned to bit 7 by the signals DX2 to DX5. Accordingly, the assignment of the first type capacitor 1C to each bit of the input digital data changes dynamically, and the DEM is realized. That is, since the first type capacitors 1C1 to 1C15 are used evenly for the upper bits 5 to 10 of the input digital data, the apparent capacitance ratio accuracy can be improved.

  FIG. 16B is a diagram for explaining the operation of the second assignment determination circuit 22 of FIG. The second allocation determination circuit 22 generates signals DY1 to DY16 based on the count value CTY from the second counter 24 that is sequentially incremented as 0, 1, 2,. To the unit 51.

  For example, when the count value CTY = 0, the second type capacitors 3C1 and 3C2 are assigned to bit 8 of the input digital data by the signals DY1 and DY2. Specifically, the switch elements SWY1, SWY2 controlled by the signals DY1, DY2 apply the reference voltage VREF to the other ends of the second type capacitors 3C1, 3C2 when the bit 8 of the input digital data is “1”. If it is “0”, GND is connected to the other end of 3C1 and 3C2.

  When the count value CTY is incremented, the allocation state of the second type capacitor 3C for each bit of the input digital data changes. That is, as shown in FIG. 16B, every time the count value CTY is incremented, the assignment state of the second type capacitor 3C to each bit by DY1 to DY16 (signal state of DY1 to DX16) is sequentially leftward. As a result, the assignment of the second type capacitor 3C to each bit of the input digital data changes dynamically.

  For example, as shown in FIG. 16B, when the count value CTY = 1, the second type capacitor 3C1 is assigned to bit 8 by the signal DY1, and the second type capacitors 3C2 to 3C5 are bit by the signals DY2 to DY5. 9 is assigned. That is, when the count value CTY = 0, 3C2 is assigned to bit 8, but when the count value is incremented to CTY = 1, 3C2 is assigned to bit 9. Accordingly, the assignment of the second type capacitor 3C to each bit of the input digital data changes dynamically, and the DEM is realized.

8). Fully Differential D / A Converter Circuit FIG. 17 shows a detailed configuration example of a fully differential D / A converter circuit. FIG. 17 is a configuration example when the number of bits of A / D conversion is 8 bits, and shows a detailed configuration example of the DAC1, DAC2, and comparison circuit 10 of FIG. The D / A conversion circuit of FIG. 17 includes a main D / A conversion circuit DAC1P connected to the non-inverting input terminal of the comparison circuit 10 and a main D / A conversion circuit DAC1N connected to the inverting input terminal. Further, a D / A conversion circuit DAC2P for code shift connected to the non-inverting input terminal of the comparison circuit 10 and a D / A conversion circuit DAC2N for code shift connected to the inverting input terminal are included.

  The configuration of the main DAC 1P on the non-inversion side (positive side) and the main DAC 1N on the inversion side (negative side) includes a capacitor array unit and a switch array unit, similarly to the main DAC 1 in FIG. The DAC 1P receives a non-inverted (positive) input signal PIN constituting a differential signal, and the DAC 1N receives an inverted (negative) input signal NIN constituting a differential signal. .

  In the sampling period, the nodes NCP and N1P of the DAC 1P are set to the common voltage (intermediate voltage) VCM by the switch elements SS1P and SS2P. The nodes NCN and N1N of the DAC 1N are set to the common voltage VCM by the switch elements SS1N and SS2N.

  In the sampling period, one end of the switch elements SA1P to SA4P and SB1P to SB4P of the DAC 1P is connected to the signal PIN on the non-inversion side of the differential signal, and one end of the switch elements SA1N to SA4N and SB1N to SB4N of the DAC 1N It is connected to the signal NIN on the inversion side of the motion signal.

  On the other hand, in the successive approximation period, one end of the switching elements SA1P to SA4P and SB1P to SB4P of the DAC 1P is connected to VREF when the corresponding bit of the successive approximation data is “1”, and is “0”. Is connected to GND.

  On the other hand, one end of each of the switching elements SA1N to SA4N and SB1N to SB4N of the DAC 1N is connected to the GND when the corresponding bit of the successive approximation data is “1”, and is one when it is “0”. Connected to VREF.

  The non-inverted code shift DAC 2P and the inverted code shift DAC 2N include a capacitor array section and a switch array section, similar to the code shift DAC 2 in FIG.

  In the sampling period, the node N2P of the DAC 2P is set to VCM by the switch element SS3P. The node N2N of the DAC 2N is set to VCM by the switch element SS3N. Further, one ends of the switching elements SC1P to SC4P of the DAC 2P and the switching elements SC1N to SC4N of the DAC 2N are connected to the VCM.

  On the other hand, in the successive approximation period, one end of the switch elements SC1P to SC4P of the DAC 2P is connected to VREF when the corresponding bit of the code data is “1”, and is connected to GND when the bit is “0”. The On the other hand, one end of each of the switching elements SC1N to SC4N of the DAC 2N is connected to GND when the corresponding bit of the code data is “1”, and is connected to VREF when the bit is “0”.

  Also with the configuration of FIG. 17, the DNL and INL of the A / D conversion circuit can be improved by the code shift method, and the occurrence of a missing code or the like can be prevented. Further, by configuring the A / D conversion circuit as a fully differential type, the amplitude can be increased, the S / N ratio can be improved, and the influence of common mode noise can be reduced.

9. Electronic Device FIG. 18 shows a configuration example of an electronic device including an A / D conversion circuit (D / A conversion circuit) of this embodiment. This electronic device includes a sensor 510, a detection circuit 520, an A / D conversion circuit 530 (D / A conversion circuit), and a processing unit 540. Various modifications may be made such as omitting some of these components or adding other components. For example, the detection circuit 520, the A / D conversion circuit 530, and the processing unit 540 can be realized by an integrated circuit device.

  As the electronic device in FIG. 18, for example, various devices such as a biological measurement device (pulse meter, pedometer, etc.), a portable information terminal, a video device (digital camera, video camera), a clock, and the like can be assumed.

  The sensor 510 is a gyro sensor, an acceleration sensor, a photo sensor, a pressure sensor, or the like, and various sensors are used according to the application of the electronic device. The detection circuit 520 amplifies the sensor signal output from the sensor 510 and extracts a desired signal. The A / D conversion circuit 530 converts the detection signal (desired signal) from the detection circuit 520 into digital data and outputs the digital data to the processing unit 540.

  The processing unit 540 performs necessary digital signal processing on the digital data from the A / D conversion circuit 530. The processing unit 540 may perform gain control of the detection circuit 520 and the like. Here, as the digital signal processing performed by the processing unit 540, various processes such as fast Fourier transform for extracting an appropriate desired signal from the sensor signal can be assumed.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. The configuration / operation of the D / A conversion circuit, A / D conversion circuit, and electronic device, the D / A conversion method, the A / D conversion method, the DEM method, the code shift method, and the like are also described in this embodiment. Without being limited, various modifications can be made.

10 comparison circuit, 20 control unit, 21, 22 first and second allocation determination circuit,
23, 24 First and second counters, 30 S / H circuit, 40 output unit,
41-43 1st-3rd capacitor array part,
51-53 1st-3rd switch array part, 80 DEM control part,
90 code data generation unit, 510 sensor, 520 detection circuit,
530 A / D conversion circuit, 540 processing unit,
CA1-CA4, CB1-CB4, CC1-CC4 capacitors,
CDA code data, CDM dummy capacitor,
CK1 to CK3 1st to 3rd clock, CPQ comparison result signal,
CS (n) code data, CTX, CTY count value,
DAC1, DAC2 first and second D / A conversion circuits, DMP DEM control signals,
DOUT output data, ENOB effective number of bits,
ESTRNG conversion prediction range width, NC comparison node,
QC A / D conversion data, RDA successive comparison data,
SA1 to SA4, SB1 to SB4, SC1 to SC4, switch element,
SADD addition signal, SAR successive approximation register,
D / A conversion signal of SCD code data, SDM switch element,
SIN sampling signal, SSW switch control signal, u comparison code

Claims (5)

A comparison circuit for performing a comparison operation in successive approximation;
A control unit having a successive approximation register for storing successive comparison data updated by the successive approximation, and a code data generation unit;
A first D / A conversion circuit connected to a comparison node of the comparison circuit and performing D / A conversion of the successive approximation data;
A second D / A conversion circuit connected to the comparison node and performing D / A conversion of code data from the code data generation unit ;
An output unit for outputting output data based on the result of the successive comparison;
Including
The controller is
Between the sampling operation and the next sampling operation of the sampling operation, a control process for performing an A / D conversion operation of m bits (m is a natural number of 2 or more) a plurality of times is performed.
The code data generator is
Generates different said code data in each time of the plurality of A / D conversion operation,
Before Symbol output section,
Based on a plurality of m-bit data obtained by the plurality of A / D conversion operations, the output data of m + j bits (j is a natural number) is output,
The controller is
Based on the data obtained by the A / D conversion operation, the code data in the A / D conversion operation, and the code data in the next A / D conversion operation, the next A / D conversion operation Find the predicted value of the resulting data,
An A / D conversion circuit , wherein an upper limit value and a lower limit value of a data range including the predicted value are set as an upper limit value and a lower limit value that determine a data range for the successive comparison . In claim 1,
The first D / A conversion circuit includes:
A capacitor array section and a switch array section;
The controller is
Control for changing the allocation of the capacitors in the capacitor array section of the first D / A converter circuit for each bit of the successive approximation data at each of the plurality of A / D conversion operations, An A / D conversion circuit, which is performed on the switch array unit of the D / A conversion circuit. In claim 1 or 2,
The second D / A conversion circuit includes:
A capacitor array section and a switch array section;
The controller is
Based on the code data, switch control for the switch array unit of the second D / A conversion circuit,
The second D / A conversion circuit includes:
An A / D conversion circuit which performs D / A conversion of the code data by switch control by the control unit. In any one of Claims 1 thru | or 3 ,
The A / D conversion circuit is set to a disabled state or a low power consumption mode from the output of the output data to the next sampling operation. An electronic apparatus comprising the A / D converter circuit according to any one of claims 1 to 4.

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