JP6137732B2 - Epitaxial wafer and method for manufacturing the same - Google Patents

Description

  The present invention relates to an epitaxial wafer and a manufacturing method thereof, and more specifically to a manufacturing method for manufacturing an epitaxial wafer with high accuracy, and an epitaxial wafer used in the manufacturing method.

  Since III-V group compound semiconductors such as InP have a band gap energy corresponding to the near infrared to infrared region, research and development of light receiving elements for communication, biopsy, night imaging and the like are being performed. In this near-infrared to infrared wavelength range, the absorption spectrum of substances related to living organisms and the environment is located. Therefore, it is important to expand the light-receiving sensitivity to the long-wavelength range of the light-receiving element using InP or the like. It has become. For example, in order to increase sensitivity in a longer wavelength region, there has been proposed a mesa type single pixel photodiode having an InGaAs / GaAsSb type 2 multiple quantum well (MQW) light receiving layer on an InP substrate. (Non-Patent Document 1). The mesa type single pixel photodiode has a cut-off wavelength of 2.39 μm, and shows sensitivity characteristics from a wavelength of 1.7 μm to 2.7 μm.

  On the other hand, in order to form a photodiode in which a plurality of pixels are arranged, such as an imaging device, it is necessary to separate each pixel from an adjacent pixel. There are two representative methods for ensuring pixel independence. One is a mesa type in which a pn junction is formed by doping during thin film growth and a groove is provided between pixels. The other is not doped during thin film growth, and impurities are selectively diffused from the window layer after the window layer is formed. This is a planar method in which a pn junction is formed by doping. In the planar method, a region where impurities are not selectively diffused occurs between the pixels, thereby separating the pixels. A near-infrared to infrared light-receiving element is strongly required to reduce the dark current because the photon energy to be received is small. In the mesa method, it is inevitable that the end of the pn junction is exposed to the atmosphere during manufacturing. For this reason, impurities such as oxygen adhere to the end of the pn junction to increase the dark current. On the other hand, the planar method can keep the dark current low. On the other hand, the mesa method has an advantage of increasing the pixel density.

  However, when impurities are selectively diffused from a window layer into a laminate such as a light receiving layer / window layer according to the planar method, when the light receiving layer is of type 2 MQW, the crystallinity of the MQW is vulnerable to impurities. is there. In order to solve this problem, a proposal has been made to interpose a relatively thin semiconductor layer called a diffusion concentration distribution adjusting layer, which is a material different from the window layer, between the type 2 MQW light-receiving layer and the window layer (patent) References 1, 2). With this structure, the impurity concentration distribution in the type 2 MQW light-receiving layer is controlled, and a near-infrared to infrared light-receiving element in which dark current is suppressed can be obtained. As another requirement, it is desirable that the diffusion concentration distribution adjusting layer inserted in order to improve the follow-up of movement of moving images or the like is made of a material having high electrical conductivity.

  The diffusion concentration distribution adjusting layer determines an appropriate distribution of the selectively diffused impurities in the light receiving layer, and requires a highly accurate growth technique for the film thickness. In general, semiconductor structures such as MQW are often formed by the MBE (Molecular Beam Epitaxy) method at the research and development stage. MOVPE: Metal Organic Vapor Phase Epitaxy). In the MOVPE method, the source gas or the like slightly changes at every manufacturing opportunity, and becomes an unstable factor of the thickness fluctuation of the diffusion concentration distribution adjusting layer. However, as described above, keeping the high-precision thickness of the diffusion concentration distribution adjusting layer stable is indispensable for stable production of high-quality light-receiving elements. If a defect is found at the final stage of manufacturing the light receiving element, it is possible to review the manufacturing conditions by observing the defect, but it is not so easy to pinpoint the cause of the defect, and the final process After that, the loss is very large.

  Conventionally, there is an example in which a test epitaxial wafer is manufactured and inspected when manufacturing an epitaxial wafer for a hetero bipolar transistor (HBT) that requires high-precision management (Patent Document 3). In this example, rather than measuring the thickness of each layer of the actual product, As missing or the like occurs, the thickness of the base layer is measured after making the thickness thicker than the actual product, and the base layer deposition conditions are set And the like.

JP 2009-206499 A JP 2011-54915 A JP 2001-284363 A

R. Sidhu, et.al. "ALong-Wavelength Photodiode on InP Using Lattice-Matched GaInAs-GaAsSb Type-II Quantum Wells, IEEE Photonics Technology Letters, Vol.17, No.12 (2005), pp.2715-2717

  It is important to form the thickness of the epitaxial layer constituting the semiconductor element with high accuracy, not limited to the diffusion concentration distribution adjusting layer in the planar photodiode. Nevertheless, a method for accurately measuring the thickness of each layer of the epitaxial multilayer has not been obtained in the manufacture of semiconductor elements.

  The present invention provides an epitaxial wafer manufacturing method capable of accurately obtaining appropriate conditions for film formation of each layer of an epitaxial multilayer constituting the semiconductor element, and an epitaxial wafer used therefor. For the purpose.

The method for producing an epitaxial wafer according to the present invention is a method for producing an epitaxial wafer comprising a III-V group semiconductor substrate and a multi-quantum well (MQW) structure positioned on the substrate. In this manufacturing method, a first III-V group semiconductor layer located on the multiple quantum well structure and a second group III-V semiconductor layer located on the first group III-V semiconductor layer Forming a third group III-V semiconductor layer between the first group III-V semiconductor layer and the multiple quantum well structure, and a film of the first group III-V semiconductor layer Measuring a thickness, and forming a third group III-V semiconductor layer and a first group III-V semiconductor layer with materials having etching selectivity , and the third group III-V The thickness of the group semiconductor layer is 0.005 to 0.05 times the thickness of the multiple quantum well structure, and the multiple quantum well structure is In _x Ga _1-x As (0.38 ≦ x ≦ 1). _{, GaAs 1-y Sb y (} 0.36 ≦ y ≦ 1) and a pair or, _{Ga 1-u In u N v} As 1-v and (0.4 ≦ u ≦ 0.8,0 <v ≦ 0.2) and _{GaAs 1-y Sb y (0.36} ≦ y ≦ 0.62) A pair.

  According to the epitaxial wafer manufacturing method and the like of the present invention, appropriate conditions for film formation of each layer of the epitaxial multilayer can be obtained with high accuracy.

It is sectional drawing for demonstrating the manufacturing method of the light receiving element in Embodiment 1 of this invention. It is sectional drawing for demonstrating the epitaxial wafer used for the manufacturing method of the light receiving element of FIG. FIG. 3 is a plan view of the epitaxial wafer of FIG. 2. It is a figure which shows the state which can remove a InP window layer partially by an etching, and can measure a level | step difference. It is a figure which shows the state which removed the InP window layer by the etching. It is a figure which shows the state which can remove a InGaAs diffusion concentration distribution adjustment layer partially by an etching, and can measure a level | step difference. It is a figure which shows the state which removed the InGaAs diffused density distribution adjustment layer by the etching. It is sectional drawing for demonstrating the manufacturing method of the epitaxial wafer in Embodiment 2 of this invention. It is a figure which shows the state which affixed the protective tape on the light reception layer, after removing the InGaAs diffusion density | concentration distribution adjustment layer by an etching. It is a figure which shows the state which can remove a light reception layer partially by an etching, and can measure a level | step difference.

<List of embodiments of the present invention>
First, an embodiment of the present invention is described: 1. a method for manufacturing an epitaxial wafer; The epitaxial wafers are listed and described.
1. Epitaxial wafer manufacturing method:
An epitaxial wafer having a multi-quantum well (MQW) structure on a III-V group semiconductor substrate is manufactured. This manufacturing method includes a first group III-V semiconductor layer positioned on a multiple quantum well structure and a second group III-V semiconductor layer positioned on the first group III-V semiconductor layer. Forming a third group III-V semiconductor layer between the first group III-V semiconductor layer and the multiple quantum well structure, and a film of the first group III-V semiconductor layer Measuring the thickness, and forming the third group III-V semiconductor layer and the first group III-V semiconductor layer with materials having etching selectivity. By forming an epitaxial wafer with a growth apparatus and measuring the thickness and the like of each layer, each layer can be accurately grown to the intended thickness. Specifically, a coating material such as a tape is attached to a predetermined region of the epitaxial wafer, and regions other than the predetermined region are removed by etching to expose the third III-V group semiconductor layer functioning as an etching stop layer. Let That is, since the etching stop layer (third III-V group semiconductor layer) is arranged under the first III-V group semiconductor layer, the cross section of the first III-V group semiconductor layer is surely exposed. Thus, the film thickness can be measured with high accuracy. Further, the X-ray diffraction image (XRD image) and the PL (photoluminescence emission) measurement can be performed on the multiple quantum well structure as it is from above the etching stop layer. As a result, basic data can be obtained for the multiple quantum well structure.

(1) The thickness of the third group III-V semiconductor layer may be 0.005 times to 0.05 times the thickness of the multiple quantum well structure. Thereby, the XRD image and the PL measurement for the multiple quantum well structure can be performed with high accuracy through the third group III-V semiconductor layer, leaving the third group III-V semiconductor layer.

(2) The first group III-V semiconductor layer may not contain phosphorus (P), and the third group III-V semiconductor layer may contain phosphorus. This makes it possible to clearly show the etching selectivity between the first group III-V semiconductor layer and the third group III-V semiconductor layer, that is, the first group III-V semiconductor layer can be easily etched. Etching can be stopped by allowing the third III-V semiconductor layer to function as an etching stop layer while removing it. Usually, since the multiple quantum well structure often does not contain P, the multiple quantum well structure and the first III-V group semiconductor layer have no etching selectivity, and these two layers and the etching stop layer are not selected. This is a desirable configuration for inspection of each layer.

Here, “the third group III-V semiconductor layer and the first group III-V semiconductor layer are made of materials having etching selectivity” means that the first etchant is a first etchant. The third group III-V semiconductor layer is etched, but the third group III-V semiconductor layer is not etched, and vice versa for another predetermined etchant. If TBP is used as a raw material for phosphorus, it decomposes at a low temperature, so that a low-temperature film can be formed. For this reason, it is possible to obtain an epitaxial laminated body having a good crystallinity without causing thermal decomposition of GaAsSb located in the lower layer, and a low dark current can be achieved. Inorganic raw material phosphine (PH ₃ ) may be used.

  Inclusion of P in the third group III-V semiconductor layer to provide etching selectivity is difficult to implement by the MBE method. This is because, as described above, in the MBE method, since a solid material (various phosphorus oxides) is used as the P material, solid phosphorus adheres to the inner wall of the growth chamber, and cleaning must be performed frequently. In the MOVPE method, since a gaseous raw material is used, the P-containing third III-V semiconductor layer can be easily used.

(3) The second III-V group semiconductor layer and the first III-V group semiconductor layer may be made of materials having etching selectivity. Specifically, the second group III-V semiconductor layer may contain phosphorus (P) and the first group III-V semiconductor layer may not contain phosphorus. Accordingly, etching selectivity can be provided between the second III-V group semiconductor layer and the first III-V group semiconductor layer arranged to suppress the surface recombination current, and the second III-V group can be provided. It becomes easy to accurately measure the film thickness by measuring the step by etching the −V group semiconductor layer to expose the cross section. In this case, the first III-V group semiconductor layer functions as an etching stop layer. In the case of the planar type, impurities are selectively diffused from the second group III-V semiconductor layer as described above to form a pn junction or pi (pin) junction at the tip thereof, so that the first group III-V group is formed. Control of the thickness of the second III-V semiconductor layer along with the semiconductor layer is important. The effect of using TBP as a phosphorus raw material is as described above.

(4) The band gap energy of the second III-V group semiconductor layer may be larger than the band gap energy of the multiple quantum well structure. Thereby, the surface recombination current can be reliably suppressed.

(5) The multiple quantum well structure has a pair of In _x Ga _1-x As (0.38 ≦ x ≦ 1) and GaAs _1-y Sb _y (0.36 ≦ y ≦ 1), or Ga _{1 -u in u N v as 1-} v (0.4 ≦ u ≦ 0.8,0 <v ≦ 0.2) and a pair of _{GaAs 1-y Sb y (0.36} ≦ y ≦ 0.62) You may make it consist of. This makes it possible to detect near-infrared to mid-infrared light having a wavelength of 2 μm to 10 μm. These materials constituting MQW have no etching selectivity with the first III-V semiconductor layer and are etched with the etching solution of the first III-V semiconductor layer, so that the third III-V described above is used. The insertion of the group semiconductor layer is effective in inspecting each layer step by step from the upper layer.

(6) The first group III-V semiconductor layer may be made of InGaAs. Since InGaAs has a low impurity diffusion rate, it is a material suitable for the role imposed on the first group III-V semiconductor layer. In addition, since there is no etching selectivity between each layer of the multiple quantum well structure, the third III-V group described above is provided between the first III-V semiconductor layer and the multiple quantum well structure. The configuration in which the semiconductor layer is inserted is effective for inspecting each layer step by step from the upper layer. In addition, since the electric resistance is low as described above, it is possible to improve the followability of moving images and the like.

(7) A buffer layer may be provided between the substrate and the multiple quantum well structure, and the buffer layer and the multiple quantum well structure may be formed of materials having etching selectivity. This makes it possible to obtain an epitaxial layered product of good crystal quality, particularly a high-quality multiple quantum well structure. In addition, a buffer layer with good crystal quality can be obtained by using a P-containing material such as InP or InGaAsP having a multiple quantum well structure and etching selectivity. As a result, the buffer layer functions as an etching stop layer, and the film thickness of the multiple quantum well structure can be accurately performed by the step measurement. In other words, the buffer layer functions as another third group III-V semiconductor layer.

(8) The substrate may be any one of (GaAs, GaP, GaSb, InP, InAs, InSb, AlSb, and AlAs). By using these substrates, it becomes possible to detect light in the near-infrared to mid-infrared region having a wavelength of 2 μm to 10 μm.

2. Epitaxial wafer An epitaxial wafer is an epitaxial wafer used in a method for manufacturing a semiconductor device. That is, the epitaxial wafer includes a III-V group semiconductor substrate and a multi-quantum well (MQW) structure positioned on the substrate. The epitaxial wafer includes a first group III-V semiconductor layer located on the multiple quantum well structure, a second group III-V semiconductor layer located on the first group III-V semiconductor layer, A third group III-V semiconductor layer located between the first group III-V semiconductor layer and the multiple quantum well structure, the third group III-V semiconductor layer and the first group III-V The semiconductor layer is formed of materials having etching selectivity. Thereby, the first III-V group semiconductor layer is selectively etched to expose the cross section, and the thickness thereof can be measured with high accuracy, and the condition setting for the production can be made appropriate.

<Detailed example of embodiment of the present invention>
(Embodiment 1)
FIG. 1 is a sectional view of a light receiving element (planar photodiode) 50 according to the first embodiment of the present invention. The light receiving element 50 is formed on the next epitaxial wafer.
(InP substrate 1 / n-type InGaAs buffer layer 2 / type 2 (InGaAs / GaAsSb) multi-quantum well (MQW) light-receiving layer 3 / InGaAs diffusion concentration distribution adjusting layer 4 / InP window layer 5)

  The main part of the pixel P is formed by the p-type region 6. The p-type region is formed by selectively diffusing zinc (Zn), which is a p-type impurity, from the surface of the window layer 5 in the opening of the selective diffusion mask pattern 36. Independence is ensured by being separated from the adjacent pixel P by a region that is not selectively diffused. A pn junction 15 or a pi junction (a pin junction in a wide range including the ground electrode side) is formed at the tip of the p-type region 6 of each pixel P. The light-receiving layer 3 is intended to be a pin junction without adding impurities in order to make it intrinsic without adding any impurities, but inevitably has a low concentration of impurities (for example, n-type impurities). Contained. For this reason, although it is called a pin type photodiode, a pn junction is actually formed at the tip of the p type region. Here, the pin junction and the pn junction are referred to as a pn junction 15.

  When a reverse bias voltage is applied to the pn junction 15 by the pixel electrode 11 and the common ground electrode 12, a depletion layer protrudes from the light receiving layer 3 for each pixel P and enters a light receiving standby state. When light enters the depletion layer of a pixel P and is received, an electron / hole pair is generated, the hole drifts to the pixel electrode 11, and the electron drifts to the ground electrode 12. An image can be obtained by reading out the charges accumulated in the pixel electrode 11 at a constant time pitch and creating an intensity distribution of the received light signal over the pixels. A near-infrared to infrared light-receiving element is strongly required to reduce the dark current because the photon energy to be received is small. In the mesa method in which the groove is provided between the pixels, it is inevitable that the end of the pn junction is exposed to the atmosphere during manufacturing. For this reason, impurities such as oxygen adhere to the end of the pn junction and dark current is increased. On the other hand, the planar method can be manufactured without exposing the end of the pn junction even during manufacturing, and the dark current can be kept low.

  When the impurity is selectively diffused from the window layer to the stacked body such as the light receiving layer / window layer according to the planar method, there is a problem that when the light receiving layer is of type 2 MQW, the crystallinity of the MQW is vulnerable to the impurity. Even with relatively low impurities, the crystallinity deteriorates and the dark current increases greatly. For this reason, when forming a pn junction, the impurity range to be introduced into the type 2 MQW light-receiving layer must be set as close to the window layer as possible, and its concentration must be controlled strictly low.

  In order to solve this problem, the diffusion concentration distribution adjusting layer 4 is disposed between the light receiving layer 3 of type 2 MQW and the window layer 5. The carrier concentration of the selectively diffused impurity needs to be in ohmic contact with the pixel electrode in the window layer, and is distributed at a high concentration, and needs to be rapidly reduced stepwise in the diffusion concentration distribution adjusting layer. The level is lowered stepwise so that it crosses the background concentration of the opposite type carrier in the light receiving layer at the upper part in the type 2 MQW light receiving layer. The intersection (plane) with the background concentration of the opposite type carrier constitutes a pn junction. With such a structure, the impurity concentration distribution in the type 2 MQW light-receiving layer 3 is strictly controlled, and a near-infrared to infrared light-receiving element in which dark current is suppressed can be obtained. As another requirement, it is desirable that the diffusion concentration distribution adjusting layer 4 inserted in order to improve the follow-up of movement of moving images or the like is made of a material having high electrical conductivity.

  The diffusion concentration distribution adjusting layer 4 determines an appropriate distribution of the selectively diffused impurities in the light receiving layer 3 and requires a highly accurate growth technique. In general, the structure of a semiconductor such as MQW is often formed by the MBE method at the research and development stage. Moreover, when it is put into practical use and enters actual production, it is manufactured by a highly efficient metal organic chemical vapor deposition (MOVPE). In the MOVPE method, the raw material gas or the like slightly changes at every manufacturing opportunity, which becomes an unstable factor of the thickness variation of the diffusion concentration distribution adjusting layer 4. However, as described above, keeping the high-precision thickness of the diffusion concentration distribution adjusting layer 4 stable is essential for stable production of a high-quality light receiving element. When the final stage of manufacturing the light receiving element is reached and a defect in the manufacturing conditions is found, it is possible to review the manufacturing conditions by observing the defect, but it is not so much possible to pinpoint the cause of the defect. It is not easy and the loss is very large after the final process.

FIG. 2 is a cross-sectional view showing a laminated structure of the epitaxial wafer 1a, and FIG. 3 is a plan view. The laminated structure in the epitaxial wafer 1a shown in FIG. 2 is as follows.
(InP substrate 1 / InGaAs buffer layer 2 / type 2 (InGaAs / GaAsSb) multiple quantum well structure light receiving layer 3 / etching stop layer 9 / InGaAs diffusion concentration distribution adjusting layer 4 / InP window layer 5)
A protective tape g is attached to the surface of the InP window layer or the second group III-V semiconductor layer 5.

-Points in the present embodiment-
The point is that an etching stop layer 9 that does not exist in the light receiving element 50 of FIG. 1 is disposed on the epitaxial wafer 1a.

  The material of the etching stop layer (third III-V semiconductor layer) 9 is selected from the InGaAs forming the diffusion concentration distribution adjusting layer or the first III-V semiconductor layer 4 by etching with respect to a predetermined etchant. Must have sex. Furthermore, the thickness of the etching stop layer 9 is preferably 0.005 to 0.05 times the thickness of the light receiving layer 3. Since the total thickness of the type 2 MQW light-receiving layer 3 is about 3 μm, it is preferable to set the thickness to a very small thickness of 15 nm to 150 nm. The reason will be explained step by step. In FIG. 3, the protective tape g is attached to the surface of the InP window layer or the second III-V group semiconductor layer 5. For example, if etching is performed using a 35% hydrochloric acid aqueous solution as an etchant with the protective tape g applied, the InP window layer 5 is etched, and InGaAs is not etched into the 35% aqueous solution, so that the upper surface of the InGaAs diffusion concentration distribution adjusting layer 4 is Exposed. Thereafter, the protective tape g is removed. As a result, as shown in FIG. 4A, the film thickness of the InP window layer 5 can be accurately measured by the step measurement. The step measurement makes it possible to measure the total thickness of the layer whose cross section is exposed with very high accuracy. Since selective diffusion of p-type impurities is performed from the surface of the window layer 5, it is important that the thickness of the window layer 5 can be measured with high accuracy. By associating the measured thickness value of the window layer 5 with the conditions during the film formation of the window layer 5, the window layer of the epitaxial wafer can be formed with high accuracy and stability.

  FIG. 4B is a diagram showing a state in which the InP window layer 5 is removed by etching with a 35% hydrochloric acid aqueous solution except for the protective tape g in FIG. 4A. Next, after the protective tape g is partially attached to the InGaAs diffusion concentration distribution adjusting layer 4, InGaAs diffusion is performed using an etchant of phosphoric acid (85%): hydrogen peroxide (30%): water = 1: 1: 4. The concentration distribution adjusting layer 4 is etched. Thereafter, the protective tape g is removed. As a result, as shown in FIG. 4C, the thickness of the InGaAs diffusion concentration distribution adjusting layer 4 can be accurately measured by the step measurement. The cross section of the InGaAs diffusion concentration distribution adjustment layer 4 can be exposed by the InP etching stop layer 9, and the thickness of the InGaAs diffusion concentration distribution adjustment layer 4 can be measured with high accuracy by the step measurement. As described above, the epitaxial wafer 1a for inspection is grown using the same lot of raw material gas, piping system, growth apparatus such as a growth chamber, and the conditions are recorded. Therefore, based on the measured thickness of the InGaAs diffusion concentration distribution adjusting layer 4 on the inspection epitaxial wafer 1a, it is possible to set the growth conditions of the InGaAs diffusion concentration distribution adjusting layer at the time of the production with high accuracy.

  From the state of FIG. 4C, the InGaAs diffusion concentration distribution adjusting layer 4 is completely removed with an etchant of phosphoric acid (85%): hydrogen peroxide solution (30%): water = 1: 1: 4. As a result, as shown in FIG. 4D, the InP etching stop layer 9 is exposed on the surface. The InP etching stop layer 9 is as thin as 15 nm to 150 nm. Therefore, the X-ray diffraction image (XRD) and photoluminescence measurement (PL measurement) of the type 2 MQW light-receiving layer 3 can be performed with the InP etching stop layer 9 disposed. That is, since the thickness is small, XRD measurement with little influence (fringe) of the InP etching stop layer 9 is possible. Further, since the thickness is small, the influence of absorption of excitation light can be reduced, and stable PL measurement can be performed. Further, since the etching stop layer 9 is made of InP and has a large band gap, the dark current can be reduced.

(Embodiment 2)
FIG. 5 is a cross-sectional view showing a laminated structure of epitaxial wafer 1a in the second embodiment of the present invention. The laminated structure is as follows.
(InP substrate 1 / InP buffer layer 29 / type 2 (InGaAs / GaAsSb) multiple quantum well structure light-receiving layer 3 / InP etching stop layer 9 / InGaAs diffusion concentration distribution adjusting layer 4 / InP window layer 5)

  The difference from the stacked structure in Embodiment 1 shown in FIG. 3A is that the buffer layer is formed of an InP layer in this embodiment. The point is that the InP buffer layer 29 has etching selectivity with the (InGaAs / GaAsSb) MQW light receiving layer 3. The InP buffer layer 29 can also be referred to as an etching stop layer. However, unlike the etching stop layer 9 located in contact with the diffusion concentration distribution adjusting layer 4, the InP buffer layer 29 is also disposed on the production epitaxial wafer or the light receiving element. May be.

  6A is a diagram showing a state in which the protective tape g is attached to the exposed surface of the light receiving layer 3 after the InP etching stop layer 9 in the state of FIG. 4D of the first embodiment is completely removed with a 35% hydrochloric acid aqueous solution. It is. Thereafter, the light-receiving layer 3 having a type 2 (InGaAs / GaAsSb) multiple quantum well structure is etched using an etchant of phosphoric acid (85%): hydrogen peroxide (30%): water = 1: 1: 4. Thereafter, the protective tape g is removed. As a result, as shown in FIG. 6B, the thickness of the light receiving layer 3 can be accurately measured by the step measurement. The cross section of the light receiving layer 3 of type 2 (InGaAs / GaAsSb) MQW is exposed, and the thickness of the light receiving layer 3 of type 2 (InGaAs / GaAsSb) MQW can be accurately measured by the step measurement. The light receiving layer 3 can be formed stably and accurately by feeding back the measured film thickness of the light receiving layer to the production.

(All organometallic vapor phase growth method)
A method for manufacturing the epitaxial wafers of the first and second embodiments by the all-organic metal vapor phase epitaxy will be described.
First, an InP substrate 1 is prepared, placed on a substrate table, and a buffer layer is formed of InGaAs or InP. When the InP buffer layer 29 is grown, tertiary butylphosphine (TBP) is used as a raw material in the all-organic vapor phase growth method. Phosphine (PH ₃ ) may be used. As for the growth of each layer above the buffer layer 2, good crystallinity can be ensured efficiently at a low growth temperature by using the all-organic metal vapor phase growth method. After the buffer layer 2, the type 2 (InGaAs / GaAsSb) MQW light-receiving layer 3, InP etching stop layer 9, InGaAs diffusion concentration distribution adjusting layer 4 and InP window layer 5 are consistently grown in the same growth chamber by an all organic MOVPE method. Grow in. At this time, as described above, the growth temperature or the substrate temperature is preferably maintained in the range of 400 ° C. or more and 525 ° C. or less. This is because if the growth temperature is higher than this temperature range, the GaAsSb in the light receiving layer 3 is damaged by heat and causes phase separation.

  If the growth temperature is lower than 400 ° C., the raw organic MOVPE gas is not sufficiently decomposed, and carbon is taken into the epitaxial layer. This is hydrocarbon carbon bonded to metal in the source gas. When carbon is mixed into the epitaxial layer, an unintended p-type region is formed, and performance degradation occurs in a state where the semiconductor element is finished. For example, in the state of the light receiving element, there is a lot of dark current, and it cannot be a practical product.

  A quartz tube is disposed in the growth chamber (chamber), and a raw material gas is introduced into the quartz tube. A substrate table is disposed in the quartz tube so as to be rotatable and airtight. The substrate table is provided with a heater for heating the substrate. The temperature of the surface of the epitaxial wafer 1a during film formation is monitored by an infrared temperature monitoring device through a window provided on the ceiling of the growth chamber. This monitored temperature is a temperature at the time of growth or a temperature called a film forming temperature or a substrate temperature. In the manufacturing method of the present invention, when an InGaAs layer or the like is formed at a temperature of 400 ° C. or more and 525 ° C. or less, 400 ° C. or more and 525 ° C. or less are temperatures measured by this temperature monitor. The forced exhaust from the quartz tube 65 is performed by a vacuum pump.

The source gas is supplied by a pipe communicating with the quartz tube. An organic metal gas source gas is put in a thermostat and maintained at a constant temperature. Hydrogen (H ₂ ) and nitrogen (N ₂ ) are used as the carrier gas. The organometallic gas is carried by a carrier gas, and is sucked by a vacuum pump and introduced into a quartz tube. The amount of carrier gas is accurately adjusted by an MFC (Mass Flow Controller). Many flow controllers, solenoid valves, and the like are automatically controlled by a microcomputer.

  After the growth of the buffer layer 2, a type 2 MQW light-receiving layer 3 having InGaAs / GaAsSb as a pair of quantum wells is formed. The thickness of GaAsSb in the quantum well is 5 nm, for example, and the thickness of InGaAs is also 5 nm, for example. In the film formation of GaAsSb, TEGa (triethylgallium), TBAs (tertiary butylarsine), and TMSb (trimethylantimony) are used. For InGaAs, TEGa, TMIn, and TBAs can be used. These source gases can be completely decomposed at a relatively low temperature of 400 ° C. or more and 525 ° C. or less, and can contribute to crystal growth. The MQW light-receiving layer 3 can be made abrupt in composition change at the interface of the quantum well by using all organic MOVPE. As a result, highly accurate spectrophotometry can be performed.

As a raw material for Ga (gallium), TEGa (triethylgallium) or TMGa (trimethylgallium) may be used. The raw material for In (indium) may be TMIn (trimethylindium) or TEIn (triethylindium). As a raw material of As (arsenic), TBAs (tertiary butylarsine) or TMAs (trimethylarsenic) may be used. AsH ₃ (arsine) may be used. The raw material for Sb (antimony) may be TMSb (trimethylantimony) or TESb (triethylantimony). Further, TIPSb (triisopropylantimony) or TDMASb (trisdimethylaminoantimony) may be used.

  The source gas is transported through the piping, introduced into the quartz tube, and exhausted. Any number of source gases can be added to the quartz tube by increasing the number of pipes. For example, even a dozen kinds of source gases are controlled by opening and closing the electromagnetic valve. The flow rate of the source gas is controlled by a flow rate controller (MFC), and the flow into the quartz tube is turned on and off by opening and closing the electromagnetic valve. The quartz tube is forcibly exhausted by a vacuum pump. There is no stagnation in the flow of the source gas, and it is performed smoothly and automatically. Therefore, the composition is switched quickly when forming the quantum well pair.

  The surface of the epitaxial wafer 1a is set to a monitored temperature. When large-sized organometallic molecules flow through the wafer surface, the compound molecules that decompose and contribute to crystal growth are in the range where they contact the surface and the film thickness range of several organometallic molecules from the surface. It is considered to be limited. However, when the surface temperature of the epitaxial wafer or the substrate temperature is excessively low, such as less than 400 ° C., huge molecules of the source gas, particularly carbon, are not sufficiently decomposed and removed and are taken into the epitaxial wafer 1a. Carbon mixed in the group III-V semiconductor becomes a p-type impurity and forms an unintended light receiving element. For this reason, the original function of the semiconductor is lowered, and the performance is deteriorated in a state of being manufactured in the light receiving element.

  When a source gas suitable for the chemical composition of the above pair is introduced by switching with an electromagnetic valve while forcibly evacuating with a vacuum pump, after the crystal of the previous chemical composition is grown with a slight inertia, the influence of the previous source gas The crystal having the changed chemical composition can be grown. As a result, the composition change at the hetero interface can be made steep. This means that the previous source gas does not substantially remain in the quartz tube 65.

  When the type 2 (InGaAs / GaAsSb) MQW light-receiving layer 3 is formed, if it grows in a temperature range exceeding 525 ° C., phase separation occurs in the MQW GaAsSb layer on a large scale, and the size and density of the convex portion K described above are increased. Contribute to the increase. On the other hand, as described above, when the growth temperature is lower than 400 ° C., carbon inevitably contained in the source gas is taken into the epitaxial wafer. Since the mixed carbon functions as a p-type impurity, it may cause performance deterioration to a level that does not result in a product when the semiconductor element is finished.

From the formation of the buffer layer 2 to the formation of the InP window layer 5, it is important to continue the growth in the same film forming chamber or quartz tube 65 by the all organic MOVPE method. That is, the epitaxial wafer 1a of the present embodiment does not have a regrowth interface. At the regrowth interface, at least one of the oxygen concentration of 1e17 cm ⁻³ or more and the carbon concentration of 1e17 cm ⁻³ or more is satisfied, the crystallinity is deteriorated, and the surface of the epitaxial multilayer is difficult to be smooth. In the present invention, the oxygen and carbon concentrations are both less than 1e17 cm ⁻³ .

  Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  According to the method for manufacturing an epitaxial wafer of the present invention, the characteristics of each layer of the epitaxial layered product is determined at the inspection stage before the production, instead of finding a defect at the final stage of the semiconductor element manufacturing process. Appropriate conditions for film formation can be obtained with high accuracy.

  1 InP substrate, 1a wafer, 2 InGaAs buffer layer, 3 type 2 MQW light receiving layer, 4 InGaAs layer (diffusion concentration distribution adjusting layer), 5 InP window layer, 6 p-type region, 9 etching stop layer, 11 p-side electrode (Pixel electrode), 12 n side electrode, 15 pn junction, 29 InP buffer layer, 35 AR (antireflection) film, 36 selective diffusion mask pattern, 50 light receiving element (light receiving element array), P pixel.

Claims (12)

An epitaxial wafer manufacturing method comprising a substrate of a III-V semiconductor and a multi-quantum well (MQW) structure positioned on the substrate,
Forming a first group III-V semiconductor layer located on the multiple quantum well structure and a second group III-V semiconductor layer located on the first group III-V semiconductor layer; When,
Forming a third group III-V semiconductor layer between the first group III-V semiconductor layer and the multiple quantum well structure;
Measuring the film thickness of the first group III-V semiconductor layer,
Forming the third group III-V semiconductor layer and the first group III-V semiconductor layer with materials having etching selectivity ;
The thickness of the third group III-V semiconductor layer is 0.005 to 0.05 times the thickness of the multiple quantum well structure,
The multiple quantum well structure includes a pair of In _x Ga _1-x As (0.38 ≦ x ≦ 1) and GaAs _1-y Sb _y (0.36 ≦ y ≦ 1), or Ga _{1-u in u N v as 1-v} (0.4 ≦ u ≦ 0.8,0 <v ≦ 0.2) and _{GaAs 1-y Sb y (0.36} ≦ y ≦ 0.62) and a pair of, An epitaxial wafer manufacturing method. 2. The method for producing an epitaxial wafer according to claim 1 , wherein the first group III-V semiconductor layer does not contain phosphorus (P), and the third group III-V semiconductor layer contains phosphorus. 3. The epitaxial wafer manufacturing method according to claim 1 , wherein the second group III-V semiconductor layer and the first group III-V semiconductor layer are made of materials having etching selectivity. Method. The manufacturing method of the epitaxial wafer of any one of Claims 1-3 with which the said 1st III-V group semiconductor layer is comprised with InGaAs. A buffer layer between the multi-quantum well structure and the substrate, and a multiple quantum well structure and the buffer layer is formed of a material with each other having an etching selectivity, one of the preceding claims 1 The method for producing an epitaxial wafer according to the item. It said substrate, (GaAs, GaP, GaSb, InP, InAs, InSb, AlSb, and AlAs) is any one of, method for manufacturing an epitaxial wafer according to any one of claims 1 to 5. An epitaxial wafer comprising a substrate of a III-V semiconductor and a multi-quantum well (MQW) structure positioned on the substrate,
A first group III-V semiconductor layer located on the multiple quantum well structure; a second group III-V semiconductor layer located on the first group III-V semiconductor layer; and the first group A third group III-V semiconductor layer positioned between the group III-V semiconductor layer and the multiple quantum well structure,
The third III-V group semiconductor layer and the first III-V group semiconductor layer are formed of materials having etching selectivity ,
The thickness of the third group III-V semiconductor layer is 0.005 to 0.05 times the thickness of the multiple quantum well structure,
The multiple quantum well structure includes a pair of In _x Ga _1-x As (0.38 ≦ x ≦ 1) and GaAs _1-y Sb _y (0.36 ≦ y ≦ 1), or Ga _{1-u in u N v as 1-v} (0.4 ≦ u ≦ 0.8,0 <v ≦ 0.2) and _{GaAs 1-y Sb y (0.36} ≦ y ≦ 0.62) and a pair of, An epitaxial wafer. The epitaxial wafer according to claim 7 , wherein the first group III-V semiconductor layer does not contain phosphorus (P), and the second group III-V semiconductor layer contains phosphorus. The epitaxial wafer according to claim 7 or 8 , wherein the second group III-V semiconductor layer and the first group III-V semiconductor layer are made of materials having etching selectivity. The epitaxial wafer according to claim 7 , wherein the first III-V group semiconductor layer is made of InGaAs. A buffer layer between the multi-quantum well structure and the substrate, and a multiple quantum well structure and the buffer layer is formed of a material with each other having an etching selectivity, one of the claims 7 to 10 1 The epitaxial wafer according to Item. The epitaxial wafer according to claim 7 , wherein the substrate is any one of (GaAs, GaP, GaSb, InP, InAs, InSb, AlSb, and AlAs).

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