JP6137944B2 - Semiconductor device, test circuit and test method - Google Patents

Description

  The present invention relates to a semiconductor device, a test circuit, and a test method.

In a test for determining a defect of a semiconductor device, a defective operation (problem) is reproduced by setting the address movement to, for example, the worst case.
An example is a write operation from a CPU (Central Processing Unit) in a chip to a memory. During a write operation, a read address for reading a write command from the memory is specified before the write address is specified. If a change in value (change from “0” to “1” or “1” to “0”) is delayed in a specific address bit of the read address and the write address, data is transferred to an address that is not the specified write address. May be erroneously written.

  When reproducing such a defect, if the address bits of the read address and the write address have the same value (that is, the value does not change), erroneous writing due to an abnormality occurring in the address bit cannot be reproduced. For this reason, it is conceivable that the value of the address bit differs between the read address and the write address. That is, it is conceivable to make the movement of address bits that may cause a problem.

  However, since the read address is determined by the arrangement position of the instruction code on the memory, it cannot be arbitrarily changed, and it is difficult to make the address movement as the worst case as described above. It is conceivable that a test circuit outside the semiconductor device supplies a dedicated address signal to the semiconductor device for testing, but when performing a malfunction check with the semiconductor device mounted on the system board Not suitable.

  Note that the CPU and the test circuit are connected to the internal bus of the chip via the bus interface, and the test circuit does not perform the access control of the peripheral circuit or memory to be tested by executing the program. There is technology. In this technique, an operation for a peripheral circuit or the like is performed by a test circuit in accordance with trigger conditions such as a peripheral circuit state and an internal bus state set in an internal table, an operation, an address, and data.

JP 11-328147 A JP 2001-51863 A

  However, the above technique does not arbitrarily set the movement of the address, and it is still difficult to reproduce a problem caused by the movement of a specific address.

  According to one aspect of the invention, a processor that is connected to a bus and executes a test program, a test target circuit that is connected to the bus, and a test circuit that is connected to the bus, the test circuit includes: A storage unit that holds a first address and a second address specified by the test program, and a request to use the bus to the processor, and the control of the bus by the processor is in a standby state. There is provided a semiconductor device including a test control unit that performs a test by sequentially supplying the first address and the second address held in a storage unit to the circuit under test via the bus.

  According to another aspect of the invention, a storage unit that holds a first address and a second address specified by a test program executed by a processor, a bus use request to the processor, and the processor A test control unit for performing a test by sequentially supplying the first address and the second address held in the storage unit to a test target circuit via the bus in a state where control of the bus is in a standby state. A test circuit is provided.

  According to another aspect of the invention, the first address and the second address specified by the test program executed by the processor are held in the storage unit, the bus is requested to the processor, and the processor A test method for performing a test by sequentially supplying the first address and the second address held in the storage unit to a test target circuit via the bus in a state where control of the bus is in a standby state. Is provided.

  According to the disclosed semiconductor device, test circuit, and test method, it becomes easy to reproduce a defect of the semiconductor device.

It is a figure which shows an example of the semiconductor device and test circuit of 1st Embodiment. It is a figure which shows an example of the semiconductor device of 2nd Embodiment. It is a figure which shows an example of the test circuit of 2nd Embodiment. It is a flowchart which shows the flow of an example of the testing method of the semiconductor device of this Embodiment (the 1). It is a flowchart which shows the flow of an example of the testing method of the semiconductor device of this Embodiment (the 2). It is a figure which shows an example of a test program. It is a timing chart which shows an example of the signal of each part at the time of transfer operation of the test program from a communication macro to RAM. It is a timing chart which shows an example of the signal of each part at the time of test program execution. It is a timing chart which shows an example of the signal of each part at the time of test circuit operation | movement. It is a figure which shows an example of abnormality generation in an address bus. It is a figure which shows an example of the signal of each part at the time of the result output process after completion | finish of test circuit operation | movement.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a semiconductor device and a test circuit according to the first embodiment.

  The semiconductor device 1 includes a processor 2, a test program input unit 3, a RAM (Random Access Memory) 4, a ROM (Read Only Memory) 5, a test target circuit 6, and a test circuit 7, which are connected to a bus 8. Yes.

The processor 2 controls each unit of the semiconductor device 1 based on a program stored in the ROM 5 and a test program input from the test program input unit 3.
The test program input unit 3 inputs a test program for the test target circuit 6. The test program input unit 3 is a communication macro, for example. Note that the test program may be stored in the ROM 5.

The RAM 4 temporarily stores at least part of a program to be executed by the processor 2. For example, the test program is developed on the RAM 4 and executed.
The ROM 5 stores programs executed by the processor 2 and various data.

  The test target circuit 6 is various peripheral circuits having a register for storing a set value or the like. For example, the test target circuit 6 is a timer or a communication interface. Note that the test program input unit 3, the RAM 4, and the ROM 5 connected to the bus 8 may be the test target circuit 6.

The test circuit 7 includes a storage unit 10, a test control unit 11, a bus output control circuit 12, and a bus input control circuit 13.
The storage unit 10 includes a dummy address storage register 10a, a survey address storage register 10b, and a data storage register 10c.

  The dummy address storage register 10a and the survey address storage register 10b hold two addresses specified by the test program. Hereinafter, the above two addresses will be referred to as a dummy address and a survey address. The investigation address is an address of the test target circuit 6 in which the data to be investigated is stored, and the dummy address is an address specified before the investigation address in order to cause a specific address to move during the test. These two addresses are described in the test program.

  The data storage register 10 c holds data read from the test target circuit 6 or data to be written to the test target circuit 6. Data to be written to the test target circuit 6 is described in a test program, for example.

  The test control unit 11 requests the processor 2 to use the bus 8. An instruction for causing the test control unit 11 to generate a use request for the bus 8 is described in the test program. When receiving the permission to use the bus 8 from the processor 2, the test control unit 11 supplies a dummy address and a check address to the bus 8 in order while waiting for the processor 2 to control the bus 8, and Perform the test.

The bus output control circuit 12 outputs a dummy address, a survey address, or write data to the bus 8 during a write test under the control of the test control unit 11.
The bus input control circuit 13 reads the data read from the test target circuit 6 through the bus 8 under the control of the test control unit 11 and supplies the data to the data storage register 10c.

Hereinafter, an example of the operation of the semiconductor device according to the first embodiment will be described.
Under the control of the processor 2, the test program input unit 3 inputs a test program. The test program is expanded in the RAM 4. By the test program developed in the RAM 4, the dummy address and the survey address are held in the dummy address storage register 10a and the survey address storage register 10b. When a write test is performed, write data described in the test program is stored in the data storage register 10c.

  In addition, the test control unit 11 requests the processor 2 to use the bus 8 according to the test program. When the processor 2 receives a request for using the bus 8 from the test control unit 11, the processor 2 issues a permission to use the bus 8. As a result, the processor 2 enters a standby state, and the bus 8 is controlled by the test circuit 7.

  When the test control unit 11 receives permission to use the bus 8 from the processor 2, the test control unit 11 causes the bus output control circuit 12 to output a dummy address and a check address to the bus 8 while the processor 2 is in a standby state.

  In the example of FIG. 1, the state of an example of an address bit (bit x) is shown among the output address from the test circuit 7 and the address bit group of the output address that transmits the bus 8 (address bus). .

  At timing t1, a dummy address is output as the output address of the test circuit 7. At the timing t2, a survey address is output as the output address of the test circuit 7. Here, the common bit x of the dummy address and the check address changes from “1” (H (High) level) to “0” (L (Low) level) in the normal state. However, for example, when a delay problem occurs in an address line that transmits bit x, the change from “1” to “0” is delayed, resulting in an abnormal waveform as shown in FIG. . In such a case, the test target circuit 6 determines that bit x is “1” instead of “0”, and for example, erroneous reading from an address different from the intended address occurs.

  After outputting the survey address, the test control unit 11 stores the data read from the test target circuit 6 based on the survey address in the data storage register 10 c via the bus input control circuit 13.

  Thereafter, the test control unit 11 cancels the use request for the bus 8. As a result, the bus 8 is controlled by the processor 2 and, for example, data is read from the data storage register 10c. Thereby, it is determined whether the intended data has been read. If bit x changes as shown in the waveform at the time of abnormality as shown in FIG. 1, the correct address is not specified, and the read data is different from the intended one, so that a malfunction has occurred. I can grasp it. The data stored in the data storage register 10c is output to the outside via a communication macro (not shown) under the control of the processor 2 so that the presence or absence of a malfunction can be determined by an external device. Good.

  When erroneous reading due to an abnormal address at the time of writing data to the test target circuit 6 is detected, data is transferred to the register of the test target circuit 6 specified by the investigation address under the control of the test control unit 11. Data stored in the storage register 10c is written. However, when an address abnormality as shown in FIG. 1 occurs, the address is erroneously written to an unintended address. After the test control unit 11 cancels the use request for the bus 8, the processor 2 reads the data at the check address from the data storage register 10c and determines whether the intended value is written.

  As described above, in the present embodiment, the dummy address and the survey address specified by the test program are held in the storage unit 10, and the test circuit 7 waits for the control of the bus 8 by the processor 2, and the test circuit 7 Are sequentially output to the bus 8 to execute the test. The dummy address and survey address values described in the test program can be changed arbitrarily. Therefore, the address movement can be arbitrarily set during the test for the test target circuit 6, and the defect can be easily reproduced.

  In addition, since it is not necessary to consider the address arrangement of the instruction code in order to make the address movement the worst case, it is necessary to create a complicated test program for reproducing the worst case as in the case where the processor 2 performs the test. It gets better.

In addition, since the address can be arbitrarily set by a test program, an address / data input / output dedicated terminal, an external address generator, and the like are not required.
In addition, by executing the test program, the test control unit 11 of the test circuit 7 issues a request for using the bus 8 to make the processor 2 stand by so that the test circuit 7 controls the bus 8. Become. As a result, it is not necessary to provide a circuit for triggering a test start in a peripheral circuit in advance, or to provide a table describing trigger conditions and the like.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor device according to the second embodiment.
The semiconductor device 20 includes a processor 21, a decoder 22, ROMs 23 and 26, a communication macro 24, a peripheral circuit 25, a RAM 27, a DMAC (Direct Memory Access Controller) 28, and a test circuit 29, which are connected to an internal bus 30. Has been. The semiconductor device 20 has an OR circuit 31.

  The processor 21 controls each unit of the semiconductor device 20 based on a program stored in the ROMs 23 and 26 or, for example, a test program input from the communication macro 24. The processor 21 may be a multiprocessor. The processor 21 is, for example, a CPU, a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The processor 21 may be a combination of two or more elements among CPU, MPU, DSP, ASIC, and PLD.

The decoder 22 switches between selecting the ROM 23 or the ROM 26 in accordance with an operation mode selection signal input from the outside.
The ROM 23 stores, for example, programs executed by the processor 21 during testing and various data.

The communication macro 24 inputs an external test program and outputs test results under the control of the processor 21 or the DMAC 28.
The peripheral circuit 25 is a timer or an input / output interface.

The ROM 26 stores programs used by the user and various data.
The RAM 27 temporarily stores at least part of a program to be executed by the processor 21.

  The DMAC 28 controls data transmission / reception between the communication macro 24 and the peripheral circuit 25 and the RAM 27. Further, the DMAC 28 issues a use request for the internal bus 30 to the processor 21 via the OR circuit 31 and receives a use permission for the internal bus 30 from the processor 21.

  The test circuit 29 supplies the address specified by the test program to the test target circuit and performs the test. The test circuit 29 issues a use request for the internal bus 30 to the processor 21 via the OR circuit 31 and receives a use permission for the internal bus 30 from the processor 21.

The OR circuit 31 notifies the processor 21 when a use request for the internal bus 30 is issued from at least one of the DMAC 28 or the test circuit 29.
The internal bus 30 includes a data bus and an address bus.

FIG. 3 is a diagram illustrating an example of a test circuit according to the second embodiment.
The test circuit 29 includes a dummy address storage register 40, a survey address storage register 41, a data storage register 42, an internal bus use request signal generation unit 43, a sequence circuit 44, a bus output control circuit 45, and a bus input control circuit 46.

The dummy address storage register 40 holds a dummy address, which is an address specified before the survey address, in order to make a specific address move during the test.
The investigation address storage register 41 holds an address designated for investigation in the test target circuit 6. These addresses are addresses set based on the test program.

The data storage register 42 holds data read from a circuit to be tested at the time of testing or data to be written to a circuit to be tested.
The internal bus use request signal generation unit 43 generates an internal bus use request signal that requests the processor 21 to use the internal bus 30. Hereinafter, it is assumed that the test circuit 29 requests use of the internal bus 30 when the internal bus use request signal is “1”.

  The sequence circuit 44 is connected to the processor 21. When the sequence circuit 44 receives a signal to permit the use of the internal bus 30 from the processor 21, the sequence circuit 44 controls the bus output control circuit 45 to send a dummy address and a check address to the internal bus 30. Supply in order. The sequence circuit 44 controls the bus input control circuit 46 during the reading test, and holds the data read from the circuit to be tested by the investigation address in the data storage register 42 via the internal bus 30. Let At the time of the write test, the sequence circuit 44 controls the bus output control circuit 45 to write the data held in the data storage register 42 to the circuit to be tested via the internal bus 30. . When the sequence circuit 44 finishes writing data to the data storage register 42 or reading data from the data storage register 42, the sequence circuit 44 controls the internal bus use request signal generation unit 43 to set the internal bus use request signal to “0”. ”

The bus output control circuit 45 outputs a dummy address, a check address, or write data to the internal bus 30 under the control of the sequence circuit 44.
The bus input control circuit 46 supplies the data read from the circuit under test to the data storage register 42 via the internal bus 30 under the control of the sequence circuit 44.

Hereinafter, an example of a test method for the semiconductor device 20 according to the present embodiment will be described by taking a read test as an example.
(Example of test method for semiconductor device 20)
FIG. 4 and FIG. 5 are flowcharts showing a flow of an example of a test method of the semiconductor device of the present embodiment.

  First, the decoder 22 receives an operation mode selection signal for selecting a program to be executed during a test stored in the ROM 23, and selects an operation mode for transferring the test program to the RAM 27 (step S1). . Thereby, the processor 21 starts the program on the ROM 23 and starts the transfer operation to the RAM 27 by the communication macro 24 (step S2).

  The communication macro 24 starts reading the test program from the outside (step S3), and the read test program is expanded on the RAM 27 (step S4). Then, the processor 21 shifts the processing from the processing of the program being executed to the above test program.

  Thereafter, under the control of the processor 21, initial setting based on the test program (step S5) and setting for the test circuit 29 are performed (step S6). As a result, the test circuit 29 is activated. In the process of step S5, for example, a baud rate and a bit length are set in the communication macro 24. In the process of step S6, the dummy address storage register 40 and the dummy address and the survey address are written into the survey address storage register 41.

Thereafter, the internal bus use request signal generation unit 43 of the test circuit 29 sets the internal bus use request signal to “1” and issues an internal bus use request (step S7).
In response to the internal bus use request, the processor 21 issues an internal bus use permission and releases the internal bus 30 to enter a standby state (step S8).

  In the test circuit 29, when the sequence circuit 44 receives the internal bus use permission (step S9), the sequence circuit 44 controls the bus output control circuit 45 to output the dummy address held in the dummy address storage register 40 to the internal bus 30. (Step S10).

  Thereafter, the sequence circuit 44 controls the bus output control circuit 45 to output the investigation address held in the investigation address storage register 41 to the internal bus 30 (step S11).

  Thereafter, the sequence circuit 44 controls the bus input control circuit 46 to store in the data storage register 42 the read data from the circuit under test read by the investigation address (step S12).

  After the processing in step S12, the sequence circuit 44 controls the internal bus use request signal generation unit 43 to set the internal bus use request signal to “0” and cancel the internal bus use request (step S13). Thereby, the operation using the internal bus 30 by the processor 21 is resumed (step S14).

  The processor 21 reads the data stored in the data storage register 42, compares it with the ideal value, and performs output processing for outputting the comparison result from the communication macro 24 (step S15).

  On the basis of the data output from the communication macro 24, an external device performs pass / fail judgment processing (step S16). The processor 21 may perform the pass / fail determination process, or the test circuit 29 holds the ideal value, and compares the ideal value with the data stored in the data storage register 42, A comparison result or a pass / fail judgment result based on the comparison result may be output.

Next, an example of a test program will be described.
(Example of test program)
FIG. 6 is a diagram illustrating an example of a test program.

  In the test program, register groups are defined first. “TEST_DA” indicates a dummy address storage register 40, “TEST_RA” indicates a survey address storage register 41, and “TEST_RD” indicates a data storage register 42. “TSET_ST” indicates an internal bus request bit storage register (not shown) in the internal bus use request signal generation unit 43. “CANREG” and “CANSTAT” indicate a communication macro transmission data register and a communication macro status register (not shown) in the communication macro 24.

  Next, each process during the test is described. First, as a code for initializing the communication macro 24, the baud rate, bit length, transmission permission setting, etc. of the communication macro 24 are described. With these codes, the process of step S5 of FIG. 4 described above is performed.

  Furthermore, an example of a code for setting the test circuit 29 is described. “MOV TEST_DA, # 7FFFEh” is a code for transferring the dummy address “7FFFEh” to the dummy address storage register 40. “MOV TEST_RA, # C0000h” is a code for transferring the survey address “C0000h” to the survey address storage register 41. “MOV TEST_ST, #FFh” is a code for transferring the internal bus use request bit “FFh” to the internal bus use request bit storage register.

With these codes, the processing in steps S6 and S7 in FIG. 4 described above is performed.
Next, a dummy code “NOP” for waiting for switching is described which causes the processor 21 to wait until the control by the processor 21 is switched to control by the sequence circuit 44 of the test circuit 29. In the example of FIG. 6, the control shifts to the control by the sequence circuit 44 at the timing of waiting for two cycles. The code “NOP” is further described, and makes the processor 21 stand by for another cycle.

  “MOV A, TEST_ST” in “WAITLOOP” described below is a code for transferring the value of the internal bus request bit storage register to an accumulator (register) (not shown) of the processor 21. “CMP A, 00h” is a code for determining whether or not the value of the accumulator is “00h”. Thereby, it is confirmed whether or not the control of the internal bus 30 by the test circuit 29 is completed. The value of the internal bus request bit storage register becomes “00h” after the data read from the circuit under test is stored in the data storage register 42 under the control of the sequence circuit 44. As a result, the internal bus use request signal becomes “0”, and the control of the internal bus 30 by the test circuit 29 is completed.

  “BNE WAITLOOP” is a code for repeating the processing in “WAITLOOP” when the value of the accumulator is not “00h”. That is, if the control of the internal bus 30 by the test circuit 29 is not completed, the processing of the processor 21 returns to the processing from the “WAITLOOP” line.

The following code is executed when the control of the internal bus 30 by the test circuit 29 is completed.
“MOV A, TEST_RD” is a code for fetching the read data from the circuit under test written in the investigation address storage register 41 into the accumulator of the processor 21.

“MOV CANREG, A” is a code for writing the read data taken into the accumulator into the communication macro transmission register.
“BBS, CANSTAT: 0, WAITLOOP1” in “WAITLOOP1” described next is until the value of the communication macro status register in the communication macro 24 becomes “0” (value indicating the end of transmission). This is a code for waiting for the operation of the processor 21.

  “// PROG END” indicates the end of the test program. In the example of the test program of FIG. 6, data read from the circuit to be tested is output as it is using the communication macro 24, but as described above, the comparison result between the ideal value and the read data is obtained. After writing to the communication macro transmission register, it may be output to the outside.

Next, taking a reading test as an example, an example of a signal of each part during a test operation of the semiconductor device 20 of the present embodiment will be described.
(An example of the signal of each part at the time of test operation of the semiconductor device 20)
FIG. 7 is a timing chart illustrating an example of signals of the respective units during the transfer operation of the test program from the communication macro to the RAM.

FIG. 7 shows an example of the internal bus 30 (address bus), the input waveform of the communication macro 24, the internal bus 30 (data bus), and the data input waveform of the RAM 27 from the top.
Between timings t <b> 10 to t <b> 11, the test program is read by the communication macro 24 and transmitted to the internal bus 30 (data bus) and input to the processor 21. The test program is written from the processor 21 to the designated address in the RAM 27 between timings t12 and t13.

From timing t14, the test program written in the RAM 27 is executed.
FIG. 8 is a timing chart showing an example of signals of the respective units when the test program is executed.

  In FIG. 8, the internal bus 30 (address bus), the data output waveform of the RAM 27, the internal bus 30 (data bus), the input waveform of the dummy address storage register 40, the input waveform of the survey address storage register 41, and the internal bus use request from the top. An example of the input waveform of the bit storage register is shown.

When the test program is executed, a write operation to each register of the test circuit 29 is performed from timing t15.
At timing t16, the dummy address described in the test program is written in the dummy address storage register 40 as described above.

At timing t17, the survey address described in the test program is written in the survey address storage register 41.
At timing t18, the value of the internal bus use request bit described in the test program (“FFh” in the case of the test program example shown in FIG. 6) is written in the internal bus use request bit storage register.

  In the above example, the dummy address and the check address are written in this order, but the order is not limited to this. The order of writing may be changed according to the code of the investigation program.

FIG. 9 is a timing chart showing an example of signals of the respective units during the test circuit operation.
In FIG. 9, the state of the internal bus 30 (address bus) from the top, the waveform of the address bit 14 when normal and abnormal, the input waveform of the internal bus use request bit storage register, the internal bus use request signal, and the internal An example of a bus use permission signal is shown. Further, an example of the waveform of the internal bus 30 (data bus) at normal time and abnormal time, the output waveform of the dummy address storage register 40 and the investigation address storage register 41, and the input waveform of the data storage register 42 are shown.

  As described above, when the value of the internal bus use request bit is written to the internal bus use request bit storage register at timing t18, the internal bus use request signal generation unit 43 outputs the internal bus use request signal at timing t19. Change from “0” to “1”.

  In response to the change in the internal bus use request signal, the processor 21 changes the internal bus use permission signal from “0” to “1”. As a result, the internal bus 30 is controlled by the test circuit 29.

  Between timings t21 to t22, the sequence circuit 44 of the test circuit 29 controls the bus output control circuit 45 to output the dummy address and the investigation address to the internal bus 30 in order. Further, the sequence circuit 44 controls the bus input control circuit 46 to store the data read from the circuit under test in the data storage register 42.

  In the example of FIG. 9, a case where the dummy address and the survey address are the values described in the test program shown in FIG. 6, “7FFFEh” and “C0000h” is shown. When the address is moved from “7FFFEh” to “C0000h”, the address bit 14 changes from “1” to “0” in the normal state. However, at the time of abnormality, for example, the change to “0” is delayed as shown in FIG. An example of the reason why such an abnormality occurs is shown below.

FIG. 10 is a diagram illustrating an example of occurrence of an abnormality in the address bus.
The case where the peripheral circuit 25 is a circuit to be tested is shown. For example, the peripheral circuit 25 includes registers 50 and 51, AND circuits 52 and 53, and an inverter circuit 54.

  In the example of FIG. 10, the address lines 30 a, 30 b, and 30 c of the internal bus 30 (address bus) are connected to the input terminal of the AND circuit 52, and the output terminal of the AND circuit 52 is connected to the register 50. The address lines 30 a and 30 b are connected to the input terminal of the AND circuit 53, and the address line 30 c is connected to the input terminal of the AND circuit 53 via the inverter circuit 54. The output terminal of the AND circuit 53 is connected to the register 51.

  The register 50 or the register 51 is selected according to the address supplied to the peripheral circuit 25 by the internal bus 30 (address bus). For example, if each address bit transmitted through the address lines 30a, 30b, and 30c is “1”, the output signal of the AND circuit 52 is “1” and the output signal of the AND circuit 53 is “0”. At this time, the register 50 is selected and reading or writing is performed. Here, when the address bit transmitted through the address line 30c becomes “0”, the output signal of the AND circuit 52 becomes “0”, the output signal of the AND circuit 53 becomes “1”, and the register 51 is selected. Become.

  However, for example, as shown in FIG. 10, when the foreign object 60 adheres to the address line 30c and the change of the address bit transmitted through the address line 30c is delayed as shown in FIG. Think. In this case, changes in the output signals of the AND circuits 52 and 53 are also delayed, and there is a possibility that the register 50 is selected where the register 51 should be selected at the time of reading or writing. As a result, erroneous reading or erroneous writing occurs.

  As shown at timings t21 to t22 in FIG. 9, the dummy address “7FFFEh” and the investigation address “C0000h” are supplied to the address bus, whereby the data of the circuit under test is read out to the data bus. However, the data read to the data bus varies depending on whether the waveform of the address bit 14 is normal or abnormal as shown in FIG. Therefore, the data stored in the data storage register 42 also changes.

  When the sequence circuit 44 sets the internal bus use request signal to “0” at timing t22, the processor 21 sets the internal bus use permission signal to “0” at timing t23. As a result, the internal bus 30 is controlled by the processor 21.

FIG. 11 is a diagram illustrating an example of a signal of each unit during a result output process after the test circuit operation is completed.
In FIG. 11, the state of the internal bus 30 (address bus) and an example of the internal bus use request signal and the internal bus use permission signal are shown from the top. Further, an example of the waveform of the internal bus 30 (data bus), the output waveform of the survey address storage register 41, the input / output waveform of the data storage register 42, and the output waveform of the communication macro 24 are shown.

  In the example of FIG. 11, the processing of the processor 21 is restarted from the timing t24. The processor 21 reads the data stored in the data storage register 42 between timings t <b> 25 to t <b> 26, makes a pass / fail judgment, and prepares to send a judgment result using the communication macro 24. Here, as described above, the determination result is written into the register of the communication macro 24. Thereby, the communication macro 24 transmits a determination result from the timing t26.

  The semiconductor device 20 and the test circuit 29 of the second embodiment have the same effects as the semiconductor device 1 and the test circuit 7 of the first embodiment. That is, when testing a circuit to be tested, it is possible to arbitrarily set the movement of an address, and it becomes easy to reproduce a defect. For example, as shown in the abnormal waveform of the address bit 14 in FIG. 9, a state in which erroneous reading or erroneous writing is performed can be set in a pinpoint manner.

  In addition, since it is not necessary to consider the address arrangement of the instruction code in order to make the address movement the worst case, it is necessary to create a complicated test program for reproducing the worst case as in the case where the processor 21 performs the test. It gets better.

In addition, since the address can be arbitrarily set by a test program, an address / data input / output dedicated terminal, an external address generator, and the like are not required.
Further, when the test program is executed, the internal bus use request signal generation unit 43 of the test circuit 29 issues a use request for the internal bus 30, causes the processor 21 to wait, and the test circuit 29 sets the internal bus 30. Control is performed. As a result, it is not necessary to provide a circuit for triggering a test start in a peripheral circuit in advance, or to provide a table describing trigger conditions and the like. Further, since the OR circuit 31 transmits the use request of the internal bus 30 output from the DMAC 28 or the test circuit 29 to the processor 21, the control subject of the internal bus 30 can be controlled by the processor 21, the DMAC 28, the test circuit with a simple configuration. 29.

As described above, one aspect of the semiconductor device, the test circuit, and the test method of the present invention has been described based on the embodiments. However, these are merely examples, and the present invention is not limited to the above description.
For example, the test program is not acquired from the outside via a communication macro and expanded in the RAM, but is stored in advance in the ROM of the semiconductor device so that self-diagnosis is performed when the semiconductor device is started. Good.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Processor 3 Test program input part 4 RAM
5 ROM
6 Test target circuit 7 Test circuit 8 Bus 10 Storage unit 10a Dummy address storage register 10b Investigation address storage register 10c Data storage register 11 Test control unit 12 Bus output control circuit 13 Bus input control circuit

Claims (6)

A processor connected to the bus and executing a test program;
A circuit under test connected to the bus;
A test circuit connected to the bus,
The test circuit includes:
A storage unit for holding a first address and a second address specified by the test program;
A request to use the bus is made to the processor, and the first address and the second address held in the storage unit are sent via the bus in a state where the bus is controlled by the processor. A test control unit for sequentially supplying the test target circuit and performing a test;
I have a,
Wherein a Rukoto inverted signal of the signal of the x bits of the first address is not set as the signal of the x bits of the second address. The test circuit includes another storage unit that holds data read from the test target circuit when the second address is designated,
After holding the data in the other storage unit, the test control unit cancels the bus use request, and the processor reads the data held in the other storage unit to determine whether the data is good or bad. The semiconductor device according to claim 1.   3. The test program according to claim 1 or 2, wherein the first address, the second address, and an instruction for causing the test control unit to generate a use request for the bus are described. The semiconductor device described. A DMA controller connected to the bus;
And a logic circuit connected between the DMA controller and the test circuit and notifying the processor of a bus use request issued from the DMA controller or the test circuit. The semiconductor device according to any one of claims 1 to 3. A storage unit for holding a first address and a second address specified by a test program executed by the processor;
A request to use the bus is made to the processor, and the first address and the second address held in the storage unit are tested via the bus in a state in which the bus is controlled by the processor. A test control unit that sequentially supplies the target circuit for testing, and
I have a,
Test circuit according to claim Rukoto inverted signal of the signal of the x bits of the first address is not set as the signal of the x bits of the second address. The storage unit holds the first address and the second address specified by the test program executed by the processor,
The test circuit requests the processor to use the bus and waits for the control of the bus by the processor, and the first address and the second address held in the storage unit are used as the bus. There line test is supplied in sequence to the test target circuit via,
An inversion signal of the x-th bit signal of the first address is set as the x-th bit signal of the second address .

Images