JP6140933B2 - Display device and control method thereof - Google Patents

Description

  The present invention relates to a display device, a control method thereof, and a computer program.

  When a document or graphic analog video signal created by a computer is displayed on a display device, it is important that the sampling clock and the effective video area of the video signal are matched between the computer and the display device. The display device has a signal format table that correlates attributes such as the frequency and polarity of the horizontal and vertical sync signals with the sampling clock and the effective video area. By reading the attributes of the sync signals output from the computer, The format can be determined. In a display device, a sampling clock required for digitizing an analog video signal from a computer is usually generated by multiplying a horizontal synchronizing signal.

  As for the frequency of this sampling clock, it is often possible to know an appropriate value from the information of the synchronization signal described above, but the appropriate value for the phase of the sampling clock differs for each computer. This is because there are different time differences between the horizontal synchronization signal and the video signal transmitted from the computer due to various factors. In addition, since there are a wide variety of signal formats output from a computer, it is extremely difficult to deal with them completely in the signal format table of the display device, and the proper value of the sampling frequency may not be known by the display device. Occur. Therefore, in order to digitize analog video signals satisfactorily, the display device must have a function for optimizing the sampling frequency and sampling phase described above, and a sampling clock automatic adjustment function that automatically realizes this has been developed. It was.

  For example, Patent Document 1 discloses the following technique as a sampling clock automatic adjustment function. In one frame of the input video signal, a process for obtaining an integrated value of the difference between the video signal values between one or two or more adjacent pixels is executed for each phase. Since the integrated value of the video signal value difference is large at a good sampling phase and small at an unsatisfactory sampling phase, the sampling frequency and the sampling phase are adjusted so that the integrated value of the acquired video signal value difference is maximized. .

  Patent Document 2 discloses the following technique as a sampling clock automatic adjustment function. Basically, it is the same as Patent Document 1, but differs in that the process of obtaining the integrated value integrates the square of the difference between the video signal values.

  For example, a case where an analog video signal as shown in FIG. 5A to 5C, the horizontal axis indicates the horizontal position of the image, and the vertical axis indicates the luminance value of the image [FIG. 5A is an analog value, FIG. 5B and FIG. 5 (c) is a digital value]. Sampling positions are a black arrow and a white arrow. FIG. 5B shows the result of sampling with a black arrow, and the rectangle in the figure is the result of sampling. Similarly, FIG. 5C shows the result of sampling with a white arrow, and the rectangle in the figure is the result of sampling. Comparing FIG. 5B and FIG. 5C, it can be seen that the result of sampling at the sampling position (sampling phase) indicated by the black arrow in FIG. This indicates that the sampling position (sampling phase) in FIG. 5B is good as disclosed in Patent Document 1 and Patent Document 2.

Japanese Patent Laid-Open No. 11-177847 Japanese Patent Laid-Open No. 2000-020008

  However, with the prior art disclosed in the above-mentioned patent documents, the sampling clock and sampling phase can be controlled well when the contrast of the video signal such as CAD and computer graphics is originally high, but sampling is good for natural images with low contrast. The clock and sampling phase may not be controlled. For example, when the analog video signal shown in FIG. 6A is sampled with a black arrow and a white arrow, a clear difference is obtained even if the difference between the adjacent pixels in FIG. 6B and FIG. 6C is compared. It is difficult to find.

  Therefore, the present invention enables good sampling processing even in sampling processing for converting an analog video signal with low contrast into a digital video signal.

The present invention for solving the above problems is a display device,
Generating means for generating a clock;
Conversion means for converting an input analog image signal into a digital image signal in accordance with the clock;
Display means for displaying an image corresponding to the digital image signal output from the conversion means;
Control means for controlling the generation means to set the phase of the clock, and
The control means includes
Based on whether there is a difference that exceeds a threshold between the maximum value and the minimum value of the difference between adjacent pixels in the digital image signal, each converted according to the clocks of a plurality of different phases ,
Wherein if there is a difference exceeding the threshold value between the maximum value and the minimum value of the difference between adjacent pixels, sets the phase of the clock based on a difference between the adjacent pixels,
When there is no difference exceeding the threshold value between the maximum value and the minimum value of the difference between the adjacent pixels, the digital images of a plurality of frames each converted according to the clocks having a plurality of different phases and setting a phase of the clock based on the difference between the signal of the frame.

  According to the present invention, it is possible to satisfactorily perform sampling processing even in sampling processing for converting an analog video signal with low contrast into a digital video signal.

3 is a diagram illustrating an example of a configuration of a display device corresponding to Embodiment 1. FIG. 5 is a flowchart illustrating an example of processing corresponding to the first embodiment. 6 is a diagram illustrating an example of a configuration of a display device corresponding to Embodiment 2. FIG. 10 is a flowchart illustrating an example of processing corresponding to the second embodiment. It is a figure for demonstrating an example at the time of sampling an analog video signal. It is a figure for demonstrating another example at the time of sampling an analog video signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an image display apparatus according to an embodiment of the present invention.

[Embodiment 1]
Hereinafter, a display device corresponding to Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 shows a configuration of a display device 100 corresponding to the first embodiment. In the present embodiment, the display device 100 will be described as a liquid crystal projector 100. The embodiment of the display device 100 is not limited to the liquid crystal projector, and may be a liquid crystal display. More generally, any device may be used as long as it is an image display device that converts an input analog signal into a digital signal for display.

  As shown in FIG. 1, the liquid crystal projector 100 includes an analog video signal input interface (IF) 101, a synchronization signal detection unit 102, an AD conversion unit 103, a sampling clock generation unit 104, a RAM 105, an inter-frame difference value calculation unit 106, image processing, and the like. A unit 107, a panel control driver 109, a display panel 108, a lamp control unit 111, a light source lamp 110, and a CPU 112.

  Next, the operation of the liquid crystal projector 100 will be described. The analog video signal input IF 101 is an interface (IF) for inputting an analog video signal to be displayed on the liquid crystal projector 100, and is, for example, a D-Sub 15 pin terminal. The synchronization signal detection unit 102 is a processing unit that detects synchronization signal information of a video signal input to the analog video signal input IF 101, and uses timing information (frequency information) of a horizontal synchronization signal (Hsync) and a vertical synchronization signal (Vsync). To detect. The synchronization signal detection unit 102 transmits the detected timing information to the CPU 112.

  The AD conversion unit 103 digitally converts the analog video signal to generate a digital video signal. The sampling clock generation unit 104 supplies a sampling clock to the AD conversion unit 103. The sampling clock generation unit 104 receives a notification of the total number of horizontal dots and the phase value of the analog video signal from the CPU 112, shifts the phase of the reference sampling clock according to the notified phase value, and supplies the clock signal to the AD conversion unit 103. The sampling clock can usually be generated by multiplying the horizontal synchronizing signal. Here, the multiplication number is the total number of horizontal dots. The RAM 105 holds the digital video signal output from the AD conversion unit 103. In addition, the inter-frame difference value calculation unit 106, which will be described later, also holds the digital video signal of the previous frame in order to calculate the difference between the digital video signal of the previous frame and the digital video signal of the current frame. The inter-frame difference value calculation unit 106 calculates the inter-frame difference between the digital video signal obtained by AD converting the analog video signal of the current frame by the AD conversion unit 103 and the digital video signal of the previous frame held in the RAM 105. Is a processing unit. Since the calculation method of the inter-frame difference is known, detailed description thereof is omitted here.

  The image processing unit 107 performs image processing such as scaling processing, contrast control, and keystone correction on the input digital video signal, and outputs the processed digital video signal to the panel control driver 109. These controls are performed according to control signals from the CPU 112. The display panel 108 is composed of image elements arranged two-dimensionally. In the present embodiment, the display panel 108 is configured as a liquid crystal panel. The panel control driver 109 controls the display panel 108 according to the digital video signal received from the image processing unit 107. The light source lamp 110 is a high-pressure mercury lamp, a xenon lamp, or the like, and projects light onto the display panel 108. The lamp control unit 111 controls the light source lamp 110.

  The CPU 112 has an internal ROM for storing drive firmware and a working memory. The CPU 112 controls the overall operation of the liquid crystal projector 100, including an image processing unit 107, a panel control driver 109, a lamp control unit 111, and AD conversion control for converting an analog video signal into a digital video signal. Details of the AD conversion will be described in a control flow described later.

  Next, the control flow of the CPU 112 in this embodiment will be described with reference to FIG. The control flow is realized by executing drive firmware inside the CPU 112. First, for AD conversion for converting an analog video signal into a digital video signal, the CPU 112 receives frequency information from the synchronization signal detection unit 102 in S201. In subsequent S202, the video signal format corresponding to the input analog video signal is detected by referring to the video signal table stored in the internal ROM based on the received frequency information. This video signal table is video signal format list data in which frequency information and the total number of horizontal dots are associated. In subsequent S <b> 203, the CPU 112 obtains the total number of horizontal dots from the detected video signal format, and sets the total number of horizontal dots in the sampling clock generation unit 104.

  In step S <b> 204, the CPU 112 sets an initial value 1 of the sampling clock phase value in the sampling clock generation unit 104. In the present embodiment, the settable phase value of the sampling clock is 1 to 32. The number of phase divisions is not limited to 32, and may be finer or coarser than 32.

  When the sampling clock generation unit 104 generates the sampling clock by shifting the phase of the reference signal based on the phase value set by the CPU 112, the AD conversion unit 103 converts the analog video signal into the digital video signal according to the sampling clock set in S205. AD conversion to In subsequent S <b> 206, the RAM 105 holds the digital video signal obtained from the AD conversion unit 103. In subsequent S 207, the inter-frame difference value calculation unit 106 calculates an inter-frame difference between the digital video signal of the previous frame held in the RAM 105 and the digital video signal of the current frame output from the AD conversion unit 103. In S208, the CPU 112 calculates that the inter-frame difference value calculated by the inter-frame difference value calculation unit 106 corresponds to the minimum value among a plurality of inter-frame difference values calculated from the initial phase value to the current phase value. Determine whether or not. The CPU 112 holds the inter-frame difference value calculated in the internal working memory, and updates the inter-frame difference value held by the calculated value when a smaller value is calculated. If it is determined that the inter-frame difference value is the minimum value (“YES” in S208), the CPU 112 stores the sampling clock phase value set in S204 in the RAM 105 in S209. The above processing from S204 to S209 is performed from the phase value 1 to 32 every time the screen is refreshed (each time one vertical synchronization signal is input).

  After the loop processing is completed, in step S210, the CPU 112 determines the sampling clock phase value temporarily saved in the RAM 105 as the optimum clock phase value, and sets the sampling clock generation unit 104 again. The sampling clock generation unit 104 supplies the sampling clock to the AD conversion unit 103 again according to the set optimum clock phase value. The AD conversion unit 103 converts the input analog video signal into a digital video signal using a sampling clock according to the optimum clock phase value, and outputs the digital video signal to the image processing unit 107. The digital video signal is also output to the RAM 105, and is held for the inter-frame difference value calculation unit 106 to calculate the inter-frame difference of the next frame.

  In the above embodiment, when calculating the inter-frame difference value, the inter-frame difference value of each pixel is summed over the entire frame, or the inter-frame difference of each pixel is summed only within a predetermined area. The result can be an inter-frame difference value. The predetermined area is an arbitrary area in the frame, and can be an area of a predetermined size including the center of the frame, for example. Furthermore, although the case where the inter-frame difference value is calculated between two frames has been described in the present embodiment, the inter-frame difference value for the number of frames of three or more may be calculated. For example, when a comparison is made with three frames, the two frames to be compared with the current frame can be two frames immediately before the current frame. In this case, for example, if the current frame is frame 0, and the two frames immediately before the current frame are changed from time-sequential to frame B and frame A, respectively, the total area of difference values of frame B and frame A, and frame A And the result of summing the area sum of the difference values of frame 0 in terms of time as an evaluation value. A minimum value is obtained by allocating the evaluation value from 1 to 32 in phase.

  Furthermore, in this embodiment, the sampling clock phase value at which the inter-frame difference value is minimized is set as a favorable phase value, but the phase value that is shifted by a half cycle from the phase value at which the inter-frame difference value is maximized is determined to be favorable. The sampling clock phase value may be used.

  As described above, in the present embodiment, the blur amount of the digital video signal after sampling the analog video signal is calculated as the inter-frame difference value, and this value is used for setting the optimum phase value of the sampling clock. This makes it possible to perform AD conversion satisfactorily even in the case of video data in which the contrast of adjacent pixels is low compared to video signals such as CAD and computer graphics such as natural images.

[Embodiment 2]
Hereinafter, with reference to FIG. 3 and FIG. 4, a display device corresponding to Embodiment 2 of the present invention will be described. A display device 300 shown in FIG. 3 is obtained by adding a difference value calculation unit 113 between adjacent pixels to the configuration of the liquid crystal projector 100 as the display device shown in the first embodiment. Therefore, description of components other than the adjacent pixel difference value calculation unit 113 is omitted here. The adjacent pixel difference value calculation unit 113 is a processing unit that calculates a difference between two adjacent pixel values in the same frame and obtains an absolute value thereof. The CPU 112 uses the result of summing the adjacent pixel difference values calculated for the pixels included in the predetermined area of the frame as the evaluation value of the adjacent pixel difference value. The size of the predetermined area may be, for example, the entire frame or an arbitrary area of the frame (for example, an area having a predetermined size including the center).

  In the present embodiment, the display device 300 will be described as a liquid crystal projector. However, the display device may be a liquid crystal display, and more generally any device as long as it is an image display device that converts an input analog signal into a digital signal for display.

  Next, the control flow of the CPU 112 in this embodiment will be described with reference to FIG. The processing from S401 to S405 is the same as S201 to S205 in FIG. After S405, the process branches into two. On the other hand, in S406, the adjacent pixel difference value calculation unit 113 calculates the difference value between adjacent pixels for the pixels included in the predetermined region of the digital video signal output from the AD conversion unit 103, and calculates the difference result for the predetermined region. Add up. Here, a case where calculation is performed for the entire frame is considered. In subsequent S 407, the set sampling phase value and the sum of the difference results are saved in the RAM 105.

  As the other processing branched after S405, the processing from S408 to S411 is performed. Since the processing here is the same as that from S206 to S209 in FIG. It should be noted that the processing from S406 and S407 and the processing from S408 to S411 is a sequence that is executed at the same time, and is executed every time the screen is refreshed (every vertical synchronization signal is input) from phase value 1 to 32. Is called.

  After the above loop processing is completed, in step S412, the CPU 112 verifies the validity of the adjacent pixel difference result calculated in step S407. Specifically, the CPU 112 determines whether there is a difference exceeding a predetermined threshold between the maximum value and the minimum value in the adjacent pixel difference result (entire frame) when the phase is changed from 1 to 32. To do. If there is a difference exceeding the predetermined threshold (“YES” in S412), the CPU 112 sets the sampling phase value that has taken the maximum value as the optimum phase value in S413. On the contrary, if there is no difference exceeding the predetermined threshold value between the maximum value and the minimum value (“No” in S412), the CPU 112 in S414 has the minimum inter-frame difference value saved in S411. The sampled phase value is set as the optimum phase value. Next, in S <b> 415, the CPU 112 sets the optimum sampling phase value set in S <b> 413 or S <b> 414 in the sampling clock generation unit 104.

  Thereafter, the sampling clock generation unit 104 supplies the sampling clock to the AD conversion unit 103 again according to the set optimum clock phase value. The AD conversion unit 103 converts the input analog video signal into a digital video signal using a sampling clock according to the optimum clock phase value, and outputs the digital video signal to the image processing unit 107. In addition, the digital video signal is also output to the RAM 105 and held for the inter-frame difference value calculation unit 106 to calculate the inter-frame difference value of the next frame.

  In the present embodiment, the maximum value and the minimum value of the adjacent pixel difference values are used in S412, but the validity verification method is not limited to this. For example, the phase of the adjacent pixel difference value variance when the phase is changed from 1 to 32 is obtained, and when the variance exceeds a predetermined variance threshold, the result of the adjacent pixel difference value is valid and the adjacent difference result is maximized. The value may be determined as the optimum phase value. In this case, when the variance is equal to or less than the variance threshold, the phase value that minimizes the interframe difference result may be determined as the optimum phase value.

  As described above, in the present embodiment, the optimum phase value of the sampling clock can be set in consideration of the difference value between adjacent pixels in the frame in addition to the difference value between frames. This makes it possible to perform AD conversion even better even in the case of video data in which the contrast of adjacent pixels is low compared to video signals such as CAD and computer graphics such as natural images.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (5)

Generating means for generating a clock;
Conversion means for converting an input analog image signal into a digital image signal in accordance with the clock;
Display means for displaying an image corresponding to the digital image signal output from the conversion means;
Control means for controlling the generation means to set the phase of the clock, and
The control means includes
Based on whether there is a difference that exceeds a threshold between the maximum value and the minimum value of the difference between adjacent pixels in the digital image signal, each converted according to the clocks of a plurality of different phases ,
Wherein if there is a difference exceeding the threshold value between the maximum value and the minimum value of the difference between adjacent pixels, sets the phase of the clock based on a difference between the adjacent pixels,
When there is no difference exceeding the threshold value between the maximum value and the minimum value of the difference between the adjacent pixels, the digital images of a plurality of frames each converted according to the clocks having a plurality of different phases display apparatus characterized by setting the phase of the clock based on the difference between the signals of the frames. Generating means for generating a clock;
Conversion means for converting an input analog image signal into a digital image signal in accordance with the clock;
Display means for displaying an image corresponding to the digital image signal output from the conversion means;
Control means for controlling the generating means to set the phase of the clock;
With
The control means includes
Based on whether or not the variance of the difference between adjacent pixels in the digital image signal each converted according to the clock of a plurality of different phases is greater than a threshold value,
Wherein when the variance of the difference between adjacent pixels is larger than the threshold value, sets the phase of the clock based on a difference between the adjacent pixels,
When the variance of the difference between the adjacent pixels is equal to or less than the threshold value, based on the difference between the frames of the digital image signal of a plurality of frames, each converted according to the clock of a plurality of different phases A display device that sets a phase of the clock . Wherein, when setting the phase of the clock based on a difference between the frames, among the plurality of different phases, to set the phase difference between the frames is minimized as the phase of the clock the display device according to claim 1 or 2, characterized. It said generating means, display apparatus according to claim 1 or 2, characterized in that for generating a clock synchronized with the input analog image signal. A display device control method comprising:
A generating step of generating a clock by the generating means of the display device;
A conversion step in which the conversion means of the display device converts the input analog image signal into a digital image signal in accordance with the clock; and
A display step in which a display unit of the display device displays an image corresponding to the digital image signal converted in the conversion step;
The control means of the display device includes a control step of setting the phase of the clock by controlling the generation means,
In the control step,
Based on whether there is a difference that exceeds a threshold between the maximum value and the minimum value of the difference between adjacent pixels in the digital image signal, each converted according to the clocks of a plurality of different phases ,
Wherein if there is a difference exceeding the threshold value between the maximum value and the minimum value of the difference between adjacent pixels, and set the phase of the clock based on a difference between the adjacent pixels,
The digital image signals of a plurality of frames, each converted according to the clocks having a plurality of different phases, when there is no difference exceeding the threshold value between the maximum value and the minimum value of the difference between the adjacent pixels control method of a display device and sets the phase of the clock based on the difference between the frames.

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