JP6143577B2 - Semiconductor integrated circuit and operation method of semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a method for operating the semiconductor integrated circuit.

  A semiconductor integrated circuit including a dynamic reconfiguration circuit that executes data processing and the like can execute a plurality of types of data processing by switching the function of the arithmetic unit mounted in the arithmetic unit and the connection between the arithmetic units. For example, this type of semiconductor integrated circuit ranks and holds states that may be changed by execution of branch processing for each state of data processing to be executed, and stores the ranking information held in the actual state. It is updated according to the transition (see, for example, Patent Document 1). Alternatively, this type of semiconductor integrated circuit holds information indicating a branch destination at the time of branch processing for each state of data processing to be executed, and reconfigures the circuit according to the held information (for example, see Patent Document 2). ).

International Publication No. 2009/096247 JP 2006-65788 A

  However, when one of the three or more branch processes is selected according to the condition determination and the arithmetic unit is reconfigured, the condition determination is executed for each branch process. Therefore, as the number of branch processes increases, the time taken for the condition determination Becomes longer.

  An object of the semiconductor integrated circuit and the semiconductor integrated circuit operating method disclosed herein is to start processing executed by an arithmetic unit according to a result of a condition determination earlier than before, and to improve the performance of the semiconductor integrated circuit. .

  According to one aspect, the semiconductor integrated circuit includes an arithmetic unit including a plurality of reconfigurable arithmetic units, and a circuit of the arithmetic unit according to a plurality of flag signals respectively indicating a result of a logical operation by the plurality of arithmetic units. A control unit that selects any one of a plurality of configuration data indicating the configuration and outputs the selected configuration data to a calculation unit;

  According to another aspect, an operation method of a semiconductor integrated circuit including an arithmetic unit including a plurality of reconfigurable arithmetic units is calculated according to a plurality of flag signals respectively indicating a result of a logical operation by the plurality of arithmetic units. One of a plurality of configuration data indicating the circuit configuration of the unit is selected, and the selected configuration data is output to the arithmetic unit.

  According to the semiconductor integrated circuit and the semiconductor integrated circuit operating method disclosed in the present disclosure, the processing executed by the arithmetic unit according to the condition determination result can be started earlier than before, and the performance of the semiconductor integrated circuit can be improved. it can.

It is a figure which shows one Embodiment of a semiconductor integrated circuit. FIG. 2 is a diagram illustrating an example of the operation of the semiconductor integrated circuit illustrated in FIG. 1. It is a figure which shows another embodiment of a semiconductor integrated circuit. It is a figure which shows the example of the arithmetic unit array shown in FIG. It is a figure which shows the example of the flag calculator shown in FIG. It is a figure which shows the example of the flag calculator shown in FIG. It is a figure which shows the example of the configuration memory shown in FIG. It is a figure which shows the example of the process performed by the arithmetic unit array shown in FIG. It is a figure which shows the example of the circuit structure of the arithmetic unit array which performs context CTXJ shown in FIG. FIG. 10 is a diagram showing the relationship between data values, flag signals, and data processing to be executed in the circuit configuration shown in FIG. 9. It is a figure which shows the example of operation | movement of the semiconductor integrated circuit which performs the process shown in FIG. FIG. 9 is a diagram showing another example of the operation of the semiconductor integrated circuit that executes the process shown in FIG. 8. It is a figure which shows another example of the process performed by the arithmetic unit array shown in FIG. It is a figure which shows the example of a circuit structure of the arithmetic unit array which performs context CTXJ shown in FIG. FIG. 15 is a diagram showing the relationship between data values, flag signals, and executed data processing in the circuit configuration shown in FIG. 14. It is a figure which shows the example of operation | movement of the semiconductor integrated circuit which performs the process shown in FIG. It is a figure which shows another example of the process performed by the arithmetic unit array shown in FIG. It is a figure which shows the example of the circuit structure of the arithmetic unit array which performs context CTXJ shown in FIG. It is a figure which shows the relationship between the value of data in the circuit structure shown in FIG. 18, a flag signal, and the data processing performed. FIG. 18 is a diagram illustrating an example of an operation of a semiconductor integrated circuit that executes the process illustrated in FIG. 17. FIG. 4 is a diagram showing another example of the operation of the semiconductor integrated circuit shown in FIG. 3. It is a figure which shows another example of a semiconductor integrated circuit diagram. It is a figure which shows the example of the arithmetic unit array shown in FIG. It is a figure which shows the example of the process performed by the arithmetic unit array shown in FIG. FIG. 25 is a diagram showing an example of the operation of a semiconductor integrated circuit that executes the process shown in FIG. 24. It is a figure which shows another example of the process performed by the arithmetic unit array shown in FIG. FIG. 27 is a diagram illustrating an example of the operation of a semiconductor integrated circuit that executes the processing illustrated in FIG. 26.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines and terminals through which signals are transmitted. A signal line through which a multi-bit signal is transmitted is indicated by a bold line.

  FIG. 1 shows an embodiment of a semiconductor integrated circuit. The semiconductor integrated circuit SEM1 of this embodiment includes a calculation unit 2 and a control unit 4. The arithmetic unit 2 can be dynamically reconfigured according to the configuration data CFG (CFG0, CFG1), and a plurality of arithmetic units OP (outputting flag signals FLG (FLG0, FLG1) according to the result of the logical operation). OP0, OP1). The control unit 4 selects one of a plurality of configuration data CFG (CFG0, CFG1) for reconfiguring the circuit of the calculation unit 2 according to the plurality of flag signals FLG, and the selected configuration data CFG is calculated by the calculation unit. Output to 2.

  For example, the control unit 4 outputs a selection signal SEL for selecting one of the configuration data CFG according to the flag signal FLG. When the configuration data CFG0 and CFG1 are stored in the memory, the selection signal SEL includes an address indicating a storage area in which the configuration data CFG0 and CFG1 are stored. Note that the memory for storing the configuration data CFG0 and CFG1 may be disposed outside the semiconductor integrated circuit SEM1.

  For example, the control unit 2 selects the configuration data CFG corresponding to the flag signal FLG indicating true. For example, the arithmetic unit 2 sets the priority of the flag signal FLG0 higher than the priority of the flag signal FLG1, and among the plurality of arithmetic units OP, the arithmetic unit OP prioritizes the result of the logical operation over the other arithmetic units OP. The output may be output as the flag signal FLG0. In this case, the control unit 4 outputs a selection signal SEL for selecting the configuration data CFG corresponding to the flag signal FLG0 having a high priority when both the flag signals FLG0 and FLG1 indicate true.

  FIG. 2 shows an example of the operation of the semiconductor integrated circuit SEM1 shown in FIG. That is, FIG. 2 shows an embodiment of a method for operating a semiconductor integrated circuit. The operation enclosed in square brackets indicates the operation of another semiconductor integrated circuit in which the arithmetic unit outputs one flag signal FLG and the control unit selects configuration data CFG based on one flag signal FLG. .

  In the arithmetic unit 2 of the semiconductor integrated circuit SEM1, the circuit is reconfigured in advance by configuration data CFGJ1 for condition determination, and the condition determination is performed by the arithmetic units OP0 and OP1 (FIG. 2A). In this example, the calculator OP0 determines whether the data x supplied to the calculator 2 is “0”, and the calculator OP1 determines whether the data x is “1”. . For example, when the data x supplied to the arithmetic unit 2 is “1”, the arithmetic unit 2 does not output the flag signal FLG0 corresponding to the output of the arithmetic unit OP0 (for example, the flag signal FLG0 indicates false) (FIG. 2 (b)). On the other hand, the computing unit 2 outputs a flag signal FLG1 corresponding to the computing unit OP1 (for example, the flag signal FLG1 indicates true) (FIG. 2 (c)).

  Based on the flag signals FLG0 and FLG1, the control unit 4 selects the configuration data CFG1 corresponding to the flag signal FLG1 indicating true and transfers it to the calculation unit 2 (FIG. 2 (d)). The arithmetic unit 2 reconfigures the circuit based on the configuration data CFG1, and then executes processing when the data x is “1” (FIG. 2E).

  On the other hand, when the arithmetic unit outputs one flag signal FLG, first, the arithmetic unit OP of the arithmetic unit determines whether or not the data x is “0” (FIG. 2 (f)). Since the data x is “1”, the flag signal FLG is not output (FIG. 2G). Based on the flag signal FLG, the control unit selects configuration data CFGJ2 for condition determination and transfers it to the calculation unit (FIG. 2 (h)). The arithmetic unit reconfigures the circuit based on the configuration data CFGJ2, and then determines whether or not the data x is “1” by the arithmetic unit OP.

  Since the data x supplied to the calculation unit is “1”, the calculation unit outputs the flag signal FLG (FIG. 2 (i)). Based on the flag signal FLG, the control unit selects the configuration data CFG1 and transfers it to the calculation unit (FIG. 2 (j)). The arithmetic unit reconfigures the circuit based on the configuration data CFG1, and then executes a process when the data x is “1” (FIG. 2 (k)).

  As shown in FIG. 2, in this embodiment, configuration data CFG is selected according to a plurality of flag signals FLG0 and FLG1. That is, the configuration data CFG for reconfiguring the computing unit 2 can be selected based on the results of a plurality of logical operations (condition determination) by the plurality of computing units OP0 and OP1. As a result, the time required for the condition determination can be shortened compared to the case where the configuration data CFG is selected according to one flag signal FLG, and the processing executed by the calculation unit 2 can be started earlier according to the result of the condition determination. . Thereby, the performance of the semiconductor integrated circuit SEM1 can be improved. In other words, in the semiconductor integrated circuit SEM1 having the dynamically reconfigurable arithmetic unit, the circuit of the arithmetic unit 2 reconfigured according to the result of the condition determination is faster than the operation shown in parentheses in FIG. Can be built.

  As described above, in the embodiment shown in FIGS. 1 and 2, it is possible to reduce the time required for the condition determination as compared with the case where the configuration data CFG is selected according to one flag signal FLG. As a result, the processing executed by the calculation unit 2 can be started quickly according to the result of the condition determination, and the performance of the semiconductor integrated circuit SEM1 can be improved.

  FIG. 3 shows another embodiment of the semiconductor integrated circuit. Elements that are the same as or similar to those described in the embodiment shown in FIGS. 1 and 2 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The semiconductor integrated circuit SEM2 of this embodiment is connected to an MCU (Micro Control Unit) 20, a memory 30, and a peripheral circuit 40 via a system bus SBUS. The semiconductor integrated circuit SEM2 includes a shared memory 12, a sequencer 14, configuration memories 16A and 16B, and an arithmetic unit array 18, and operates in synchronization with a clock signal, for example.

  The system bus SBUS is used for communication between the MCU 20 and the semiconductor integrated circuit SEM2, the memory 30, and the peripheral circuit 40. For example, the semiconductor integrated circuit SEM2, the MCU 20, the memory 30, the peripheral circuit 40, and the system bus SBUS are mounted on the system SYS2. The MCU 20, the memory 30, the peripheral circuit 40, and the system bus SBUS may be arranged in the semiconductor integrated circuit SEM2.

  The MCU 20 executes, for example, a program stored in the memory 30 to control the operations of the semiconductor integrated circuit SEM2 and the peripheral circuit 40, and also controls the overall operation of the system SYS2. The MCU 20 writes data of a circuit constructed in the arithmetic unit array 18 to the configuration memory 16A, and writes information indicating an address of the configuration memory 16A to the configuration memory 16B. Further, the MCU 20 writes data to be calculated by the arithmetic unit array 18 to the shared memory 12, and reads out the data obtained by the calculation by the arithmetic unit array 24 and written to the shared memory 12 from the shared memory 12.

  The memory 30 is a flash memory, SRAM (Static Random Access Memory), or the like, and stores a program executed by the MCU 20 and data used by the MCU 20 and the peripheral circuit 40. The peripheral circuit 40 is a communication circuit, a timer, an AD (Analog to Digital) converter, a DA (Digital to Analog) converter, or the like.

  The shared memory 12 is accessible by the MCU 20 and the arithmetic unit array 18 and is, for example, an SRAM. The shared memory 12 holds data (calculation data, that is, input data) calculated by the calculator array 18 and data (calculation result data, that is, output data) obtained by calculation by the calculator array 18.

  When the shared memory 12 receives a control signal, an address signal, and data (calculation data) indicating a write request from the MCU 20 via the system bus SBUS, the shared memory 12 writes the received calculation data in an area indicated by the address signal. When the shared memory 12 receives a control signal and an address signal indicating a read request from the MCU 20 via the system bus SBUS, the shared memory 12 outputs data (operation result data) held in an area indicated by the address signal to the MCU 20.

  Further, when the shared memory 12 receives the control signal CNT indicating the read request and the address signal AD from the arithmetic unit array 18, the shared memory 12 outputs the arithmetic data held in the area indicated by the address signal AD to the arithmetic unit array 18. When the shared memory 12 receives the control signal CNT, the address signal AD, and the data (calculation result data) indicating the write request from the arithmetic unit array 18, the shared memory 12 writes the received calculation result data in the area indicated by the address signal AD.

  The configuration memory 16 </ b> A has a plurality of storage areas for storing data of circuits constructed in the arithmetic unit array 18. The circuit data includes information indicating the function of each circuit and information indicating a connection between the circuits. When the configuration memory 16A receives the control signal CNTa indicating the read request and the address signal ADa from the sequencer 14, the configuration memory 16A outputs the data RDT of the circuit constructed in the arithmetic unit array 18 to the arithmetic unit array 18 as configuration data CFG.

  The configuration memory 16B has a plurality of storage areas for storing eight sets of addresses ADa and ADb, a branch control flag BRA, and an end flag ENDS stored in the registers REG0 to REG7 of the sequencer 14. When the configuration memory 16B receives the control signal CNTb indicating the read request and the address signal ADb from the sequencer 14, the configuration memory 16B stores the addresses ADa, ADb, the branch control flag BRA, and the end flag ENDS stored in the storage area corresponding to the address signal ADb. The value of is output.

  The data held in the configuration memories 16A and 16B is written from the MCU 20 via the system bus SBUS according to the specifications of the system in which the semiconductor integrated circuit SEM2 is mounted before the sequencer 14 starts operation. An example of the configuration memories 16A and 16B is shown in FIG.

  The sequencer 14 includes a control circuit CNTL, a register REG (REG0, REG1, REG2, REG3, REG4, REG5, REG6, REG7), selectors SSEL1, SSEL2, and an incrementer INC. The sequencer 14 selects one of a plurality of configuration data CFG indicating the circuit configuration of the arithmetic unit array 18 according to the plurality of flag signals FLG, and outputs the selected configuration data CFG to the arithmetic unit array 18. It is an example of a part.

  The control circuit CNTL includes, for example, a state machine, and controls the configuration change (context switching) of the arithmetic unit array 18. The context switching control by the control circuit CNTL is determined according to the register data REGD written from the configuration memory 16B to the register REG.

  The control circuit CNTL generates a trigger signal TRG indicating the timing at which the configuration data CFG is transferred from the configuration memory 16A to the arithmetic unit array 18 and a stall signal STL for temporarily stopping the operation of the arithmetic unit array 18. Have

  The control circuit CNTL receives from the arithmetic unit array 18 an end signal END indicating completion of data processing (context) by the arithmetic unit array 18 and a flag signal FLG (FLG0, FLG1, FLG2, FLG3, FLG4, FLG5, FLG6, FLG7). . Each flag signal FLG indicates a result (true or false) of a logical operation (condition determination) by the arithmetic unit array 18. The number of flag signals FLG may be two or more.

  In response to the end signal END, the control circuit CNTL outputs the control signal CNTa to the configuration memory 16A and outputs the control signal CNTb to the configuration memory 16B. The control circuit CNTL outputs a stall signal STL to the arithmetic unit array 18 when the operation of the arithmetic unit array 18 is temporarily stopped.

  The control circuit CNTL outputs a selection signal BS1 to the selector SSEL1 based on the flag signal FLG. For example, the control circuit CNTL outputs a selection signal BS1 for selecting the register REG corresponding to the flag signal FLG indicating true. When there are a plurality of flag signals FLG indicating true, the control circuit CNTL outputs a selection signal BS1 for selecting the register REG corresponding to the flag signal FLG having a higher priority than the other flag signals FLG. For example, the priority is set higher as the number of the flag signal FLG is smaller. The association between the result of the logical operation in the arithmetic unit array 18 and the priority of the flag signal FLG is executed by the network circuit NWF in the arithmetic unit array 18 as described in FIG. The control circuit CNTL fixes the selection signal BS1 to “0” during the period when the branch control flag BRA in the reset state is received, and causes the selector SSEL1 to select the information stored in the register REG0.

  Each of the registers REG0 to REG7 holds eight sets of address values included in the register data REGD read from the configuration memory 16B according to the control signal CNTb and the address signal ADb from the control circuit CNTL. One set of address values held by the registers REG0 to REG7 is used as an address ADa for accessing the configuration memory 16A and an address ADb for accessing the configuration memory 16B. For example, the registers REG0 to REG7 correspond to the flag signals FLG0 to FLG7, respectively. Like the flag signal FLG, the lower the number, the higher the priority.

  If the configuration memory 16B has a holding circuit that holds the register data REGD until the next read request is received, the sequencer 14 may not have the registers REG0 to REG7. In this case, the register data REGD is supplied to the input terminal of the selector SSEL1.

  The selector SSEL1 selects one set of addresses ADa and ADb output from the registers REG0 to REG7 in accordance with the selection signal BS1 generated by the control circuit CNTL based on the flag signal FLG. The selector SSEL1 outputs the selected addresses ADa and ADb to the configuration memories 16A and 16B. Then, configuration data CFG indicating a context to be executed next is read from the storage area of the configuration memory 16A indicated by the address ADa. Also, the values of eight sets of addresses ADa, ADb, branch control flag BRA, and end flag ENDS newly stored in the registers REG0 to REG7 are read from the storage area of the configuration memory 16B indicated by the address ADb.

  That is, the sequencer 14 has a function of determining the circuit to be reconfigured next in the arithmetic unit array 18 from eight types in accordance with flag signals FLG0 to FLG7 indicating the results of the plurality of condition determinations by the arithmetic unit array 18. . As a result, it becomes possible to execute the multi-branch condition determination corresponding to the case statement shown in FIG. 8 or the if statement shown in FIG. 13 at a time, and the rewrite frequency of the arithmetic unit array 18 is reduced as compared with the conventional case. It becomes possible. Furthermore, by assigning priority to the flag signals FLG0 to FLG7, the correct register REG can be selected by the selector SSEL1 even when a plurality of flag signals FLG indicate true.

  The branch control flag BRA is set (= "1") when a conditional branch based on the flag signal FLG is executed, and is reset (= "0") when a conditional branch based on the flag signal FLG is not executed. For example, the end flag ENDS is reset when the context for condition determination is executed, and is set when the context for calculation selected by the condition determination is executed. When the end flag ENDS is set, the control circuit CNTL performs desired data processing and stops the operation of the sequencer 14 after the calculation result is obtained.

The incrementer INC holds the address value ADa stored in the register REG0, and outputs the held address value ADa to the selector SSEL2. Further, when the branch control flag BRA is reset, the incrementer INC sequentially increases the held address ADa by “1” and outputs the increased address value ADa to the selector SSEL2. The incrementer INC is an example of an update circuit that sequentially updates one of the addresses ADa output from the configuration memory 16B when the valid flag BRA indicates invalidity. The incrementer INC may decrease the address value ADa by “1”.

  The selector SSEL2 selects the address value ADa output from the selector SSEL1 while the branch control flag BRA is set, and selects the address value ADa output from the incrementer INC while the branch control flag BRA is reset. That is, when the sequencer 14 does not execute the conditional branch process according to the logic of the flag signal FLG, the sequencer 14 sequentially updates the address ADa held in the register REG0 and reads the configuration data CFG from the configuration memory 16A.

  The computing unit array 18 includes a network circuit NWD, a plurality of computing units OP, a plurality of flag computing units FOP, a network circuit NWF, and a flag computing unit DFOP. The arithmetic unit array 18 is an arithmetic module that realizes a predetermined data processing procedure (data flow) by connecting the arithmetic unit OP, the flag arithmetic unit FOP, and the flag arithmetic unit DFOP via the network circuits NWD and NWF. The computing unit array 18 can switch the operation specifications of the computing unit OP, the flag computing unit FOP, and the flag computing unit DFOP and the connection specifications between the computing unit OP and the flag computing unit FOP during the operation of the MCU 20. That is, the arithmetic unit array 18 is a dynamic reconfiguration circuit. The computing unit array 18 is an example of a computing unit including a plurality of reconfigurable computing units OP and FOP. Note that the number of computing units OP and flag computing units FOP mounted on the computing unit array 18 is determined according to design specifications (circuit scale, power consumption, and computation contents). An example of the arithmetic unit array 18 is shown in FIG.

  FIG. 4 shows an example of the arithmetic unit array 18 shown in FIG. The arithmetic unit array 18 includes the network circuit NWD shown in FIG. 3, n (n is a positive integer) arithmetic unit OP, m (m is a positive integer) flag arithmetic unit FOP, network circuit NWF, flag calculation A DFOP, a counter ACOUNT, and a memory control circuit MCNT.

  The network circuit NWD includes a data output terminal DO (DO0 [1: 0],..., DOn [1: 0]) for outputting data to each arithmetic unit OP, and a data input terminal for receiving data from each arithmetic unit OP. DI (DI0,..., DIn). The numerical value “[1: 0]” of the data output terminal DO indicates the port number. For example, each data output terminal DO is 64 bits (two 32-bit ports), and each data input terminal DI is 32 bits (one 32-bit port).

  The network circuit NWD includes data input terminals DIM (DIM0,..., DIMp) that receive data from the shared memory 12 shown in FIG. 3 and data output terminals DOM (DOM0,. ., DIMp). For example, each data input terminal DIM and each data output terminal DOM are 32 bits (that is, “p” is “31”).

  The network circuit NWD changes the connection specifications between the arithmetic units OP according to the configuration data CFG from the configuration memory 16A received in synchronization with the trigger signal TRG. After changing the connection specification, the network circuit NWD transfers the input data DIM received from the shared memory 12 as output data DO to a predetermined computing unit OP.

  Each computing unit OP has a data input port DI [1: 0] that receives output data DO from the network circuit NWD, and a data output port DO that outputs data obtained by the computation. The numerical value “[1: 0]” of the data input terminal DI indicates a port number. For example, each computing unit OP has two data input ports DI (DI [1], DI [0]) and one data output port DO, and the number of data input ports DI and data output ports DO is: It can be changed according to the specification of the arithmetic unit OP, and is not limited to the example shown in FIG.

  Each arithmetic unit OP also receives flag input terminals FI1 and FI0 that receive a pair of flag signals AFO (AFO0,..., AFOn) from the network circuit NWF, and a flag output terminal that outputs the flag signal AFI to the network circuit NWF. FO. Each of the flag input terminals FI1 and FI0 and the flag output terminal FO is 2 bits.

  Then, each computing unit OP is switched to, for example, a computing unit that performs any of the four arithmetic operations or a plurality of types of logical operations in accordance with the configuration data CFG received in synchronization with the trigger signal TRG. The computing unit OP computes data received by at least one of the input ports DI0 and DI1, and outputs the computation result to the output port DO or the flag output terminal FO. The result of the arithmetic operation is output to the output port DO, and the result of the comparison process or sign determination is output to the flag output terminal FO as a flag signal.

  Each computing unit OP selects one of the data received at the data input port DI [1: 0] based on the flag signal from the other computing unit OP or the flag computing unit FOP received at the flag input terminals FI1 and FI0. It may be operated as a selector. The arithmetic unit OP stops operating while receiving the stall signal STL.

  Each flag calculator FOP has flag input terminals FI1 and FI0 that receive a flag signal from the calculator OP or another flag calculator FOP via the network circuit NWF, and a flag output terminal FO that outputs the result of the flag calculation. . Each of the flag input terminals FI1 and FI0 and the flag output terminal FO is 2 bits.

  The flag arithmetic unit FOP executes a logical product or logical sum processing of flag signals, thereby enabling condition determination based on the determination results of the plurality of arithmetic units OP and FOP. Each flag computing unit FOP is switched to a flag computing unit that executes one of a plurality of types of logical operations in accordance with configuration data CFG received in synchronization with the trigger signal TRG. Each flag calculator FOP executes a flag calculation in synchronization with the clock signal, and outputs the calculation result to the flag output terminal FO. The flag calculator FOP stops its operation while receiving the stall signal STL.

  The network circuit NWF has 2-bit flag output terminals AFO1, AFO0 (AFO01, AFO00,..., AFOn1, AFOn0) for outputting a flag signal to each arithmetic unit OP. The network circuit NWF has flag input terminals AFI (AFI0,..., AFIn) that receive flag signals from the respective arithmetic units OP. Further, the network circuit NWF has 2-bit flag output terminals FFO1, FFO0 (FFO01, FFO00,..., FFOm1, FFOm0) for outputting a flag signal to each flag calculator FOP. The network circuit NWF has a 1-bit flag input terminal FFI (FFI0,..., FFIm) that receives a flag signal from each flag calculator FOP. Each of the flag output terminals AFO1 and AFO0, the flag input terminal AFI, the flag output terminals FFO1 and FFO0, and the flag input terminal FFI are 2 bits.

  The network circuit NWF has a function of connecting the flag output terminal FO of the computing unit OP or the flag computing unit FOP to the flag input terminal FI of another computing unit OP or the flag computing unit FOP according to the configuration data CFG. Have. The network circuit NWF has a function of connecting the calculator OP and the flag output terminal FO of the flag calculator FOP to any one of the flag terminals FLG (FLG0 to FLG7) according to the configuration data CFG.

  That is, the network circuit NWF has a connection specification between the arithmetic unit OP and the flag arithmetic unit FOP and a transfer specification of the flag signal to the flag terminal FLG according to the configuration data CFG received in synchronization with the trigger signal TRG. Has the function to change. The network circuit NWF is an example of a connection unit that connects the outputs of the arithmetic units OP and FOP and the flag terminal FLG that outputs a flag signal FLG according to priority.

  As described in FIG. 3, the priority of the flag signals FLG0 to FLG7 is higher as the number is smaller. The network circuit NWF can connect the output of an arbitrary arithmetic unit OP or flag arithmetic unit FOP to any one of flag terminals FLG0 to FLG7 according to the priority. As a result, flag signals FLG0 to FLG7 in which priorities are set can be output from the network circuit NWF to the sequencer 14, and the priority determination processing by the sequencer 14 can be omitted.

  The flag calculator DFOP operates in either the normal mode or the default mode according to the configuration data CFG received in synchronization with the trigger signal TRG. The flag calculator DFOP outputs the flag signal FLG7 received at the 2-bit flag input terminal FI7 as the flag signal FLG7 from the flag output terminal FO during the normal mode. Flag calculator DFOP outputs flag signal FLG7 indicating true when flag signals FLG6-FLG0 received at 2-bit flag input terminals FI6-FI0 respectively indicate false or invalid during the default mode. Further, flag calculator DFOP outputs flag signal FLG7 indicating false when any of flag signals FLG6-FLG0 received at flag input terminals FI6-FI0 indicates true during the default mode.

  The flag calculator DFOP is an example of a flag control circuit that outputs a flag signal FLG7 indicating true to the sequencer 14 when any of the plurality of flag signals FLG0 to FLG6 output from the calculators OP and FOP indicates false. . An example of the flag calculator DFOP is shown in FIG.

  For example, each flag signal FLG is 2 bits, the upper bits indicate true or false, and the lower bits indicate valid or invalid. When the result of the comparison process or sign determination is true, the flag signal FLG is set to binary “11”. When the result of the comparison process or sign determination is false, the flag signal FLG is It is set to the binary number “10”. When an operation that does not involve the output of the flag signal FLG is executed, the flag signal FLG is set to “00” or “01”, which is a binary number indicating invalidity. In the following description, the 2-digit numerical value indicating the value of the flag signal FLG is a binary number.

  In this embodiment, the arithmetic unit array 18 outputs a plurality of flag signals FLG having priorities set in advance, and causes the sequencer 14 to select a context to be executed next in accordance with the priorities of the flag signals FLG. As a result, the number of clock cycles used in the condition determination for determining the context for executing the next operation can be reduced as compared with the conventional case, and the operation efficiency of the arithmetic unit array 18 can be improved.

  The counter ACOUNT generates, for example, an index signal IDX indicating an increment of the address signal AD generated by the memory control circuit MCNT according to the execution of the context. The counter ACOUNT counts the number of cycles required for context processing, and outputs an end signal END when determining the end of the context being executed. The counter ACOUNT changes the value and increment of the index signal IDX and the generation specification and generation timing of the end signal END according to the configuration data CFG received in synchronization with the trigger signal TRG. Further, the counter ACOUNT stops its operation while receiving the stall signal STL.

  The memory control circuit MCNT generates the address signal AD from the reference value of the address signal AD included in the configuration data CFG and the value of the index signal IDX from the counter ACOUNT, and the shared memory shown in FIG. 3 together with the control signal CNT. 12 is output. Then, by controlling the operation of the shared memory 12 by the memory control circuit MCNT, data is exchanged between the shared memory 12 and the arithmetic unit array 18 via the network circuit NWD. The memory control circuit MCNT can change the generation timing of the address signal AD and the control signal CNT according to the configuration data CFG received in synchronization with the trigger signal TRG.

  FIG. 5 shows an example of the flag calculator FOP shown in FIG. The flag calculator FOP includes a flip-flop FF1, polarity inverters PRVS0 and PRVS1, selectors SEL0 and SEL1, and a flag calculator FLGOP.

  The flip-flop FF1 receives the 3-bit configuration data CFG in synchronization with the clock signal CLK during the effective level of the trigger signal TRG, and outputs the received configuration data CFG as the control signal C [2: 0].

  The polarity inverter PRVS0 inverts the polarity of the flag signal received at the input terminal FI0 [1: 0], and the polarity inverter PRVS1 inverts the polarity of the flag signal received at the input terminal FI1 [1: 0]. For example, the polarity inverters PRVS0 and PRVS1 convert the flag signal “11” indicating true into a flag signal “10” indicating false, the flag signal “10” indicating false, and the flag signal “11” indicating true. Convert to By providing the flag computing unit FOP with a function for inverting the polarity of the flag signal, for example, the number of flag computing units FOP used in the processing equivalent to the nesting processing of the if statement shown in FIG. This can be reduced compared to the case without the function.

  The selector SEL0 selects the flag signal received at the input terminal FI0 [1: 0] when the control signal C [0] is high level, and the polarity is inverted by the polarity inverter PRVS0 when the control signal C [0] is low level. Select the inverted flag signal. Then, the selector SEL0 outputs the selected signal as the flag signal FI0 to the flag calculation unit FLGOP.

  The selector SEL1 selects a flag signal received at the input terminal FI1 [1: 0] when the control signal C [1] is high level, and the polarity is inverted by the polarity inverter PRVS1 when the control signal C [1] is low level. Select the inverted flag signal. Then, the selector SEL1 outputs the selected signal as the flag signal FI1 to the flag calculation unit FLGOP.

  For example, when the control signal C [2] is at a high level (“1”), the flag calculation unit FLGOP outputs the logical product (AND) of the flag signals FI0 and FI1 as the flag signal FO [1: 0]. For example, when the control signal C [2] is at a low level (“0”), the flag calculation unit FLGOP outputs the logical sum (OR) of the flag signals FI0 and FI1 as the flag signal FO [1: 0]. When at least one of the flag signals FI0 and FI1 is invalid (“00” or “01”), the flag calculation unit FLGOP outputs a flag signal FO [1: 0] (“00”) indicating invalidity.

  FIG. 6 shows an example of the flag calculator DFOP shown in FIG. The flag calculator DFOP includes a flip-flop FF2, AND circuits AND1, AND0, an OR circuit OR, a NOR circuit NOR, and selectors SEL3, SEL2.

  The flip-flop FF2 receives the 9-bit configuration data CFG in synchronization with the clock signal CLK during the effective level of the trigger signal TRG, and outputs the received configuration data CFG as the control signal C [8: 0].

  The AND circuit AND1 (AND10, AND11, AND12, AND13, AND14, AND15, AND16, AND17) receives the upper bits of the flag signals FLG0 to FLG7. The AND circuit AND1j (j is any one of 0 to 7) outputs a logical product of the upper bit FIj [1] of the flag signal FLGj and the control signal C [j] as the flag signal FGj1. The control signal C [j] is set to a high level when the upper bit FIj [1] is used for condition determination (when input is valid), and the upper bit FIj [1] is not used for condition determination (input). Is set to low level. That is, the AND circuit AND1j functions as a mask circuit that masks the flag signal FLGj that is not used for condition determination.

  The OR circuit OR outputs a high level when at least one of the flag signals FGj1 is at a high level, and outputs a low level when all the flag signals FGj1 are at a low level. In other words, the OR circuit OR outputs a signal indicating the valid state to the selector SEL3 when at least one of the flag signals FGj1 indicates the valid state of the flag signal FLG.

  The selector SEL3 selects the output of the OR circuit OR when the control signal C [8] is at a high level, and selects the upper bit FI7 [1] of the flag signal FLG7 when the control signal C [8] is at a low level. Then, the selector SEL3 outputs the selected signal to the output terminal FO1 as the upper bits of the flag signal FLG7.

  The AND circuit AND0 (AND00, AND01, AND02, AND03, AND04, AND05, AND06, AND07) receives the lower bits of the flag signals FLG0-FLG7. The AND circuit AND0k (k is one of 0 to 7) outputs a logical product of the lower bits FIk [0] of the flag signal FLGk and the control signal C [k] as the flag signal FGk0. The control signal C [k] is set to a high level when the lower bit FIk [0] is used for condition determination (when the input is valid), and when the lower bit FIk [0] is not used for condition determination (input). Is set to low level. That is, the AND circuit AND0j functions as a mask circuit that masks the flag signal FLGk that is not used for condition determination.

  The NOR circuit NOR outputs a low level when at least one of the flag signals FGk0 is at a high level, and outputs a high level when all the flag signals FGk1 are at a low level. In other words, the NOR circuit NOR outputs a signal indicating true to the selector SEL0 when all the flag signals FGk1 indicate false. The NOR circuit NOR outputs a signal indicating false to the selector SEL2 when at least one of the flag signals FGk1 indicates true.

  The selector SEL2 selects the output of the NOR circuit NOR when the control signal C [8] is at a high level, and selects the lower bit FI70 of the flag signal FLG7 when the control signal C [8] is at a low level. Then, the selector SEL2 outputs the selected signal to the output terminal FO0 as the lower bit of the flag signal FLG7.

  The flag calculator DFOP operates in the normal mode or the default mode. In the normal mode, the control signal C [8] is set to the low level, and the selectors SEL3 and SEL2 select the flag signals FI7 [1] and FI7 [0], respectively. Then, the flag calculator DFOP outputs the flag signal FLG7 from the network circuit NWF to the sequencer 14 (FIG. 3) as the flag signal FLG7.

  In the default mode, the selectors SEL3 and SEL2 receive the high level control signal C [8] and select the outputs of the OR circuit OR and the NOR circuit NOR, respectively. The flag calculator DFOP outputs a flag signal FLG7 (“11”) indicating true to the sequencer 14 when all the flag signals FLG0 to FLG6 from the network circuit NWF are false. The flag calculator DFOP outputs a flag signal FLG7 (“10”) indicating false when any of the flag signals FLG0 to FLG6 from the network circuit NWF is true.

  FIG. 7 shows an example of the configuration memories 16A and 16B shown in FIG. For example, the configuration memory 16A has 32 storage areas for storing configuration data CFG for constructing a circuit in the arithmetic unit array 18. The configuration data CFG is, for example, several hundred bits, and includes information for setting the functions of the arithmetic unit OP, flag arithmetic units FOP, DFOP, network circuits NWD, NWF, counter ACOUNT, and memory control circuit MCNT shown in FIG. Including. That is, the configuration data CFG includes the specification of the context CTX executed by the arithmetic unit array 18.

  The 32 storage areas of the configuration memory 16A can be identified by a 5-bit address ADa. Then, the configuration memory 16A executes a read operation according to the control signal CNTa, and reads the information read from the storage area indicated by the address signal ADa via the read circuit indicated by a triangle in FIG. Output as. Note that the configuration memory 16A may store 64 types of circuit specifications using 6-bit addresses, and may store 16 types of circuit specifications using 4-bit addresses. The configuration memory 16A is an example of a first storage unit that includes a plurality of storage areas that hold a plurality of configuration data CFGs and is accessed by an address ADa.

  For example, the configuration memory 16B has 16 storage areas for storing eight sets of addresses ADa and ADb, a branch control flag BRA, and an end flag ENDS transferred to the registers REG0 to REG7 shown in FIG. The 16 storage areas of the configuration memory 16B can be identified by a 4-bit address ADb.

  Each storage area of the configuration memory 16B has eight sub areas for storing eight sets of addresses ADa and ADb corresponding to the registers REG0 to REG7, and two flag areas for storing a branch control flag BRA and an end flag ENDS. And have. For example, each sub-area is 9 bits (ADa = 5 bits, ADb = 4 bits), each flag area is 1 bit, and each storage area is 74 bits. Then, the configuration memory 16B executes a read operation in accordance with the control signal CNTb, and reads the information read from the storage area indicated by the address signal ADb as register data REGD via the read circuit indicated by a triangle in FIG. Output. The configuration memory 16B is an example of a second storage unit that includes a plurality of storage areas that store a plurality of sets of addresses ADa and ADb and is accessed by the address ADb.

  As shown in FIG. 7, the configuration data CFG and the register data REGD for switching the circuit configuration of the arithmetic unit array 18 are stored in the configuration memories 16A and 16B independent of each other. As a result, as will be described with reference to FIG. 21, the capacity of the memory mounted on the semiconductor integrated circuit SEM2 can be reduced as compared with the conventional case, and the circuit scale of the semiconductor integrated circuit SEM2 can be reduced as compared with the conventional case.

  Instead of the configuration memories 16A and 16B, a configuration memory having 32 storage areas for storing the configuration data CFG, the eight addresses AD, the control flag BRA, and the end flag ENDS may be arranged. In this case, the registers REG0 to REG7 shown in FIG. 3 each hold eight addresses AD read from the configuration memory. The sequencer 14 selects the address AD held in any of the registers REG0 to REG7 in response to the flag signals FLG0 to FLG7 indicating the result of the condition determination. Then, the selected address AD and one control signal are output to the configuration memory, and the configuration data CFG, eight addresses AD, the control flag BRA, and the end flag ENDS are read from the configuration memory.

  FIG. 8 shows an example of processing to be executed by the arithmetic unit array 18 shown in FIG. In this example, the arithmetic unit array 18 in the semiconductor integrated circuit SEM2 constructs a circuit (context CTXJ) that performs condition determination based on reception of the configuration data CFG. For example, the arithmetic unit array 18 executes the process of the context CTXJ and determines whether the data “x” received from the shared memory 12 is “0”, “1”, “2”, or “3”. . That is, the context CTXJ executes a process corresponding to a switch statement such as C language shown in FIG. The arithmetic unit array 18 outputs the determination result to the sequencer 14 as flag signals FLG0 to FLG3 and FLG7. In this example, the condition determination is executed four times and there are five branch destinations, so five flag signals FLG0 to FLG3 and FLG7 are used. Flag signals FLG4-FLG6 are set to a level indicating invalidity.

  The sequencer 14 reads from the configuration memory 16A the configuration data CFG for constructing a circuit that the arithmetic unit array 18 performs next processing based on the values of the flag signals FLG0 to FLG3 and FLG7. The arithmetic unit array 18 uses the configuration data CFG read from the configuration memory 16A to construct a circuit (any one of the contexts CTX0 to CTX4) that performs the next process.

  For example, when the values of the flag signals FLG0 to FLG3 and FLG7 indicate “x = 0”, the arithmetic unit array 18 is constructed in a circuit that executes the context CTX0 (processing A). For example, “x = 0” is indicated by the trueness of the flag signal FLG0 and the falseness of the flag signals FLG1 to FLG3 and FLG7. When the values of the flag signals FLG0 to FLG3 and FLG7 indicate “x = 1”, the arithmetic unit array 18 is constructed in a circuit that executes the context CTX1 (processing B). For example, “x = 1” is indicated by true of the flag signal FLG1 and false of the flag signals FLG0, FLG2, FLG3, and FLG7.

  When the values of the flag signals FLG0 to FLG3 and FLG7 indicate “x = 2”, the arithmetic unit array 18 is constructed in a circuit that executes the context CTX2 (processing C). For example, “x = 2” is indicated by true of the flag signal FLG2 and false of the flag signals FLG0, FLG1, FLG3, and FLG7. When the values of the flag signals FLG0 to FLG3 and FLG7 indicate “x = 3”, the arithmetic unit array 18 is constructed in a circuit that executes the context CTX3 (processing D). For example, “x = 3” is indicated by true of the flag signal FLG3 and false of the flag signals FLG0 to FLG2 and FLG7.

  On the other hand, if the flag signals FLG0-FLG3, FLG7 indicate that none of “x = 0”, “x = 1”, “x = 2”, “x = 3” Is constructed in a context CTX4 for executing the process E. For example, the fact that none of “x = 0”, “x = 1”, “x = 2”, and “x = 3” is indicated by the flag signal FLG7 being true and the flag signals FLG0 to FLG3 being false. Then, after the execution of the context CTXJ, the arithmetic unit array 18 executes any one of the contexts CTX0 to CTX4 newly constructed based on the values of FLG0 to FLG3 and FLG7.

  In the semiconductor integrated circuit SEM2 shown in FIG. 3, when any one of a plurality of processes is selectively executed according to the result of the condition determination, the data process to be executed is determined by one condition determination context CTXJ. be able to. That is, since a plurality of condition determination contexts CTX are not constructed for determining the data processing to be executed, the timing from the condition determination to the start of the data processing can be made earlier than before. As a result, the performance of the semiconductor integrated circuit SEM2 can be improved as compared with the conventional one.

  FIG. 9 shows an example of the circuit configuration of the arithmetic unit array 18 that executes the context CTXJ shown in FIG. FIG. 9 shows a state in which the arithmetic unit array 18 is constructed in a circuit (context CTXJ) that performs condition determination based on reception of the configuration data CFG. In other words, FIG. 9 shows a calculation flow (also referred to as a data flow) for sequentially executing a predetermined calculation.

  For example, the network circuit NWD connects the data terminal RDT of the shared memory 12 that outputs data “x” to the data input terminal DI0 of the arithmetic units OP0, OP1, OP2, and OP3 based on the configuration data CFG. The arithmetic unit OP0 is constructed as a circuit for determining whether or not the data “x” received at the data input terminal DI0 is “0” based on the configuration data CFG. The arithmetic unit OP0 outputs a flag signal (“11”) indicating true from the flag output terminal FO when the data “x” is “0”, and the data “x” is not “0”. A flag signal (“10”) indicating false is output from the flag output terminal FO.

  The arithmetic units OP1, OP2, and OP3 whose circuits are constructed by the configuration data CFG operate in the same manner as the arithmetic unit OP0. That is, the arithmetic unit OP1 outputs a flag signal indicating true from the flag output terminal FO when the data “x” is “1”, and false from the flag output terminal FO when the data “x” is not “1”. A flag signal indicating is output. The arithmetic unit OP2 outputs a flag signal indicating true from the flag output terminal FO when the data “x” is “2”, and indicates false from the flag output terminal FO when the data “x” is not “2”. Outputs a flag signal. The arithmetic unit OP3 outputs a flag signal indicating true from the flag output terminal FO when the data “x” is “3”, and indicates false from the flag output terminal FO when the data “x” is not “3”. Outputs a flag signal. Note that when the processing corresponding to the switch statement shown in FIG. 8 is executed, the plurality of computing units OP (two or more of OP0 to OP3) do not output the flag signals indicating true redundantly.

  The network circuit NWF connects the flag output terminals FO of the arithmetic units OP0, OP1, OP2, and OP3 to the flag terminals FLG0, FLG1, FLG2, and FLG3 of the sequencer 14 based on the configuration data CFG. The network circuit NWF connects the flag output terminals FO of the arithmetic units OP0, OP1, OP2, and OP3 to the flag input terminals FI0, FI1, FI2, and FI3 of the sequencer 14 of the flag arithmetic unit DFOP, respectively. The network circuit NWF outputs a value (“00”) indicating that the flag signal is invalid to the vacant flag terminals FLG4 to FLG6 of the sequencer 14, respectively.

  Based on the configuration data CFG, the flag calculator DFOP enables the flag input terminals FI3 [1: 0] -FI0 [1: 0] shown in FIG. 6, and the flag input terminals FI7 [1: 0] -FI4. Disable [1: 0]. Based on the configuration data CFG, the flag calculator DFOP connects the output of the OR circuit OR shown in FIG. 6 to the flag output terminal FO [1] via the selector SEL3. Also, the flag calculator DFOP connects the output of the NOR circuit NOR to the flag output terminal FO [0] via the selector SEL2 based on the configuration data CFG. In other words, the flip-flop FF of the flag calculator DFOP shown in FIG. 6 sets the value of the control signal C [8: 0] to “10F” in hexadecimal based on the configuration data CFG, and sets the default mode Works with.

  When the flag signals FLG3 to FLG0 received at the flag input terminals FI3 [0] to FI0 [0] all indicate false, the flag calculator DFOP outputs the flag signal FLG7 indicating true according to the logic shown in FIG. Output from the flag output terminal FO [0]. As a result, the logic of the flag signal FLG for selecting a process when none of the determination conditions is met can be generated more easily than when the logic is generated using the calculator OP or the flag calculator FOP.

  The sequencer 14 generates the selection signal BS1 shown in FIG. 3 based on the logic of the flag signals FLG0 to FLG3 and FLG7. Further, the sequencer 14 selects one of a set of addresses ADa and ADb held in the registers REG0 to REG3 and REG7 by the selector SSEL1, and selects the selected addresses ADa and ADb together with the control signals CNTa and CNTb in the configuration memory 16A, To 16B.

  In the example shown in FIG. 9, before execution of the context CTXJ shown in FIG. 8, valid addresses ADa are stored in registers REG0-REG3, REG7 (FIG. 3) corresponding to the flag signals FLG0-FLG3, FLG7, respectively. . For example, the registers REG0 to REG3 and REG7 respectively hold the address ADa of the configuration memory 16A in which the configuration data CFG corresponding to the contexts CTX0 to CTX4 is stored.

  Then, based on the logic of the flag signals FLG0 to FLG7, new configuration data CFG is read from the configuration memory 16A, and the arithmetic unit array 18 performs a circuit (context CTX0 shown in FIG. 8) for executing the next processing. -Any of CTX4).

  FIG. 10 shows the relationship between the value of the data x, the flag signal FLG, and the data processing to be executed in the circuit configuration shown in FIG. When the value of the data x is “0”, “1”, “2”, “3”, the flag signals FLG0, FLG1, FLG2, FLG3 are set to true (“11”) as indicated by shading. The Then, the configuration data CFG is transferred to the arithmetic unit array 18 according to the flag signal FLG indicating true, and any one of the contexts CTX0, CTX1, CTX2, and CTX3 is executed.

  When the value of the data x is not “0”, “1”, “2”, or “3”, the flag signal FLG7 is set to true (“11”), and the configuration data CFG is input to the arithmetic unit array 18. The context CTX4 is executed.

  FIG. 11 shows an example of the operation of the semiconductor integrated circuit SEM2 that executes the processing shown in FIG. In the example shown in FIG. 11, since the arithmetic unit array 18 operates in the default mode, the selectors SEL3 and SEL2 of the flag arithmetic unit DFOP shown in FIG. 6 select the outputs of the OR circuit OR and the NOR circuit NOR, respectively. In the registers REG0 to REG3 and REG7, the addresses ADa and ADb of the configuration memories 16A and 16B in which the configuration data CFG of the contexts CTX0 to CTX4 are stored are stored in advance (FIG. 11A).

  In this example, the context CTXJ shown in FIG. 8 is executed in the first to fifth clock cycles, and the context CTX2 is executed in the sixth and subsequent clock cycles (FIGS. 11B and 11C). . That is, based on the result of the condition determination of the context CTXJ, the context CTX2 circuit is constructed in the arithmetic unit array 18 and the process C is executed. The circuit corresponding to the context CTXJ is transferred to the arithmetic unit array 18 before the first clock cycle. In the example shown in FIG. 11, since the conditional branch based on the flag signal FLG is executed, the value of the branch control flag BRA shown in FIG. 3 is set to “1”. Also, the value of the end flag ENDS shown in FIG. 3 is set to “1” by the read operation of the configuration memory 16B in response to the end of execution of the context CTX2.

  In the second clock cycle, data x (= 2) is read from the data terminal RDT of the shared memory 12, and the read data x is supplied to the arithmetic units OP0-OP3 via the network circuit NWD ( FIG. 11 (d)). Until the second clock cycle, the flag signals FLG0 to FLG7 are set to an invalid level ("00" or "01") (FIG. 11 (e)). The flag calculator DFOP receives the lower bits FI7 [0] -FI0 [0] of the invalid flag signals FLG0-FLG6, and outputs the high level “1” output from the NOR circuit NOR to the lower bits FI7 [0] of the flag signal FLG7. ] (FIG. 11 (f)).

  In the third clock cycle, the arithmetic units OP0-OP3 execute the condition determination shown in FIG. 9 and output flag signals FLG0-FLG3 indicating the execution results, respectively (FIG. 11 (g)). In this example, the arithmetic unit OP2 outputs a flag signal FLG2 indicating true (“11”), and the arithmetic units OP0, OP1, and OP3 output flag signals FLG0, FLG1, and FLG3 indicating false (“10”), respectively. Output.

  The flag calculator DFOP outputs a flag signal FLG7 indicating false (“10”) according to the values of the flag signals FLG0 to FLG6 (FIG. 11 (h)). The arithmetic unit array 18 outputs the end signal END together with the output of the flag signals FLG0 to FLG7 (FIG. 11 (i)). The control circuit CNTL of the sequencer 14 sets the selection signal BS1 to “2” in response to the flag signal FLG2 indicating true (FIG. 11 (j)).

  In the fourth clock cycle, the selector SSEL1 of the sequencer 14 outputs the address values ADa2 and ADb2 held by the register REG2 to the configuration memories 16A and 16B according to the selection signal BS1 (FIG. 11 (k)). The control circuit CNTL outputs a control signal CNTa that indicates a read request to the configuration memory 16A and a control signal CNTb that indicates a read request to the configuration memory 16B (FIGS. 11 (l) and 11 (m)).

  In the fifth clock cycle, the configuration memory 16A outputs the configuration data CFG indicating the context CTX2 from the storage area indicated by the address value ADa2 (FIG. 11 (n)). The configuration memory 16B outputs the register data REGD from the storage area indicated by the address value ADb2 (FIG. 11 (o)). The control circuit CNTL sets the trigger signal TRG to the high level in accordance with the output of the configuration data CFG from the configuration memory 16A (FIG. 11 (p)).

  Then, in the sixth clock cycle, the arithmetic unit array 18 takes in the configuration data CFG in accordance with the high level of the trigger signal TRG and constructs a circuit for executing the context CTX2 (FIG. 11 (q)). The arithmetic unit array 18 operates the circuit constructed in the sixth clock cycle, and executes the context CTX2 (processing C) from the seventh clock cycle.

  FIG. 12 shows another example of the operation of the semiconductor integrated circuit SEM2 that executes the processing shown in FIG. The same operations as those in FIG. 11 are denoted by the same reference numerals as those in FIG. In this example, a circuit of the context CTX4 is constructed in the arithmetic unit array 18 based on the result of the condition determination of the context CTXJ shown in FIG.

  In the third clock cycle, the arithmetic units OP0-OP3 execute the condition determination shown in FIG. 9 and output flag signals FLG0-FLG3 indicating the execution results, respectively (FIG. 12 (g)). In this example, the arithmetic units OP0 to OP3 output flag signals FLG0 to FLG3 indicating false (“10”), respectively. Therefore, the flag calculator DFOP outputs a flag signal FLG7 indicating true (“11”) according to the values of the flag signals FLG0 to FLG6 (FIG. 12 (h)). The control circuit CNTL of the sequencer 14 sets the selection signal BS1 to “7” in response to the flag signal FLG7 indicating true (FIG. 12 (j)).

  In the fourth clock cycle, the selector SSEL1 of the sequencer 14 outputs the address values ADa7 and ADb7 held by the register REG7 to the configuration memories 16A and 16B according to the selection signal BS1 (FIG. 12 (k)). The control circuit CNTL outputs a control signal CNTa indicating a read request to the configuration memory 16A and a control signal CNTb indicating a read request to the configuration memory 16B (FIGS. 12L and 12M).

  In the fifth clock cycle, the configuration memory 16A outputs the configuration data CFG indicating the context CTX4 from the storage area indicated by the address value ADa4 (FIG. 12 (n)). The configuration memory 16B outputs the register data REGD from the storage area indicated by the address value ADb4 (FIG. 12 (o)).

  Then, in the sixth clock cycle, the arithmetic unit array 18 takes in the configuration data CFG in accordance with the high level of the trigger signal TRG, and constructs a circuit that executes the context CTX4 (FIG. 12 (q)). The arithmetic unit array 18 operates the circuit constructed in the sixth clock cycle, and executes the context CTX4 (processing E) from the seventh clock cycle.

  FIG. 13 shows another example of processing to be executed by the arithmetic unit array 18 shown in FIG. Detailed description of the same processing as in FIG. 8 is omitted.

  In this example, the arithmetic unit array 18 executes a process of context CTXJ (condition determination), and executes a process corresponding to an if statement such as C language shown in FIG. For example, when the data x is larger than “100” and the product of the data y and z is smaller than “1000”, the arithmetic unit array 18 executes the context CTX0 (processing A). When the data x is larger than “100” and the product of the data y and z is “1000” or more, the arithmetic unit array 18 executes the context CTX1 (Process B). When the data x is “100” or less, the arithmetic unit array 18 executes the context CTX2 (processing C).

  The arithmetic unit array 18 outputs the determination result of the data x, y, z to the sequencer 14 as flag signals FLG0, FLG1, FLG7. In this example, the condition determination is executed twice, and since there are three branch destinations, three flag signals FLG0, FLG1, and FLG7 are used. Flag signals FLG2-FLG6 are set to a level indicating invalidity. The logic for generating the flag signals FLG0, FLG1, and FLG7 will be described with reference to FIG.

  The sequencer 14 reads from the configuration memory 16A the configuration data CFG for constructing a circuit that the arithmetic unit array 18 performs next processing based on the values of the flag signals FLG0, FLG1, and FLG7. The arithmetic unit array 18 uses the configuration data CFG read from the configuration memory 16A in accordance with the execution result of the context CTXJ to construct a circuit (any one of the contexts CTX0 to CTX2) to be executed next.

  FIG. 14 shows an example of the circuit configuration of the arithmetic unit array 18 that executes the context CTXJ shown in FIG. Detailed description of the same processing as in FIG. 9 is omitted.

  FIG. 14 shows a state in which the arithmetic unit array 18 is constructed in a circuit (context CTXJ) that executes condition determination based on reception of the configuration data CFG, as in FIG.

  For example, the network circuit NWD connects the data terminal RDT of the shared memory 12 that outputs the data “x” to the data input terminal DI0 of the arithmetic unit OP0 based on the configuration data CFG, and the data “y”, “z” The data terminal RDT of the shared memory 12 that outputs "" is connected to the data input terminals DI0 and DI1 of the arithmetic unit OP1. The arithmetic unit OP0 is constructed as a circuit for determining whether or not the data “x” received at the data input terminal DI0 is larger than “100” based on the configuration data CFG. The arithmetic unit OP0 outputs “11” indicating true from the flag output terminal FO when the data “x” is larger than “100”, and the flag output terminal when the data “x” is “100” or less. “10” indicating false is output from the FO.

  The computing unit OP1 obtains the product of the data “y” received at the data input terminal DI0 and the data “z” received at the data input terminal DI1 based on the configuration data CFG, and the obtained product is obtained as the data output terminal DO. It is constructed in the circuit that outputs from. The computing unit OP2 is constructed in a circuit that determines whether the product of the data “y” and “z” output from the computing unit OP1 is smaller than “1000” based on the configuration data CFG. When the product of the data “y” and “z” is smaller than “1000”, the arithmetic unit OP2 outputs “11” indicating true from the flag output terminal FO, and the product of the data “y” and “z” is “ In the case of 1000 or more, “10” indicating false is output from the flag output terminal FO.

  The flag calculator FOP0 is constructed as a circuit that determines the logical product of the flag signals output from the flag output terminals FO of the calculators OP0 and OP2 based on the configuration data CFG. The flag calculator FOP0 outputs a flag signal indicating true from the flag output terminal FO when true is output from the flag output terminals FO of the calculators OP0 and OP2. The flag calculator FOP0 outputs a flag signal indicating false when false is output from at least one of the flag output terminals FO of the calculators OP0 and OP2.

  The flag calculator FOP1 receives a flag signal output from the flag output terminal FO of the calculator OP0 at the flag input terminal FI0, and receives a flag signal output from the flag output terminal FO of the calculator OP2 at the flag input terminal FI1. The flag calculator FOP1 is a signal obtained by inverting the flag signal output from the flag output terminal FO of the calculator OP0 and the flag signal output from the flag output terminal FO of the calculator OP2 based on the configuration data CFG. It is constructed in a circuit that determines the logical product of. In FIG. 14, the symbol “/ FI1” shown in the flag calculator FOP1 indicates that the logic of the flag signal received at the flag input terminal FI1 is inverted.

  The flag calculator FOP1 outputs a flag signal indicating true from the flag output terminal FO when true is output from the flag output terminal FO of the calculator OP0 and false is output from the flag output terminal FO of the calculator OP2. The flag calculator FOP1 outputs a flag signal indicating false from the flag output terminal FO when false is output from the flag output terminal FO of the calculator OP0 or when true is output from the flag output terminal FO of the calculator OP2. .

  As shown in FIG. 5, since the flag calculator FOP1 includes the polarity inverters PRVS0 and PRVS1, a value obtained by inverting the flag signal FLG output from the calculator OP2 without using another flag calculator FOP. The condition determination can be executed using. That is, the number of flag calculators FOP used for condition determination can be reduced as compared with the case where a flag calculator without the polarity inverters PRVS0 and PRVS1 is used. When the number of flag calculators FOP used for condition determination decreases, the number of flag calculators FOP mounted on the calculator array 18 can be reduced, and the circuit scale of the calculator array 18 can be reduced.

  When the processing corresponding to the “if” statement shown in FIG. 13 is executed, the plurality of flag calculators FOP0 and FOP1 do not output the flag signal FO indicating true redundantly.

  The network circuit NWF connects the flag output terminals FO of the flag calculators FOP0 and FOP1 to the flag terminals FLG0 and FLG1 of the sequencer 14 based on the configuration data CFG. The network circuit NWF connects the flag output terminal FO of the arithmetic unit OP0 to the flag input terminals FI0 of the flag arithmetic units FOP0 and FOP1, and the flag output terminal FO of the arithmetic unit OP2 to the flag input terminals FI1 of the flag arithmetic units FOP0 and FOP1. Connecting.

  The network circuit NWF connects the flag output terminals FO of the flag calculators FOP0 and FOP1 to the flag terminals FLG0 and FLG1 of the sequencer 14 of the flag calculator DFOP. The network circuit NWF outputs a value (“00”) indicating that the flag signal is invalid to the vacant flag terminals FLG3 to FLG6 of the sequencer 14, respectively.

  Based on the configuration data CFG, the flag calculator DFOP enables the flag input terminals FI1 [1: 0] -FI0 [1: 0] shown in FIG. 6, and the flag input terminals FI7 [1: 0] -FI2 Disable [1: 0]. The flag calculator DFOP operates in the default mode based on the configuration data CFG, and outputs the outputs of the OR circuit OR and the NOR circuit NOR shown in FIG. 6 as the flag signal FLG7. Flag operation unit DFOP outputs flag signal FLG7 indicating true when flag signals FLG1-FLG0 received at flag input terminals FI1 [0] -FI0 [0] all indicate false.

  The sequencer 14 operates in the same manner as described with reference to FIG. That is, the sequencer 14 reads new configuration data CFG from the configuration memory 16A based on the logic of the flag signals FLG0 to FLG7, and the arithmetic unit array 18 is a circuit that executes the next processing (shown in FIG. 13). Any of the contexts CTX0 to CTX2) is constructed.

  FIG. 15 is a diagram showing the relationship between the values of data x, y, z, the flag signal FLG, and the data processing to be executed in the circuit configuration shown in FIG. When the result of the condition determination is true, the corresponding flag signals FLG0 and FLG1 are set to true (“11”) as shown by shading. Then, similarly to FIG. 10, the configuration data CFG corresponding to the flag signal FLG indicating true is transferred to the arithmetic unit array 18, and one of the contexts CTX0 and CTX1 is executed.

  When the result of the condition determination is false, the flag signal FLG7 is set to true, the configuration data CFG corresponding to the flag signal FLG7 indicating true is transferred to the arithmetic unit array 18, and the context CTX2 is executed.

  FIG. 16 shows an example of the operation of the semiconductor integrated circuit SEM2 that executes the processing shown in FIG. Detailed description of the same operations as those in FIG. 11 is omitted. In this example, the circuit of the context CTX1 is constructed in the arithmetic unit array 18 based on the result of the condition determination of the context CTXJ shown in FIG. The circuit corresponding to the context CTXJ is transferred to the arithmetic unit array 18 before the first clock cycle.

  In the second clock cycle, the data x (= 120), y (= 20), z (= 60) is read from the shared memory 12, and the read data x, y, z passes through the network circuit NWD. To the arithmetic units OP0 and OP1 (FIG. 16A).

  In the third clock cycle, the arithmetic unit OP0 executes the condition determination shown in FIG. 9 and outputs “11” indicating true (FIG. 16B). The calculator OP1 executes the calculation shown in FIG. 9 and outputs the execution result (“1200”) (FIG. 16C).

  In the fourth clock cycle, the arithmetic unit OP2 executes the condition determination shown in FIG. 9 and outputs “10” indicating false (FIG. 16D). The flag calculators FOP0 and FOP1 execute the condition determination shown in FIG. 9, and respectively output a flag signal FLG0 indicating false (“10”) and a flag signal FLG1 indicating true (“11”) (FIG. 9). 16 (e), (f)). The flag calculator DFOP outputs a flag signal FLG7 indicating false (“10”) according to the values of the flag signals FLG0 to FLG6 (FIG. 16 (g)). The control circuit CNTL of the sequencer 14 sets the selection signal BS1 to “1” in response to the flag signal FLG1 indicating true (FIG. 16 (h)).

  In the fifth clock cycle, the selector SSEL1 of the sequencer 14 outputs the address values ADa1 and ADb1 held by the register REG1 to the configuration memories 16A and 16B according to the selection signal BS1 (FIG. 16 (i)). As in FIG. 11, configuration data CFG indicating the context CTX1 is read from the configuration memory 16A (FIG. 16 (j)). The arithmetic unit array 18 constructs a circuit that executes the context CTX1 in the ninth clock cycle based on the configuration data CFG, and the context CTX1 (processing B) is executed from the eighth clock cycle (FIG. 16). (K)).

  FIG. 17 shows still another example of processing to be executed by the arithmetic unit array 18 shown in FIG. Detailed description of the same processing as in FIGS. 8 and 13 is omitted.

  In this example, the arithmetic unit array 18 executes a process of context CTXJ (condition determination), and executes a process corresponding to an if statement such as C language shown in FIG. For example, when the data x is larger than “100” and the product of the data y and z is smaller than “1000”, the arithmetic unit array 18 executes the context CTX0 (processing A). When the data x is larger than “100” and the product of the data y and z is “1000” or more, the arithmetic unit array 18 executes the context CTX1 (Process B).

  When the data x is “100” or less and the data y is smaller than “200”, the arithmetic unit array 18 executes the context CTX2 (processing C). When the data x is “100” or less and the data y is “200” or more, the arithmetic unit array 18 executes the context CTX3 (Process D).

  The arithmetic unit array 18 outputs the determination result of the data x, y, z to the sequencer 14 as flag signals FLG0, FLG1, FLG2, FLG7. In this example, the condition determination is executed three times and there are four branch destinations, so four flag signals FLG0, FLG1, FLG2, and FLG7 are used. Flag signals FLG3-FLG6 are set to a level indicating invalidity. The logic for generating the flag signals FLG0, FLG1, FLG2, and FLG7 will be described with reference to FIG.

  FIG. 18 shows an example of the circuit configuration of the arithmetic unit array 18 that executes the context CTXJ shown in FIG. Detailed description of the same processing as in FIGS. 9 and 14 is omitted.

  FIG. 18 shows a state in which the arithmetic unit array 18 is constructed in a circuit (context CTXJ) that executes condition determination based on the reception of the configuration data CFG, as in FIG. FIG. 18 shows that the operation unit OP3 that determines the value of the data y and outputs the flag signal FLG2 is added, and the flag signal FLG2 output from the operation unit OP3 is connected to the flag input terminal FI2 of the flag operation unit DFOP. This is the same as FIG.

  The arithmetic unit OP3 is constructed in a circuit that determines whether or not the data “y” is smaller than “200” based on the configuration data CFG. The arithmetic unit OP3 outputs “11” indicating true from the flag output terminal FO when the data “y” is smaller than “200”, and false from the flag output terminal FO when the data “y” is “200” or more. “10” is output.

  Based on the configuration data CFG, the flag calculator DFOP enables the flag input terminals FI2 [1: 0] -FI0 [1: 0] shown in FIG. 6, and the flag input terminals FI7 [1: 0] -FI3. Disable [1: 0]. The flag calculator DFOP operates in the default mode based on the configuration data CFG, and outputs the outputs of the OR circuit OR and the NOR circuit NOR shown in FIG. 6 as the flag signal FLG7. Flag operation unit DFOP outputs flag signal FLG7 indicating true when flag signals FLG2-FLG0 received at flag input terminals FI2 [0] -FI0 [0] all indicate false.

  FIG. 19 is a diagram showing the relationship between the values of data x, y, and z, flag signal FLG, and data processing to be executed in the circuit configuration shown in FIG. When the result of the condition determination is true, the corresponding flag signals FLG0, FLG1, and FLG2 are set to true (“11”) as indicated by shading. As in FIG. 15, the configuration data CFG corresponding to the flag signal FLG indicating true is transferred to the arithmetic unit array 18 and any one of the contexts CTX0, CTX1, and CTX2 is executed.

  When the data x is larger than “100”, the product of data y and z is smaller than “1000”, and the data y is smaller than “200”, the two flag signals FLG0 and FLG2 are set to true (“11”). Is done. When the data x is larger than “100”, the product of the data y and z is “1000” or more and the data y is smaller than “200”, the two flag signals FLG1 and FLG2 are true (“11”). Is set. When a plurality of flag signals FLG0 and FLG2 (or FLG1 and FLG2) indicating true are generated, the control circuit CNTL sets the flag signal FLG0 (or FLG1) having a higher priority than the flag signal FLG2 as shown in FIG. The corresponding selection signal BS1 is output.

  When the result of the condition determination is false, the flag signal FLG7 is set to true, the configuration data CFG corresponding to the flag signal FLG7 indicating true is transferred to the arithmetic unit array 18, and the context CTX3 is executed.

  FIG. 20 shows an example of the operation of the semiconductor integrated circuit SEM2 that executes the processing shown in FIG. Detailed descriptions of operations similar to those in FIGS. 11 and 16 are omitted.

  In this example, since the value of the data x is larger than “100” and the product of the data y and z is “1000” or more, the flag signal FLG1 is set to true (“11”) as in FIG. (FIG. 20A). Further, since the value of the data y is smaller than “200”, the flag signal FLG2 is set to true (“11”) (FIG. 20B).

  When the control circuit CNTL receives a plurality of flag signals FLG indicating true, the control circuit CNTL operates in accordance with a flag signal FLG having a high priority (ie, a low number). In this example, the control circuit CNTL ignores the flag signal FLG2 indicating true, and sets the selection signal BS1 to “1” based on the flag signal FLG1 whose number is smaller than the flag signal FLG2. The semiconductor integrated circuit SEM2 operates in the same manner as in FIG. 16 after the sixth clock cycle.

  By setting the priority to the flag signals FLG0 to FLG7, the circuit of the arithmetic unit array 18 is reconfigured based on the correct configuration data CFG even when a plurality of flag signals FLG0 to FLG7 indicating true are output. be able to. In other words, even when a plurality of flag signals FLG0 to FLG7 indicating true are output, the circuit of the arithmetic unit array 18 is not reconfigured by erroneous configuration data CFG, and the arithmetic unit array 18 Does not malfunction.

  FIG. 21 shows another example of the operation of the semiconductor integrated circuit SEM2 shown in FIG. The same operations as those in FIG. 11 are denoted by the same reference numerals as those in FIG. In this example, the context CTX3 is executed based on the result of the condition determination by the context CTX0, and the context CTX6 is executed based on the result of the condition determination by the context CTX3. After the context CTX6, the branch control flag BRA is reset to the low level, the address ADa is sequentially incremented regardless of the condition determination, and the configuration data CFG is read from the configuration memory 16A.

  First, in the first to fifth clock cycles, as in FIG. 11, the sequencer 14 selects the addresses ADa3 and ADb3 stored in the register REG2 based on the flag signal FLG2 indicating true (FIG. 21 (a)). ), (B)). Then, in the sixth clock cycle, the circuit of the arithmetic unit array 18 is updated with the configuration data CFG indicating the context CTX3 read from the configuration memory 16A (FIG. 21 (c)).

  Note that the address ADb1 stored in the registers REG0, REG3, REG7 and the like is commonly used when the configuration data CFG stored in the configuration memory 16A is read in the order of the address ADa. In the storage area indicated by the address ADb1 of the configuration memory 16B, a branch control flag BRA indicating a reset state and dummy addresses ADa and ADb are stored.

  In the seventh to ninth clock cycles, the sequencer 14 selects the addresses ADa6 and ADb1 stored in the register REG0 based on the flag signal FLG0 indicating true (FIGS. 21D and 21E). Here, since the branch control flag BRA read from the configuration memory 16B is high until the eighth clock cycle, the selector SSEL2 shown in FIG. 3 selects the output of the selector SSEL1. That is, the sequencer 14 outputs the addresses ADa and ADb stored in the register REG selected according to the flag signal FLG.

  In this example, the branch control flag BRA included in the register data REGD read from the configuration memory 16B in the ninth clock cycle is in a reset state (low level) (FIG. 21 (f)). The sequencer 14 receives the value of the branch control flag BRA in synchronization with the trigger signal TRG, and sets the selection signal BS1 to “0” regardless of the value of the flag signal FLG (FIG. 21 (g)).

  The incrementer INC shown in FIG. 3 takes in the address ADa (ADa6 in this example) stored in the register REG0 in accordance with the change of the branch control flag BRA from the high level to the low level, and the address every time the context CTX is executed. ADa is incremented (FIGS. 21 (h) and (i)). For example, the incrementer INC increases the address ADa in synchronization with the high level of the end signal END.

  While the branch control flag BRA is at the low level, the selector SSEL2 outputs the address ADa generated by the incrementer INC to the configuration memory 16A instead of the address ADa stored in the registers REG0 to REG7. Since the selection signal BS1 is set to “0” while the branch control flag BRA is at the low level, the sequencer 14 outputs the address ADb stored in the register REG0 to the configuration memory 16B (FIG. 21 (j)).

  When the branch control flag BRA indicates a reset state, the operation of the selector SSEL1 is stopped, and the address ADa is sequentially generated by the incrementer INC. As a result, the possibility that the logical level of each bit of the address ADa changes can be reduced, and power supply noise generated with the change of the address ADa can be suppressed.

  When the configuration data CFG is read from the configuration memory 16A in the order of the address ADa, the result of the condition determination is not used. In this case, the information stored in the configuration memory 16B can be commonly used by a plurality of contexts CTX. As a result, the range of the address ADb in the configuration memory 16B can be made smaller than the range of the address ADa in the configuration memory 16A. In other words, when the context CTX to be executed next can be determined without using the result of the condition determination, the capacity of the memory mounted in the semiconductor integrated circuit SEM2 shown in FIG. This can be reduced compared to the case where it is realized with

  FIG. 22 shows another example of the semiconductor integrated circuit SEM. Elements that are the same as or similar to those shown in FIG. 3 are given the same reference numerals, and detailed descriptions thereof are omitted. The semiconductor integrated circuit SEM3 includes a shared memory 12, a sequencer 14A, a configuration memory 16, and an arithmetic unit array 18A. The shared memory 12 is the same as or similar to that shown in FIG. The semiconductor integrated circuit SEM3 is connected to the system bus SBUS connected to the MCU 20, the memory 30, and the peripheral circuit 40, as in FIG. That is, the semiconductor integrated circuit SEM3, the MCU 20, the memory 30, the peripheral circuit 40, and the system bus SBUS are mounted on the system SYS3.

  The arithmetic unit array 18A includes a network circuit NWD, a plurality of arithmetic units OP, a plurality of flag arithmetic units FOP, and a network circuit NWF2. The arithmetic unit array 18A does not have the flag arithmetic unit DFOP of the arithmetic unit array 18 shown in FIG. The network circuit NWF2 of the arithmetic unit array 18A generates one flag signal FLG (2 bits).

  For example, like the configuration memory 16A shown in FIG. 3, the configuration memory 16 has a 5-bit address terminal AD, a data terminal RDT of several hundred bits, and data of several hundred bits output from the data terminal RDT. And a storage area for holding Configuration data CFG, which is data of several hundred bits output from the data terminal RDT, includes information indicating the specification of the context CTX and information of the register data REGD shown in FIG.

  The sequencer 14A includes a control circuit CNTL2, a register REG (REG0, REG1), and a selector SSEL3. The control circuit CNTL2 outputs the trigger signal TRG and the stall signal STL to the arithmetic unit array 18, and receives the end signal END and one flag signal FLG from the arithmetic unit array 18. The flag signal FLG indicates the result (true or false) of the logical operation by the arithmetic units in the arithmetic unit array 18. The control circuit CNTL2 outputs a control signal CNT to the configuration memory 16 based on the flag signal FLG and the end signal END, and outputs a selection signal BS2 to the selector SSEL3. The control circuit CNTL2 generates the selection signal BS2 according to whether one flag signal FLG is true or false.

  Each of the registers REG0 and REG1 holds register data REGD read from the configuration memory 16 in response to the control signal CNT from the control circuit CNTL2 and the address signal AD from the selector SSEL3. Each of the registers REG0 to REG1 outputs the held register data REGD to the selector SSEL3. The value of the register data REGD held in each of the registers REG0 to REG1 includes the value of the address AD used for accessing the configuration memory 16.

  The selector SSEL3 selects the register REG0 according to the value of the selection signal BS2 corresponding to the true flag signal FLG, and selects the register REG1 according to the selection signal BS2 corresponding to the false flag signal FLG. Then, the selector SSEL2 outputs the address AD stored in the selected register REG to the configuration memory 16.

  FIG. 23 shows an example of the arithmetic unit array 18A shown in FIG. The arithmetic unit array 18A includes a network circuit NWD similar to that in FIG. 4, n (n is a positive integer) arithmetic units OP, m (m is a positive integer) flag arithmetic unit FOP, a counter ACOUNT, and a memory control circuit. It has MCNT and network circuit NWF2. The network circuit NWF2 outputs a flag output from the flag output terminal FO of either the arithmetic unit OP or the flag arithmetic unit FOP as the flag signal FLG based on the configuration data CFG. That is, the arithmetic unit array 18A is the same as the arithmetic unit array 18 shown in FIG. 4 except that it does not have the flag arithmetic unit DFOP shown in FIG. 4 and outputs one flag signal FLG.

  FIG. 24 shows an example of processing executed by the arithmetic unit array 18A shown in FIG. The processing executed by the arithmetic unit array 18A is the same as the processing shown in FIG. That is, the arithmetic unit array 18A executes one of the process A, the process B, the process C, the process D, and the process E according to the value of the data “x” received from the shared memory 12.

  However, the arithmetic unit array 18A sequentially updates the circuits in the arithmetic unit array 18A based on whether one flag signal FLG is true or false, and the processing to be executed is processing A, processing B, processing C, processing D, processing E is judged one by one. For this reason, the arithmetic unit array 18A executes processing of contexts CTXJ1, CTXJ2, CTXJ3, and CTXJ4 (condition determination) more than in FIG.

  For example, when the value of the data “x” is “2” and the process C is executed, the circuit in the arithmetic unit array 18A is rewritten twice for condition determination. When the value of the data “x” does not correspond to any of “0”, “1”, “2”, and “3” and the process E is executed, the circuit in the arithmetic unit array 18A It is rewritten four times for judgment.

  FIG. 25 shows an example of the operation of the semiconductor integrated circuit SEM3 that executes the processing shown in FIG. Detailed description of the same operations as those in FIG. 11 is omitted. The sequencer 14A receives one flag signal FLG from the arithmetic unit array 18A, and executes one condition determination at a time. Therefore, in the second, sixth, and tenth clock cycles, data x (= 2) is read from the data terminal RDT of the shared memory 12 (FIGS. 25A, 25B, and 25C).

  The arithmetic unit array 18A determines that the data x is not “0” in the third clock cycle, and determines that the data x is not “1” in the seventh clock cycle (FIG. 25 (d), (E)). The arithmetic unit array 18A determines that the data x is “2” in the eleventh clock cycle, and executes the context CTX2 (processing C) from the fifteenth clock cycle (FIG. 25 (f), (g )).

  In FIG. 25, the timing at which execution of the context CTX2 is started is eight clock cycles later than the timing at which execution of the context CTX2 is started in FIG. That is, the semiconductor integrated circuit SEM2 shown in FIG. 3 can start the context CTX2 earlier by 8 clock cycles than the semiconductor integrated circuit SEM3 shown in FIG.

  FIG. 26 shows another example of processing to be executed by the arithmetic unit array 18A shown in FIG. The processing executed by the arithmetic unit array 18A is the same as the processing shown in FIG. That is, the arithmetic unit array 18A executes a process corresponding to an if statement such as C language similar to FIG.

  However, the arithmetic unit array 18A sequentially updates the circuits in the arithmetic unit array 18A based on whether one flag signal FLG is true or false, and whether the processing to be executed is processing A, processing B, or processing C. Are determined one by one. For this reason, the arithmetic unit array 18A executes processing of contexts CTXJ1 and CTXJ2 (condition determination) more than in FIG.

  FIG. 27 shows an example of the operation of the semiconductor integrated circuit SEM3 that executes the processing shown in FIG. Detailed descriptions of operations similar to those in FIGS. 11 and 25 are omitted. The sequencer 14A receives one flag signal FLG from the arithmetic unit array 18A, and executes one condition determination at a time. Therefore, in the second and seventh clock cycles, the data x, y, z are read from the data terminal RDT of the shared memory 12 (FIGS. 27A and 27B).

  The arithmetic unit array 18A detects that the determination by the context CTXJ1 is false ("10") in the third clock cycle, and the determination by the context CTXJ2 is true ("11") in the eighth clock cycle. It is detected (FIG. 27 (c), (d)). Then, the arithmetic unit array 18A executes the context CTX1 (processing B) from the 12th clock cycle (FIG. 27E). In FIG. 27, the timing at which the execution of the context CTX1 is started is four clock cycles later than the timing at which the execution of the context CTX1 is started in FIG. That is, the semiconductor integrated circuit SEM2 illustrated in FIG. 3 can start the context CTX1 four clock cycles earlier than the semiconductor integrated circuit SEM3 illustrated in FIG.

  As described above, in the embodiment shown in FIGS. 3 to 21 as well as the embodiment shown in FIGS. 1 and 2, the processing executed by the arithmetic unit array 18 can be started quickly according to the result of the condition determination. The performance of the integrated circuit SEM2 can be improved.

  Further, the configuration data CFG and the register data REGD for switching the circuit configuration of the arithmetic unit array 18 are stored in the configuration memories 16A and 16B independent of each other. Thereby, the capacity of the memory mounted on the semiconductor integrated circuit SEM2 can be reduced as compared with the conventional one, and the circuit scale of the semiconductor integrated circuit SEM2 can be reduced as compared with the conventional one.

  By setting the priority to the flag signals FLG0 to FLG7, the circuit of the arithmetic unit array 18 is reconfigured based on the correct configuration data CFG even when a plurality of flag signals FLG0 to FLG7 indicating true are output. be able to. In other words, even when a plurality of flag signals FLG0 to FLG7 indicating true are output, the circuit of the arithmetic unit array 18 is not reconfigured by erroneous configuration data CFG, and the arithmetic unit array 18 Does not malfunction.

  The network circuit NWF connects the outputs of the arithmetic units OP and FOP to any of the flag terminals FLG0 to FLG7 according to the priority, and outputs the flag signal FLG to which the priority is assigned. The degree determination process can be omitted.

  The flag calculator DFOP outputs a flag signal FLG7 indicating true when the flag signals FLG0 to FLG6 indicate false. As a result, the logic of the flag signal FLG for selecting a process when none of the determination conditions is met can be generated more easily than when the logic is generated using the calculator OP or the flag calculator FOP.

  When the branch control flag BRA indicates a reset state, the operation of the selector SSEL1 is stopped, and the address ADa is sequentially generated by the incrementer INC. As a result, the possibility that the logic level of each bit of the address ADa changes can be reduced, and the power supply noise generated with the change of the address ADa can be suppressed.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  2 ... arithmetic unit; 4 ... control unit; 12 ... shared memory; 14, 14A ... sequencer; 16A, 16B ... configuration memory; 18, 18A ... arithmetic unit array; 20 ... MCU; ACOUNT ... Counter; ADa, ADb ... Address signal; BRA ... Branch control flag; CFG ... Configuration data; CNTL ... Control circuit; DFOP ... Flag calculator; END ... End signal; ENDS ... End flag; FLG ... Flag signal; ... Flag operation unit; FOP ... Flag operation unit; INC ... Incrementor; MCNT ... Memory control circuit; NWD, MWF ... Network circuit; OP ... Operation unit; PRVS0, PRVS1 ... Polarity inverter; REG ... Register; REGD ... Register data ; SBUS ... System bus; SEM1, SE 2, SEM3 ... semiconductor integrated circuit; SSEL1, SSEL2, SSEL3 ... selector; STL ... stall signal; TRG ... trigger signal

Claims (6)

A computing unit including a plurality of reconfigurable computing units;
In response to a plurality of flag signals indicating the results of logical operations by a plurality of the arithmetic units, one of a plurality of configuration data indicating a circuit configuration of the arithmetic unit is selected, and the selected configuration data is selected from the arithmetic unit. a control unit for outputting a,
A first storage unit including a plurality of storage areas for holding the plurality of configuration data and accessed by a first address;
A plurality of storage areas for storing a plurality of sets of the first address and the second address, and a second storage unit accessed by the second address ,
The control unit selects one of a plurality of sets of the first address and the second address output from the second storage unit according to the flag signal, and selects the selected first address the semiconductor integrated circuit is output to the first storage unit, and wherein the Rukoto comprises a first selector for outputting the second address selected in the second storage unit. The said calculating part is provided with the flag control circuit which outputs the flag signal which shows true to the said control part, when all of the said several flag signals output from the said calculator show false. 2. The semiconductor integrated circuit according to 1. The control unit selects one of the plurality of sets of the first address and the second address output from the second storage unit in response to the flag signal indicating true, and indicates true When receiving a plurality of flag signals, a set of the first address and the second address corresponding to one of the flag signals having a higher priority than the other flag signals among the plurality of flag signals indicating true The semiconductor integrated circuit according to claim 1 , wherein: is selected. The semiconductor integrated circuit according to claim 3 , wherein the arithmetic unit includes a connection unit that connects an output of the arithmetic unit and a flag terminal that outputs the flag signal according to the priority. Each of the storage areas of the second storage unit includes an area for storing a valid flag for validating an operation of selecting the configuration data according to the flag signal,
The controller is
An update circuit for sequentially updating one of the first addresses output from the second storage unit when the valid flag indicates invalid;
When the valid flag indicates valid, the first address output from the first selector is selected, and when the valid flag indicates invalid, the first address output from the update circuit is selected. the semiconductor integrated circuit according to any one of claims 1 to 4, characterized in that it comprises a second selector for outputting a first address selected in the first storage unit. An operation method of a semiconductor integrated circuit including an arithmetic unit including a plurality of reconfigurable arithmetic units, a first storage unit, and a second storage unit ,
In response to a plurality of flag signals each indicating a result of a logical operation by a plurality of the arithmetic units, one of a plurality of configuration data indicating a circuit configuration of the arithmetic unit is selected.
Outputting the selected configuration data to the computing unit ;
Accessing the first storage unit by a first address, wherein the first storage unit includes a plurality of storage areas for holding the plurality of configuration data;
Accessing the second storage unit by a second address, wherein the second storage unit includes a plurality of storage areas for storing a plurality of sets of the first address and the second address;
One of a plurality of sets of the first address and the second address output from the second storage unit is selected according to the flag signal, and the selected first address is stored in the first storage unit. outputs, operation method of a semiconductor integrated circuit, characterized in that it comprises and outputting the second selected address in the second storage unit.

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