JP6149003B2 - SIMD type processor - Google Patents

Description

  The present invention relates to a SIMD type processor applied to, for example, image data processing.

  A SIMD (Single Instruction Multiple Data) processor is a processor that processes a plurality of data in parallel with one instruction. The SIMD type processor includes a plurality of processor elements. Each processor element includes a plurality of registers and an arithmetic unit, and processes one data.

  One application of the SIMD type processor is image processing. This is because the image data is composed of a plurality of pixel data, and the image processing performs the same processing (for example, filter processing) on each pixel data.

  One data is processed in each processor element, but a technique for improving this and processing a plurality of data at one time in each processor element has been proposed (for example, see Patent Document 1).

JP 2006-260479 A (summary)

  The problem of wiring congestion inevitably occurs in the processor, and the SIMD type processor is no exception.

  An object of this invention is to provide the SIMD type processor which can reduce wiring congestion.

  A SIMD type processor according to the present invention that achieves the above object is a SIMD type processor including a plurality of processor elements, each of the plurality of processor elements including a plurality of registers and N (N is two or more). (Integer) arithmetic circuit, N number of arithmetic circuits corresponding to N arithmetic circuits, N input buses for transmitting data to the corresponding arithmetic circuit, and the input bus and the output unit of the register are connected A register bus that is a bus, and the SIMD type processor pre-allocates one or more arithmetic circuits to each of the plurality of registers included in each of the plurality of processor elements, and stores them in the registers Data is allocated in advance using the register bus and the input bus. A register control unit configured to execute control to be transmitted to one or more of the arithmetic circuits for each of the plurality of registers included in each of the plurality of processor elements; With respect to the registers in which the number of the arithmetic circuits is less than N, the register bus is provided for the input bus corresponding to the arithmetic circuit to which data is transmitted one-to-one, and the arithmetic in which data is not transmitted The register bus is not provided for the input bus corresponding one-to-one with the circuit.

  In the SIMD type processor according to the present invention, as an arithmetic circuit to which data is transmitted, a register in which the number of allocated arithmetic circuits is less than N is assigned to an input bus corresponding to the arithmetic circuit to which data is transmitted one-to-one. On the other hand, a register bus is provided, and no register bus is provided for an arithmetic bus that does not transmit data and an input bus corresponding to one to one. That is, for registers other than the register to which data is transmitted to all of the N arithmetic circuits belonging to the processor element, there is no register bus connected to the arithmetic circuit to which data is not transmitted and the one-to-one input bus. As a result, the number of register buses included in each of the plurality of processor elements can be reduced, and wiring congestion can be reduced.

  In the above configuration, the plurality of processor elements are arranged side by side in the main scanning direction, and in each of the plurality of processor elements, the plurality of registers are arranged in the sub scanning direction, and each of the plurality of processor elements is , One-to-one corresponding to the N arithmetic circuits, including N multiplexers that output to the corresponding arithmetic circuit, and configured from the plurality of registers that are continuous in the sub-scanning direction When each of the plurality of processor elements is a register group, N register groups having different combinations of registers correspond to the N input buses on a one-to-one basis, and There is a one-to-one correspondence with the N multiplexers, and the N arithmetic circuits The data output from the first register group, which is the register group corresponding to the multiplexer, is transmitted to the input section of each multiplexer. Included in the processor element located on one side of the processor element including the input bus and the multiplexer and on the other side of the processor element, and configured by the registers in the same row as the first register group The input bus for transmitting data output from the register group is connected.

  In this configuration, the input section of each multiplexer includes an input bus for transmitting data output from a register group (first register group) corresponding to the multiplexer in a one-to-one relationship, and the multiplexer. An input bus that transmits data output from a register group that is included in the processor elements located on one side of the processor element and on the other side of the processor element and that is composed of registers in the same row as the first register group is connected. The Therefore, the pixel data of the pixels located around the pixel of interest can be sent to one arithmetic circuit, so that filter processing can be realized.

  According to the present invention, wiring congestion can be reduced.

1 is a schematic diagram illustrating an outline of an internal structure of an image forming apparatus including a SIMD type processor according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of the image forming apparatus illustrated in FIG. 1. It is a block diagram which shows the structure of the SIMD type processor which concerns on this embodiment. It is a schematic diagram which shows a part of image by which a 3 * 3 filter process is performed by the SIMD type | mold processor which concerns on this embodiment. FIG. 5 is a schematic diagram illustrating a state in which pixel values of an (N−1) th line to an (N + 2) th line illustrated in FIG. 4 are set in each register of the SIMD type processor illustrated in FIG. 3. FIG. 5 is a schematic diagram illustrating a state in which pixel values of an (N + 1) th line to an (N + 4) th line illustrated in FIG. 4 are set in each register of the SIMD type processor illustrated in FIG. 3. In this embodiment, it is a schematic diagram which shows a processor element in case the number M of registers is 32. FIG. In this embodiment, it is a schematic diagram which shows a processor element in case the number N of arithmetic circuits is 3. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing an outline of an internal structure of an image forming apparatus 1 including a SIMD type processor 3 (FIG. 3) according to an embodiment of the present invention. The image forming apparatus 1 can be applied to, for example, a digital multifunction machine having functions of a copy, a printer, a scanner, and a facsimile. The image forming apparatus 1 is disposed on the apparatus main body 100, an original reading unit 200 disposed on the apparatus main body 100, an original feeding unit 300 disposed on the original reading unit 200, and an upper front surface of the apparatus main body 100. An operation unit 400 is provided.

  The document feeding unit 300 functions as an automatic document feeding device, and can feed a plurality of documents placed on the document placing unit 301 so that the document reading unit 200 can read them continuously.

  The document reading unit 200 includes a carriage 201 on which an exposure lamp or the like is mounted, a document table 203 made of a transparent member such as glass, a CCD (Charge Coupled Device) sensor (not shown), and a document reading slit 205. When reading a document placed on the document table 203, the document is read by the CCD sensor while moving the carriage 201 in the longitudinal direction of the document table 203. On the other hand, when reading a document fed from the document feeding unit 300, the carriage 201 is moved to a position facing the document reading slit 205, and the document fed from the document feeding unit 300 is scanned. Reading is performed by the CCD sensor through the reading slit 205. The CCD sensor outputs the read original as image data.

  The apparatus main body 100 includes a sheet storage unit 101, an image forming unit 103, and a fixing unit 105. The sheet storage unit 101 is disposed at the lowermost part of the apparatus main body 100 and includes a sheet tray 107 that can store a bundle of sheets. In the bundle of sheets stored in the sheet tray 107, the uppermost sheet is sent out toward the sheet conveyance path 111 by driving the pickup roller 109. The sheet is conveyed to the image forming unit 103 through the sheet conveyance path 111.

  The image forming unit 103 forms a toner image on the conveyed paper. The image forming unit 103 includes a photosensitive drum 113, an exposure unit 115, a developing unit 117, and a transfer unit 119. The exposure unit 115 generates light modulated in accordance with image data (image data output from the document reading unit 200, image data transmitted from a personal computer, image data received by facsimile, etc.), and is uniformly charged. Irradiate to the peripheral surface of the photosensitive drum 113. As a result, an electrostatic latent image corresponding to the image data is formed on the peripheral surface of the photosensitive drum 113. In this state, toner is supplied to the peripheral surface of the photosensitive drum 113 from the developing unit 117, so that a toner image corresponding to the image data is formed on the peripheral surface. This toner image is transferred by the transfer unit 119 to the sheet conveyed from the sheet storage unit 101 described above.

  The sheet on which the toner image is transferred is sent to the fixing unit 105. In the fixing unit 105, heat and pressure are applied to the toner image and the paper, and the toner image is fixed to the paper. The paper is discharged to the stack tray 121 or the paper discharge tray 123.

  The operation unit 400 includes an operation key unit 401 and a display unit 403. The display unit 403 has a touch panel function, and displays a screen including soft keys. The user operates the soft key while viewing the screen to make settings necessary for executing functions such as copying.

  The operation key unit 401 is provided with operation keys including hard keys. Specifically, a start key 405, a numeric keypad 407, a stop key 409, a reset key 411, a function switching key 413 for switching between copy, printer, scanner, and facsimile are provided.

  A start key 405 is a key for starting operations such as copying and facsimile transmission. A numeric keypad 407 is a key for inputting numbers such as the number of copies and a facsimile number. A stop key 409 is a key for stopping a copy operation or the like halfway. The reset key 411 is a key for returning the set contents to the initial setting state.

  The function switching key 413 includes a copy key, a transmission key, and the like, and is a key for switching between a copy function, a transmission function, and the like. When the copy key is operated, an initial copy screen is displayed on the display unit 403. When the transmission key is operated, an initial screen for facsimile transmission and mail transmission is displayed on the display unit 403.

  FIG. 2 is a block diagram showing a configuration of the image forming apparatus 1 shown in FIG. The image forming apparatus 1 has a configuration in which an apparatus main body 100, a document reading unit 200, a document feeding unit 300, an operation unit 400, a control unit 500, and a communication unit 600 are connected to each other by a bus. Since the apparatus main body 100, the document reading unit 200, the document feeding unit 300, and the operation unit 400 have already been described, description thereof will be omitted.

  The control unit 500 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), an image memory, and the like. The CPU executes control necessary for operating the image forming apparatus 1 for the above-described components of the image forming apparatus 1 such as the apparatus main body 100. The ROM stores software necessary for controlling the operation of the image forming apparatus 1. The RAM is used for temporary storage of data generated during execution of software, storage of application software, and the like. The image memory temporarily stores image data (image data output from the document reading unit 200, image data transmitted from a personal computer, image data received by facsimile, etc.).

  The control unit 500 further includes a SIMD type processor 3. This will be described in detail later.

  The communication unit 600 includes a facsimile communication unit 601 and a network I / F unit 603. The facsimile communication unit 601 includes an NCU (Network Control Unit) that controls connection of a telephone line with a destination facsimile, and a modulation / demodulation circuit that modulates / demodulates a signal for facsimile communication. The facsimile communication unit 601 is connected to the telephone line 605.

  The network I / F unit 603 is connected to a LAN (Local Area Network) 607. A network I / F unit 603 is a communication interface circuit for executing communication with a terminal device such as a personal computer connected to the LAN 607.

  FIG. 3 is a block diagram showing the configuration of the SIMD type processor 3 according to this embodiment. The SIMD type processor 3 includes a plurality of processor elements 4, a global processor 11, an external interface 12, and a plurality of buses 13.

  The plurality of processor elements 4 are arranged side by side in the main scanning direction D1. The plurality of processor elements 4 have the same configuration, and the configuration of the processor element 4 will be described with reference to the processor element 4a.

  The processor element 4a includes four registers 5a, 5b, 5c, 5d, two arithmetic circuits 6a, 6b, two input buses 7a, 7b, and two multiplexers 8a, 8b. When the registers 5a, 5b, 5c, and 5d are not distinguished, they are referred to as a register 5. When the arithmetic circuits 6a and 6b are not distinguished, they are referred to as an arithmetic circuit 6. When the input buses 7a and 7b are not distinguished, they are referred to as the input bus 7. When the multiplexers 8a and 8b are not distinguished, they are referred to as a multiplexer 8.

  The processor element 4 a further includes a register bus 10 that is a bus that connects the input bus 7 and the output of the register 5.

  The register 5 stores 16-bit data. The arithmetic circuit 6 is an arithmetic and logic unit that calculates 16-bit data. The input bus 7 and the register bus 10 transmit 16-bit data. The multiplexer 8 outputs the input 16-bit data. In the present embodiment, an example in which the arithmetic circuit 6 processes 16-bit data will be described. However, data that can be processed by the arithmetic circuit 6 is not limited to 16 bits.

  The four registers 5 are arranged in the sub-scanning direction D2 in the order of the registers 5a, 5b, 5c, and 5d. The outputs of the registers 5a, 5b and 5c are connected to the input bus 7a by the register bus 10. The outputs of the registers 5b, 5c, 5d are connected to the input bus 7b by the register bus 10.

  Among the four registers 5, an element constituted by three registers 5 continuous in the sub-scanning direction D2 is referred to as a register group 9. Two register groups 9 having different combinations of the three registers 5 are provided. One is a register group 9a composed of registers 5a, 5b, and 5c, and the other is a register group 9b composed of registers 5b, 5c, and 5d. When the register groups 9a and 9b are not distinguished, they are referred to as a register group 9.

  Data transmitted using the input bus 7a is input to the multiplexer 8a. The data output from the multiplexer 8a is input to the arithmetic circuit 6a. On the other hand, the data transmitted using the input bus 7b is input to the multiplexer 8b. The data output from the multiplexer 8b is input to the arithmetic circuit 6b.

  As described above, each of the plurality of processor elements 4 corresponds to the M registers 5, the N arithmetic circuits 6, and the N arithmetic circuits 6 on a one-to-one basis. N input buses 7 for transmitting data, and N multiplexers 8 corresponding to N arithmetic circuits 6 on a one-to-one basis and outputting to the corresponding arithmetic circuits 6 are included. In each of the plurality of processor elements 4, N register groups 9 having different combinations of registers 5 correspond to N input buses 7 on a one-to-one basis, and to N multiplexers 8 on a one-to-one basis. And one-to-one correspondence with the N arithmetic circuits 6. In the present embodiment, M is 4 and N is 2 in the description. However, M is an integer of 2 or more, and N may be an integer of 2 or less and 2 or more.

  The input portion of the multiplexer 8a of the processor element 4a has an input bus 7a for transmitting data output from the register group 9a, and data output from the register group 9a provided in the processor element 4 adjacent to the processor element 4a. Is connected to the input bus 7a. Thereby, as will be described later, 3 × 3 filter processing can be executed. Similarly, the input portion of the multiplexer 8b of the processor element 4a has an input bus 7b for transmitting the data output from the register group 9b, and an output from the register group 9b provided in the processor element 4 on both sides of the processor element 4a. An input bus 7b for transmitting data to be transmitted is connected.

  In this way, the input section of each multiplexer 8 has an input bus 7 for transmitting data output from the first register group, which is the register group 9 corresponding to the multiplexer 8 on a one-to-one basis, It is included in the processor element 4 located on one side of the processor element 4 including the multiplexer 8 and the other side of the other, and is output from the register group 9 including the registers 5 in the same row as the first register group. An input bus 7 for transmitting data is connected.

  The global processor 11 controls the operation of each processor element 4 by executing a program stored in the global processor 11.

  The global processor 11 includes a register control unit 14. The register control unit 14 performs the following control. Data stored in the register 5a is transmitted to the arithmetic circuit 6a using the register bus 10 and the input bus 7a. The data stored in the register 5b is transmitted to the arithmetic circuits 6a and 6b using the register bus 10 and the input buses 7a and 7b. The data stored in the register 5c is transmitted to the arithmetic circuits 6a and 6b using the register bus 10 and the input buses 7a and 7b. The data stored in the register 5d is transmitted to the arithmetic circuit 6b using the register bus 10 and the input bus 7b.

  As described above, the register control unit 14 assigns one or more arithmetic circuits 6 in advance to each of the plurality of registers 5 included in each of the plurality of processor elements 4, and stores the data stored in the register 5. Using the register bus 10 and the input bus 7, control to be transmitted to one or more pre-assigned arithmetic circuits 6 is executed for each of the plurality of registers 5 included in each of the plurality of processor elements 4.

  Among the plurality of registers 5, the register bus 10 has a one-to-one correspondence with the arithmetic circuit 6 to which data is transmitted for the register 5 in which the number of arithmetic circuits 6 assigned in advance is less than N. And the register bus 10 is not provided for the input bus 7 corresponding one-to-one with the arithmetic circuit 6 that does not transmit data.

  More specifically, the registers 5 in which the number of one or more arithmetic circuits 6 is less than N (here, 2) are the registers 5a and 5d. Although the register bus 10 for connecting the output of the register 5a and the input bus 7a is provided, the register bus 10 for connecting the output of the register 5a and the input bus 7b is not provided. The register bus 10 that connects the output of the register 5d and the input bus 7b is provided, but the register bus 10 that connects the output of the register 5d and the input bus 7a is not provided.

  The register bus 10 that connects the output of the register 5a and the input bus 7b is not provided. This is because the data stored in the register 5a is not used for the operation of the arithmetic circuit 6b, as will be described later with reference to FIGS.

  Similarly, the register bus 10 that connects the output of the register 5d and the input bus 7a is not provided. This is because the data stored in the register 5d is not used for the operation of the arithmetic circuit 6a, as will be described later with reference to FIGS.

  The bus 13 is connected to the register 5 at the same position in the sub-scanning direction D2, in other words, the input section of the register 5 located at the same row. Data is transferred to the register 5 via the external interface 12 and the bus 13.

  FIG. 4 is a schematic diagram showing a part of an image that is subjected to 3 × 3 filter processing by the SIMD type processor 3. A part of the image is composed of 30 pixels 20, and 5 pixels 20 are arranged in the main scanning direction D1, and 6 pixels 20 are arranged in the sub-scanning direction D2.

  Five pixels 20 having pixel values “a1” to “a5” arranged in the main scanning direction D1 belong to the (N−1) th line. Hereinafter, similarly, the five pixels 20 having pixel values “b1” to “b5” arranged in the main scanning direction D1 belong to the Nth line. The five pixels 20 having pixel values “c1” to “c5” arranged in the main scanning direction D1 belong to the (N + 1) th line. Five pixels 20 having pixel values “d1” to “d5” arranged in the main scanning direction D1 belong to the (N + 2) th line. The five pixels 20 arranged in the main scanning direction D1 having pixel values “e1” to “e5” belong to the (N + 3) th line. The five pixels 20 arranged in the main scanning direction D1 having pixel values “f1” to “f5” belong to the (N + 4) th line.

  The (N−1) th line, the Nth line, the N + 1th line, the N + 2nd line, the N + 3rd line, and the N + 4th line are lines that are continuously arranged in the sub-scanning direction D2. Each line is composed of pixels 20 arranged continuously in the main scanning direction D1.

  FIG. 5 is a schematic diagram showing a state in which the pixel values of the (N−1) th line to the (N + 2) th line shown in FIG. 4 are set in each register 5 of the SIMD type processor 3 shown in FIG. The 3 × 3 filter processing for the pixels 20 constituting the Nth line and the 3 × 3 filter processing for the pixels 20 constituting the N + 1th line are executed simultaneously.

  For example, in the 3 × 3 filter process for the pixel 20 with the pixel value b3, the arithmetic circuit 6a of the processor element 4a performs an operation using the pixel values a2, a3, a4, b2, b4, c2, c3, and c4. . Further, for example, in the 3 × 3 filter process for the pixel 20 with the pixel value c3, the arithmetic circuit 6b of the processor element 4a performs an operation using the pixel values b2, b3, b4, c2, c4, d2, d3, d4. Run.

  FIG. 6 is a schematic diagram showing a state where the pixel values of the (N + 1) th line to the (N + 4) th line shown in FIG. 4 are set in each register 5 of the SIMD type processor 3 shown in FIG. The 3 × 3 filtering process for the pixels 20 constituting the N + 2th line and the 3 × 3 filtering process for the pixels 20 constituting the N + 3th line are executed simultaneously.

  For example, in the 3 × 3 filter process for the pixel 20 having the pixel value d3, the arithmetic circuit 6a of the processor element 4a performs an operation using the pixel values c2, c3, c4, d2, d4, e2, e3, e4. . Further, for example, in the 3 × 3 filter process for the pixel 20 with the pixel value e3, the arithmetic circuit 6b of the processor element 4a performs an operation using the pixel values d2, d3, d4, e2, e4, f2, f3, and f4. Run.

  The main effects of this embodiment will be described. Referring to FIG. 3, in the present embodiment, as arithmetic circuit 6 to which data is transmitted, register 5 (registers 5 a and 5 d) in which the number of arithmetic circuits 6 assigned is less than N (here, 2). A register bus 10 is provided for the input bus 7 corresponding to the arithmetic circuit 6 to which data is transmitted, and a register for the input bus 7 corresponding to the arithmetic circuit 6 to which the data is not transmitted. The bus 10 is not provided. That is, the registers 5 other than the registers 5b and 5c to which data is transmitted to all of the two arithmetic circuits 6 belonging to the processor element 4 are connected to the arithmetic circuit 6 to which data is not transmitted and the input bus 7 corresponding to one-to-one. The register bus 10 to be used is not provided. As a result, the number of register buses 10 included in each of the plurality of processor elements 4 can be reduced, so that wiring congestion can be reduced.

  Further, in the present embodiment, an input bus 7 for transmitting data output from the register group 9 (first register group) corresponding to the multiplexer 8 in a one-to-one relationship with the multiplexer 8 in the input section of each multiplexer 8. And from the register group 9 that is included in the processor element 4 that is located on one side of the processor element 4 including the multiplexer 8 and on the other side of the processor element 4 and that is composed of the registers 5 in the same row as the first register group. An input bus 7 for transmitting the output data is connected. Therefore, since the pixel data of the pixels 20 positioned around the pixel 20 of interest can be sent to one arithmetic circuit 6, the filter processing can be realized.

  In this embodiment, the case where the number M of the registers 5 belonging to each processor element 4 is four has been described, but the number M may be an integer of 2 or more. For example, the case where the number M of the registers 5 is 32 will be briefly described. FIG. 7 is a schematic diagram showing the processor element 4 when the number M of the registers 5 is 32.

  The 32 registers 5 are arranged in the sub-scanning direction D2 in the order of the registers 5-0 to 5-31. The output units of the registers 5-0 to 5-18 are connected to the input bus 7a by the register bus 10. The output units of the registers 5-13 to 5-31 are connected to the input bus 7b by the register bus 10.

  An input bus 7a included in three consecutive processor elements 4 on one side of the processor element 4a and an input bus 7a included in three consecutive processor elements 4 on the other side of the processor element 4a It is connected to the input of the multiplexer 8a of the element 4a. Similarly, an input bus 7b included in three consecutive processor elements 4 on one side of the processor element 4a and an input bus 7b included in three consecutive processor elements 4 on the other side of the processor element 4a. Is connected to the input of the multiplexer 8b of the processor element 4a. As a result, a 7 × 7 filter process can be executed.

  As described above, referring to FIG. 3, the input bus 7a of the processor element 4a, the input bus 7a of the processor element 4 successively arranged next to one side of the processor element 4a, and the other side of the other of the processor elements 4a Are connected to the input of the multiplexer 8a of the processor element 4a. Similarly, the input bus 7b of the processor element 4a, the input bus 7b of the processor element 4 continuously arranged next to one side of the processor element 4a, and the processor element 4 successively arranged next to the other side of the processor element 4a Is connected to the input of the multiplexer 8b of the processor element 4a. Thereby, it can be set as the structure which can perform arbitrary filter processes of 3x3 or more.

  Referring to FIG. 7, data stored in registers 5-13 to 5-18 can be transmitted to two arithmetic circuits 6a and 6b. These registers 5 store pixel value data and filter processing parameters transmitted to the two arithmetic circuits 6a and 6b.

  In the present embodiment, the number N of the arithmetic circuits 6, the multiplexers 8, and the input buses 7 belonging to one processor element 4 has been described as being 2. However, the number N is equal to or less than the number M and equal to or greater than 2. Any integer is acceptable. FIG. 8 is a schematic diagram showing the processor element 4 when the number N is three.

  The processor element 4 includes five registers 5a, 5b, 5c, 5d, 5e, three arithmetic circuits 6a, 6b, 6c, three input buses 7a, 7b, 7c, and three multiplexers 8a, 8b and 8c are included.

  The five registers 5 are arranged in the sub-scanning direction D2 in the order of the registers 5a, 5b, 5c, 5d, and 5e. The outputs of the registers 5a, 5b and 5c are connected to the input bus 7a by the register bus 10. The outputs of the registers 5b, 5c, 5d are connected to the input bus 7b by the register bus 10. The outputs of the registers 5c, 5d, and 5e are connected to the input bus 7c by the register bus 10.

  A register group 9a is constituted by the registers 5a, 5b and 5c. A register group 9b is constituted by the registers 5b, 5c, and 5d. A register group 9c is constituted by the registers 5c, 5d, and 5e.

  The input bus 7a is connected to the input unit of the multiplexer 8a, and the output of the multiplexer 8a is connected to the input unit of the arithmetic circuit 6a. The input bus 7b is connected to the input unit of the multiplexer 8b, and the output of the multiplexer 8b is connected to the input unit of the arithmetic circuit 6b. The input bus 7c is connected to the input unit of the multiplexer 8c, and the output of the multiplexer 8c is connected to the input unit of the arithmetic circuit 6c.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 3 SIMD type processor 4, 4a Processor element 5, 5a-5e, 5-0-5-31 Register 6, 6a, 6b Arithmetic circuit 7, 7a, 7b Input bus 8, 8a, 8b Multiplexer 9, 9a, 9b Register group 10 Register bus 11 Global processor 12 External interface 13 Bus 14 Register control unit 20 Pixel

Claims (2)

A SIMD type processor having a plurality of processor elements,
Each of the plurality of processor elements is
Multiple registers,
N arithmetic circuits (N is an integer of 2 or more);
N input buses corresponding one-to-one with the N arithmetic circuits and transmitting data to the corresponding arithmetic circuits;
A register bus that is a bus connecting the input bus and the output of the register,
The SIMD type processor pre-allocates one or more arithmetic circuits to each of the plurality of registers included in each of the plurality of processor elements, and the data stored in the register is transferred to the register bus and A register control unit configured to execute control for transmitting to the one or more pre-assigned arithmetic circuits using the input bus for each of the plurality of registers included in each of the plurality of processor elements; Prepared,
Among the plurality of registers, the number of the pre-assigned arithmetic circuits is less than N, and the register is connected to the input bus corresponding to the arithmetic circuit to which data is transmitted one-to-one. A SIMD processor in which a bus is provided and the register bus is not provided for the input bus corresponding to the arithmetic circuit in which data is not transmitted. The plurality of processor elements are arranged side by side in the main scanning direction,
In each of the plurality of processor elements, the plurality of registers are arranged side by side in the sub-scanning direction,
Each of the plurality of processor elements includes N multiplexers corresponding to the N arithmetic circuits in a one-to-one correspondence and outputting to the corresponding arithmetic circuits,
N registers having different combinations of registers in each of the plurality of processor elements, when a register group is an element constituted by the registers continuous in the sub-scanning direction among the plurality of registers. A group has a one-to-one correspondence with the N input buses, a one-to-one correspondence with the N multiplexers, and a one-to-one correspondence with the N arithmetic circuits. And
The input section of each multiplexer has the input bus for transmitting data output from the first register group which is the register group corresponding to the multiplexer in a one-to-one relationship, and the processor including the multiplexer The input for transmitting data output from the register group, which is included in the processor element located on one side of the element and on the other side of the element, and is configured by the registers in the same row as the first register group The SIMD type processor according to claim 1, to which a bus is connected.

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