JP6153740B2 - Magnetic detection circuit using magnetic detection element - Google Patents

Description

  In this specification, a magnetic detection circuit using a magnetic detection element having at least four terminals is disclosed.

As disclosed in Non-Patent Document 1, a magnetic detection element having four terminals has been developed. This element has the following characteristics (1) and (2).
(1) When a current is applied between the first terminal and the third terminal, a voltage difference proportional to the magnetic flux density is generated between the second terminal and the fourth terminal,
(2) When a current is applied between the second terminal and the fourth terminal, a voltage difference proportional to the magnetic flux density is generated between the first terminal and the third terminal.
However, the offset voltage is also superimposed on the voltage difference generated in (1), and the offset voltage is also superimposed on the voltage difference generated in (2). Therefore, it is necessary to remove the influence of the offset voltage.

  In the technique of Non-Patent Document 1, when the voltage difference proportional to the magnetic flux density is VH and the offset voltage is VOFF, the voltage difference V1 generated in (1) is approximately VH + VOFF and is generated in (2). The voltage difference V2 to be removed eliminates the influence of the offset voltage by utilizing the property of approximately VH−VOFF. That is, when V1 and V2 are added, the relationship of (VH + VOFF) + (VH−VOFF) = 2 · VH is used to remove the influence of the offset voltage.

Toshiba review Vol.65, No.1, (2010), pp27-31, high-performance magnetic sensor using Si Hall elements, Toru Takeda, Kyoko Kurashima, Miho Mochizuki

The above (1) and (2) do not occur simultaneously. In the technique of Non-Patent Document 1, (1) and (2) are alternately switched over time. In the technique of Non-Patent Document 1, the voltage difference V1 observed during the period (1) is held, and the held voltage difference V1 is added to the voltage difference V2 observed during the period (2). .
If the change speed of the magnetic flux density to be observed is low, no problem arises even with the technique of Non-Patent Document 1. However, if the changing speed of the magnetic flux density is high, for example, a problem that the magnetic flux density in the period (1) is not known until the period (2) is realized becomes apparent. For example, the magnetic flux density may be measured in order to know the timing when the magnetic flux density reaches a predetermined value, and the problem that the magnetic flux density in the period (1) is not known until the period (2) becomes a practical obstacle. is there. As a matter of course, there is a limit to speeding up the switching frequency of the period (1) and the period (2) due to constraints such as the responsiveness of the processing apparatus. A technique for amplifying a voltage proportional to the magnetic flux density without delay is required.

  In the present specification, a technique for removing the influence of the offset voltage caused by the magnetic detection element having the above-described four terminals without using a method of “holding a value and using it later” is disclosed.

As illustrated in FIG. 4, the magnetic detection circuit disclosed in the present specification includes a power source 1, an energization switch 2, a magnetic detection element 4, an input side switch 26, a differential amplifier 17, and an output side switch. 28, a first output terminal T1, a second output terminal T2, and a switch switching circuit 36.
The magnetic detection element 4 has four terminals, and the numbers surrounded by circles in FIG. 4 indicate the terminal numbers. The magnetic detection element 4 has the following characteristics.
(1) When energized between the first terminal and the third terminal, a voltage including a voltage component proportional to the magnetic flux density and an element offset voltage component is output between the second terminal and the fourth terminal,
(2) When energized between the second terminal and the fourth terminal, a voltage including a voltage component proportional to the magnetic flux density and an element offset voltage component is output between the first terminal and the third terminal.
In this specification, the period (1) is referred to as a first mode, and the period (2) is referred to as a second mode. The technique disclosed in this specification can be applied to a magnetic detection element having at least four terminals, for example, a magnetic detection element having a fifth terminal, a sixth terminal,... can do. For example, the present technology can be applied to the fifth terminal to the eighth terminal among the first terminal to the eighth terminal.
The differential amplifier 17 includes a first input k, a second input m, a first output p, and a second output q. A voltage difference obtained by amplifying the voltage difference (n) between the first input k and the second input m is generated between the first output p and the second output q.
The switch switching circuit 36
(1a) The energizing switch 2 connects the power source 1 and the first terminal, connects the third terminal and the ground line,
(1b) The input side switch 26 connects the fourth terminal to the first input k and connects the second terminal to the second input m.
(1c) a state in which the output-side switch 28 connects the first output p to the first output terminal T1 and connects the second output q to the second output terminal T2.
(2a) The energizing switch 2 connects the power source 1 and the second terminal, connects the fourth terminal and the ground line,
(2b) The input-side switch 26 connects the third terminal to the first input k and connects the first terminal to the second input m.
(2c) The output side switch 28 alternately switches the state in which the first output p is connected to the second output terminal T2 and the second output q is connected to the first output terminal T1.
The mode is switched to the first mode (1) by (1a) to (1c), and the mode is switched to the second mode (2) by (2a) to (2c).
(1a) to (1c) may not be simultaneous. (1a) may precede and (1b) (1c) may be delayed. Or the order of (1a) (1b) (1c) may be sufficient. Similarly, (2a) may precede and (2b) (2c) may be delayed. Or the order of (2a) (2b) (2c) may be sufficient. If the mode is switched to (2a) after (1c) and switched to (1a) after (2c), the first mode and the second mode are switched alternately.

According to the above-described magnetic detection circuit, the input side switch 26 connects the terminals shown in Table 1 to the first input k and the second input m of the differential amplifier 17, and the first input k and the second input of the differential amplifier 17. The voltage difference between the inputs m is shown in Table 1.

As apparent from Table 1, the voltage difference input to the differential amplifier 17 is obtained by superimposing a voltage proportional to the magnetic flux density on the element offset voltage, and the superimposed magnetic flux density proportional voltage is positive or negative in the first mode and the second mode. The relationship is reversed by mode. That is, the voltage difference input to the differential amplifier is superimposed on the element offset voltage (DC voltage component) by the voltage modulated by the magnetic flux density proportional voltage (voltage modulated by the switching frequency between the first mode and the second mode). Voltage.
A voltage difference obtained by amplifying the modulated magnetic flux density proportional voltage is generated between the output terminals p and q of the differential amplifier 17. Since the differential amplifier 17 functions as a high-pass filter determined by the time constant of the feedback CR included in the differential amplifier 17, even if a DC voltage component (element offset voltage) is superimposed on the input voltage, the DC voltage Will not be affected. The differential amplifier 17 outputs a voltage obtained by amplifying a voltage obtained by modulating the magnetic flux density proportional voltage.
The output side switch 28 demodulates a voltage obtained by amplifying the modulated magnetic flux density proportional voltage. A voltage difference obtained by amplifying the magnetic flux density proportional voltage is generated between the first output terminal T1 and the second output terminal T2. The influence of the element offset voltage does not occur at the first output terminal T1 and the second output terminal T2.

  According to the magnetic detection circuit disclosed in this specification, the sign of the element offset voltage input to the differential amplifier 17 is the same in both the first mode and the second mode, and the element offset voltage is input as a DC component. . Therefore, the output voltage of the differential amplifier 17 is not affected by the element offset voltage, and a voltage obtained by amplifying the modulated magnetic flux density proportional voltage is generated. Since the above relationship is always obtained, there is no need to wait for the mode to be reversed in order to cancel the influence of the element offset voltage. The effect of the element offset voltage can be removed without time delay.

In the conventional technique, the detection value in the first mode is held and added to the detection value in the second mode using the relationship in which the sign of the element offset voltage is inverted between the first mode and the second mode. To eliminate the influence of the element offset voltage. In the conventional technique, the influence of the element offset voltage is removed after waiting for the mode to be reversed, so that the detection result is delayed.
According to the magnetic detection circuit disclosed in this specification, an element generated in the magnetic detection element is obtained by obtaining a relationship in which the sign of the element offset voltage input to the differential amplifier is maintained the same throughout the first mode and the second mode. The influence of the offset voltage is removed, and a voltage obtained by amplifying the magnetic flux density proportional voltage is obtained. There is no need to wait for the mode to reverse to eliminate the effect of the element offset voltage. Therefore, the phenomenon that the detection result is delayed by the mode inversion time does not occur.
According to the magnetic detection circuit disclosed in the present specification, when the magnetic flux density changes with the passage of time, it is possible to obtain a detection result that follows the time change of the magnetic flux density without delay.

A 4-terminal magnetic detection element, its energization mode, and the voltage obtained will be described. 1 shows a conventional magnetic detection circuit. The voltage change in the case of the conventional magnetic detection circuit is shown. The magnetic detection circuit of an Example is shown. The voltage change by the magnetic detection circuit of an Example is shown. The continuation of the voltage change in the case of the magnetic detection circuit of the embodiment is shown. The influence of the power supply voltage will be described. Fig. 4 shows an improved embodiment of the magnetic detection circuit. Fig. 4 shows a sample and hold circuit utilized in the improved embodiment. Fig. 6 shows the voltage change in the case of the magnetic detection circuit of the improved embodiment. Fig. 5 shows a buffer circuit for use in the improved embodiment. The effect obtained by the buffer circuit is shown. Fig. 5 shows a clock signal used in the magnetic detection circuit of the improved embodiment. 6 shows another improved magnetic detection circuit according to another embodiment.

The main features of the embodiments described below are exemplified below. Both are included in the technical scope of the present invention.
(Feature 1) The differential amplifier has two inputs and two outputs.
(Feature 2) The differential amplifier is a charge amplifier.
(Characteristic 3) The differential amplifier is a charge amplifier that also functions as a high-pass filter that passes only a higher frequency than the frequency determined by the time constant of the feedback CR.
(Feature 4) The differential amplifier includes a feedback capacitor and a feedback resistor connected in parallel to the feedback capacitor.
(Feature 5) The value of the feedback resistor is large, and the change speed of the output voltage of the differential amplifier is slow.
(Characteristic 6) The feedback resistor is composed of a MOS, and the resistance value is equal to or greater than mega ohms.
(Feature 7) The differential amplifier outputs a voltage difference from which the influence of the element offset voltage is removed.
(Feature 8) The differential amplifier outputs a voltage including an offset voltage of the operational amplifier. However, the offset voltage of the operational amplifier included in the output voltage is not amplified and can be sufficiently removed by a primary LPF (low pass filter).
(Feature 9) A sample-and-hold circuit for removing chopper noise (spike noise) remaining in the demodulated magnetic flux density proportional voltage is provided.
(Feature 10) An LPF (low pass filter) for removing the offset voltage of the operational amplifier is provided.
(Characteristic 11) The cutoff frequency of the LPF is set mainly in a band for removing thermal noise, and the upper limit of the observable signal frequency is high.
(Feature 12) The LPF is incorporated in the difference circuit.

(4-terminal magnetic detection element)
The four-terminal magnetic detection element used in the embodiment uses a Hall element that outputs a voltage proportional to the magnetic flux density. As shown in FIG. 1, the four-terminal magnetic detection element includes first to fourth terminals (in FIG. 1, numbers surrounded by circles indicate terminal numbers). The line segment connecting the terminals and the line segment connecting the second terminal and the fourth terminal are in a perpendicular relationship.
When a current of a predetermined value is supplied from the first terminal to the third terminal of the four-terminal magnetic detection element in a state where the four-terminal magnetic detection element is placed in a magnetic field, a voltage represented by the expression (1) is generated at the fourth terminal. The voltage shown by the equation (2) is generated at the second terminal. A state in which current is supplied from the first terminal to the third terminal is referred to as a first mode. In FIG. 1, 1 that is not circled indicates the first mode. In Expression (1) and Expression (2), etc., VH1 is a voltage proportional to the magnetic flux density extending in the direction perpendicular to the flat surface of the four-terminal magnetic detection element. If the magnetic flux density in the direction perpendicular to the paper surface at the position where the four-terminal magnetic detection element is present is B, VH1 is proportional to B. The value of B can be determined from the value of VH1. If the value of the magnetic flux density B varies with time, the value of VH1 also varies with time.

  As shown in Equation (1) and the like, the output voltage of the four-terminal magnetic detection element includes VOFF1 and VIN10 in addition to VH1. VIN10 is an average voltage of the fourth terminal voltage and the second terminal voltage. VIN10 does not change with time. The value of VIN10 is a value determined as a result of detecting the fourth terminal voltage and the second terminal voltage. VIN10 is equally superimposed on the fourth terminal voltage and the second terminal voltage. VOFF1 has a positive value superimposed on the fourth terminal voltage and a negative value superimposed on the second terminal voltage. This value is referred to as an element offset voltage in this specification. VOFF1 is an element offset voltage in the first mode.

  When a current of a predetermined value is passed from the second terminal to the fourth terminal of the four-terminal magnetic detection element placed in a magnetic field, a voltage expressed by equation (3) is generated at the first terminal and (4) at the third terminal. A voltage expressed by the equation is generated. A state in which current is supplied from the second terminal to the fourth terminal is referred to as a second mode. In FIG. 1, 2 not surrounded by a circle indicates the second mode. In Expressions (3) and (4), etc., VH2 is a voltage proportional to the magnetic flux density extending in the direction perpendicular to the flat surface of the four-terminal magnetic detection element, and VIN20 is the average of the third terminal voltage and the first terminal voltage. VOFF2 is an element offset voltage in the second mode.

In the case of a four-terminal magnetic detection element, when the energization current values in the first mode and the second mode are equal and the magnetic flux densities in the first mode and the second mode are equal, VH1 = VH2. If the first mode and the second mode are switched at a higher speed than the change rate of the magnetic flux density, VH1 = VH2 as shown in the equation (5). The element offset voltage in the first mode and the second mode has a relationship of VOFF1 = −VOFF2, as shown in the equation (6). VIN10 and VIN20 are not necessarily equal, but neither VIN10 nor VIN20 changes with time.
As shown in equation (5), when VH1 = VH2 = VH and as shown in equation (6), VOFF1 = −VOFF2 = VOFF, the fourth terminal voltage and the second terminal voltage in the first mode, and The first terminal voltage and the third terminal voltage in the second mode are as shown in equations (1a) to (4a).
The graph of FIG. 1 shows changes in the first to fourth terminal voltages shown in (1a) to (4a) when the magnetic flux density B changes in a sinusoidal waveform with respect to time. In FIG. 1, for the sake of clarity, the switching period between the first mode and the second mode is displayed longer than the actual time. In practice, it switches faster.

FIG. 2 shows a conventional processing circuit that amplifies the magnetic flux density proportional voltage VH by eliminating the influence of the element offset voltage VOFF. The technique described in Non-Patent Document 1 is embodied so that it can be compared with Examples described later.
In FIG. 2, reference numeral 1 is a constant current circuit for supplying a constant current. Reference numeral 4 is a four-terminal magnetic detection element. Reference numeral 2 denotes a switch for energization. When the switch S1 is turned on, the switch S2 is turned off, and when the switch S1 is turned off, the switch S2 is turned on. A switching circuit (not shown) turns on / off / on the switch S1 and turns off / on / off the switch S2 at short time intervals.
When the switch S1 is turned on, a constant current is passed from the first terminal of the four-terminal magnetic detection element 4 to the third terminal (becomes the first mode). When the switch S2 is turned on, a constant current is passed from the second terminal of the four-terminal magnetic detection element to the fourth terminal (becomes the second mode).

Reference numerals 6 and 8 are sample and hold circuits. The sample hold circuit 6 is connected to the fourth terminal via the switch S1. While the switch S1 is off, the voltage at the fourth terminal at the timing immediately before the switch S1 is turned off (the fourth terminal voltage in the first mode). ). The sample hold circuit 8 is connected to the second terminal via the switch S1. While the switch S1 is off, the voltage of the second terminal at the timing immediately before the switch S1 is turned off (the second terminal voltage in the first mode). ).
Reference numerals 10 and 12 are addition circuits. The adder circuit 10 is connected to the first terminal via the switch S2, and is also connected to the sample hold circuit 6. The adder circuit 10 has a voltage held in the sample hold circuit 6 at a voltage at the first terminal (first terminal voltage in the second mode) at a timing immediately before the switch S2 is turned off (timing immediately before the switch S1 is turned on). The voltage that is added is output. The adder circuit 12 is connected to the third terminal via the switch S2, and is also connected to the sample hold circuit 8. The adder circuit 12 has a voltage held in the sample hold circuit 8 at a voltage at the third terminal (third terminal voltage in the second mode) at a timing immediately before the switch S2 is turned off (timing immediately before the switch S1 is turned on). The voltage that is added is output. A delay time corresponding to ½ of a cycle for switching between the first mode and the second mode occurs between the timing at which the sample and hold circuits 6 and 8 sample and hold and the timing at which the addition circuits 10 and 12 add.

A horizontal solid line shown in FIG. 3A indicates a voltage held in the sample hold circuit 6. A black circle shown in FIG. 3B indicates one voltage (first terminal voltage in the second mode) added by the adder circuit 10, and a black circle shown in FIG. 3A indicates the other voltage added by the adder circuit 10. (The fourth terminal voltage in the first mode). The black circles in FIG. 3C indicate the result of addition performed by the adder circuit 10. Note that the relationship between the first mode and the second mode with respect to the time change of the magnetic flux density B is reversed in FIGS. The relationship between the time change of the magnetic flux density B and the mode switching timing is not limited. As shown in FIG. 3A, the voltage at the fourth terminal is a value obtained by adding 1/2 of the positive element offset voltage VOFF and the magnetic flux density proportional voltage VH to the average voltage VIN10. As shown in FIG. 3B, the voltage at the first terminal is a value obtained by adding 1/2 of the negative element offset voltage -VOFF and the magnetic flux density proportional voltage VH to the average voltage VIN20. Therefore, as shown in FIG. 3C, the output voltage of the adder circuit 10 is VIN10 + VIN20 + 2 × VH (magnetic flux density proportional voltage), and the influence of the element offset voltage VOFF is eliminated. Actually, VIN10 + VIN20 may be out of the power supply voltage range. Therefore, the adding circuit 10 adds the half value of the voltage indicated by the black circle in FIG. 3A and the half value of the voltage indicated by the black circle in FIG. The output voltage of the adder circuit 10 is (VIN10 + VIN20) / 2 + VH.
Similarly, the horizontal solid line shown in FIG. 3D indicates the voltage held in the sample hold circuit 8. The black circle shown in FIG. 3 (e) indicates one voltage (the third terminal voltage in the second mode) added by the adding circuit 12, and the black circle shown in FIG. (The second terminal voltage in the first mode). The black circle in (f) of FIG. 3 shows the result of addition by the adder circuit 12. As shown in FIG. 3D, the voltage at the second terminal is a value obtained by adding 1/2 of the negative element offset voltage −VOFF and the negative magnetic flux density proportional voltage −VH to the average voltage VIN10. . As shown in FIG. 3E, the voltage at the third terminal is a value obtained by adding ½ of the positive element offset voltage VOFF and the negative magnetic flux density proportional voltage −VH to the average voltage VIN20. Therefore, as shown in FIG. 3F, the output voltage of the adder circuit 12 becomes VIN10 + VIN20-2 × VH (magnetic flux density proportional voltage), and the influence of the element offset voltage VOFF is eliminated. Actually, VIN10 + VIN20 may be out of the power supply voltage range. Therefore, the adding circuit 12 adds the half value of the voltage indicated by the black circle in FIG. 3D and the half value of the voltage indicated by the black circle in FIG. The output voltage of the adder circuit 10 is (VIN10 + VIN20) / 2−VH.
FIG. 3 (g) shows the voltage difference between FIG. 3 (c) and FIG. 3 (f), and the AC voltage is inverted between plus 2 × VHMAX and minus 2 × VHMAX. The operational amplifier 16 outputs a voltage obtained by amplifying the AC voltage. The value of VH (magnetic flux density proportional voltage) can be specified from the amplified voltage of the operational amplifier 16, and further the value of magnetic flux density B can be specified.

  The output voltage of the operational amplifier 16 in FIG. 2 is a voltage obtained by superimposing an amplifier offset voltage on a voltage obtained by amplifying VH (magnetic flux density proportional voltage). In the technique of Non-Patent Document 1, the input side switch 14 and the output side switch 18 using the switch SA and the switch SB are used to remove the influence of the amplifier offset voltage. When the switch SA is turned on, the switch SB is turned off, and when the switch SA is turned off, the switch SB is turned on. A switching circuit (not shown) turns the switch SA on, off, on,..., And turns the switch SB off, on, off,. The switching cycle of the switches SA and SB may be equal to or different from the switching cycle of the switches S1 and S2.

  The voltage difference in (h) while the switch SA is on is G × VH + G × VAMPOFF (amplifier offset voltage). Reference numeral 22 is a sample hold circuit, which holds the voltage difference (h) at the timing immediately before the switch SA is turned off. The voltage difference in (h) while SB is on is + G × VH−G × VAMPOFF. Reference numeral 24 outputs a voltage obtained by adding the voltage (G × VH + G × VAMPOFF) held in the sample hold circuit 22 to the voltage difference (G × VH−G × VAMPOFF) at the timing immediately before the switch SB is turned off. This is an adding circuit. The output voltage of the adder circuit 24 is 2 × G × VH, and the influence of VAMPOFF (amplifier offset voltage) is removed.

According to the conventional processing circuit shown in FIG. 2, although the influence of the element offset voltage VOFF can be removed, for that purpose, the processing must be waited until the switch S2 is turned off after the switch S1 is turned off. The processing is delayed by a half cycle of the switching cycle of the switches S1 and S2.
When detecting a change in magnetic flux density over time when a magnet fixed to a rotating body passes in the vicinity of a magnetic detection element to detect a rotation angle or the like, the change rate of the magnetic flux density becomes high. The switching cycle of the switches S1 and S2 is limited by the characteristics of the parts that constitute the circuit, and cannot be speeded up unnecessarily. The switching period of the switches S1 and S2 may not be sufficiently shortened with respect to the change period of the magnetic flux density, and detection delay may be a problem. The following embodiment corresponds to this.

(Example)
FIG. 4 shows a processing circuit of the embodiment. The same members as those in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.
The relationship between the constant current circuit 1, the four-terminal magnetic detection element 4, and the energization switch 2 is the same as in FIG. In the circuit of FIG. 4, the sample hold circuits 6 and 8 and the adder circuits 10 and 12 are not used. The connection relationship between the input side switch 26 and the four-terminal magnetic detection element 4 is different from that in FIG. In FIG. 2, the input side switch 26 switches between the first terminal and the fourth terminal and switches between the second terminal and the third terminal, whereas in FIG. 4, the input side switch 26 includes the first terminal and the second terminal. And the third terminal and the fourth terminal are switched. In FIG. 2, the switching cycle of the energizing switch 2 may be different from the switching cycle of the input side switch 14 and the output side switch 18, but in FIG. 4, the energizing switch 2, the input side switch 26, and the output side The switching cycle of the switch 28 is made uniform. However, the presence of a phase difference is allowed as exemplified in the examples described later. FIG. 4 illustrates a case where there is no phase difference. In this embodiment, each of the energization switch 2, the input side switch 26, and the output side switch 28 includes a switch S1 and a switch S2. In the present embodiment, a fully differential amplifier 17 is constituted by the operational amplifier 16, the capacitors C1, C2, C3, C4, the resistors R1, R2, and the like. The fully differential amplifier 17 is a capacitive type and operates as a charge amplifier. The feedback resistor R1 is connected in parallel to the feedback capacitor C2, and the feedback resistor R2 is connected in parallel to the feedback capacitor C4. The feedback resistors R1 and R2 stabilize the DC bias point.

  The switch switching circuit 36 switches each of the energizing switch 2, the input side switch 26, and the output side switch 28. The switch switching circuit 36 turns off the switch S2 when the switch S1 included in each of the energizing switch 2, the input side switch 26, and the output side switch 28 is turned on, and turns on the switch S2 when the switch S1 is turned off. . The switch switching circuit 36 turns on / off / on the switch S1 and turns off / on / off the switch S2 at short intervals. In this embodiment, the first mode and the second mode are switched at 500 kHz.

When the switch S1 of the energization switch 2 is turned on, a constant current is passed from the first terminal to the third terminal of the four-terminal magnetic detection element 4 to enter the first mode. When the switch S2 of the energization switch 2 is turned on, a constant current is passed from the second terminal of the four-terminal magnetic detection element 4 to the fourth terminal, and the second mode is set.
In the circuit of the embodiment, the connection relationship of the input side switch 26 is changed from FIG. In the first mode, the fourth terminal voltage is input to the first input k of the differential amplifier circuit 17, and the second terminal voltage is input to the second input m of the differential amplifier circuit 17. In the second mode, the third terminal voltage is input to the first input k of the differential amplifier circuit 17, and the first terminal voltage is input to the second input m of the differential amplifier circuit 17. The sample-and-hold circuits 6 and 8 and the addition circuits 10 and 12 which are necessary in the conventional circuit are not necessary.

FIG. 5K shows the voltage at the first input k of the differential amplifier circuit 17. In the first mode, the fourth terminal voltage is input, and in the second mode, the third terminal voltage is input. The fourth terminal voltage in the first mode is a value obtained by adding ½ of the positive element offset voltage VOFF and the positive magnetic flux density proportional voltage VH to the average voltage VIN10 of the fourth terminal voltage and the second terminal voltage. . The third terminal voltage in the second mode is a value obtained by adding 1/2 of the positive element offset voltage VOFF and the negative magnetic flux density proportional voltage VH to the average voltage VIN20 of the third terminal voltage and the first terminal voltage. .
FIG. 5M shows a voltage at the second input m of the differential amplifier circuit 17. In the first mode, the second terminal voltage is input, and in the second mode, the first terminal voltage is input. The second terminal voltage in the first mode is a value obtained by adding the negative element offset voltage -VOFF 1/2 and the negative magnetic flux density proportional voltage VH to the average voltage VIN10 of the fourth terminal voltage and the second terminal voltage. is there. The first terminal voltage in the second mode is a value obtained by adding the negative element offset voltage -VOFF 1/2 and the positive magnetic flux density proportional voltage VH to the average voltage VIN20 of the third terminal voltage and the first terminal voltage. is there.

  (N) in FIG. 5 shows the voltage difference shown in (n) in FIG. In the first mode, a voltage difference between the fourth terminal voltage and the second terminal voltage is obtained. Since the same average voltage VIN10 is superimposed on the fourth terminal voltage and the second terminal voltage, the influence of the average voltage VIN10 is removed from the voltage difference. On the other hand, since the positive terminal offset voltage ½ is superimposed on the fourth terminal voltage and the negative terminal offset voltage ½ is superimposed on the second terminal voltage, the voltage difference includes the element The offset voltage VOFF remains. The voltage difference (n) in the first mode is 2 × VH + VOFF. In the second mode, there is a voltage difference between the third terminal voltage and the first terminal voltage. Since the same average voltage VIN20 is superimposed on the third terminal voltage and the first terminal voltage, the influence of the average voltage VIN20 is removed from the voltage difference. On the other hand, since the half of the positive element offset voltage 2 is superimposed on the third terminal voltage and the half of the offset element offset voltage is superimposed on the first terminal voltage, the voltage difference is The element offset voltage VOFF remains. The voltage difference (n) in the second mode is −2 × VH + VOFF. The graph shown in FIG. 5 (n) shows the temporal change of the voltage difference (n). The voltage difference (n) is inverted between a state where the voltage is higher than the average value and a state where the voltage is lower than the average value, following the switching of the modes, with the element offset voltage VOFF as an average value. The graph shown in FIG. 5 (n) shows the voltage difference observed when the magnetic flux density B changes in a sinusoidal waveform with respect to time. The voltage difference (n) is obtained by superimposing a voltage modulated with a magnetic flux density proportional voltage at the switching frequency between the first mode and the second mode on the DC voltage component of the element offset voltage VOFF.

A voltage obtained by amplifying the voltage difference (n) is generated at one output p of the operational amplifier 16, and a voltage obtained by inverting it is generated at the other output q. However, the differential amplifier 17 includes feedback capacitors C2 and C4, a feedback resistor R1 connected in parallel to the feedback capacitor C2, and a feedback resistor R2 connected in parallel to the feedback capacitor C4. The low frequency voltage or DC voltage component is removed. Since the differential amplifier 17 is a charge amplifier that uses a feedback capacitor and a feedback resistor, it functions as a high-pass filter. The differential amplifier 17 does not amplify a DC voltage component that does not vary with time in the voltage included in the voltage difference (n), and amplifies only an AC voltage that varies with time.
Specifically, as described in the specification and drawings of Japanese Patent Application No. 2011-022106 filed earlier by the present applicants, an amplified signal that inverts the sign in accordance with switching between the first mode and the second mode is provided. When demodulating, the error corresponding to the switching frequency overlaps between the first mode and the second mode. In order to reduce the error, it is advantageous that the feedback resistors R1 and R2 have a large resistance value in the order of mega ohms. In this embodiment, a large resistance value is realized using MOS. As described in the specification and drawings of Japanese Patent Application No. 2011-56744 filed earlier by the present applicants, high resistance can be reduced in size when MOS is used.
To be exact, the output voltage of the differential amplifier 17 is superimposed with the amplifier offset voltage of the operational amplifier 16 on the amplified signal whose sign is inverted in accordance with switching between the first mode and the second mode. However, since the differential amplifier 17 is composed of a charge amplifier, the amplifier offset voltage is not amplified. The amplifier offset voltage superimposed on the output voltage of the differential amplifier 17 is on the order of millivolts and is at a level below thermal noise.

FIG. 6P shows the voltage of the first output p of the differential amplifier 17. This is a waveform obtained by amplifying the waveform of (n) in FIG. The element offset voltage VOFF included in (n) of FIG. 5 is a direct-current voltage component and thus does not affect the amplified voltage. Instead, it fluctuates around a voltage level obtained by adding the amplifier offset voltage VAMPOFF to the reference voltage VREF of the operational amplifier 16. The reference voltage VREF is obtained by resistively dividing the power supply voltage for driving the operational amplifier 16 and is equal to ½ of the power supply voltage. The amplifier offset voltage VAMPOFF is a minute voltage that is not amplified as described above.
(Q) in FIG. 6 shows the voltage of the second output q of the differential amplifier 17. The waveform of (n) in FIG. 5 is amplified and inverted. The element offset voltage VOFF included in (n) of FIG. 5 is a direct-current voltage component and thus does not affect the amplified voltage. Instead, it fluctuates around a voltage level obtained by subtracting the amplifier offset voltage VAMPOFF from the reference voltage VREF of the operational amplifier 16. The reference voltage VREF in FIG. 6 (q) is equal to the reference voltage VREF in FIG. 6 (p). The amplifier offset voltage VAMPOFF in FIG. 6 (q) has the same magnitude as the amplifier offset voltage VAMPOFF in FIG. 6 (p), and the sign is inverted.

  The output side switch 28 demodulates the magnetic flux density proportional voltage (modulated by the input side switch 26). 6 (r) shows the voltage in FIG. 4 (r), and FIG. 6 (s) shows the voltage in FIG. 4 (s).

To be precise, the voltages in FIG. 6 (r) and FIG. 6 (s) are affected by the amplifier offset voltage VAMPOFF whose sign is inverted in synchronization with the switching between the first mode and the second mode. However, as described above, the magnitude is not amplified and is a minute voltage equal to or lower than thermal noise, and is negligible. In FIG. 6 (r) and FIG. 6 (s), it is ignored.
In the voltages shown in (r) and (s) of FIG. 6, noise (so-called chopper noise) generated at the switching timing of the modulation switch (input side switch 26) and the demodulation switch (output side switch 28) is generated. Duplicate.
In this embodiment, circuits 30 and 32 having a sample and hold function are used for removing chopper noise. The details of the circuits 30 and 32 are described in detail in the specification and drawings of Japanese Patent Application No. 2011-022106 filed earlier by the applicant of the present application, and redundant description is omitted. Matters described in the specification and drawings of Japanese Patent Application No. 2011-022106 constitute part of the specification and drawings of the present application.

  FIG. 6 (t) illustrates the processing contents obtained by the circuits 30 and 32. The circuits 30 and 32 have a built-in hold circuit, and the voltage VT at the timing t1 immediately before the timing t2 at which the switches S1 and S2 are inverted is reduced for a short time (for example, from 1/4 of the cycle at which the switches S1 and S2 are inverted). For a short period). When the holding time ends, the output voltages of the circuits 30 and 32 change from the holding voltage to match the input voltage. When the circuits 30 and 32 are used, chopper noise can be removed.

  The circuit 34 in FIG. 4 is a differential circuit having a low-pass filter function, and outputs a voltage of voltage (t) −voltage (u). FIG. 6 (v) shows the voltage output by the difference circuit 34, and a voltage proportional to the magnetic flux is superimposed around the reference voltage VREF. From the voltage proportional to the magnetic flux, chopper noise that is likely to occur by modulation after switching between the first mode and the second mode is removed, and changes in proportion to the magnetic flux. The low-pass filter provided in the difference circuit 34 can be set to a high frequency band that removes thermal noise. Although the circuit 34 including the low-pass filter is used, the cutoff frequency can be set high, and therefore, processing up to a high speed change in the magnetic flux density can be performed.

As shown in FIG. 4, the differential amplifier 17 includes capacitors C1, C2, C3 and C4, a resistor R1 connected in parallel to the capacitor C2, and a resistor R2 connected in parallel to the capacitor C4.
It is preferable to use a charge amplifier that uses In the case of a charge amplifier, the influence of the offset voltage can be eliminated by making the offset voltage of the magnetic detection element 4 a direct current component. Further, the amplifier offset voltage is not amplified, and a circuit for removing the influence of the amplifier offset voltage is not required.
However, this is not to be a charge amplifier of a type in which a resistor is connected in parallel with the feedback capacitor. For example, Japanese Journal of Applied Physics, Vol. 46, No.4B, 2007, pp.2252-2256, “0.6V Supply Complementary Metal Oxide Semiconductor Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization” An amplifier is disclosed. Even if this type of charge amplifier is used, the influence of the element offset voltage can be eliminated.

  What is important is that the influence of the element offset voltage VOFF is eliminated between the first terminal T1 and the second terminal T2, and a voltage with a short time delay from the magnetic flux density proportional voltage VH is obtained. If the above voltage difference is obtained between the first terminal T1 and the second terminal T2, the subsequent processing circuit can be designed in various ways. In this embodiment, the element offset voltage VOFF is applied to the input terminal of the differential amplifier 17 as a DC component, while the magnetic flux density proportional voltage is modulated and applied so as to be differentially applied. The former purpose is achieved by switching the connection relationship of the amplifier 17. The holding circuits 6 and 8 and the addition circuits 10 and 12 are not necessary, and the time delay can be shortened.

In the above embodiment, the case where the first mode and the second mode are switched and used has been specifically described.
The influence of the element offset voltage is removed by the two-mode switching. However, the element offset voltage that can be removed by two-mode switching is limited to a component that is proportional to the energization amount of the magnetic detection element. In order to eliminate the influence of an element offset voltage or the like proportional to the square of the energization amount of the magnetic detection element, it is useful to use a multi-mode switching technique such as a 4-mode or 8-mode. For example, in a magnetic detection device having four terminals, the first mode in which current is supplied from the first terminal to the third terminal, the second mode in which current is supplied from the second terminal to the fourth terminal, and the third terminal to the first terminal. A third mode for energization and a fourth mode for energization from the fourth terminal to the second terminal can be realized. Even in such a case, the two-mode switching technique can be applied. For example, the technique of the present invention can be applied between the first and second modes, or the technique of the present invention can be applied between the third and fourth modes. Although the whole is a four-mode or eight-mode switching technique, the two-mode switching technique disclosed in this specification may be implemented in some of them. The claims of this application also apply in such a case.

  As shown in (k) of FIG. 5, the fourth terminal voltage and the third terminal voltage are alternately input to the first input k of the differential amplifier 17. The fourth terminal voltage input in the first mode is expressed by the equation (1a) in FIG. 1, and the third terminal voltage input in the second mode is expressed by the equation (4a) in FIG. Actually, depending on the characteristics of the switches S1 and S2, the voltage represented by the equation (1a) and the voltage represented by the equation (4a) are alternately input to the first input k of the differential amplifier 17. Similarly, the voltage represented by the expression (2a) and the voltage represented by the expression (3a) are alternately input to the second input m of the differential amplifier 17. In that case, there is no problem in the circuit of FIG.

  However, depending on the characteristics of the switches S1 and S2, the power supply voltage may be affected when the switches S1 and S2 are switched. A graph 72 in FIG. 7 shows the time change of the voltage input to the first input k of the differential amplifier 17. Here, the case where the switches S1 and S2 are switched at a sufficiently high speed with respect to the changing speed of the magnetic flux density is illustrated, and the magnetic flux density proportional voltage VH is illustrated as being constant. As apparent from FIG. 4, when both the switches S1 and S2 are turned on when the switches S1 and S2 are switched, the first input k is grounded. The graph 72 shows a transient change to the ground voltage during the period from the voltage of the fourth terminal in the first mode to the voltage of the third terminal in the second mode, and the graph of the third terminal in the second mode. A state in which the voltage is transiently changed to the ground voltage during the period from the voltage to the voltage at the fourth terminal in the first mode is shown. A graph 74 in FIG. 7 shows the time change of the voltage input to the second input m of the differential amplifier 17. As apparent from FIG. 4, when both the switches S1 and S2 are turned on when the switches S1 and S2 are switched, the power supply voltage VCC is applied to the second input m. The graph 74 shows a transition from the voltage at the second terminal in the first mode to the voltage at the first terminal in the second mode, which changes transiently to the power supply voltage VCC, and the first terminal in the second mode. It shows a state in which the power supply voltage VCC is transiently changed from the current voltage to the voltage of the second terminal in the first mode.

  (N) of FIG. 7 shows the voltage difference between the first input k and the second input m. If a phenomenon occurs in which both the switches S1 and S2 are turned on when the switches S1 and S2 are switched, the voltage difference once becomes −VCC, and then, from the fourth terminal voltage shown in the equation (1a), the equation (2a) shows. The value is obtained by subtracting the second terminal voltage (when the first mode is entered). Or it becomes -VCC once, and becomes the value which reduced the 1st terminal voltage shown in Formula (3a) from the 3rd terminal voltage shown in Formula (4a) after that (when it will be in the 2nd mode). The differential amplifier 17 outputs a voltage obtained by amplifying the voltage difference. The output of the differential amplifier 17 is affected by the transient period, resulting in a measurement error. Alternatively, due to the influence of the transition period, a voltage outside the range that can be handled by the differential amplifier 17 is applied to the differential amplifier 17, or the output voltage is saturated and a circuit reset process is required. .

  If the phenomenon in which both the switches S1 and S2 are turned on occurs when the switches S1 and S2 are switched, and the output voltage of the differential amplifier 17 is transiently affected by the power supply voltage VCC or the ground voltage, the improvement in FIG. It is preferable to apply.

In the circuit of FIG. 8, the circuits indicated by reference numerals 36, 38, and 40 are added to the circuit of FIG. A duplicate description of the parts common to FIG. 4 is omitted.
Reference numeral 36 is a sample-and-hold circuit that receives the voltage immediately before the switch S1 is turned off (fourth terminal voltage in the first mode) and the switch S2 that is turned on and the third terminal voltage in the second mode. The voltage immediately before the switch S2 is turned off (the third terminal voltage in the second mode) is set so that the switch S1 is turned on and the fourth terminal voltage in the first mode is input. Hold until. Reference numeral 38 is also a sample and hold circuit, and the voltage just before the switch S1 is turned off (second terminal voltage in the first mode) is input, and the switch S2 is turned on and the first terminal voltage in the second mode is input. The voltage immediately before the switch S2 is turned off (the first terminal voltage in the second mode) is maintained, and the switch S1 is turned on and the second terminal voltage in the first mode is input. Hold until.

FIG. 9 shows a circuit configuration of the sample hold circuit 36. The same applies to the sample hold circuit 38. The circuit 36 will be described below.
As shown in (b), the clock signal CLK2B becomes low at the timing t1 immediately before the switch S1 is turned off and shifts to the second mode, and the switch S2 is turned on and the third terminal voltage in the second mode is stabilized. Then, it becomes high at the timing t2 at which input is started, goes low at the timing t3 immediately before the switch S2 is turned off and shifts to the first mode, the switch S1 is turned on, and the fourth terminal voltage in the first mode is stabilized. It goes high at the timing t4 when the input starts.
While the clock signal CLK2B is high, the switch M1 is turned on, and the voltage input to IN is output to OUT as it is. When the switch S2 is turned on to shift to the second mode and the third terminal voltage starts to be input stably (after timing t2), the third terminal voltage is output as it is. Similarly, when the switch S1 is turned on to shift to the first mode and the fourth terminal voltage starts to be stably input (after timing t4), the fourth terminal voltage is output as it is.
While the clock signal CLK2B is low, the switch M1 is turned off, and the voltage of the capacitor CH is output to OUT. The voltage of the capacitor CH is equal to the voltage input to IN immediately before the switch M1 is turned off. Between timings t1 and t2, the voltage (the fourth terminal voltage in the first mode) input to IN at timing t1 is output to OUT. Between timings t3 and t4, the voltage (the third terminal voltage in the second mode) input to IN at timing t3 is output to OUT.
As will be described later, the output voltages of the sample and hold circuits 36 and 38 are applied to the gate of the MOS. Therefore, it is not necessary to incorporate an operational amplifier that operates as a voltage follower in the sample and hold circuits 36 and 38. The sample and hold circuits 36 and 38 need only have a simple circuit configuration.

  The switch M1 is a MOS type, and the amount of charge charged in the gate changes when the switch M1 is turned on and off, and the change in the amount of charge affects the voltage of the capacitor CH. In order to remove the influence, a dummy switch M2 is provided. The dummy switch M2 operates with the clock signal CLK2 obtained by inverting the clock signal CLK2B. At the timing when the charge of the capacitor CH decreases by the switch M1, the dummy switch M2 injects the charge into the capacitor CH, and the switch M1 changes the charge of the capacitor CH. At the increasing timing, the dummy switch M2 decreases the charge of the capacitor CH. Although the dummy switch M2 is involved in charge injection / release, it does not have a switch function, and the capacitors CH and OUT are always connected.

A graph 92 in FIG. 10 shows the output voltage of the sample hold circuit 36. The influence of the ground voltage generated when the switches S1 and S2 are switched is removed, and the fourth terminal voltage in the first mode and the third terminal voltage in the second mode are alternately input. Similarly, the influence of the power supply voltage generated when the switches S1 and S2 are switched is removed from the output voltage (graph 94) of the sample hold circuit 38, and the second terminal voltage in the first mode and the first voltage in the second mode are removed. Terminal voltage is input alternately.
FIG. 10 (n) shows a voltage difference between the first input k and the second input m. The influence of the power supply voltage and the ground voltage generated when the switches S1 and S2 are switched is removed, and the third terminal voltage and the first terminal voltage in the second mode are determined from the voltage difference between the fourth terminal voltage and the second terminal voltage in the first mode. The voltage difference changes smoothly. Centered around the element offset voltage (VOFF), a period in which the positive magnetic flux density proportional voltage is superimposed (the first mode and the subsequent switch switching period), and a period in which the negative magnetic flux density proportional voltage is superimposed (the second mode and it) The following switch switching periods) come alternately. As described above, the differential amplifier 17 removes a DC voltage component (element offset voltage (VOFF)) and amplifies a voltage difference that varies with time. A voltage obtained by amplifying VH is output. According to this embodiment, the influence of the element offset voltage (VOFF) can be removed, the influence of the power supply voltage (VCC) can be removed, and the influence of the ground voltage (GRD) can be removed.

Reference numeral 40 in FIG. 8 is a buffer circuit, the details of which are shown in FIG. Here, Vb is a bias voltage, and is set between the power supply voltage Vcc and the ground voltage GRD. The bias voltage Vb is set to a magnitude that allows a constant current to flow through the upper MOS in the buffer circuit 40. The output voltage OUT of the sample hold circuit 36 is input to IN +, the output voltage OUT of the sample hold circuit 38 is input to IN−, and OUT + is connected to the first input k of the differential amplifier circuit 17. OUT− is connected to the second input m of the differential amplifier circuit 17.
The buffer circuit 40 is a source follower circuit, and separates the resistance of the magnetic detection element 4 and the input capacitance (C1, C3) of the differential amplifier 17. When the buffer circuit 40 is added, the input impedance up to the differential amplifier 17 is lowered, and the responsiveness to the time of the voltage input to the first input k and the second input m of the differential amplifier 17 is improved. In this example, the input impedance was reduced from the 10 kΩ level to the 10 Ω level.
FIG. 12 shows the time change of the voltage input to the first input k when shifting from the first mode to the second mode. “Hold” indicates a period during which the sample hold circuit 36 is holding. When the holding time ends, the voltage input to the first input k changes from the fourth terminal voltage in the first mode to the third terminal voltage in the second mode.

  A graph 98 shows a case where the buffer circuit 40 is not used, and it takes time to change from the fourth terminal voltage in the first mode to the third terminal voltage in the second mode. A graph 96 shows a case where the buffer circuit 40 is used, and shifts to the third terminal voltage in the second mode in a short time. By using a buffer circuit, the transition period due to mode switching is shortened, the waiting time until a voltage useful for determining the magnetic flux density can be detected can be shortened, and the detection delay time can be shortened. it can. In addition, a period during which a voltage useful for determining the magnetic flux density can be measured becomes longer.

The sample periods of the sample and hold circuits 30 and 32 are preferably set within the sample period of the sample and hold circuits 36 and 38. For example, the sample hold circuits 30 and 32 enable the voltage during the period indicated by B in FIG. 9B and hold the voltage during periods other than B. By doing so, it is possible to eliminate the ripple effect that occurs during mode switching and the ripple effect that occurs during demodulation.
FIG. 13A shows a clock CLK signal for switching the switches S1 and S2. (B) shows the clock signal CLK2 instructing the sample and hold circuits 36 and 38. While the clock signal CLK2 is high, it is held, and when it is low, the input voltage is output. (C) shows the clock signal CLK3 instructing the demodulator (output side switch). (d) shows the clock signal MASK3 instructing the sample and hold circuits 30 and 32. While the clock signal is high, it is held and when it is low, the input voltage is output. A period for outputting the input voltage is called a sampling period. During the sampling periods T1 and T2 of the sample and hold circuits 30 and 32, a voltage that enables the sample and hold circuits 36 and 38 to determine the current magnetic flux density proportional voltage VH is output, and the switches S1 and S2 are switched. This corresponds to a period in which the influence of the power supply voltage and the ground voltage that sometimes occurs is eliminated, and the ripple that occurs at the demodulation timing is also lost. The measured values in the sampling periods T1, T2 make it possible to determine the magnetic flux density proportional voltage VH at that time. According to the circuits shown in FIGS. 8 and 13, it is possible to remove the influence of the element offset voltage, the power supply voltage, the ground voltage, the ripple at the time of demodulation, and measure the magnetic flux density proportional voltage VH at that time without time delay. And In this embodiment, a sample hold circuit is used. The sample-and-hold circuit does not use the held value later (a time delay occurs in such a usage method), but is for removing the influence of noise and ripple. In the periods T1 and T2, the magnetic flux density can be measured without time delay.

The buffer circuit 40 is also useful when the sample hold circuits 36 and 38 are unnecessary. An embodiment in which the sample hold circuits 36 and 38 are not added but the buffer circuit 40 is added is also useful. For example, in FIG. 14, when the energizing switches S1 and S2 are switched at different timings, the energizing switches S1 and S2 for switching modes and the input switches S3 and S4 for modulating the magnetic flux density proportional voltage are switched at different timings. An embodiment is shown in which the power supply voltage or the like is prevented from affecting the voltage input to the differential amplifier. In this embodiment, the sample hold circuits 36 and 38 are not added, but the buffer circuit 40 is added.
In the circuit of FIG. 14, the switch S1 is switched by the clock signal CLK1, and the switch S2 is switched by the inverted clock signal CLK1B (the waveform is not shown). In order to generate a clock signal for instructing the input switches S3 and S4, a clock signal CLK2B is prepared. A clock signal CLK4 is generated from the clock signal CLK1 and the clock signal CLK2B, and the switch S3 is switched by the clock signal CLK4. A clock signal CLK5 is generated from a clock signal CLK1B and a clock signal CLK2B (not shown), and the switch S4 is switched by the clock signal CLK5.

  According to the present embodiment, the sample hold circuits 36 and 38 are not required to input the voltage after the influence of the power supply voltage and the ground voltage associated with the mode switching to the buffer circuit 40 is input. Even in such a case, it is effective to use the buffer circuit 40 to increase the rate of change of the voltage input to the differential amplifier 17 with respect to time.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.
The technical scope of the claims described below is not limited to the examples. The examples are merely illustrative.

1: power supply 2: energization switch 4: magnetic detection element 26: input side switch 16: operational amplifier C1, C2, C3, C4: feedback capacitor 17: differential amplifier 28: output side switch T1: first output terminal T2: first 2 output terminal 36: switch switching circuit S1, S2: switch 30 which one is turned on, the other is turned off 30, 32: sample hold circuit 34: differential circuit 36 having a low pass filter circuit 38: sample hold circuit 40: buffer circuit

Claims (7)

A power source, an energizing switch, a magnetic detection element, an input side switch, a fully differential charge amplifier , an output side switch, a first output terminal, a second output terminal, and a switch switching circuit;
The magnetic detection element includes at least a first terminal to a fourth terminal,
(1) When energized between the first terminal and the third terminal, a voltage including a voltage component proportional to a magnetic flux density and an element offset voltage component is output between the second terminal and the fourth terminal,
(2) When energized between the second terminal and the fourth terminal, a voltage including a voltage component proportional to a magnetic flux density and an element offset voltage component is output between the first terminal and the third terminal,
The fully differential charge amplifier includes a first input, a second input, a first output, and a second output, and a voltage difference obtained by amplifying a voltage difference between the first input and the second input is the first difference. Occurs between one output and the second output;
The switch switching circuit is
(1) The energizing switch connects a power source and the first terminal to connect the third terminal to a ground line, and the input-side switch connects the fourth terminal to the first input and the second terminal. A state in which a terminal is connected to the second input, and the output-side switch connects the first output to the first output terminal and connects the second output to the second output terminal;
(2) The energizing switch connects a power source and the second terminal to connect the fourth terminal to a ground line, and the input-side switch connects the third terminal to the first input and connects the first terminal. The terminal is connected to the second input, and the output side switch alternately switches the state in which the first output is connected to the second output terminal and the second output is connected to the first output terminal. A magnetic detection circuit. Each of the energizing switch, the input side switch, and the output side switch includes a switch pair that turns off when one is turned on,
The magnetic detection circuit according to claim 1, wherein the switch pair of the energization switch, the input side switch, and the output side switch is inverted simultaneously. The magnetic detection element comprises 5 or more terminals;
The magnetic detection circuit according to claim 1, wherein the circuit according to claim 1 is connected to four of the terminals. A first sample and hold circuit is inserted before the first input of the fully differential charge amplifier ;
A second sample-and-hold circuit is inserted before the second input of the fully differential charge amplifier ;
4. The device according to claim 2, wherein the first sample hold circuit and the second sample hold circuit hold values immediately before switching between the energization switch and the input side switch until after the switching is completed. The magnetic detection circuit according to 1 above. The magnetic detection circuit according to claim 4, wherein a buffer circuit is inserted between the first sample hold circuit, the second sample hold circuit, and the fully differential charge amplifier . The switch switching circuit is
(1) The energizing switch connects the power source and the first terminal to connect the third terminal to the ground line, and then the input-side switch connects the fourth terminal to the first input. A state in which the second terminal is connected to the second input, and the output-side switch connects the first output to the first output terminal and connects the second output to the second output terminal;
(2) The energizing switch connects the power source and the second terminal to connect the fourth terminal to the ground line, and then the input-side switch connects the third terminal to the first input. The first terminal is connected to the second input, and the output side switch alternately connects the first output to the second output terminal and connects the second output to the first output terminal. The magnetic detection circuit according to claim 1, wherein switching is performed. The magnetic detection circuit according to claim 6, wherein a buffer circuit is inserted between the input side switch and the fully differential charge amplifier .

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