JP6156038B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Nitride semiconductors typified by GaN, AlN, InN, and mixed crystals thereof have attracted a great deal of attention as high-power electronic devices and short-wavelength light-emitting devices because of their excellent material characteristics. For example, as high-power electronic devices, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMT). The HEMT can be used for applications such as a high-power / high-efficiency amplifier and a high-power switching device. In addition, research on a two-terminal device such as a Schottky Barrier Diode (SBD) is underway.

JP 2007-134456 A Japanese Patent Laid-Open No. 1-261871

  The formation process of the gate electrode in the HEMT is positioned as an important process for determining device characteristics. In particular, the interface state caused by the process residue or process damage in the previous step is preferably reduced as much as possible in order to cause gate leakage current and hysteresis characteristics and suppress deterioration of characteristics and deterioration of reliability. Also in SBD, the formation process of the anode electrode having a Schottky junction is positioned as an important process for the same reason as the formation process of the gate electrode of the HEMT.

In the HEMT, there are so-called enhancement type (E-mode) transistors and depletion type (D-mode) transistors. In the E-mode transistor, it is advantageous to use a metal (Ti, Ta, etc.) having a low work function as the gate electrode. In the D-mode transistor, it is advantageous to use a metal (Ni, Pt, Cu, etc.) having a high work function as the gate electrode.
In the SBD, since a low turn-on voltage is required for the anode electrode, it is necessary to use a metal (Ti, Al, etc.) having a low work function.

  Ti or the like, which is a metal having a low work function, is usually deposited by sputtering. However, when it is deposited on a compound semiconductor layer such as GaN or AlGaN, its surface is greatly damaged by sputtering. Due to this damage, there is a problem that the characteristic deterioration due to the interface state and the reliability deterioration occur as described above.

  The present invention has been made in view of the above problems, and can easily and reliably suppress the generation of an interface state between an electrode and a semiconductor layer, and manufacture a highly reliable semiconductor device having excellent device characteristics. It aims to provide a method.

One aspect of a method for manufacturing a semiconductor device includes a step of forming an insulating film having an opening above a semiconductor layer, a step of depositing a first metal on the insulating film so as to fill the opening, Forming a second metal, which is a metal having a work function lower than that of the first metal , only on a portion of the first metal that is aligned above the opening; processing the first metal; and Forming a metal layer that fills the opening with the first metal under the metal, and performing heat treatment at a temperature lower than the melting point of the second metal, and depositing the second metal in a lower layer portion. Forming the step.

One embodiment of a method for manufacturing a semiconductor device includes a step of forming an insulating film having a first opening in a first region and a second opening in a second region above the semiconductor layer, and the first opening and The first metal is deposited on the insulating film so as to embed the second opening, and work is performed more than the first metal only in a position aligned above the first opening on the first metal. Forming a second metal having a low function; processing the first metal; and filling the first region with the first metal under the second metal in the first region the layers in the second region and forming a second metal layer filling the second opening with said first metal, at above the semiconductor layer, wherein the first region third metal of the third metal Forming a layer, a fourth metal layer of the third metal in the second region; Heat treatment is performed at a temperature lower than the melting point of the second metal, and in the first region, a first Schottky electrode formed by depositing the second metal in a lower layer portion of the first metal layer, and the third A first ohmic electrode in which the metal layer is in ohmic contact with the semiconductor layer; a second Schottky electrode of the second metal layer in the second region; and a fourth metal layer in ohmic contact with the semiconductor layer. Forming a second ohmic electrode.

  According to each aspect described above, the generation of the interface state between the electrode and the semiconductor layer can be easily and reliably suppressed, and a highly reliable semiconductor device having excellent device characteristics can be realized.

It is a schematic sectional drawing which shows the manufacturing method of the compound semiconductor device by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view illustrating the method of manufacturing the compound semiconductor device according to the first embodiment in order of processes subsequent to FIG. 1. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the compound semiconductor device by 2nd Embodiment. FIG. 4 is a schematic cross-sectional view showing main steps of the method for manufacturing the compound semiconductor device according to the second embodiment following FIG. 3. FIG. 5 is a schematic cross-sectional view showing main steps of the method for manufacturing the compound semiconductor device according to the second embodiment following FIG. 4. It is a schematic sectional drawing which shows the manufacturing method of the compound semiconductor device by 3rd Embodiment to process order. FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the compound semiconductor device according to the third embodiment in order of processes subsequent to FIG. 6. FIG. 8 is a schematic cross-sectional view showing the method of manufacturing the compound semiconductor device according to the third embodiment in order of processes subsequent to FIG. 7. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the compound semiconductor device by 4th Embodiment. FIG. 10 is a schematic cross-sectional view showing the main steps of the method for manufacturing the compound semiconductor device according to the fourth embodiment following FIG. 9. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the compound semiconductor device by 5th Embodiment. FIG. 12 is a schematic cross-sectional view showing main steps of the method for manufacturing the compound semiconductor device according to the fifth embodiment following FIG. 11. It is a characteristic view which shows the relationship between the gate-source voltage (Vgs) and the drain current (Id) about the compound semiconductor device produced by 5th Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the compound semiconductor device by 6th Embodiment. FIG. 15 is a schematic cross-sectional view showing main steps of the method for manufacturing the compound semiconductor device according to the sixth embodiment following FIG. 14. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the compound semiconductor device by 7th Embodiment. FIG. 17 is a schematic cross-sectional view showing the main steps of the method for manufacturing the compound semiconductor device according to the seventh embodiment, following FIG. 16. FIG. 18 is a schematic cross-sectional view showing the main steps of the method for manufacturing the compound semiconductor device according to the seventh embodiment, following FIG. 17. It is a connection diagram which shows schematic structure of the power supply device by 8th Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 9th Embodiment.

Hereinafter, various aspects of the compound semiconductor device will be described in detail with reference to the drawings together with the manufacturing method thereof.
In the following drawings, there are constituent members that are not shown in a relatively accurate size and thickness for convenience of illustration.
Further, in the following embodiments, an element isolation step for defining each element structure is appropriately performed, but a specific description is omitted. In the element isolation step, element isolation is performed by implanting argon (Ar) or the like into the element isolation region of the compound semiconductor stacked structure, or using an STI (Shallow Trench Isolation) method.

(First embodiment)
In the present embodiment, a device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated on the same substrate is disclosed as a compound semiconductor device.
1 to 2 are schematic cross-sectional views showing the method of manufacturing the compound semiconductor device according to the first embodiment in the order of steps.

First, as shown in FIG. 1A, a compound semiconductor multilayer structure 2 is formed on, for example, a semi-insulating SiC substrate 1 as a growth substrate. As the growth substrate, a Si substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the SiC substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor multilayer structure 2 includes a buffer layer 2a, an electron transit layer 2b, an intermediate layer 2c, and an electron supply layer 2d.

  In the AlGaN / GaN.HEMT, two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2b and the electron supply layer 2d (more precisely, the intermediate layer 2c) during the operation. This 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 2b and the compound semiconductor (here, AlGaN) of the electron supply layer 2d.

More specifically, the following compound semiconductors are grown on the SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the SiC substrate 1, AlN is about 200 nm thick, i (Intensive Undoped) -GaN is about 3 μm thick, i-AlGaN is about 5 nm thick, and n-AlGaN is about 30 nm thick. Grows sequentially. Thereby, the buffer layer 2a, the electron transit layer 2b, the intermediate layer 2c, and the electron supply layer 2d are formed. As the buffer layer 2a, AlGaN may be used instead of AlN, or GaN may be grown at a low temperature.

As growth conditions for AlN, a mixed gas of trimethylaluminum (TMAl) gas and ammonia (NH ₃ ) gas is used as a source gas. As a growth condition for GaN, a mixed gas of trimethylgallium (TMGa) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMAl gas as an Al source and TMGa gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing the AlGaN of the electron supply layer 2d as n-type, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

Subsequently, as shown in FIG. 1B, the gate electrode 3A is simultaneously formed on the HEMT side, and the electrode layer 3a is simultaneously formed on the SBD side.
Specifically, first, the surface of the compound semiconductor multilayer structure 2 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 2, it is possible to obtain a good surface (becomes an interface with various electrodes described later) having extremely low interface states.

  Next, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied on the compound semiconductor multilayer structure 2, and the resist is processed by lithography to form openings that expose the planned site for forming the gate electrode on the HEMT side and the planned site for forming the anode electrode on the SBD side. Thus, a resist mask having each opening is formed.

In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Using the resist mask, Ni / Au as the first metal is deposited on the resist mask including the inside of each opening exposing the surface of the compound semiconductor multilayer structure 2 by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. As described above, the gate electrode 3A, which is a Schottky electrode, is simultaneously formed on the HEMT side, and the electrode layer 3a is simultaneously formed on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 1C, the upper layer portion 3b is formed only on the electrode layer 3a on the SBD side.
Specifically, first, a resist mask for forming the upper layer portion is formed. A resist is applied to the entire surface, and the resist is processed by lithography to form an opening exposing only the upper surface of the electrode layer 3a on the SBD side. Thus, a resist mask having the opening is formed.

In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Using the resist mask, Ti as the second metal is deposited on the resist mask including the inside of the opening exposing the upper surface of the electrode layer 3a by, for example, vapor deposition. The thickness of Ti is about 30 nm. The resist mask and Ti deposited thereon are removed by a lift-off method. As a result, the upper layer portion 3b serving as a cap layer is formed only on the electrode layer 3a on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 2A, the source electrode 4A and the drain electrode 4B are simultaneously formed on the HEMT side, and the cathode electrode 4C is simultaneously formed on the SBD side.
Specifically, first, a resist mask for forming the source electrode 4A, the drain electrode 4B, and the cathode electrode 4C is formed. Resist is applied to the entire surface of the compound semiconductor multilayer structure 2, and the resist is processed by lithography to expose the planned site for forming the source and drain electrodes on the HEMT side and the planned site for forming the cathode electrode on the SBD side. Form. Thus, a resist mask having each opening is formed.

Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer and Al is the upper layer) is deposited on the resist mask including the inside of each opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thus, the source electrode 4A and the drain electrode 4B are formed on the HEMT side, and the cathode electrode 4C is formed on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 2B, a passivation film 5 is formed.
Specifically, an insulating film such as SiN is deposited on the entire surface of the compound semiconductor multilayer structure 2 to a thickness of about 2 nm to 200 nm by a plasma CVD method or the like. Thereby, the passivation film 5 is formed.

Subsequently, as shown in FIG. 2C, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal that is the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 550 ° C. (Annealing). By this heat treatment, ohmic contact with the electron supply layer 2d is established with respect to the source electrode 4A and the drain electrode 4B on the HEMT side and with respect to the cathode electrode 4C on the SBD side, respectively, which become ohmic electrodes. At the same time, by the heat treatment, Ti in the upper layer portion 3b diffuses downward into the electrode layer 3a on the SBD side, Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 3a, and lower layer portion 3c. Is formed. The lower layer portion 3c is formed with a thickness of about 1 nm to 2 nm, for example. The electrode layer 3a, the upper layer portion 3b, and the lower layer portion 3c form an anode electrode 3B that is a Schottky electrode.

  In the present embodiment, the heat treatment for forming the anode electrode 3B by thermally diffusing Ti is performed in combination with the heat treatment for obtaining the ohmic contact of the source electrode 4A, the drain electrode 4B, and the cathode electrode 4C. As a result, it is not necessary to provide a heat treatment step for forming the anode electrode 3B, and the number of steps can be reduced.

  Thereafter, various processes such as formation of an interlayer insulating film, the shape of each wiring connected to the gate electrode 3A, the source electrode 4A, the drain electrode 4B, the anode electrode 3B, and the cathode electrode 4C are performed. Thus, a compound semiconductor device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated is formed on the SiC substrate 1.

  In this embodiment, an upper layer portion made of a second metal such as Ti is formed only on an electrode that requires a low work function, and Ti or the like is deposited on the lowermost surface of the electrode by heat treatment. As a result, it is possible to form an electrode (in this embodiment, the anode electrode 3B) having a different work function and a good bottom surface (interface with the compound semiconductor multilayer structure) with few interface states.

  In Patent Document 1, the work function is reduced by the diffusion of In or the like into Si for the purpose of separately creating the threshold voltage of the Si semiconductor device. However, in this case, a low melting point metal such as In, Ga, Tl or the like is used as the metal to be diffused, and the heat treatment is performed at a temperature higher than the melting point of the metal. The compound semiconductor device as in this embodiment is characterized by being capable of high-temperature operation. When a low-melting point metal such as In is present at the Schottky interface, characteristic degradation due to reaction with other metals and semiconductors and It causes a decrease in reliability. Therefore, the technique of Patent Document 1 cannot be applied to this embodiment.

  In the present embodiment, particularly considering application to a compound semiconductor device, a metal material having a high melting point, a low work function, and capable of thermal diffusion by heat treatment at a temperature lower than the melting point is selected as a suitable second metal. We studied as hard as possible. As a result, it has been found that a metal selected from Ti, Mo, Ta, W and the like is the best metal material as the second metal. In particular, Ti has a melting point as high as about 1660 ° C. and a work function as low as about 4.3 eV. As a first metal having a high work function, Ti is deposited on, for example, Ni widely used as a gate material of a GaN-based transistor, and at a temperature of about 600 ° C. sufficiently lower than the melting point (550 ° C. is exemplified in this embodiment). Heat treatment. Thereby, it was grasped that Ti diffuses downward into Ni and selectively precipitates at the interface with the Ni compound semiconductor layer. From this result, it was shown that the high work function Ni electrode and the low work function Ti electrode can be separately formed depending on the presence or absence of the Ti cap layer. The base first metal can be formed simultaneously as an electrode layer common to the two types of electrodes.

  In the present embodiment, when the above two types of electrodes are formed on the same substrate, a first metal such as Ni is deposited by vapor deposition without directly depositing Ti or the like on the compound semiconductor layer. . For one electrode, a high work function is realized with the first metal. With respect to the other electrode, after depositing a second metal such as Ti on the first metal, the second metal is diffused into the first metal to substantially achieve a low work function. As a result, it is possible to form the surface of the compound semiconductor layer in a favorable interface state free from process residues and process damage using the same process and with as few processes as possible.

  As described above, according to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and surely suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized. To do.

(Second Embodiment)
In the present embodiment, as in the first embodiment, as a compound semiconductor device, a device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated on the same substrate is disclosed, but the configuration of each electrode is different. This is different from the first embodiment. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
3 to 5 are schematic cross-sectional views illustrating main processes of the method for manufacturing the compound semiconductor device according to the second embodiment.

  In the present embodiment, as in the first embodiment, first, the process of FIG. At this time, the compound semiconductor multilayer structure 2 is formed on the SiC substrate 1.

Subsequently, as shown in FIG. 3A, an insulating film 11 is formed.
Specifically, first, the surface of the compound semiconductor multilayer structure 2 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 2, it is possible to obtain a good surface (becomes an interface with various electrodes described later) having extremely low interface states.

  Next, for example, SiN is deposited on the entire surface of the compound semiconductor multilayer structure 2 to a thickness of about 100 nm by a plasma CVD method or the like. A resist is applied to the entire surface of the deposited SiN, and the resist is processed by lithography to form openings that expose the HEMT gate electrode formation planned site and the SBD anode electrode formation planned site. Thus, a resist mask having each opening is formed.

SiN is dry etched using this resist mask. Thereby, in SiN, the opening which exposes the surface of the compound semiconductor laminated structure 2 is formed in the site where the HEMT gate electrode is to be formed and the site where the SBD anode electrode is to be formed. Thus, the insulating film 11 having the openings 11a and 11b is formed.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 3B, Ni / Au 12 is deposited.
In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Ni / Au 12 is deposited on the insulating film 11 so as to fill the openings 11a and 11b, for example, by sputtering. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm.

Subsequently, as shown in FIG. 3 (c), the upper layer portion 13b is formed only at the position aligned above the opening 11b.
In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Ti is deposited on the entire surface of the insulating film 11 by, eg, sputtering. The thickness of Ti is about 30 nm. A resist is applied on the deposited Ti, and the resist is processed by lithography to leave the resist so as to cover a position aligned above the opening 11b on the SBD side. Thus, a resist mask is formed.

Using this resist mask, Ti is removed by dry etching. As described above, Ti remains only in the position aligned above the opening 11b on the SBD side, and the upper layer portion 13b serving as the cap layer is formed.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 4A, the gate electrode 13A and the electrode layer 13a are simultaneously formed on the HEMT side and the SBD side, respectively.
Specifically, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied onto the Ni / Au 12 and the upper layer portion 13b, and the resist is processed by lithography, so that the resist is left so as to cover the portion where the gate electrode is to be formed on the HEMT side and the upper layer portion 13b on the SBD side. Thus, a resist mask is formed.

Using this resist mask, Ni / Au 12 is removed by ion milling and dry etching. Thus, the gate electrode 13A made of Ni / Au 12 remaining on the HEMT side and the electrode layer 13a made of Ni / Au 12 remaining under the upper layer portion 13b are simultaneously formed on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 4B, an interlayer insulating film 14 is formed.
Specifically, an insulating film such as SiO ₂ is deposited on the entire surface of the insulating film 11 to a thickness of about 500 nm by a CVD method or the like. Thereby, the interlayer insulating film 14 is formed.

Subsequently, as shown in FIG. 4C, openings 15 a, 15 b, and 15 c are formed in the insulating film 11 and the interlayer insulating film 14.
Specifically, a resist is applied to the entire surface of the interlayer insulating film 14, and the resist is processed by lithography. A source electrode formation planned portion and a drain electrode formation planned portion are formed on the HEMT side, and a cathode electrode is formed on the SBD side. Each opening that exposes the site is formed. Thus, a resist mask having each opening is formed.

Using this resist mask, the insulating film 11 and the interlayer insulating film 14 are dry-etched. As a result, in the insulating film 11 and the interlayer insulating film 14, openings 15 a and 15 b that expose the surface of the compound semiconductor multilayer structure 2 are formed at the site where the source electrode is to be formed and the region where the drain electrode is to be formed on the HEMT side. . On the SBD side, an opening 15 c that exposes the surface of the compound semiconductor multilayer structure 2 is formed at a site where the cathode electrode is to be formed.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 5A, the source electrode 15A and the drain electrode 15B are simultaneously formed on the HEMT side, and the cathode electrode 15C is simultaneously formed on the SBD side.
Specifically, first, as an electrode material, for example, Ti / Al (Ti is the lower layer and Al is the upper layer) is deposited on the interlayer insulating film 14 so as to fill the openings 15a, 15b, and 15c by, for example, sputtering. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm.

  A resist is applied on the deposited Ti, and the resist is processed by lithography. The HEMT side is aligned only above the opening 15a and above the opening 15b, and the SBD side is positioned above the opening 15c. Leave the resist only. Thus, a resist mask is formed.

Using this resist mask, Ti / Al is removed by dry etching. Thus, the source electrode 15A and the drain electrode 15B are formed on the HEMT side, and the cathode electrode 15C is formed on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 5B, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal as the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 650 ° C. (Annealing). This heat treatment establishes ohmic contact with the electron supply layer 2d for the source electrode 15A and the drain electrode 15B on the HEMT side and for the cathode electrode 15C on the SBD side, respectively. At the same time, Ti in the upper layer portion 13b diffuses downward into the electrode layer 13a on the SBD side, and Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 13a. Is formed. The lower layer portion 13c is formed to a thickness of about 1 nm to 2 nm, for example. The electrode layer 13a, the upper layer portion 13b, and the lower layer portion 13c form an anode electrode 13B.

  In the present embodiment, the heat treatment for thermally diffusing Ti to form the anode electrode 13B is performed in combination with the heat treatment for obtaining ohmic contacts of the source electrode 15A, the drain electrode 15B, and the cathode electrode 15C. Thereby, it is not necessary to provide a single heat treatment step for forming the anode electrode 13B, and the number of steps can be reduced.

  Thereafter, various processes such as formation of an interlayer insulating film and the shape of each wiring connected to the gate electrode 13A, the source electrode 15A, the drain electrode 15B, the anode electrode 13B, and the cathode electrode 15C are performed. Thus, a compound semiconductor device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated is formed on the SiC substrate 1.

  According to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and reliably suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized.

(Third embodiment)
In the present embodiment, as in the first embodiment, as a compound semiconductor device, a device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated on the same substrate is disclosed, but the compound semiconductor multilayer structure is on the SBD side. It is different in different points. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
6 to 8 are schematic cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the third embodiment in the order of steps.

First, as shown in FIG. 6A, a compound semiconductor multilayer structure 21 is formed on, for example, a semi-insulating SiC substrate 1 as a growth substrate. As the growth substrate, a Si substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the SiC substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor multilayer structure 21 includes a buffer layer 21a, an electron transit layer 21b, an intermediate layer 21c, an electron supply layer 21d, and an n-GaN layer 21e.

  In the AlGaN / GaN.HEMT, two-dimensional electron gas (2DEG) is generated in the vicinity of the interface between the electron transit layer 21b and the electron supply layer 21d (more precisely, the intermediate layer 21c) during the operation. This 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 21b and the compound semiconductor (here, AlGaN) of the electron supply layer 21d.

Specifically, the following compound semiconductors are grown on the SiC substrate 1 by, for example, the MOVPE method. The MBE method or the like may be used instead of the MOVPE method.
On the SiC substrate 1, AlN is about 200 nm thick, i (Intensive Undoped) -GaN is about 3 μm thick, i-AlGaN is about 5 nm thick, and n-AlGaN is about 30 nm thick. , N-GaN is sequentially grown to a thickness of about 200 nm. Thereby, the buffer layer 21a, the electron transit layer 21b, the intermediate layer 21c, the electron supply layer 21d, and the cap layer 21e are formed. As the buffer layer 21a, AlGaN may be used instead of AlN, or GaN may be grown at a low temperature.

As a growth condition of AlN, a mixed gas of TMAl gas and NH ₃ gas is used as a source gas. As a growth condition of GaN, a mixed gas of TMGa gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMAl gas as an Al source and TMGa gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When the AlGaN and n-GaN layers 21e of the electron supply layer 21d are grown as n-type, for example, SiH ₄ gas containing, for example, Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si and GaN are added to the GaN and AlGaN. Doping. The doping concentration of Si in the electron supply layer 21d is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ . The doping concentration of Si in the n-GaN layer 21e is set to a relatively low concentration, for example, about 2 × 10 ¹⁷ / cm ³ .

Subsequently, as shown in FIG. 6B, the n-GaN layer 21e is processed and left only on the SBD side.
Specifically, a resist is applied to the entire surface of the n-GaN layer 21e, and the resist is processed by lithography to form a resist mask that covers the SBD side on the surface of the n-GaN layer 21e and exposes the HEMT side.
Using this resist mask, the n-GaN layer 21e is dry-etched. Chlorine etching gas is used for dry etching. In the n-GaN layer 21e, the HEMT side portion is removed, and only the SBD side portion remains.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

  In the present embodiment, in the compound semiconductor multilayer structure 21, the n-GaN layer 21e is formed only on the SBD side. Due to the relatively thick n-GaN layer 21e, each electrode formed on the n-GaN layer 21e is greatly separated from 2DEG. With this configuration, the influence of 2DEG in AlGaN / GaN SBD is eliminated as much as possible, and a highly reliable SBD can be obtained.

Subsequently, as shown in FIG. 6C, the gate electrode 3A is simultaneously formed on the HEMT side and the electrode layer 3a is simultaneously formed on the SBD side.
Specifically, first, the surface of the compound semiconductor multilayer structure 21 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 21, it is possible to obtain a good surface (becomes an interface with various electrodes to be described later) with very few interface states.

  Next, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied onto the compound semiconductor multilayer structure 21, and the resist is processed by lithography to form openings that expose the planned formation site of the gate electrode on the HEMT side and the planned formation site of the anode electrode on the SBD side. Thus, a resist mask having each opening is formed.

In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Using the resist mask, Ni / Au as the first metal is deposited on the resist mask including the inside of each opening exposing the surface of the compound semiconductor multilayer structure 21, for example, by vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 3A is simultaneously formed on the electron supply layer 21d on the HEMT side, and the electrode layer 3a is simultaneously formed on the n-GaN layer 21e on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 7A, the upper layer portion 3b is formed only on the electrode layer 3a on the SBD side.
Specifically, first, a resist mask for forming the upper layer portion is formed. A resist is applied to the entire surface, and the resist is processed by lithography to form an opening that exposes only the upper surface of the electrode layer 3a on the SBD side. Thus, a resist mask having the opening is formed.

In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Using the resist mask, Ti as the second metal is deposited on the resist mask including the inside of the opening exposing the upper surface of the electrode layer 3a by, for example, vapor deposition. The thickness of Ti is about 30 nm. The resist mask and Ti deposited thereon are removed by a lift-off method. As a result, the upper layer portion 3b serving as a cap layer is formed only on the electrode layer 3a on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 7B, the source electrode 4A and the drain electrode 4B are simultaneously formed on the HEMT side, and the cathode electrode 4C is simultaneously formed on the SBD side.
Specifically, first, a resist mask for forming a source electrode, a drain electrode, and a cathode electrode is formed. Resist is applied to the entire surface of the compound semiconductor multilayer structure 21, and the resist is processed by lithography to expose the portions where the source and drain electrodes are to be formed on the HEMT side and the portions where the cathode electrode is to be formed on the SBD side. Form. Thus, a resist mask having each opening is formed.

Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer and Al is the upper layer) is deposited on the resist mask including the inside of each opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thus, the source electrode 4A and the drain electrode 4B are formed on the electron supply layer 21d on the HEMT side, and the cathode electrode 4C is formed on the n-GaN layer 21e on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 8A, a passivation film 5 is formed.
Specifically, an insulating film such as SiN is deposited on the entire surface of the compound semiconductor multilayer structure 21 to a thickness of about 2 nm to 200 nm by a plasma CVD method or the like. Thereby, the passivation film 5 is formed.

Subsequently, as shown in FIG. 8B, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal that is the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 550 ° C. (Annealing). This heat treatment establishes ohmic contact with the electron supply layer 2d for the source electrode 4A and the drain electrode 4B on the HEMT side and for the cathode electrode 4C on the SBD side, respectively. At the same time, by the heat treatment, Ti in the upper layer portion 3b diffuses downward into the electrode layer 3a on the SBD side, Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 3a, and lower layer portion 3c. Is formed. The lower layer portion 3c is formed with a thickness of about 1 nm to 2 nm, for example. The electrode layer 3a, the upper layer portion 3b, and the lower layer portion 3c form an anode electrode 3B.

  In the present embodiment, the heat treatment for forming the anode electrode 3B by thermally diffusing Ti is performed in combination with the heat treatment for obtaining the ohmic contact of the source electrode 4A, the drain electrode 4B, and the cathode electrode 4C. As a result, it is not necessary to provide a heat treatment step for forming the anode electrode 3B, and the number of steps can be reduced.

  Thereafter, various processes such as formation of an interlayer insulating film, the shape of each wiring connected to the gate electrode 3A, the source electrode 4A, the drain electrode 4B, the anode electrode 3B, and the cathode electrode 4C are performed. Thus, a compound semiconductor device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated is formed on the SiC substrate 1.

  As described above, according to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and surely suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized. To do.

(Fourth embodiment)
In the present embodiment, as in the first embodiment, as a compound semiconductor device, a device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated on the same substrate is disclosed, but the compound semiconductor multilayer structure is on the SBD side. It is different in different points. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
9 to 10 are schematic cross-sectional views showing main steps of the method for manufacturing the compound semiconductor device according to the fourth embodiment.

  In the present embodiment, as in the first embodiment, first, the process of FIG. At this time, the compound semiconductor multilayer structure 2 is formed on the SiC substrate 1.

Subsequently, as shown in FIG. 9A, an electrode recess 2A is formed in the electron supply layer 2d only on the SBD side.
More specifically, a resist is applied to the entire surface of the compound semiconductor multilayer structure 2, and the resist is processed by lithography to form a resist mask having an opening that exposes only a portion where the anode electrode on the SBD side is to be formed.
Using this resist mask, the electron supply layer 2d is dry-etched to a predetermined depth. Chlorine etching gas is used for dry etching. As a result, in the electron supply layer 2d, the electrode recess 2A is formed at the site where the anode electrode on the SBD side is to be formed. The remaining etching amount of the electron supply layer 2d depends on the required performance as an AlGaN / GaN SBD element.

Subsequently, as shown in FIG. 9B, the gate electrode 3A is simultaneously formed on the HEMT side, and the electrode layer 3a is simultaneously formed on the SBD side.
Specifically, first, the surface of the compound semiconductor multilayer structure 2 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 2, it is possible to obtain a good surface (becomes an interface with various electrodes described later) having extremely low interface states.

  Next, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied onto the compound semiconductor multilayer structure 2, and the resist is processed by lithography to expose the gate electrode formation planned portion on the HEMT side and the electrode recess 2A that is the anode electrode formation planned portion on the SBD side. Each opening is formed. Thus, a resist mask having each opening is formed.

In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Using the resist mask, Ni / Au as the first metal is deposited on the resist mask including the inside of each opening exposing the surface of the compound semiconductor multilayer structure 2 by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 3A is simultaneously formed on the electron supply layer 2d on the HEMT side, and the electrode layer 3a is formed on the SBD side so as to fill the electrode recess 2A of the electron supply layer 2d.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 9C, the upper layer portion 3b is formed only on the electrode layer 3a on the SBD side.
Specifically, first, a resist mask for forming the upper layer portion is formed. A resist is applied to the entire surface, and the resist is processed by lithography to form an opening exposing only the upper surface of the electrode layer 3a on the SBD side. Thus, a resist mask having the opening is formed.

In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Using the resist mask, Ti as the second metal is deposited on the resist mask including the inside of the opening exposing the upper surface of the electrode layer 3a by, for example, vapor deposition. The thickness of Ti is about 30 nm. The resist mask and Ti deposited thereon are removed by a lift-off method. As a result, the upper layer portion 3b serving as a cap layer is formed only on the electrode layer 3a on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 10A, the source electrode 4A and the drain electrode 4B are simultaneously formed on the HEMT side, and the cathode electrode 4C is simultaneously formed on the SBD side.
Specifically, first, a resist mask for forming the source electrode 4A, the drain electrode 4B, and the cathode electrode 4C is formed. Resist is applied to the entire surface of the compound semiconductor multilayer structure 2, and the resist is processed by lithography to expose the planned site for forming the source and drain electrodes on the HEMT side and the planned site for forming the cathode electrode on the SBD side. Form. Thus, a resist mask having each opening is formed.

Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer and Al is the upper layer) is deposited on the resist mask including the inside of each opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thus, the source electrode 4A and the drain electrode 4B are formed on the electron supply layer 21d on the HEMT side, and the cathode electrode 4C is formed on the n-GaN layer 21e on the SBD side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 10B, a passivation film 5 is formed.
Specifically, an insulating film such as SiN is deposited on the entire surface of the compound semiconductor multilayer structure 2 to a thickness of about 2 nm to 200 nm by a plasma CVD method or the like. Thereby, the passivation film 5 is formed.

Subsequently, as shown in FIG. 10C, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal that is the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 550 ° C. (Annealing). This heat treatment establishes ohmic contact with the electron supply layer 2d for the source electrode 4A and the drain electrode 4B on the HEMT side and for the cathode electrode 4C on the SBD side, respectively. At the same time, by the heat treatment, Ti in the upper layer portion 3b diffuses downward into the electrode layer 3a on the SBD side, Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 3a, and lower layer portion 3c. Is formed. The lower layer portion 3c is formed with a thickness of about 1 nm to 2 nm, for example. The electrode layer 3a, the upper layer portion 3b, and the lower layer portion 3c form an anode electrode 3B.

  In the present embodiment, the heat treatment for forming the anode electrode 3B by thermally diffusing Ti is performed in combination with the heat treatment for obtaining the ohmic contact of the source electrode 4A, the drain electrode 4B, and the cathode electrode 4C. As a result, it is not necessary to provide a heat treatment step for forming the anode electrode 3B, and the number of steps can be reduced.

  Thereafter, various processes such as formation of an interlayer insulating film, the shape of each wiring connected to the gate electrode 3A, the source electrode 4A, the drain electrode 4B, the anode electrode 3B, and the cathode electrode 4C are performed. Thus, a compound semiconductor device in which AlGaN / GaN.HEMT and AlGaN / GaN.SBD are integrated is formed on the SiC substrate 1.

  As described above, according to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and surely suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized. To do.

(Fifth embodiment)
In the present embodiment, as a compound semiconductor device, a device in which E-mode • AlGaN / GaN • HEMT and D-mode • AlGaN / GaN • HEMT are integrated on the same substrate is disclosed. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
11 to 12 are schematic cross-sectional views illustrating main processes of the compound semiconductor device manufacturing method according to the fifth embodiment.

  In the present embodiment, as in the first embodiment, first, the process of FIG. At this time, the compound semiconductor multilayer structure 2 is formed on the SiC substrate 1.

Subsequently, as shown in FIG. 11A, the gate electrode 22A and the electrode layer 22a are simultaneously formed on the E-mode / HEMT side and the D-mode / HEMT side, respectively.
Specifically, first, the surface of the compound semiconductor multilayer structure 2 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 2, it is possible to obtain a good surface (becomes an interface with various electrodes described later) having extremely low interface states.

  Next, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied on the compound semiconductor multilayer structure 2, and the resist is processed by lithography to form openings that expose the formation sites of the gate electrodes on the E-mode / HEMT side and the D-mode / HEMT side, respectively. Thus, a resist mask having each opening is formed.

In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Using the resist mask, Ni / Au as the first metal is deposited on the resist mask including the inside of each opening exposing the surface of the compound semiconductor multilayer structure 2 by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 22A is formed on the E-mode / HEMT side and the electrode layer 22a is formed on the D-mode / HEMT side simultaneously.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 11B, the upper layer portion 22b is formed only on the electrode layer 22a on the D-mode / HEMT side.
Specifically, first, a resist mask for forming the upper layer portion is formed. A resist is applied to the entire surface, and the resist is processed by lithography to form an opening exposing only the upper surface of the electrode layer 22a on the D-mode / HEMT side. Thus, a resist mask having the opening is formed.

In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Using the resist mask, Ti as the second metal is deposited on the resist mask including the inside of the opening exposing the upper surface of the electrode layer 22a, for example, by vapor deposition. The thickness of Ti is about 30 nm. The resist mask and Ti deposited thereon are removed by a lift-off method. As a result, the upper layer portion 22b serving as the cap layer is formed only on the electrode layer 22a on the D-mode / HEMT side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 11C, the source electrode 23A and the drain electrode 23B are simultaneously formed on the E-mode / HEMT side, and the source electrode 23C and the drain electrode 23D are simultaneously formed on the D-mode / HEMT side.
Specifically, first, a resist mask for forming the source electrode 23A and the drain electrode 23B, and the source electrode 23C and the drain electrode 23D is formed. Resist is applied to the entire surface of the compound semiconductor multilayer structure 2, and the resist is processed by lithography to expose the formation sites of the source electrode and the drain electrode on the E-mode / HEMT side and the D-mode / HEMT side, respectively. Form. Thus, a resist mask having each opening is formed.

Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer and Al is the upper layer) is deposited on the resist mask including the inside of each opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thus, the source electrode 23A and the drain electrode 23B are formed on the E-mode / HEMT side, and the source electrode 23C and the drain electrode 23D are formed on the D-mode / HEMT side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, a passivation film 5 is formed as shown in FIG.
Specifically, an insulating film such as SiN is deposited on the entire surface of the compound semiconductor multilayer structure 2 to a thickness of about 2 nm to 200 nm by a plasma CVD method or the like. Thereby, the passivation film 5 is formed.

Subsequently, as shown in FIG. 12B, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal that is the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 550 ° C. (Annealing). By this heat treatment, ohmic contact with the electron supply layer 2d is established with respect to the source electrode 23A and the drain electrode 23B on the E-mode / HEMT side, and with respect to the source electrode 23C and the drain electrode 23D on the D-mode / HEMT side. At the same time, the heat treatment causes Ti in the upper layer portion 22b to diffuse downward into the electrode layer 22a on the D-mode / HEMT side, and Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 22a. A lower layer portion 22c is formed. The lower layer portion 22c is formed to a thickness of about 1 nm to 2 nm, for example. The electrode layer 22a, the upper layer portion 22b, and the lower layer portion 22c form a gate electrode 22B.

  In the present embodiment, the heat treatment for thermally diffusing Ti to form the gate electrode 22B is performed in combination with the heat treatment for obtaining the ohmic contact between the source electrode 23A and the drain electrode 23B, and the source electrode 23C and the drain electrode 23D. . As a result, it is not necessary to provide a single heat treatment step for forming the gate electrode 22B, thereby reducing the number of steps.

  Thereafter, various steps such as formation of an interlayer insulating film, the shape of each wiring connected to the gate electrode 22A, the source electrode 23A, the drain electrode 23B, the gate electrode 22B, the source electrode 23C, and the drain electrode 23D are performed. As a result, a compound semiconductor device in which E-mode · AlGaN / GaN · HEMT and D-mode · AlGaN / GaN · HEMT are integrated is formed on the SiC substrate 1.

  Regarding the compound semiconductor device manufactured according to the present embodiment, the relationship between the gate-source voltage (Vgs) and the drain current (Id) was examined. The result is shown in FIG. Since the gate electrode 22A has a high Ni work function, an E-mode operation is realized, and the gate electrode 22B has a Ti work function low, so a D-mode operation is realized. Since Ni of the gate electrode 22A and Ni of the electrode layer 22a are formed at the same time, sufficient cleaning of the surface of the compound semiconductor multilayer structure 2 results in extremely low interface states and two types of threshold voltages (Vth). It was confirmed that a compound semiconductor device was realized.

  As described above, according to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and surely suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized. To do.

(Sixth embodiment)
In the present embodiment, as in the fifth embodiment, a device in which E-mode · AlGaN / GaN · HEMT and D-mode · AlGaN / GaN · HEMT are integrated on the same substrate is disclosed as a compound semiconductor device. This embodiment is different from the fifth embodiment in that it has a so-called MIS type structure. In addition, about the same thing as the structural member of 5th Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
14 to 15 are schematic cross-sectional views showing main processes of the method for manufacturing the compound semiconductor device according to the sixth embodiment.

  In the present embodiment, as in the first embodiment, first, the process of FIG. At this time, the compound semiconductor multilayer structure 2 is formed on the SiC substrate 1.

Subsequently, as shown in FIG. 14A, a gate insulating film 24 is formed.
Specifically, first, the surface of the compound semiconductor multilayer structure 2 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 2, it is possible to obtain a good surface (becomes an interface with various electrodes described later) having extremely low interface states.

Next, for example, Al ₂ O ₃ is deposited as an insulating material on the compound semiconductor multilayer structure 2. Al ₂ O ₃ is deposited to a thickness of about 2 nm to 200 nm, here about 10 nm, for example, by atomic layer deposition (ALD method). Thereby, the gate insulating film 24 is formed.

Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

Subsequently, as shown in FIG. 14B, the gate electrode 22A is formed on the E-mode / HEMT side, and the electrode layer 22a is formed on the D-mode / HEMT side simultaneously.
Specifically, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied on the gate insulating film 24, and the resist is processed by lithography to form openings that expose the formation sites of the gate electrodes on the E-mode / HEMT side and the D-mode / HEMT side, respectively. Thus, a resist mask having each opening is formed.

In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Using the resist mask, Ni / Au as the first metal is deposited on the resist mask including the inside of each opening exposing the surface of the gate insulating film 24 by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 22A is formed on the E-mode / HEMT side and the electrode layer 22a is formed on the D-mode / HEMT side simultaneously.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 14C, the upper layer portion 22b is formed only on the electrode layer 22a on the D-mode / HEMT side.
Specifically, first, a resist mask for forming the upper layer portion is formed. A resist is applied to the entire surface, and the resist is processed by lithography to form an opening exposing only the upper surface of the electrode layer 22a on the D-mode / HEMT side. Thus, a resist mask having the opening is formed.

In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Using the resist mask, Ti as the second metal is deposited on the resist mask including the inside of the opening exposing the upper surface of the electrode layer 22a, for example, by vapor deposition. The thickness of Ti is about 30 nm. The resist mask and Ti deposited thereon are removed by a lift-off method. As a result, the upper layer portion 22b serving as the cap layer is formed only on the electrode layer 22a on the D-mode / HEMT side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 15A, openings 24a, 24b, 24c, and 24d are formed in the gate insulating film 24.
More specifically, a resist is applied to the entire surface of the gate insulating film 24, and the resist is processed by lithography. On the surface of the gate insulating film 24, the source electrode on the E-mode / HEMT side and the D-mode / HEMT side and Each opening is formed to expose a portion where the drain electrode is to be formed. Thus, a resist mask having each opening is formed.

The gate insulating film 24 is dry etched using this resist mask. As described above, the gate insulating film 24 has openings 24a, 24b, and 24c that expose the surface of the compound semiconductor multilayer structure 2 at the portions where the source and drain electrodes are to be formed on the E-mode / HEMT side and the D-mode / HEMT side. , 24d are formed.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 15B, the source electrode 23A and the drain electrode 23B are simultaneously formed on the E-mode / HEMT side, and the source electrode 23C and the drain electrode 23D are simultaneously formed on the D-mode / HEMT side.
Specifically, a resist mask for forming the source electrode 23A and the drain electrode 23B, and the source electrode 23C and the drain electrode 23D is formed. A resist is applied to the entire surface of the gate insulating film 24, and the resist is processed by lithography to form openings that expose the openings 24a, 24b, 24c, and 24d of the gate insulating film 24, respectively. Thus, a resist mask having each opening is formed.

Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer and Al is the upper layer) is deposited on the resist mask including the inside of each opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thus, the source electrode 23A and the drain electrode 23B for embedding the openings 24a and 24b are formed on the E-mode / HEMT side, and the source electrode 23C and the drain electrode 23D for embedding the openings 24c and 24d are formed on the D-mode / HEMT side. The
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 15C, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal that is the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 550 ° C. (Annealing). By this heat treatment, ohmic contact with the electron supply layer 2d is established with respect to the source electrode 23A and the drain electrode 23B on the E-mode / HEMT side, and with respect to the source electrode 23C and the drain electrode 23D on the D-mode / HEMT side. At the same time, the heat treatment causes Ti in the upper layer portion 22b to diffuse downward into the electrode layer 22a on the D-mode / HEMT side, and Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 22a. A lower layer portion 22c is formed. The lower layer portion 22c is formed to a thickness of about 1 nm to 2 nm, for example. The electrode layer 22a, the upper layer portion 22b, and the lower layer portion 22c form a gate electrode 22B.

  In the present embodiment, the heat treatment for thermally diffusing Ti to form the gate electrode 22B is performed in combination with the heat treatment for obtaining the ohmic contact between the source electrode 23A and the drain electrode 23B, and the source electrode 23C and the drain electrode 23D. . As a result, it is not necessary to provide a single heat treatment step for forming the gate electrode 22B, thereby reducing the number of steps.

  Thereafter, various steps such as formation of an interlayer insulating film, the shape of each wiring connected to the gate electrode 22A, the source electrode 23A, the drain electrode 23B, the gate electrode 22B, the source electrode 23C, and the drain electrode 23D are performed. Thus, a compound semiconductor device in which the MIS structure E-mode • AlGaN / GaN • HEMT and D-mode • AlGaN / GaN • HEMT are integrated is formed on the SiC substrate 1.

  As described above, according to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and surely suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized. To do.

(Seventh embodiment)
In the present embodiment, as in the sixth embodiment, as a compound semiconductor device, a device having a MIS structure in which E-mode • AlGaN / GaN • HEMT and D-mode • AlGaN / GaN • HEMT are integrated on the same substrate. Is disclosed. The present embodiment is different from the sixth embodiment in that the compound semiconductor multilayer structure is different on the E-mode / HEMT side. In addition, about the same thing as the structural member of 6th Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
16 to 18 are schematic cross-sectional views showing main steps of the compound semiconductor device manufacturing method according to the seventh embodiment.

  In the present embodiment, as in the first embodiment, first, the process of FIG. At this time, the compound semiconductor multilayer structure 2 is formed on the SiC substrate 1.

Subsequently, as shown in FIG. 16A, an electrode recess 2B is formed in the electron supply layer 2d only on the E-mode / HEMT side.
Specifically, a resist is applied to the entire surface of the compound semiconductor multilayer structure 2, and the resist is processed by lithography to form a resist mask having an opening that exposes only the formation region of the gate electrode on the E-mode / HEMT side. To do.
Using this resist mask, the electron supply layer 2d is dry-etched to a predetermined depth. Chlorine etching gas is used for dry etching. Thereby, in the electron supply layer 2d, an electrode recess 2B is formed at a site where the gate electrode on the E-mode / HEMT side is to be formed. The electrode recess may be formed so that the electron supply layer 2d remains at the etching site or until the electron transit layer 2b is reached.

  By forming the electrode recess 2B, the E-mode operation can be performed more reliably in the gate electrode in which the electrode recess 2B is embedded via the gate insulating film.

Subsequently, a gate insulating film 24 is formed as shown in FIG.
Specifically, first, the surface of the compound semiconductor multilayer structure 2 is sufficiently cleaned using an organic solvent, acid, alkali, or the like. By cleaning the surface of the compound semiconductor multilayer structure 2, it is possible to obtain a good surface (becomes an interface with various electrodes described later) having extremely low interface states.

Next, for example, Al ₂ O ₃ is deposited as an insulating material on the compound semiconductor multilayer structure 2. Al ₂ O ₃ is deposited to a thickness of about 2 nm to 200 nm, here about 10 nm, for example, by atomic layer deposition (ALD method). Thereby, the gate insulating film 24 is formed.

Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

Subsequently, as shown in FIG. 16C, the gate electrode 22A and the electrode layer 22a are simultaneously formed on the E-mode / HEMT side and the D-mode / HEMT side.
Specifically, a resist mask for forming the gate electrode and the electrode layer is formed. A resist is applied on the gate insulating film 24, and the resist is processed by lithography. As a result, the E-mode / HEMT side has an opening that exposes a portion that is aligned above the electrode recess 2B that is the gate electrode formation planned site, and the D-mode / HEMT side has a gate electrode formation planned site. Each of the openings for exposing is formed. Thus, a resist mask having each opening is formed.

In this embodiment, a material (first metal) containing Ni, Pt, Cu or the like, which is a metal having a high work function, is used as the material for the gate electrode and the electrode layer. Here, Ni / Au (Ni is the lower layer and Au is the upper layer) is exemplified as the first metal.
Using the resist mask, Ni / Au as the first metal is deposited on the resist mask including the inside of each opening exposing the surface of the gate insulating film 24 by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 22A for embedding the electrode recess 2B through the gate insulating film 24 is formed on the E-mode / HEMT side, and the electrode layer 22a is simultaneously formed on the gate insulating film 24 on the D-mode / HEMT side. The
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 17A, the upper layer portion 22b is formed only on the electrode layer 22a on the D-mode / HEMT side.
Specifically, first, a resist mask for forming the upper layer portion is formed. A resist is applied to the entire surface, and the resist is processed by lithography to form an opening exposing only the upper surface of the electrode layer 22a on the D-mode / HEMT side. Thus, a resist mask having the opening is formed.

In the present embodiment, a material (second metal) containing Ti, Mo, Ta, W or the like, which is a refractory metal having a work function lower than that of the first metal, is used as the material of the upper layer portion. Here, Ti is exemplified as the second metal.
Using the resist mask, Ti as the second metal is deposited on the resist mask including the inside of the opening exposing the upper surface of the electrode layer 22a, for example, by vapor deposition. The thickness of Ti is about 30 nm. The resist mask and Ti deposited thereon are removed by a lift-off method. As a result, the upper layer portion 22b serving as the cap layer is formed only on the electrode layer 22a on the D-mode / HEMT side.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 17B, openings 24 a, 24 b, 24 c, and 24 d are formed in the gate insulating film 24.
More specifically, a resist is applied to the entire surface of the gate insulating film 24, and the resist is processed by lithography. On the surface of the gate insulating film 24, the source electrode on the E-mode / HEMT side and the D-mode / HEMT side and Each opening is formed to expose a portion where the drain electrode is to be formed. Thus, a resist mask having each opening is formed.

The gate insulating film 24 is dry etched using this resist mask. As described above, the gate insulating film 24 has openings 24a, 24b, and 24c that expose the surface of the compound semiconductor multilayer structure 2 at the portions where the source and drain electrodes are to be formed on the E-mode / HEMT side and the D-mode / HEMT side. , 24d are formed.
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 18A, the source electrode 23A and the drain electrode 23B are simultaneously formed on the E-mode / HEMT side, and the source electrode 23C and the drain electrode 23D are simultaneously formed on the D-mode / HEMT side.
Specifically, a resist mask for forming the source electrode 23A and the drain electrode 23B, and the source electrode 23C and the drain electrode 23D is formed. A resist is applied to the entire surface of the gate insulating film 24, and the resist is processed by lithography to form openings that expose the openings 24a, 24b, 24c, and 24d of the gate insulating film 24, respectively. Thus, a resist mask having each opening is formed.

Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer and Al is the upper layer) is deposited on the resist mask including the inside of each opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thus, the source electrode 23A and the drain electrode 23B for embedding the openings 24a and 24b are formed on the E-mode / HEMT side, and the source electrode 23C and the drain electrode 23D for embedding the openings 24c and 24d are formed on the D-mode / HEMT side. The
The resist mask is removed by wet processing using a predetermined chemical solution or ashing processing using oxygen plasma.

Subsequently, as shown in FIG. 18B, the SiC substrate 1 is heat-treated.
More specifically, the SiC substrate 1 is heat-treated in a nitrogen atmosphere at a temperature lower than the melting point of the refractory metal that is the second metal, here Ti, preferably about 400 ° C. to 1000 ° C., for example, about 550 ° C. (Annealing). By this heat treatment, ohmic contact with the electron supply layer 2d is established with respect to the source electrode 23A and the drain electrode 23B on the E-mode / HEMT side, and with respect to the source electrode 23C and the drain electrode 23D on the D-mode / HEMT side. At the same time, the heat treatment causes Ti in the upper layer portion 22b to diffuse downward into the electrode layer 22a on the D-mode / HEMT side, and Ti precipitates at the interface between AlGaN in the electron supply layer 2d and Ni in the electrode layer 22a. A lower layer portion 22c is formed. The lower layer portion 22c is formed to a thickness of about 1 nm to 2 nm, for example. The electrode layer 22a, the upper layer portion 22b, and the lower layer portion 22c form a gate electrode 22B.

  In the present embodiment, the heat treatment for thermally diffusing Ti to form the gate electrode 22B is performed in combination with the heat treatment for obtaining the ohmic contact between the source electrode 23A and the drain electrode 23B, and the source electrode 23C and the drain electrode 23D. . As a result, it is not necessary to provide a single heat treatment step for forming the gate electrode 22B, thereby reducing the number of steps.

  Thereafter, various steps such as formation of an interlayer insulating film, the shape of each wiring connected to the gate electrode 22A, the source electrode 23A, the drain electrode 23B, the gate electrode 22B, the source electrode 23C, and the drain electrode 23D are performed. Thus, a compound semiconductor device in which the MIS structure E-mode • AlGaN / GaN • HEMT and D-mode • AlGaN / GaN • HEMT are integrated is formed on the SiC substrate 1.

  As described above, according to this embodiment, the generation of the interface state between each electrode and the compound semiconductor layer is easily and surely suppressed, and a highly reliable compound semiconductor device having excellent device characteristics is realized. To do.

  In the fifth embodiment, as in the present embodiment, the electrode recess 2B is formed on the E-mode / HEMT side of the compound semiconductor multilayer structure 2, and the electrode recess 2B is formed without forming the gate insulating film 24. The gate electrode 22A may be formed so as to be embedded.

  In the first to seventh embodiments, a heat treatment for diffusing the second metal (such as Ti) downward into the electrode layer (such as Ni) is performed to obtain ohmic contact between the source electrode and the drain electrode (and cathode electrode). However, both processes may be performed separately. In that case, the heat treatment for downward diffusion is preferably performed at a temperature lower than the melting point of the refractory metal that is the second metal, for example, about 400 ° C. to 800 ° C. In addition, the heat treatment for obtaining the ohmic contact may be unnecessary if the ohmic contact is obtained.

(Eighth embodiment)
In the present embodiment, a power supply device to which one compound semiconductor device selected from the first to seventh embodiments is applied is disclosed.
FIG. 19 is a connection diagram illustrating a schematic configuration of the power supply device according to the eighth embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 31 and a low-voltage secondary circuit 32, and a transformer 33 disposed between the primary circuit 31 and the secondary circuit 32. The
The primary circuit 31 includes an AC power supply 34, a so-called bridge rectifier circuit 35, and a plurality (four in this case) of switching elements 36a, 36b, 36c, and 36d. The bridge rectifier circuit 35 includes a switching element 36e.
The secondary circuit 22 includes a plurality of (here, three) switching elements 37a, 37b, and 37c.

  In the present embodiment, when one kind of compound semiconductor device selected from the first to fourth embodiments is applied, the switching elements 36a, 36b, 36c, 36d, and 36e of the primary side circuit 31 correspond to the present embodiment. The compound semiconductor device is an AlGaN / GaN.HEMT. The diode of the bridge rectifier circuit 35 is the AlGaN / GaN SBD of the compound semiconductor device of the embodiment.

When one type of compound semiconductor device selected from the fifth to seventh embodiments is applied, the compound semiconductor device of the embodiment is applied to the switching elements 36a, 36b, 36c, 36d, and 36e of the primary circuit 31. AlGaN / GaN.HEMT. In this case, the E-mode · AlGaN / GaN · HEMT and the D-mode · AlGaN / GaN · HEMT of the embodiment are appropriately applied.
On the other hand, the switching elements 37a, 37b, and 37c of the secondary circuit 32 are normal MIS • FETs using silicon.

  In this embodiment, the generation of interface states between each electrode and the compound semiconductor layer is easily and reliably suppressed, and highly reliable AlGaN / GaN.HEMT and AlGaN / GaN.SBD having excellent device characteristics are obtained. Applies to high voltage circuits. As a result, a highly reliable high-power power supply circuit is realized.

(Ninth embodiment)
In the present embodiment, a high-frequency amplifier to which one kind of compound semiconductor device selected from the first to seventh embodiments is applied is disclosed.
FIG. 20 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the ninth embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43.
The digital predistortion circuit 41 compensates for nonlinear distortion of the input signal. The mixer 42a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 43 amplifies an input signal mixed with an AC signal, and has an AlGaN / GaN HEMT as a compound semiconductor device selected from the first to seventh embodiments. In FIG. 20, for example, by switching the switch, the output side signal can be mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.

  In the present embodiment, a highly reliable AlGaN / GaN HEMT having excellent device characteristics is applied to a high-frequency amplifier by easily and reliably suppressing the generation of interface states between each electrode and the compound semiconductor layer. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to ninth embodiments, AlGaN / GaN.HEMT and AlGaN / GaN.SBD are exemplified as the compound semiconductor device. In addition to AlGaN / GaN HEMT and AlGaN / GaN SBD, the compound semiconductor device can be applied to the following devices.

・ Other device example 1
In this example, InAlN / GaN.HEMT and InAlN / GaN.SBD are disclosed as compound semiconductor devices.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first to seventh embodiments described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of i-InAlN, and the electron supply layer is formed of n-InAlN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, similar to the AlGaN / GaN HEMT and AlGaN / GaN SBD described above, the generation of interface states between each electrode and the compound semiconductor layer can be easily and reliably suppressed, and excellent device characteristics can be obtained. A highly reliable compound semiconductor device is realized.

・ Other HEMT examples 2
In this example, InAlGaN / GaN.HEMT and InAlGaN / GaN.SBD are disclosed as compound semiconductor devices.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first to seventh embodiments described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of i-InAlGaN, and the electron supply layer is formed of n-InAlGaN.

  According to this example, similar to the AlGaN / GaN HEMT and AlGaN / GaN SBD described above, the generation of interface states between each electrode and the compound semiconductor layer can be easily and reliably suppressed, and excellent device characteristics can be obtained. A highly reliable compound semiconductor device is realized.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Appendix 1) A step of forming a metal layer of a first metal above the semiconductor layer;
Forming a second metal, which is a metal having a lower work function than the first metal, on the metal layer;
And performing a heat treatment at a temperature lower than the melting point of the second metal to form a first electrode formed by depositing the second metal in a lower layer portion.

  (Additional remark 2) The said 2nd metal is at least 1 sort (s) chosen from Ti, Mo, Ta, and W, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Additional remark 3) The said 1st metal is at least 1 sort (s) chosen from Ni, Pt, and Cu, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.

  (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, further comprising a step of forming a second electrode of the first metal together with the metal layer above the semiconductor layer. Production method.

(Additional remark 5) It further includes the process of forming a 3rd electrode on the said semiconductor layer,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the third electrode is brought into ohmic contact with the semiconductor layer together with the formation of the first electrode by the heat treatment.

  (Supplementary note 6) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 5, further comprising a step of cleaning a surface of the semiconductor layer before forming the metal layer.

  (Additional remark 7) The said semiconductor layer is a compound semiconductor laminated structure, The manufacturing method of the semiconductor device of any one of Additional remark 1-6 characterized by the above-mentioned.

(Appendix 8) Above the semiconductor layer, forming a first metal layer of a first metal in a first region and forming a second metal layer of the first metal in a second region;
Forming a second metal which is a metal having a lower work function than the first metal on the first metal layer in the first region;
Forming a third metal layer of a third metal in the first region and a fourth metal layer of the third metal in the second region above the semiconductor layer;
Heat treatment is performed at a temperature lower than the melting point of the second metal, and in the first region, a first Schottky electrode formed by depositing the second metal in a lower layer portion of the first metal layer, and the third A first ohmic electrode in which the metal layer is in ohmic contact with the semiconductor layer; a second Schottky electrode of the second metal layer in the second region; and a fourth metal layer in ohmic contact with the semiconductor layer. Forming a second ohmic electrode formed. A method for manufacturing a semiconductor device, comprising:

  (Additional remark 9) The said 2nd metal is at least 1 sort (s) chosen from Ti, Mo, Ta, and W, The manufacturing method of the semiconductor device of Additional remark 8 characterized by the above-mentioned.

  (Additional remark 10) The said 1st metal is at least 1 sort (s) chosen from Ni, Pt, and Cu, The manufacturing method of the semiconductor device of Additional remark 8 or 9 characterized by the above-mentioned.

(Appendix 11) a semiconductor layer;
A first electrode formed above the semiconductor layer,
In the first electrode, a second metal that is at least one selected from Ti, Mo, Ta, and W is thermally diffused in a metal layer of the first metal, and the second metal is deposited in a lower layer portion. A semiconductor device characterized by that.

  (Supplementary note 12) The semiconductor device according to supplementary note 11, wherein the first metal is at least one selected from Ni, Pt, and Cu.

(Additional remark 13) The 2nd electrode formed above the semiconductor layer is further included,
13. The semiconductor device according to appendix 11 or 12, wherein the second electrode is made of the first metal.

  (Supplementary note 14) The semiconductor device according to any one of supplementary notes 11 to 13, wherein the semiconductor layer has a compound semiconductor multilayer structure.

(Supplementary Note 15) A power supply device including a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A semiconductor layer;
A first electrode formed above the semiconductor layer,
In the first electrode, the second metal, which is at least one selected from Ti, Mo, Ta, and W, is thermally diffused in the metal layer of the first metal at a temperature lower than the melting point of the second metal. The power supply device, wherein the second metal is deposited in the lower layer portion.

(Supplementary Note 16) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A semiconductor layer;
A first electrode formed above the semiconductor layer,
In the first electrode, the second metal, which is at least one selected from Ti, Mo, Ta, and W, is thermally diffused in the metal layer of the first metal at a temperature lower than the melting point of the second metal. The high frequency amplifier, wherein the second metal is deposited in a lower layer portion.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2, 21 Compound semiconductor laminated structure 2a, 21a Buffer layer 2b, 21b Electron travel layer 2c, 21c Intermediate layer 2d, 21d Electron supply layer 21e n-GaN layer 2A, 2B Electrode recesses 3A, 13A, 22A, 22B Gate electrodes 3B, 13B Anode electrodes 3a, 13a, 22a Electrode layers 3b, 13b, 22b Upper layer portions 3c, 13c, 22c Lower layer portions 4A, 15A, 23A, 23C Source electrodes 4B, 15B, 23B, 23D Drain electrodes 4C, 15C Cathodes Electrode 5 Passivation film 11 Insulating films 11a, 11b, 15a, 15b, 15c, 24a, 24b, 24c, 24d Opening 12 Ni / Au
14 Interlayer insulating film 24 Gate insulating film 31 Primary side circuit 32 Secondary side circuit 33 Transformer 34 AC power supply 35 Bridge rectifier circuit 36a, 36b, 36c, 36d, 36e, 37a, 37b, 37c Switching element 41 Digital predistortion circuit 42a 42b Mixer 43 Power amplifier

Claims (10)

Forming an insulating film having an opening above the semiconductor layer ;
Depositing a first metal on the insulating film so as to fill the opening;
Forming a second metal, which is a metal having a work function lower than that of the first metal , only at a position aligned above the opening on the first metal;
Processing the first metal to form a metal layer that fills the opening with the first metal under the second metal ;
And performing a heat treatment at a temperature lower than the melting point of the second metal to form a first electrode formed by depositing the second metal in a lower layer portion.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal is at least one selected from Ti, Mo, Ta, and W.   The method for manufacturing a semiconductor device according to claim 1, wherein the first metal is at least one selected from Ni, Pt, and Cu.   The method for manufacturing a semiconductor device according to claim 1, further comprising forming a second electrode of the first metal together with the metal layer above the semiconductor layer. Forming a third electrode on the semiconductor layer;
5. The method of manufacturing a semiconductor device according to claim 1, wherein the third electrode is brought into ohmic contact with the semiconductor layer together with the formation of the first electrode by the heat treatment. 6.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of cleaning a surface of the semiconductor layer before forming the metal layer.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer has a compound semiconductor stacked structure. Forming an insulating film having a first opening in the first region and a second opening in the second region above the semiconductor layer ;
Depositing a first metal on the insulating film so as to fill the first opening and the second opening;
Forming a second metal, which is a metal having a work function lower than that of the first metal , only in a portion that is aligned above the first opening on the first metal;
By processing the first metal, wherein the first region of the first metal layer filling the first opening under the second metal in the first metal, wherein the second opening in the second region Forming a second metal layer embedded with the first metal ;
Forming a third metal layer of a third metal in the first region and a fourth metal layer of the third metal in the second region above the semiconductor layer;
Heat treatment is performed at a temperature lower than the melting point of the second metal, and in the first region, a first Schottky electrode formed by depositing the second metal in a lower layer portion of the first metal layer, and the third A first ohmic electrode in which the metal layer is in ohmic contact with the semiconductor layer; a second Schottky electrode of the second metal layer in the second region; and a fourth metal layer in ohmic contact with the semiconductor layer. Forming a second ohmic electrode formed. A method for manufacturing a semiconductor device, comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the second metal is at least one selected from Ti, Mo, Ta, and W.   10. The method of manufacturing a semiconductor device according to claim 8, wherein the first metal is at least one selected from Ni, Pt, and Cu.

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