JP6158036B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  As an example of a power semiconductor device, there is an IGBT (Insulated Gate Bipolar Transistor). In the IGBT, for example, a p-type collector layer, an n-type base layer, and a p-type base layer are provided on the collector electrode. A trench gate electrode is provided through a gate insulating film in a trench that penetrates the p-type base layer and reaches the n-type base layer. Further, an n-type emitter layer connected to the emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base layer.

  In the IGBT, a channel is formed in the p-type base layer by applying a positive voltage to the gate electrode. Electrons are injected from the n-type emitter layer into the n-type base layer, and at the same time, holes are injected from the p-type collector layer into the n-type base layer. Thereby, a current flows between the collector electrode and the emitter electrode.

  In order to reduce the on-resistance between the collector electrode and the emitter electrode in the on-state of the IGBT, there is a method for suppressing the discharge of holes from the n-type base layer. In this method, by suppressing the holes discharged from the n-type base layer to the emitter electrode, the amount of injected electrons is relatively increased, and the on-resistance of the IGBT is reduced. For example, a structure in which a p-type layer (floating layer) electrically sandwiched between trench gate electrodes is provided between p-type base layers, that is, a so-called trench enhanced gate transistor (IEGT) has been proposed.

  However, in the trench IEGT, there is a problem that the potential of the floating layer sandwiched between the trench gate electrodes varies due to switching, and the gate potential varies due to coupling between the floating layer and the gate electrode. To solve this problem, a method has been proposed in which a shield electrode connected to the emitter electrode is provided between the trench gate electrode and the floating layer to shield potential fluctuations in the floating layer.

JP 2012-99696 A

  The problem to be solved by the present invention is to provide a semiconductor device capable of reducing on-resistance.

The semiconductor device of the embodiment includes a collector electrode, a first conductivity type collector layer provided on the collector electrode, a second conductivity type first base layer provided on the collector layer, and the first A first conductive type second base layer provided on the base layer; an electrically insulated first conductive type floating layer provided on the first base layer; and the first base layer And between the first base layer, the floating layer, and the gate electrode through an insulating film, and between the first base layer, the floating layer, and the gate electrode. a first electrical conductor provided, the second base layer surface to the emitter layer of the second conductivity type which is selectively provided, an emitter electrode provided on said second base layer and the emitter layer, the The potential mode connected to the first conductor Includes a capacitor circuit, the.

It is a schematic diagram of the principal part of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic diagram of the principal part of the semiconductor device of a comparison form. It is a schematic diagram of the principal part of the semiconductor device of 2nd Embodiment. It is a schematic diagram of the principal part of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is a schematic diagram of the principal part of the semiconductor device of 5th Embodiment. It is a schematic diagram of the principal part of the semiconductor device of 6th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are denoted by the same reference numerals, and the description of the members and the like once described is omitted as appropriate.

Herein, n ⁺ -type, n-type, n ^- notation and type, n ⁺ -type, n-type, n ^- n-type impurity concentration in the order of type means that are lower. Further, ^{p +} -type, p-type, p ^- -type notation, ^{p +} -type, p-type, p ^- in the order of type impurity concentration of the p-type means that are lower.

(First embodiment)
The semiconductor device of the present embodiment includes a collector electrode, a first conductivity type collector layer provided on the collector electrode, a second conductivity type first base layer provided on the collector layer, and a first base layer. A first conductivity type second base layer provided thereon; an electrically insulated first conductivity type floating layer provided on the first base layer; and a first base layer and a second base layer A gate electrode provided with an insulating film between the base layer, a first conductor provided with an insulating film between the first base layer, the floating layer, and the gate electrode; and a second base A second conductivity type emitter layer selectively provided on the layer surface; and an emitter electrode provided on the second base layer and the emitter layer.

  FIG. 1 is a schematic diagram of a main part of the semiconductor device of this embodiment. FIG. 1A is a schematic cross-sectional view of the main part, and FIG. 1B is a schematic plan view of the main part. FIG. 1A is a cross-sectional view taken along line AA in FIG. In FIG. 1B, the emitter electrode 26 and the insulating layer 32 illustrated in FIG. 1A are not displayed.

  The semiconductor device of this embodiment includes a trench IEGT (hereinafter also simply referred to as IEGT). Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The IEGT 100 of this embodiment includes a collector electrode 10, a p-type collector layer 12, an n ⁻ -type base layer (first base layer) 14, a p-type base layer (second base layer) 16, a p-type floating layer 18, A gate electrode (trench gate electrode) 20, a shield electrode (first conductor) 22, an n ⁺ -type emitter layer 24, and an emitter electrode 26 are provided. Here, “n ⁺ emitter layer 24” can also be referred to as “n ⁺ source layer 24”.

The p-type collector layer 12, the n ⁻ -type base layer (first base layer) 14, the p-type base layer (second base layer) 16, and the p-type floating layer 18 are formed of, for example, single crystal silicon (Si). Is done. In each layer, the p-type impurity is, for example, B (boron), and the n-type impurity is, for example, phosphorus (P) or arsenic (As).

  The collector electrode 10 is a metal, for example. A p-type collector layer 12 is provided on the collector electrode 10. The contact between the collector electrode 10 and the p-type collector layer 12 is preferably an ohmic contact.

An n ⁻ type base layer 14 is provided on the p type collector layer 12. The n ⁻ type base layer 14 functions as a drift layer of the IEGT 100.

A p-type base layer 16 is provided on the n ⁻ -type base layer 14. A p-type floating layer 18 is provided on the n ⁻ -type base layer 14. The p-type floating layer 18 is electrically insulated from the surroundings. That is, the p-type floating layer 18 is in an electrically floating state. Since holes do not flow into the p-type floating layer 18, it functions as a barrier against holes.

The IEGT 100 includes a gate electrode 20 provided between the n ⁻ type base layer 14 and the p type base layer 16 via an insulating film 28. A shield electrode 22 is provided between the n ⁻ -type base layer 14, the p-type floating layer 18, and the gate electrode 20 via an insulating film 28. The insulating film 28 between the gate electrode 20 and the p-type base layer 16 functions as a gate insulating film.

  The gate electrode 20 and the shield electrode 22 are provided in the same trench 30 with an insulating film 28 interposed therebetween. The gate electrode 20 and the shield electrode 22 are in contact with the insulating film 28 sandwiched therebetween.

The trench 30 has one end in the p-type base layer 16 and the p-type floating layer 18 and the other end in the n ⁻ -type base layer 14. One end of the gate electrode 20 and the shield electrode 22 is closer to the p-type base layer 16 than the boundary between the p-type base layer 16 and the n ⁻ -type base layer 14, and the other end is connected to the p-type base layer 16 and the n ⁻ -type base. It is on the n ⁻ -type base layer 14 side from the boundary of the layer 14. Furthermore, one end of the gate electrode 20 is closer to the n ⁺ -type emitter layer 24 side than the position where the boundary between the n ⁺ -type emitter layer 24 and the p-type base layer 16 intersects the insulating film 28.

In the IEGT 100, a MOSFET (Metal Oxide Semiconductor Field) having an n ⁺ -type emitter layer 24 as a source, an n ⁻ -type base layer 14 as a drain, a p-type base layer 16 as a base, an insulating film 28 as a gate insulating film, and a gate electrode 20 as a gate. An Effect Transistor structure is formed.

  The gate electrode 20 and the shield electrode 22 are, for example, polycrystalline silicon containing n-type impurities. The insulating film 28 is, for example, a silicon oxide film.

  The gate electrode 20 has a function of controlling channel formation in the p-type base layer 16. Further, the shield electrode 22 has a function of suppressing the influence of the potential fluctuation of the p-type floating layer 18 from reaching the potential of the gate electrode 20. For example, the shield electrode 22 has the same potential as the emitter electrode 26.

An n ⁺ -type emitter layer 24 is selectively provided on the surface of the p-type base layer 16. The n ⁺ type emitter layer 24 has an n type impurity concentration higher than that of the n ⁻ type base layer 14.

  An insulating film 32 is provided on the p-type base layer 16, the p-type floating layer 18, the gate electrode 20, and the shield electrode 22. The insulating film 32 is, for example, a silicon oxide film.

An emitter electrode 26 is provided on the insulating film 32. The insulating film 32 is provided with an opening, and an emitter electrode 26 is provided so as to be in contact with the p-type base layer 16 and the n ⁺ -type emitter layer 24 exposed in the opening.

The emitter electrode 26 is, for example, a metal. The contacts between the emitter electrode 26 and the p-type base layer 16 and the n ⁺ -type emitter layer 24 are preferably ohmic contacts.

  In the IEGT 100 according to the present embodiment, an area surrounded by a broken-line frame in FIG.

  Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described. 2 to 7 are schematic cross-sectional views showing the method for manufacturing the semiconductor device of this embodiment.

For example, boron (B) is ion-implanted as a p-type impurity into an n ⁻ -type single crystal silicon substrate (n ⁻ -type base layer) 14 containing an n-type impurity, and then thermally diffused. A p-type impurity layer to be the p-type floating layer 18 is formed.

  Next, for example, the trench 30 is formed by the RIE method using a mask material (not shown) formed by film deposition by a CVD (Chemical Vapor Deposition) method, a lithography method, and a RIE (Reactive Ion Etching) method as a mask. At this time, a wall 31 that divides the trench 30 into a trench 30a and a trench 30b is formed in the trench 30 by lithography. That is, the width of the wall 31 is greater than the limit of lithography. After the trench 30 is formed, the mask material is peeled off (FIG. 2).

  Next, the insulating film 28 is formed by, for example, thermal oxidation (FIG. 3). At this time, the oxidation conditions are set so that the walls 31 are all oxidized.

  Next, for example, n-type polycrystalline silicon 19 is deposited so as to fill the trench 30 (FIG. 4). The n-type polycrystalline silicon 19 is deposited by, for example, a CVD method.

  Next, the polycrystalline silicon 19 is etched back by, for example, CDE (Chemical Dry Etching) (FIG. 5). By this etch back, the gate electrode 20 and the shield electrode 22 are formed in the trench 30.

Next, the n ⁺ -type emitter layer 24 is selectively formed on the surface of the p-type base layer 16 by, for example, lithography and ion implantation. Then, for example, the insulating film 32 is deposited by the CVD method (FIG. 6). The insulating film 32 is, for example, a silicon oxide film.

Next, the insulating film 32 is patterned by lithography and RIE (FIG. 7). By this patterning, an opening 33 is provided on the p-type base layer 16 and the n ⁺ -type emitter layer 24.

  Thereafter, the p-type collector layer 12, the collector electrode 10, the emitter electrode 26, and the like are formed by a known manufacturing method, and the IEGT 100 shown in FIG. 1 is manufactured.

  Next, the operation and effect of the semiconductor device of this embodiment will be described.

  FIG. 8 is a schematic diagram of a main part of a semiconductor device of a comparative form. The semiconductor device of the comparative form includes IEGT900. In the IEGT 900 of the comparative form, the region surrounded by a broken line frame in FIG. 8 is regarded as one unit, and this unit is repeatedly arranged.

Unlike the IEGT 100 of the present embodiment, the IEGT 900 includes a gate electrode 20 and a shield electrode 22. Each is formed in a different trench. Therefore, three p-type base layers 16 are provided in one unit. In addition, four n ⁺ -type emitter layers 24 are provided in one unit.

Table 1 shows the n ⁺ -type emitter layer width per unit, the p-type base layer width, and the ratio between the n ⁺ -type emitter layer width and the p-type base layer width of the IEGT 100 of the present embodiment and the IEGT 900 of the comparative embodiment. (Emitter / base ratio). Note that, as shown in FIGS. 1A and 8, the width of one p-type base layer 16 is Wp. Further, as shown in FIG. 1B, the width of one n ⁺ -type emitter layer 24 is Wn.

As shown in Table 1, the IEGT 100 of this embodiment has a larger emitter / base ratio per unit than the IEGT 900 of the comparative embodiment. Accordingly, in the IEGT 100, the flow of holes from the n ⁻ type base layer 14 to the p type base layer 16 is relatively suppressed, and electrons are effectively injected from the n ⁺ type emitter layer 24 to the n ⁻ type base layer 14. The amount increases. Therefore, the on-resistance of IEGT is reduced. In other words, the IEGT on-current increases.

Further, as shown in Table 1, the IEGT 100 of this embodiment has a smaller n ⁺ -type emitter layer width per unit than the IEGT 900 of the comparative embodiment. Accordingly, the saturation current of IEGT is reduced, and even when a short circuit occurs in a circuit incorporating IEGT, the amount of current flowing through the circuit is suppressed. Therefore, it is possible to suppress the circuit from being destroyed. Alternatively, it is possible to lengthen the time until the circuit is destroyed.

  Here, as shown in FIGS. 1A and 8, the width of the p-type floating layer 18 is Wp ′. The ratio of the sum of the widths of the p-type base layer 16 and the sum of the widths of the p-type floating layer 18 in one unit ((sum of Wp) / (sum of Wp ′)) is 1/5 or more and 1/1 or less It is desirable to be in the range. In other words, it is desirable that (total sum of Wp) :( total sum of Wp ′) is in the range of 1: 1 to 1: 5.

  When (the sum of Wp) / (the sum of Wp ′) is smaller than 1/5, the proportion of the p-type base layer 16 is reduced, so that the resistance of the MOSFET structure increases and the on-resistance of IEGT becomes too high. There is a fear. On the other hand, if the ratio is larger than 1/1, the flow of holes into the p-type base layer is not sufficiently suppressed, and the on-resistance of IEGT may be excessively increased.

  In the present embodiment, the thickness of the insulating film 28 between the gate electrode 20 and the shield electrode 22 is larger than the thickness of the insulating film 28 between the gate electrode 20 and the p-type base layer 16. This is desirable from the viewpoint of reducing the capacitance between the shield electrodes 22.

  Further, the configuration in which the shield electrode 22 is set to the same potential as the emitter electrode 26 has been described as an example, but the configuration in which the shield electrode 22 is fixed to a potential other than the emitter electrode 26 is not excluded.

  According to the semiconductor device of the present embodiment, it is possible to reduce the on-resistance of IEGT and the saturation current.

(Second Embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment, except that the first conductor is electrically insulated and further includes a potential monitor circuit connected to the first conductor. Therefore, a part of the description overlapping the first embodiment is omitted.

  FIG. 9 is a schematic view of a main part of the semiconductor device of this embodiment. In the IEGT 200 of the present embodiment, the first conductor that functions as a shield electrode in the first embodiment is a floating electrode 42. The semiconductor device of this embodiment includes a potential monitor circuit 44 connected to the floating electrode 42 and a protection circuit 46.

  The potential monitor circuit 44 monitors the potential fluctuation of the p-type floating layer 18 indirectly by monitoring the potential of the floating electrode 42. Thereby, for example, it is possible to detect an abnormal operation in which an overcurrent flows into the p-type floating layer 18.

  The protection circuit 46 has a function of, for example, turning off the power of a circuit in which the IEGT 200 is incorporated when an abnormality is detected by the potential monitor circuit 44. As a result, it is possible to prevent the circuit incorporating the IEGT 200 from being destroyed.

  Note that the potential monitor circuit 44 and the protection circuit 46 can be provided on the same semiconductor substrate as the IEGT 200. Alternatively, it may be configured to be provided as a separate element from the IEGT 200.

  According to the semiconductor device of the present embodiment, it is possible to reduce the on-resistance of IEGT and the saturation current. Further, it is possible to suppress the abnormal operation of the IEGT and to suppress the destruction of the circuit due to the abnormal operation.

(Third embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that the semiconductor device further includes a second conductor provided via an insulating film between the first conductor and the floating layer. Therefore, a part of the description overlapping the first embodiment is omitted.

  FIG. 10 is a schematic diagram of a main part of the semiconductor device of this embodiment. FIG. 10A is a schematic cross-sectional view of the main part, and FIG. 10B is a schematic plan view of the main part. FIG. 10A is a cross-sectional view taken along the line AA in FIG. In FIG. 10B, the emitter electrode 26 and the insulating layer 32 illustrated in FIG. 10A are not displayed.

The IEGT 300 of this embodiment includes a collector electrode 10, a p-type collector layer 12, an n ⁻ -type base layer (first base layer) 14, a p-type base layer (second base layer) 16, a p-type floating layer 18, A gate electrode 20, a shield electrode (first conductor) 22, a floating electrode (second conductor) 50, an n ⁺ -type emitter layer 24, and an emitter electrode 26 are provided.

The IEGT 300 includes a gate electrode 20 provided via an insulating film 28 between the n ⁻ type base layer 14 and the p type base layer 16. A shield electrode 22 is provided between the n ⁻ type base layer 14 and the gate electrode 20 with an insulating film 28 interposed therebetween. Furthermore, a floating electrode 50 is provided between the shield electrode 22 and the p-type floating layer 18 via an insulating film 28. The insulating film 28 between the gate electrode 20 and the p-type base layer 16 functions as a gate insulating film.

  The gate electrode 20, the shield electrode 22, and the floating electrode 50 are provided in the same trench 30 with the insulating film 28 interposed therebetween. The gate electrode 20 and the shield electrode 22 are in contact with the insulating film 28 sandwiched therebetween. The shield electrode 22 and the floating electrode 50 are in contact with the insulating film 28 sandwiched therebetween.

  The IEGT 300 according to the present embodiment has a configuration in which the unit surrounded by a broken-line frame in FIG.

  Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described. 11 to 20 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of this embodiment.

For example, boron (B) is ion-implanted as a p-type impurity into an n ⁻ -type single crystal silicon substrate (n ⁻ -type base layer) 14 containing an n-type impurity, and then thermally diffused. A p-type impurity layer to be the p-type floating layer 18 is formed.

  Next, for example, the trench 30 is formed by the RIE method using a mask material (not shown) formed by film deposition by the CVD method, lithography method and RIE method as a mask. After the trench formation, the mask material is peeled off (FIG. 11).

  Next, the insulating film 28a is formed by, for example, thermal oxidation (FIG. 12).

  Next, for example, n-type polycrystalline silicon 19 is deposited so as to fill the trench 30 (FIG. 13). The n-type polycrystalline silicon is deposited by, for example, a CVD method.

  Next, the polycrystalline silicon 19 is etched back by, for example, the CDE method (FIG. 14). By this etch back, the shield electrode 22 is formed in the trench 30.

  Next, the insulating film 28a is etched back by, eg, wet etching (FIG. 15). By this etch back, a part of the side surface of the shield electrode 22 in the trench 30 is exposed.

  Next, the insulating film 28b is formed by, for example, thermal oxidation (FIG. 16).

  Next, for example, n-type polycrystalline silicon 21 is deposited so as to fill the trench 30 (FIG. 17). The n-type polycrystalline silicon 21 is deposited by, for example, a CVD method.

  Next, the polycrystalline silicon 21 is etched back by, for example, the CDE method (FIG. 18). By this etch back, the gate electrode 20 and the floating electrode 50 are formed in the trench 30.

Next, the n ⁺ -type emitter layer 24 is selectively formed on the surface of the p-type base layer 16 by, for example, lithography and ion implantation. Then, for example, the insulating film 32 is deposited by the CVD method (FIG. 19). The insulating film 32 is, for example, a silicon oxide film.

Next, the insulating film 32 is patterned by lithography and RIE (FIG. 20). By this patterning, an opening 33 is provided on the p-type base layer 16 and the n ⁺ -type emitter layer 24.

  Thereafter, the p-type collector layer 12, the collector electrode 10, the emitter electrode 26, and the like are formed by a known manufacturing method, and the IEGT 300 shown in FIG. 10 is manufactured.

  According to the present embodiment, by providing the floating electrode 50 between the shield electrode 22 and the p-type floating layer 18, even if the potential of the p-type floating layer 18 rises due to overcurrent or the like, p The electric field applied to the insulating film 28 between the mold floating layer 18 and the shield electrode 22 is relaxed. Therefore, destruction of the insulating film 28 is suppressed, and a semiconductor device having excellent reliability is realized.

  Further, according to the present embodiment, the pattern of the three electrodes in the trench 30 can be formed without using a lithography method. Therefore, the structure in the trench can be finely manufactured with good controllability.

  In the IEGT 300 of the present embodiment, it is desirable that the end portion of the shield electrode 22 is closer to the p-type collector layer 12 than the gate electrode 20. This is because the shielding effect by the shield electrode 22 is improved.

  According to the semiconductor device of the present embodiment, it is possible to reduce the on-resistance of IEGT and the saturation current. Further, the resistance of the insulating film in the trench is improved, and high reliability is realized. In addition, it is possible to manufacture a fine electrode structure with good controllability.

(Fourth embodiment)
The semiconductor device of this embodiment is the same as that of the third embodiment except that the second conductor is electrically at the same potential as the emitter electrode. Therefore, a part of the description overlapping the third embodiment is omitted.

  The structure of the IEGT of this embodiment is the same as that of the third embodiment shown in FIG. The second conductor is not electrically insulated but becomes a second shield electrode having the same potential as the emitter electrode.

  According to the semiconductor device of the present embodiment, it is possible to reduce the on-resistance of IEGT and the saturation current. It is also possible to manufacture a fine structure with good controllability.

(Fifth embodiment)
The semiconductor device of this embodiment is the same as that of the third embodiment, except that it further includes a potential monitor circuit connected to the second conductor. Therefore, a part of the description overlapping the third embodiment is omitted.

  FIG. 21 is a schematic diagram of a main part of the semiconductor device of the present embodiment. The IEGT 400 of this embodiment includes a potential monitor circuit 44 connected to the floating electrode 50 and a protection circuit 46.

  The potential monitor circuit 44 monitors the potential fluctuation of the p-type floating layer 18 indirectly by monitoring the potential of the floating electrode 50. Thereby, for example, it is possible to detect an abnormal operation in which an overcurrent flows into the p-type floating layer 18.

  The protection circuit 46 has a function of, for example, turning off the power of a circuit in which the IEGT is incorporated when an abnormality is detected by the potential monitor circuit 44. As a result, it is possible to prevent the circuit incorporating the IEGT from being destroyed.

  Note that the potential monitor circuit 44 and the protection circuit 46 can be provided on the same semiconductor substrate as the IEGT 400. Alternatively, it may be configured as a separate element from the IEGT 400.

  According to the semiconductor device of the present embodiment, it is possible to reduce the on-resistance of IEGT and the saturation current. Further, it is possible to suppress the abnormal operation of the IEGT and to suppress the destruction of the circuit due to the abnormal operation. It is also possible to manufacture a fine structure with good controllability.

(Sixth embodiment)
The semiconductor device of the present embodiment, except that the second conductivity type barrier layer is further provided between the second conductivity type first base layer and the first conductivity type second base layer, This is the same as in the third embodiment. Therefore, a part of the description overlapping the third embodiment is omitted.

FIG. 22 is a schematic view of a main part of the semiconductor device of this embodiment. The IEGT 500 of this embodiment further includes an n-type barrier layer 52 between the n ⁻ -type base layer 14 and the p-type base layer 16. The n-type barrier layer 52 has an n-type impurity concentration higher than that of the n ⁻ -type base layer 14.

The n-type barrier layer 52 functions as a barrier against holes. Therefore, the amount of electrons injected from the n ⁺ -type emitter layer 24 to the n ⁻ -type base layer 14 is effectively increased. Therefore, the on-resistance of IEGT 500 is reduced.

  According to the semiconductor device of this embodiment, the on-resistance of IEGT is further reduced. Also, a reduction in saturation current can be realized. And it becomes possible to manufacture a fine electrode structure with good controllability.

  As described above, in the embodiment, the case where the first conductivity type is p-type and the second conductivity type is n-type has been described as an example. However, the first conductivity type is n-type and the second conductivity type is p-type. Is also possible.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 collector electrode 12 p-type collector layer 14 n ^- type base layer (first base layer)
16 p-type base layer (second base layer)
18 p-type floating layer 20 gate electrode 22 shield electrode (first conductor)
24 n ⁺ type emitter layer 26 Emitter electrode 28 Insulating film 44 Potential monitor circuit 50 Floating electrode (second conductor)
100 IGBT
200 IGBT
300 IGBT
400 IGBT
500 IGBT

Claims (5)

A collector electrode;
A collector layer of a first conductivity type provided on the collector electrode;
A first base layer of a second conductivity type provided on the collector layer;
A second base layer of a first conductivity type provided on the first base layer;
A first conductive type floating layer provided on the first base layer and electrically insulated;
Between the first base layer, and a gate electrode provided via an insulating film between said second base layer,
A first conductor provided through an insulating film between the first base layer, the floating layer, and the gate electrode;
A second conductivity type emitter layer selectively provided on the surface of the second base layer;
An emitter electrode provided on the second base layer and the emitter layer;
A potential monitor circuit connected to the first conductor;
A semiconductor device comprising: A collector electrode;
A collector layer of a first conductivity type provided on the collector electrode;
A first base layer of a second conductivity type provided on the collector layer;
A second base layer of a first conductivity type provided on the first base layer;
A first conductive type floating layer provided on the first base layer and electrically insulated;
A gate electrode provided between the first base layer and the second base layer via an insulating film;
A first conductor provided through an insulating film between the first base layer, the floating layer, and the gate electrode;
A second conductor provided via an insulating film between the first conductor and the floating layer ;
A second conductivity type emitter layer selectively provided on the surface of the second base layer;
An emitter electrode provided on the second base layer and the emitter layer;
A potential monitor circuit connected to the second conductor;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the first conductor is electrically insulated from the emitter electrode and the gate electrode. 3. The semiconductor device according to claim 2, wherein the second conductor is electrically insulated from the emitter electrode and the gate electrode . The first conductor is a semiconductor device electrically claim 2 or claim 4, wherein the a emitter electrode at the same potential.

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