JP6160360B2 - Electronic device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic device and a manufacturing method thereof.

  There is known a structure in which when an electrode pad is formed on a semiconductor substrate on which a solid-state imaging device is formed, a dummy electrode pad is also formed. In this case, the pad openings that expose the electrode pads made of aluminum or aluminum alloy and the dummy electrode pads are formed simultaneously.

  Since the ratio of the area of the electrode pad to the entire element increases by the exposed area of the dummy electrode pad, the individual electrode pads can be used depending on the etching solution, developer, etc. used in forming the pad opening. The battery effect acting on the surface of the electrode becomes weak, and corrosion of the electrode pad is suppressed.

JP 2006-269592 A JP 2008-004598 A

  According to the structure as described above, if the corrosion of the electrode pad is to be effectively suppressed, the pad area is increased, which hinders downsizing of the element. Further, when a sufficient area for forming the dummy electrode pad cannot be secured, the corrosion prevention effect of the electrode pad is weakened.

  An object of the present invention is to provide an electronic device capable of preventing the occurrence of an abnormality on the surface of a metal pattern exposed from an opening without hindering the miniaturization of the element, and a method for manufacturing the same.

According to one aspect of the present embodiment, an insulating film formed above a semiconductor substrate is electrically connected within an element formation region of the semiconductor substrate and exposed through a first opening of the insulating film. is a first metal pattern formed from a first metallic material, are electrically connected to the semiconductor substrate around the area of the element forming region, exposed through the second opening of the insulating film, the first A second metal pattern formed from a second metal material having the same ionization tendency as that of the first metal material and serving as a sacrificial pattern that hinders the battery effect of the first metal pattern by the patterning liquid; and the total exposed area of the second metal pattern It has a total exposed area of the following are electrically connected to the semiconductor substrate in the region of the periphery of the element forming region is exposed through the third opening of the insulating film, the said first metallic material Is formed from the second metal material from the third metallic material of a large ionization tendency, the second metal pattern through the semiconductor substrate than the first electron transfer path between the first metal pattern through the semiconductor substrate A second metal movement path between the third metal pattern formed at a position where the electric resistance is reduced, and a patterning process formed on the insulating film and using the patterning liquid, There is provided an electronic device comprising: a fourth opening exposing the first metal pattern; and a coating insulating film formed with the exposed portion exposing the second metal pattern and the third metal pattern. Is done.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

  According to this embodiment, it is possible to prevent the occurrence of abnormality on the surface of the metal pattern exposed from the opening without hindering the miniaturization of the element.

1A and 1B are a plan view and a partially enlarged plan view showing an example of a semiconductor wafer on which an electronic device according to an embodiment is formed. 2A and 2B are a cross-sectional view and a plan view illustrating a part of an element formation region and a part of a scribe line in a semiconductor wafer on which the electronic device according to the embodiment is formed. FIG. 3 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 4 is a cross-sectional view illustrating a process of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 5 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 6 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 7 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 8 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 9 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 10 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 11 is a cross-sectional view illustrating a step of forming the multilayer wiring structure of the electronic device according to the embodiment. 12A and 12B are plan views illustrating a process of forming the multilayer wiring structure of the electronic device according to the embodiment. FIG. 13 is a plan view illustrating a modification of the electronic device according to the embodiment. FIG. 14 is a plan view showing the relationship between the areas of the test electrode pad and the sacrificial metal turn in the electronic device according to the embodiment. FIG. 15 is a plan view showing a relationship between distances between contact portions of an actual device electrode pad, a test element test electrode pad, and a sacrificial metal pattern in the electronic device according to the embodiment. FIG. 16 is a cross-sectional view illustrating an electronic device according to a comparative example.

  Embodiments will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.

  FIG. 1A is a plan view of a semiconductor wafer on which an electronic device according to this embodiment is formed, and FIG. 1B is an enlarged plan view showing a part thereof. The semiconductor wafer is formed with transistors, contact regions, monitor elements and the like as illustrated in the cross-sectional views and plan views of FIGS. 2A and 2B. Further, as shown in the cross-section of FIG. A multilayer wiring structure is formed on the semiconductor wafer. Thereafter, as shown in the cross-sectional views of FIGS. 4 to 11, electrode pads, bumps, and the like are formed on the semiconductor wafer, and then the semiconductor wafer is divided into elements.

  1A and 1B, a plurality of semiconductor device formation regions 2 are arranged vertically and horizontally in a surface direction on a silicon substrate 1 which is a wafer-like semiconductor substrate. In the silicon substrate 1, scribe lines 20 are arranged in a lattice-like boundary region that partitions the plurality of semiconductor device formation regions 2. The scribe line 20 has a cutting device for separating and dividing the semiconductor device forming regions 2 from each other, for example, a region in which a blade of a dicing saw is put in the center.

  First, in the semiconductor device formation region 2, as shown in the cross-sectional and plan views of FIGS. 2A and 2B, a MOS transistor, a contact region, and the like are formed on a p-type silicon substrate 1. 2A shows a cross section taken along the line II in FIG. 2B.

  A P well 3 is formed in a part of the semiconductor device (element) formation region 2 in the p-type silicon substrate 1. The P well 3 is formed by ion-implanting a p-type impurity such as boron into the silicon substrate 1 using a resist pattern (not shown) as a mask. In the P well 3, an active region 5 and a contact region 11 that are partitioned by an element isolation insulating film 4 a are disposed adjacent to each other. In this embodiment, the element isolation insulating film 4a employs shallow trench isolation (STI) having a structure in which a recess is formed in the upper portion of the silicon substrate 1 and an insulating film is embedded therein. As the element isolation insulating film 4, LOCOS (local oxidation of silicon) formed by thermal oxidation may be adopted.

  A gate electrode 7 is formed in the active region 5 through a gate insulating film 6, and n-type extension regions 8a and 8b having low impurity concentrations are formed in the P-well 3 on both sides by n-type impurity ion implantation. Yes. The gate electrode 7 is formed, for example, by patterning a polysilicon film. An insulating sidewall 13 is formed on the side wall of the gate electrode 7. Further, n-type high concentration impurity regions 8c and 8d are formed on both sides of the region where the gate electrode 7 and the sidewall 13 are formed by n-type impurity ion implantation.

  Thus, on both sides of the gate electrode 7, the n-type extension regions 8a and 8b and the n-type high concentration impurity regions 8c and 8d are connected to form n-type source / drain regions 9s and 9d. Silicide layers 10a, 10b, and 10c are formed on the surface layers of the gate electrode 7 and the n-type high concentration impurity regions 8c and 8d on both sides thereof.

  In the contact region 11 in the P well 3, a p-type contact region 12 of a p-type impurity having a concentration higher than that of the P well 3 is formed by ion implantation, and a silicide layer 10d is formed on the surface layer thereof.

In the semiconductor device forming region 2, the above-described gate electrode 7, n-type source / drain regions 9s, 9d, n-type MOS transistors _{T 11} for actual device or the like P-well 3 is formed. In the semiconductor device forming region 2, rather than only the n-type MOS transistor _{T 11} is formed, the other n-type MOS transistor (not shown), and active elements such p-type MOS transistor (not shown), the resistor A passive element such as a capacitor may be formed.

  The scribe line 20 of the silicon substrate 1 has a predetermined width, and in the region, for example, first, second and third P wells 22a, 22b, in order from the boundary with the semiconductor device formation region 2, 22c is formed. The first, second and third P wells 22a, 22b and 22c are formed separately from each other by ion implantation of p-type impurities using a resist pattern (not shown).

  As shown in FIG. 1B, the first P well 22a is a region to which a seal ring 61, which will be described later, is electrically connected, and the second P well 22b is This is an area where a crack stopper 62 (described later) is electrically connected. For example, the seal ring 61 and the crack stopper 62 have a frame shape surrounding the semiconductor device formation region 2. Accordingly, the first and second P wells 22a and 22b may be formed to double surround the semiconductor device formation region 2. The third P well 22c is a region where at least one monitor element, for example, a MOS transistor is formed, and has a transistor forming active region 23a and a contact region 23b.

  In the silicon substrate 1, an element isolation insulating film 4b, for example, STI is formed surrounding the first to third P wells 22a, 22b, and 22c. Further, in the third P well 22c, the element isolation insulating film 4c is also formed between the active region 23a and the contact region 23b. The element isolation insulating films 4b and 4c in the scribe line 20 are formed by the same method as the element isolation insulating film 4a in the semiconductor device formation region 2.

  A gate electrode 27 is formed on the active region 23a of the third P well 22c via a gate insulating film 26. In the third P well 22c on both sides of the active region 23a, n impurity having a low impurity concentration is formed by ion implantation. Mold extension regions 28a and 28b are formed. The gate electrode 27 is formed, for example, by patterning a polysilicon film. An insulating sidewall 33 is formed on the side wall of the gate electrode 27. Further, n-type high concentration impurity regions 28c and 28d are formed on both sides of the region including the gate electrode 27 and the sidewall 33 by ion implantation.

  Thus, on both sides of the gate electrode 27, the n-type extension regions 28a and 28b and the n-type high concentration impurity regions 28c and 28d are connected to form n-type source / drain regions 29s and 29d. Silicide layers 30a, 30b, and 30c are formed on the surface layers of the gate electrode 27 and the n-type high impurity regions 28c and 28d on both sides thereof, respectively.

  Further, a p-type contact region 32 having a higher impurity concentration than that of the third P well 22c is formed in the contact region 23b in the third P well 22c by ion implantation, and a silicide layer 30d is formed on the surface layer thereof. ing. The silicide layers 30a, 30b, 30c, and 30d in the scribe line 20 may be formed simultaneously with the silicide layers 10a, 10b, and 10c in the semiconductor device formation region 2.

The above-described gate electrode 27, n-type source / drain regions 29s, 29d, and the like third P-well 22c n-type MOS transistor _{T 21} is a monitor element is formed. Incidentally, within the scribe line 20, instead of only n-type MOS transistor _{T 21} is formed, the other n-type MOS transistor (not shown), p-type MOS transistor (not shown), such as other monitoring element is It may be formed.

On the silicon substrate 1 on which the n-type MOS transistors T ₁₁ and T ₂₁ , the p-type contact regions 12 and 32, etc. are formed as described above, a multilayer wiring structure is formed as shown in FIG. The wiring of the multilayer wiring structure is formed by a damascene method or a dual damascene method.

As the multilayer wiring structure, first, a first interlayer insulating film 37 is formed on the silicon substrate 1, thereby covering the n-type MOS transistors T ₁₁ and T ₂₁ , the p-type contact regions 12 and 32, and the like. As the first interlayer insulating film 37, for example, a silicon oxide film is formed by a CVD method, and the surface thereof is planarized by, for example, chemical mechanical polishing (CMP).

Next, the gate electrode 7 and the n-type source / drain regions 9s of n-type MOS transistors _{T 11} of the semiconductor device forming region 2, the contact hole on the silicide layer 10a~10d of 9d and p-type contact region 12 surface Form. At the same time, the gate electrode 27 and the n-type source / drain regions 29s of the n-type MOS transistors _{T 21} in the scribe line 20, and the upper silicide layer 30a~30d of the surface of each of the 29d and the p-type contact region 32, first, Contact holes are formed on the second P wells 22a and 22b. The contact holes on the first and second P wells 22a and 22b are formed, for example, at one or a plurality of positions or the entire region surrounding the semiconductor device formation region 2. Thereafter, conductive plugs 35a to 35d and 36a to 36f are formed in the contact holes. The conductive plugs 35a to 35d and 36a to 36f are formed by forming, for example, a titanium nitride film or a tungsten film in the contact hole. Note that the tungsten film and the titanium nitride film formed on the upper surface of the first interlayer insulating film 37 are removed by, for example, a CMP method.

  Next, a second interlayer insulating film 38 and a protective insulating film 39 are sequentially formed on the first interlayer insulating film 37. For example, a silicon carbide oxide (SiOC) film having a dielectric constant lower than that of the silicon oxide film is formed as the second interlayer insulating film 38 by the CVD method, and an SiC film is formed as the protective insulating film 39 by the CVD method, for example. Thereafter, the protective insulating film 39 and the second interlayer insulating film 38 are patterned using photolithography and etching.

  Thereby, a plurality of first-layer wiring grooves passing over the conductive plugs 35a to 35d in the semiconductor device formation region 2, and a plurality of first-layer wiring grooves passing over the conductive plugs 36a to 36f in the scribe line 20 A first annular groove is formed. The first-layer annular groove is formed in a double ring shape on each of the first and second P wells 22a and 22b that double surround the semiconductor device forming region 2 to the outside, and the first and second P wells 22a. , 22b are connected to each of the conductive plugs 36e, 36f. Thereafter, the grooves are filled with copper. Thereby, first-layer copper wirings 51a to 51d are formed in the first-layer wiring trench in the semiconductor device formation region 2 by the damascene method. In the scribe line 20, annular first layer copper patterns 51 e and 51 f that double surround the semiconductor device forming region 2 and first layer copper wirings 51 g to 51 j are formed by a damascene method.

Thus, the gate electrode 7 of the MOS transistor _{T 11} of the semiconductor device forming region 2, n-type source / drain regions 9s, conductive plugs 35a Each 9d, 35b, first layer wiring 51a via 35c, 51b, 51c is connected. The first-layer wiring 51d is electrically connected to the p-type contact region 12 through the conductive plug 35d.

Further, the gate electrode 27 of the p-type MOS transistors _{T 21} in the scribe line 20, n-type source / drain regions 29s, the conductive plugs 36a on top of each 29d, 36b, first layer wiring 51h~51j through 36c Is connected. A first layer copper wiring 51g is connected to the p-type contact region 32 via a conductive plug 36d. At the same time, annular first layer copper patterns 51e and 51f are electrically connected to the first and second P wells 22a and 22b in the scribe line 20 via the conductive plugs 36e and 36f, respectively. .

  As a method of forming the first layer copper wirings 51a to 51d and 51g to 51j and the annular first layer copper patterns 51e and 51f, for example, the following method is adopted.

  First, a titanium film, for example, as a copper diffusion prevention conductive film is formed on the upper surfaces of the second interlayer insulating film 38 and the protective insulating film 39 and the inner surfaces of the first-layer wiring groove and the first-layer annular groove therein by sputtering. Thereafter, a copper seed film is formed by sputtering. Subsequently, using the copper seed layer as an electrode, the copper film is filled in the first layer wiring groove and the first layer annular groove by electrolytic plating. Thereafter, the copper diffusion preventing conductive film, the copper seed layer, and the copper film formed on the protective insulating film 39 are removed by CMP.

  According to such a damascene method, the copper film or the like left in the first-layer wiring groove becomes the above-described first-layer copper wiring 51a to 51d, 51g to 51j, and the copper film or the like left in the first-layer annular groove is It is used as an annular first layer copper pattern 51e, 51f.

  Next, a first barrier insulating film 40 and a third interlayer insulating film 41 are sequentially formed on the protective insulating film 39, the first layer copper wirings 51a to 51d, 51g to 51j, and the first layer copper patterns 51e and 51f.

  The first barrier insulating film 40 is a film that prevents diffusion of copper, and a silicon nitride film, a silicon carbide (SiC) film, or the like is formed by a sputtering method, a CVD method, or the like. In addition, as the third interlayer insulating film 41, for example, either a SiOC film or a SiC film is formed by a CVD method. A silicon nitride layer serving as a polishing stopper layer may be formed as an upper layer portion of the third interlayer insulating film 41. Barrier insulating films 42, 44, and 46 described later are formed of the same material as the first barrier insulating film 40, and interlayer insulating films 43, 45, and 47 described later are formed of the same material as the third interlayer insulating film 41. Is done.

  Next, in the third interlayer insulating film 41 and the first barrier insulating film 40, a first-layer via hole is formed on the first-layer copper wiring 52a above the p-type contact region 12 and the like in the semiconductor device formation region 2. Then, a part of the first-layer wiring 51a is exposed from the via hole. Thereafter, a second-layer wiring groove connected to the first-layer via hole is formed in the upper layer portion of the third interlayer insulating film 41. The via hole and the wiring groove are formed by using photolithography and etching including those described later.

  Thereafter, a copper diffusion prevention conductive film and a copper seed film are sequentially formed in the first via hole and the second wiring groove, and then a copper film is formed on the copper seed film by electrolytic plating. These films are removed from the second interlayer insulating film 41 by the CMP method. As a result, the second layer copper wiring 52d including the first layer via is formed by the dual damascene method from the first layer via hole and the copper film left in the second layer wiring trench. Including the following examples, a conductive film such as titanium nitride or tantalum nitride is formed as the copper diffusion preventing conductive film.

  By the same method, on the annular first layer copper patterns 51e and 51f above the first and second P wells 22a and 22b in the scribe line 20 in the third interlayer insulating film 41 and the first etch stop layer 40. An annular second-layer copper pattern 52a, 52b overlapping with the first-layer via is formed by a dual damascene method. Similarly, a second-layer copper wiring 52c having a first-layer via is also formed on the first-layer wiring 51g on the scribe line 20 such as the p-type contact region 32 by the dual damascene method, and at the same time, another first-layer wiring is formed. Second-layer copper wiring (not shown) is also formed on 51h, 51i, 51j.

  Next, a second barrier insulating film 42 and a fourth interlayer insulating film 43 are formed on the second layer copper wirings 52 c and 52 d, the second layer copper patterns 52 a and 52 b, and the third interlayer insulating film 41. Thereafter, a third-layer copper wiring 53d with a via is formed in the semiconductor device formation region 2 in the second barrier insulating film 42 and the fourth interlayer insulating film 43 by the same method as described above by the dual damascene method. Further, the third layer copper wiring 53c with vias is dually formed on the second layer copper wiring 52c in the region within the scribe line 20 in the second barrier insulating film 42 and the fourth interlayer insulating film 43 by the same method as described above. At the same time, the annular third layer copper patterns 53c and 53b with vias are formed on the annular second layer copper patterns 52a and 52b.

  Next, a third barrier insulating film 44 and a fifth interlayer insulating film 45 are formed on the third layer copper wirings 53a and 53d, the third layer copper patterns 53b and 53c, and the fourth interlayer insulating film 43. Further, in the third barrier insulating film 44 and the fifth interlayer insulating film 45, third-layer copper wirings 53c and 53d, and fourth-layer copper wiring 54c with vias connected to each of the annular third-layer copper patterns 53a and 53b. , 54d and annular fourth-layer copper patterns 54a, 54b with vias are formed by a dual damascene method.

Next, a fourth barrier insulating film 46 and a sixth interlayer insulating film 47 are formed on the fourth layer copper wirings 54 a and 54 d, the fourth layer copper patterns 54 b and 54 c, and the fifth interlayer insulating film 45. Furthermore, fifth-layer copper wirings 55c and 55d with vias connected to the fourth-layer copper wirings 54c and 54d and the fourth-layer copper patterns 54a and 54b in the fourth barrier insulating film 46 and the sixth interlayer insulating film 47, respectively. And annular fifth-layer copper patterns 55a and 55b with vias are formed by a dual damascene method.

  As a result, in the semiconductor device formation region 2, the first to fifth layer wirings 51d to 55d are electrically connected in the thickness direction via the conductive plug 35d on the silicide layer 10d on the surface of the p-type contact region 12. Connected. In the scribe line 20, the first to fifth layer wirings 51 g and 52 c to 55 c are electrically connected in the thickness direction via the conductive plug 36 d on the silicide layer 30 d on the surface of the p-type contact region 32. . Furthermore, annular first to fifth layer copper patterns 51e, 52a to 55a are electrically connected to the first P well 22a via a conductive plug 36e. In addition, annular first to fifth layer copper patterns 51f and 52b to 55b are electrically connected to the second P well 22b via a conductive plug 36f.

  Next, a fifth barrier insulating film 48 and a seventh interlayer insulating film 49 are formed on the fifth layer copper wirings 55c and 55d, the fifth layer copper patterns 55a and 55b, the sixth interlayer insulating film 47, and the like. Thereafter, the fifth barrier insulating film 48 and the seventh interlayer insulating film 49 are patterned using photolithography and etching. As a result, openings for exposing the fifth-layer copper wirings 55c and 55d are formed, and annular openings for exposing the annular fifth-layer copper patterns 55a and 55b are formed.

  Next, after a metal film having aluminum as a main conductor layer is formed in the openings and on the fifth barrier insulating film 48, the seventh interlayer insulating film 49, etc., the metal film is formed by photolithography and etching. Pattern. Thereby, in the semiconductor formation region 2, the metal pad 56d made of aluminum is formed in and around the opening on the fifth-layer copper wiring 55d. Although not particularly illustrated, a plurality of metal pads 56 d are formed in the semiconductor device formation region 2. At the same time, annular metal patterns 56a and 56b connected to the annular fifth layer copper patterns 55a and 55b above the first and second P wells 22a and 22b in the scribe line 20 through the annular openings are formed. To do. At the same time, in the scribe line 20, a metal pattern to be the test electrode pad 56 c made of aluminum is formed in the opening on the fifth layer copper wiring 55 c above the p-type contact region 32 and on the seventh interlayer insulating film 49 in the vicinity thereof. Form.

  Thereby, in the scribe line 2, the first to fifth layer copper patterns 51e, 52a to 55a and the metal pattern 56a are electrically connected to the upper surface of the first P well 22a via the conductive plug 36e in the thickness direction. Connected and stacked. This laminated structure is used as the seal ring 61. As shown in FIG. 1B, the seal ring 61 is formed in a region of the scribe line 20 that is closer to the semiconductor device formation region 2 than the monitor element. Thus, the seal ring 61 surrounds the semiconductor device formation region 2 to prevent moisture from entering the semiconductor device formation region 2 from the outside and crack growth at the time of cutting along the center of the scribe line 2. As a function.

  In the scribe line 2, the annular first-layer to fifth-layer copper patterns 51 f, 52 b to 55 b and the metal pattern 56 b are electrically connected in the thickness direction via the conductive plug 36 f on the second P well 22 b. Connected and stacked. This laminated structure is used as an annular crack stopper 62. As shown in FIG. 1B, the crack stopper 62 is formed in an annular shape so as to be closer to the semiconductor device formation region 2 than the monitor element and surround the seal ring 61. Thereby, the crack stopper 62 has a function of preventing a crack from extending toward the semiconductor device 2 when the silicon substrate 1 is cut along the scribe line 20.

In the scribe line 2, the test electrode pad 56 c is formed on the p-type contact region 32 in the thickness direction via the silicide layer 30 d, the conductive plug 36 d, and the first to fifth layer copper wirings 51 g and 52 c to 55 c. It is electrically connected and used as one of the test terminals. The gate electrode 27 of n-type MOS transistor _{T 21} is a monitor device, n-type source / drain regions 29s, the copper wiring also on the 29d (not shown), the test electrode pads (not shown) are stacked.

  Next, as illustrated in FIG. 4, for example, a silicon nitride film is formed as a protective insulating film 50 on the seventh interlayer insulating film 49, the metal pad 56d, the metal patterns 56a and 56b, and the test electrode pad 56c by the CVD method. Form. Thereafter, the protective insulating film 50 is patterned by photolithography and etching. As a result, openings 50b, 50c, and 50d are formed on the metal pattern 56b above the annular crack stopper 62 in the scribe line 20, the test electrode pad 56c, and the metal pad 56d in the semiconductor device formation region 2, respectively. To do. In the following description, it is assumed that the seal ring 61 formed in the region between the semiconductor device formation region 2 and the crack stopper 62 is covered with the protective insulating film 50.

  Next, as illustrated in FIG. 5, after applying a first photosensitive resin, for example, photosensitive polyimide, as the first covering insulating film 63 on the protective insulating film 50 and in the openings 50 b, 50 c, 50 d, The first photosensitive resin is exposed, developed, and the like. As a result, in the semiconductor device formation region 2, the upper opening 63 d is formed on the opening 50 d exposing the metal pad 56 d, and the other region is covered with the first covering insulating film 63. Further, in the scribe line 2, the first covering insulating film 63 is left around both the seal ring and the monitor element of the annular opening 50 b on the annular crack stopper 62, and is removed in other regions. . In addition, an annular upper opening 63 b is formed in the first covering insulating film 63 on the annular opening 50 b exposing the annular metal pattern 56 b above the annular crack stopper 62 in the protective insulating film 50. Is done.

  Next, as illustrated in FIG. 6, a copper diffusion prevention conductive film 64 and a copper seed film 65 are formed on the upper surface of the first covering insulating film 63 and the inner surfaces of the openings 63d and 50d in the semiconductor device formation region 2 by sputtering. Form. For example, a titanium film is formed as the copper diffusion preventing conductive film 64. At the same time, a copper diffusion preventing conductive film 64 and a copper seed film 65 are formed on the upper surfaces of the first covering insulating film 63 and the protective insulating film 50 of the scribe line 20 and the inner surfaces of the openings 63b and 50b. Thereafter, a photoresist 67 is applied on the copper sheet film 65, and exposure, development, and the like are performed thereon. As a result, in the semiconductor device formation region 2, a wiring forming opening 67d drawn from the metal pad 56d exposed in the openings 63d and 50d is formed in the photoresist 67. At the same time, in the scribe line 20, the annular sacrificial pattern forming opening 67 b exposing the first covering insulating film 63 in and around the annular openings 63 b and 50 b on the annular crack stopper 62 is photo-photographed. It is formed in the resist 67.

  Next, copper is formed in the wiring forming opening 67d and the sacrificial pattern forming opening 67b by an electrolytic plating method using the copper diffusion preventing conductive film 64 and the copper seed film 65 as electrodes. As a result, a copper lead wiring 66d, which is a metal pattern drawn from the metal pad 56d, is formed in the wiring formation opening 67d in the semiconductor device formation region 2. A copper sacrificial metal pattern 66 b is formed in an annular shape along the crack stopper 62 in the annular sacrificial pattern forming opening 67 b of the scribe line 2. Note that a plurality of lead wirings 66d are formed in the semiconductor formation region 2 although not particularly illustrated. The sacrificial metal pattern 66b may have a shape in which a part of the annular shape is interrupted.

Next, the photoresist 67 is removed, and the copper seed layer 65 and the copper diffusion preventing conductive film 64 exposed thereby are etched. In this case, the lead wiring 66d and the sacrificial metal pattern 66b serve as a mask. Thereby, as illustrated in the cross-sectional view of FIG. 7 and the plan view of FIG. 12A , the first covering insulating film 63 is exposed in the semiconductor device formation region 2. In the scribe line 20, the protective insulating film 50 and the test electrode pad 56c are exposed, and the upper surface of the first covering insulating film 63 is substantially covered with the sacrificial metal pattern 66b on the side of the test electrode pad 56c.

  Next, as illustrated in FIG. 8, the second covering insulating film is formed on the copper lead wiring 66d, the copper sacrificial metal pattern 66b, the first covering insulating film 63, the protective insulating film 50, the test electrode pad 56c, and the like. A second photosensitive resin such as photosensitive polyimide is applied as 68. Thereafter, the second photosensitive resin is exposed to light, developed, and the like, thereby forming a pad opening 68d that exposes the pad portion of the copper lead wiring 66d in the semiconductor device formation region 2, and the other regions. 2 The covering insulating film 68 is left. A part of the planar shape is illustrated in FIG. Further, in the scribe line 20, the second photosensitive resin that is the second covering insulating film 68 is removed. 8 and the subsequent sectional views, the copper seed layer 65 and the copper diffusion preventing conductive film 64 are omitted.

  Incidentally, the first and second photosensitive resins used as the first and second coating insulating films 63 and 68 are developed using an alkaline developer R after exposure. Among them, when developing the second photosensitive resin used as the second covering insulating film 68, the photosensitive resin is gradually removed in the scribe line 20 to expose the aluminum test electrode pad 56c, which is sacrificed. A battery effect is produced together with the metal pattern 66b.

That is, aluminum ions (Al ²⁺ ) migrate from the aluminum test electrode pad 56c having a high ionization tendency into the developing solution R, and electrons (2e ⁻ ) remain in the test electrode pad 56c. Copper also has a lower ionization tendency than aluminum. For this reason, the electrons generated in the test electrode pad 56c pass through the copper wirings 51g, 52c to 55c, the conductive plug 36d, the silicide layer 30d, and the p-type contact region 32 below the third P well 22c. Move to. The electrons reaching the third P well 22c further move to the copper sacrificial metal pattern 66b through the p-type silicon substrate 1, the second P well 22b, and the crack stopper 62. Thus, the electrons that have reached the sacrificial metal pattern 66b molecularize hydrogen ions (2H ⁺ ) present in the developer, and generate hydrogen (H ₂ ) gas on the surface of the sacrificial metal pattern 66b.

In this case, with respect to the center of the aluminum test electrode pad 56c, the shortest distance L ₁ from the center of the connection portion of the copper lead wire 66d and the metal pad 56d is the shortest distance from the center of the sacrificial metal pattern 66b Longer than L _{2 and} high in resistance value. Therefore, by setting the condition of L ₁ > L ₂ as a trial, electrons in the test electrode pad 56c hardly move to the copper lead wiring 66d, and generation of hydrogen on the exposed surface of the copper lead wiring 66d is suppressed. Is done.

Further, in the scribe line 20, an aluminum test electrode pad (not shown) is connected to the gate electrode 27 of the n-type MOS transistor T ₂₁ and the n-type source / drain regions 29 s and 29 d via the conductive plugs 36 d and 36 e. ) Is connected. Therefore, electrons are easily moved to the third P well 22c through the n-type source / drain regions 29s and 29d. Further, electrons are difficult to move from the third P well 22c to the n-type source / drain regions 29s and 29d because of the pn junction. Therefore, the electrons that have reached the p-type contact region 32 preferentially flow into the second P well 22b.

  By the way, in order to facilitate movement of electrons generated in the test electrode pad 56c through the silicon substrate 1 to the conductive sacrificial metal pattern 66b, as illustrated in FIG. 13, the second P of the element isolation insulating film 4b is used. The separation between the well 22b and the third P well 22c may be eliminated, and the second P well 22b may be included in the third P well 22c. In this case, the sacrificial metal pattern 66 b is connected to the silicide layer 30 d on the surface of the contact region 32 through the crack stopper 62. For this reason, when electrons move from the test electrode pad 56c made of aluminum to the sacrificial metal pattern 66b made of copper, the silicide 30d on the surface of the contact region 32 having a high impurity concentration becomes a part of the electron transfer path, and the electricity in the electron transfer path Resistance becomes low. Thereby, the movement of the electrons to the semiconductor device formation region 2 is prevented.

Meanwhile, as in the comparative example shown in FIG. 16, in the structure in which the sacrificial metal pattern 66b is not formed and the crack stopper 62 is covered with the protective insulating film 50, the test electrode pad 56c made of aluminum and the copper product are made in the developer. A battery effect is generated in the lead wiring 66d. For this reason, hydrogen gas is generated in and around the copper lead wiring 66d exposed from the opening 68d of the second covering insulating film 68, and the second covering insulating film 68 and the copper lead wiring 66d are surrounded around the exposed surface. Adhesion decreases. As a result, the second covering insulating film 68 is lifted from the copper lead wiring 66d, so that inconvenience that a solder bump connection failure to be formed on the lead wiring 66d in the opening 68d is likely to occur in the next step. . On the other hand, in the present embodiment, since the battery effect is preferentially generated between the sacrificial metal pattern 66b in the scribe line 20 and the test electrode pad 56c, the second covering insulation in the semiconductor device formation region 2 is achieved. A decrease in adhesion between the film 68c and the lead wiring 66d can be prevented.

  Thus, in the present embodiment, the sacrificial metal pattern 66b is exposed around the semiconductor device formation region 2 and the copper film is closest to the aluminum test electrode pad 56c. From this, hydrogen is preferentially generated. As a result, the second covering insulating film 68 that exposes a part of the copper lead wiring 66d in the semiconductor device formation region 2 is prevented from floating around the opening 68d, and the solder bumps on the copper lead wiring 66d are prevented. Formation can be performed satisfactorily. Solder bumps are formed by the method illustrated in the cross sections of FIGS. 9 and 10 after cleaning the second covering insulating film 68, the protective insulating film 50, and the like.

In FIG. 9, a base conductive film 69 and a copper seed film 70 are formed in the opening 68d for bump formation and on the second covering insulating film 68, the protective insulating film 50, the sacrificial metal pattern 66b, the test electrode pad 56c, and the like. Are formed in order. For example, Ti is formed as the base conductive film 69. Thereafter, a photoresist 74 is applied on the copper seed film 70, and thereafter, the photoresist 74 is subjected to exposure, development, and the like. Thereby, an opening 74d for bump formation is formed in the photoresist 74, and the opening 68d for bump formation of the second coating insulating film 68 and its periphery are exposed. Thereafter, a nickel layer 71 and a solder layer 72 are formed on the copper seed film 70 in the bump forming openings 74d and 68d by an electrolytic plating method using the copper seed film 70 as a part of the electrode.

  Next, the photoresist 74 is removed, the solder layer 72 is used as a mask, and the exposed copper seed film 70 and Ti base metal film 69 are etched and removed by a sputtering method. Thereby, the upper surfaces of the second covering insulating film 68 and the protective insulating film 50 are exposed. Thereafter, as illustrated in FIG. 10, the solder layer 72 is heated and reflowed to form a hemispherical surface and used as the solder bump 73.

Next, a dicing blade is inserted into the center line of the scribe line 20 of the wafer-like semiconductor substrate 1 shown in FIG. 1 to cut the semiconductor substrate 1 so that the semiconductor device formation region 2 is separated into chips. During dicing, the seal ring 61 and the crack stopper 62 as shown in FIG. 1B surround the semiconductor device formation region 2. In this case, as illustrated in the cross-sectional view of FIG. 11, in the scribe line 20, the n-type MOS transistor T ₂₁ , the test electrode pad 56c, and the like are destroyed and removed. Further, since the blade of the dicing saw 75 is inserted so that the seal ring 61 and the crack stopper 62 close to the semiconductor device forming region 2 are left, at least a part of the sacrificial metal pattern 66b is exposed on the crack stop 62. It becomes.

When the first and second coating insulating films 63 and 68 made of resin are present on the scribe line 20 during dicing, the resin adheres to the blade of the dicing saw 75, so that it is necessary to remove the resin from the blade after cutting. Make it worse. On the other hand, in this embodiment, the resin-made second covering insulating film 68 is left slightly under the sacrificial metal pattern 66b, and most of the sacrificial metal pattern 66b is formed in the semiconductor device after dicing. It is made to remain around the area 2. For this reason, it can prevent that resin adheres to the blade of a dicing saw in said embodiment.

According to the above embodiment, the second covering insulating film 68 covering the semiconductor device forming region 2 is patterned to form the opening 68d exposing a part of the copper lead wiring 66d. A copper sacrificial metal pattern 66b is formed. For this reason, when the opening 68d is formed in the second covering insulating film 68, the exposed area of copper in other regions of the semiconductor device formation region 2 increases, so that the battery effect of the copper lead wiring 66d is weakened. Deterioration of the lead wiring 66d is suppressed. In addition, since the dummy metal pattern is not formed in the semiconductor device formation region 2 in order to weaken the battery effect, the occurrence of an abnormality on the surface of the lead wiring 66d exposed from the opening 68d without hindering the downsizing of the semiconductor device. Can be suppressed. In addition, in the scribe line 20 outside the semiconductor device formation region 2, the test electrode pad 56c having a larger ionization tendency than the lead wiring 66d is brought close to the sacrificial metal pattern 66b . Thereby, the battery effect by the test electrode pad 56c and the sacrificial metal pattern 66b is preferential, and the generation of the battery effect in the lead wiring 66d can be further suppressed. If the sacrificial metal pattern 66b is connected to the upper end of at least one of the seal ring 61 and the crack stopper 62, deterioration of the lead wiring 66d can be suppressed.

By the way, as shown in FIG. 14, the exposed area of the sacrificial metal pattern 66b in the scribe line 20 per unit length along the length of the boundary between the scribe line 20 and the semiconductor device formation region 2 is S ₁ , n tests. the sum of the exposed area _{S 2} of use the electrode pads 56c and _{S 2} × n. Here, the test electrode pad 56c includes a test electrode pad (not shown) that is electrically connected to the gate electrode 27, the source / drain regions 29s, 29d, and the like of the n-type MOS transistor T21.

In this case, it is preferable to set the size of the sacrificial metal pattern 66b so that the condition of S ₁ ≧ nS ₂ is satisfied. This is to prevent electrons per unit surface area generated by the plurality of aluminum test electrode pads 56c from exceeding the capacity per unit surface area for accepting electrons of the sacrificial metal pattern 66b. This prevents electrons from moving to the copper lead wiring 66d in the semiconductor device formation region 2 through the p-type silicon substrate 1, the P well 22b, and the like.

FIG. 15 shows a plurality of conductive plugs 35d, 36d, and 36f that electrically connect the copper lead wiring 66d, the copper sacrificial metal pattern 66b, and the aluminum test electrode pad 56c to the silicon substrate 1, respectively. Shows the distance. That is, the distance of the conductive plugs 36d to be electrically connected to the conductive plugs 35d and the test electrode pad 56c is electrically connected to the lead wire 66d on a silicon substrate 1 and L _11. Further, a distance L ₂₁ between the conductive plug 36d electrically connected to the test electrode pad 56c on the silicon substrate 1 and the conductive pad 36f electrically connected to the sacrificial metal pattern 66b is set. In this case, in order to move the electrons generated in the test electrode pad 56c to the sacrificial metal pattern 66b and not to the extraction wiring 66d, it is preferable to set the condition of L ₁₁ > L ₂₁ . In this case, in the plan view shown in FIG. 2B, the same conditions are applied to the respective lead wirings 66d in the semiconductor device formation region 2 arranged on both sides of the scribe line 20.

  By the way, the sacrificial metal pattern 66b in the scribe line 20 may be arranged on both sides of the test electrode pad 56c as shown in FIG. 1B, or as shown in FIG. You may form in only one side among the right and left of 56c.

  In the above embodiment, the test electrode pad 56c electrically connected to the contact region 32 in the silicon substrate 1 connected to the monitor element via the conductive plug 36d or the like is formed of aluminum. It may be. The annular sacrificial metal pattern 66b may be formed of a copper alloy or the like. Further, in the region surrounding the semiconductor device formation region 2, the material of the sacrificial metal pattern 66b electrically connected to the silicon substrate 1 and the material of the test electrode pad 56c electrically connected to the silicon substrate 1 are respectively described above. It is not limited to things. For example, the metal material of the test electrode pad 56c may be a material that has a different ionization tendency than the metal material of the sacrificial metal pattern 66b and the metal material of the lead wiring 66d, and preferably a material that is larger. Thereby, corrosion and generation of hydrogen on the surface of the lead wiring 66d exposed from the opening 68d of the second covering insulating film 68 are suppressed.

  In the above-described embodiment, a semiconductor device and a method for forming the semiconductor device are described. However, the test electrode pad and the sacrificial pad are applied to an electronic device such as a solid-state imaging device such as a CCD or a CMOS sensor, and A sacrificial metal pattern 66b or the like may be formed around the periphery.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Appendix 1) An insulating film formed above the semiconductor substrate, a first metal pattern electrically connected to an element formation region of the semiconductor substrate and exposed through the first opening of the insulating film; A second metal pattern electrically connected to the semiconductor substrate around the element formation region and exposed through the second opening of the insulating film, and electrically connected to the semiconductor substrate around the element formation region The first metal material of the first metal pattern and the second metal material of the second metal pattern exposed from the third opening of the insulating film are formed of a third metal material having different ionization tendency. And an electronic device comprising three metal patterns.
(Supplementary note 2) The electronic device according to supplementary note 1, wherein a plurality of the element formation regions in the semiconductor substrate are arranged in a plane direction via a scribe line around the element formation region.
(Supplementary note 3) The electronic device according to Supplementary note 1 or Supplementary note 2, wherein an ionization tendency of the third metal material is larger than an ionization tendency of the first metal material and the second metal material.
(Supplementary note 4) The electronic device according to any one of supplementary notes 1 to 3, wherein the first metal pattern is formed of the same metal as the second metal pattern.
(Additional remark 5) The said 3rd metal pattern is a test electrode pad electrically connected to a part of monitor element formed in the said semiconductor substrate around the said element formation area, The additional remark 1 characterized by the above-mentioned. Or an electronic device according to any one of appendix 4.
(Appendix 6) The appendix 1 to appendix 5, wherein the second metal pattern is connected to at least one of a metal crack stopper or a metal seal ring formed on the semiconductor substrate. The electronic device according to any one of the above.
(Supplementary note 7) The seal ring, which is covered with the insulating film in a region between the crack stopper and the element formation region, is formed above the semiconductor substrate around the element formation region. 7. The electronic device according to 6.
(Supplementary note 8) Any one of Supplementary notes 1 to 7, wherein a distance between the third metal pattern and the first metal pattern is equal to or greater than a distance between the second metal pattern and the third metal pattern. Electronic device described in one.
(Supplementary Note 9) A plurality of the third metal patterns are formed.
The electronic device according to any one of the above.
(Supplementary note 10) The total area of the second metal pattern per unit length along the edge of the element formation region is larger than the total area of the third metal pattern per unit length. 1 to 9. The electronic device according to appendix 9.
(Supplementary Note 11) The first metal pattern is electrically connected to the first one-conductivity type region of the semiconductor substrate through a first conductive plug, and the second metal pattern includes a second conductive plug. The third metal pattern is electrically connected to the second one conductivity type region of the semiconductor substrate through a third conductive plug. The electronic device according to any one of Supplementary Note 1 to Supplementary Note 10, wherein the electronic devices are connected to each other.
(Additional remark 12) The distance between the said 1st conductive plug and the said 3rd conductive plug is more than the distance between the said 2nd conductive plug and the said 3rd conductive plug, The additional remark 11 characterized by the above-mentioned. The electronic device according to.
(Supplementary Note 13) The second metal pattern and the third metal pattern are electrically connected through the silicide film on the surface of the semiconductor substrate through the second conductive plug and the third conductive plug. The electronic device according to appendix 11 or appendix 12, characterized in that.
(Supplementary Note 14) The first metal pattern is formed from either copper or a copper alloy, the second metal pattern is formed from either copper or a copper alloy, and the third metal pad is any of aluminum or an aluminum alloy. 14. The electronic device according to any one of supplementary notes 1 to 13, wherein the electronic device is formed.
(Supplementary Note 15) An insulating film formed above the semiconductor substrate, a first metal pattern electrically connected to an element formation region of the semiconductor substrate and exposed through the first opening of the insulating film; A second metal pattern electrically connected to the semiconductor substrate in a region around the element formation region and exposed through a second opening of the insulating film; and the semiconductor substrate in the region around the element formation region A third metal material that is electrically connected to and exposed through a third opening of the insulating film, and the first metal material of the first metal pattern and the second metal material of the second metal pattern are different in ionization tendency A step of forming a photosensitive resin film on the third metal pattern formed from, a step of exposing the photosensitive resin film, and developing the photosensitive resin film using a developer, The element Forming a fourth opening exposing the first metal pattern from the photosensitive resin film in the formation region, and removing the photosensitive resin from the surrounding region of the element formation region; Forming a bump on the first metal pattern exposed from the opening.
(Supplementary Note 16) After developing the photosensitive resin film, a blade of a cutting machine is put in the peripheral region of the element formation region of the semiconductor substrate to make the element formation region into a chip shape and the third metal Item 17. The method for manufacturing an electronic device according to Item 16, further comprising a step of removing the pattern.
(Supplementary note 17) The supplementary note 15 or the supplementary note 16, wherein a plurality of the element formation regions in the semiconductor substrate are arranged in a plane direction via a scribe line which is the peripheral region of the element formation region. Electronic device manufacturing method.
(Supplementary note 18) The electronic device according to any one of supplementary notes 15 to 17, wherein an ionization tendency of the third metal material is larger than an ionization tendency of the first metal material and the second metal material. Manufacturing method.
(Supplementary note 19) The total area of the second metal pattern per unit length along the edge of the element formation region is larger than the total area of the third metal pattern per unit length. The manufacturing method of the electronic device of 15 thru | or appendix 18.
(Supplementary note 20) Any one of Supplementary notes 15 to 18, wherein a distance between the third metal pattern and the first metal pattern is equal to or greater than a distance between the second metal pattern and the third metal pattern. The manufacturing method of the electronic device as described in one.

1 Silicon substrate (semiconductor wafer)
2 Semiconductor device formation region 3, 22a-22c P wells 4a, 4b, 4c Element isolation insulating films 10a-10c, 30a-30d Silicide layer 12, 32 p-type contact region 20 Scribe lines 35a-35c, 36a-36f Conductive plug 37, 38, 41, 43, 45, 47, 49 Interlayer insulating film 40, 42, 44, 46, 48 Barrier insulating film 50 Protective insulating film 50c Openings 51a-51d, 51g-51j Copper wirings 52c, 53c, 54c, 55c Copper wirings 52d, 53d, 54d, 55d Copper wirings 51e, 51f Copper patterns 52a, 53a, 54a, 55a Copper patterns 52b, 53b, 54b, 55b Copper patterns 56a, 56b Metal patterns 56c Metal pads for testing 56d Metal pads 61 Seals Ring 62 Crack stopper 63, 68 Cover Enmaku 66b sacrificial metal pattern 66d lead wires 63b, 63d, 68d opening 73 solder bumps R developer _{T 11, T 21} n-type MOS transistor

Claims (5)

An insulating film formed above the semiconductor substrate;
A first metal pattern electrically connected within an element formation region of the semiconductor substrate, exposed through a first opening of the insulating film, and formed from a first metal material ;
Electrically connected to the semiconductor substrate in a region around the element formation region, exposed through the second opening of the insulating film, and formed from a second metal material having the same ionization tendency as the first metal material; A second metal pattern serving as a sacrificial pattern that hinders the battery effect of the first metal pattern by the patterning liquid ;
Has a total exposed area of less total exposed area of the second metal pattern is electrically connected to the semiconductor substrate in the region of the periphery of the element forming region is exposed through the third opening of the insulating film , is formed from a third metal material of a larger ionization tendency than the second metal material and the first metallic material, a first of said semiconductor than electron transfer path between the first metal pattern through the semiconductor substrate A third metal pattern formed at a position where the second electron movement path between the second metal pattern and the second metal pattern through the substrate has a smaller electric resistance ;
A fourth opening that exposes the first metal pattern and an exposed portion that exposes the second metal pattern and the third metal pattern formed by patterning using the patterning liquid formed over the insulating film. A coating insulating film formed with
An electronic device comprising: The electronic device according to claim 1, wherein the second metal pattern has an annular shape surrounding the element formation region or a shape in which the annular shape is interrupted. An insulating film formed above the semiconductor substrate is electrically connected within an element formation region of the semiconductor substrate, exposed through a first opening of the insulating film, and formed from a first metal material . a first metal pattern is electrically connected to the semiconductor substrate around the area of the element forming region, exposed through the second opening of the insulating film, the second metal of the same ionization tendency as the first metal material A second metal pattern formed of a material and a total exposed area equal to or less than a total exposed area of the second metal pattern, and electrically connected to the semiconductor substrate in the peripheral region of the element formation region; the exposed through the third opening of the insulating film, it is formed from a third metal material of a larger ionization tendency than the second metal material and the first metallic material, between the first metal pattern through the semiconductor substrate of On the third metal pattern towards the second electron transfer path between the second metal pattern through the semiconductor substrate than the first electron transfer path is formed at a position where electric resistance decreases, the photosensitive Forming a conductive resin film;
Exposing the photosensitive resin film;
The photosensitive resin film is developed with a developer using a developer to form a fourth opening that exposes the first metal pattern from the photosensitive resin film in the element formation region, and the element As the sacrificial metal pattern that removes the photosensitive resin from the surrounding area of the formation area to expose the second metal pattern and the third metal pattern and hinders the battery effect of the first metal pattern by the developer. Using a second metal pattern ;
Forming bumps on the first metal pattern exposed from the fourth opening;
A method for manufacturing an electronic device, comprising:   After developing the photosensitive resin film, a blade of a cutting machine is put in the peripheral area of the element forming area of the semiconductor substrate to make the element forming area into a chip shape and to remove the third metal pattern. The method for manufacturing an electronic device according to claim 3, further comprising a step. 5. The method of manufacturing an electronic device according to claim 3, wherein the second metal pattern has an annular shape surrounding the element formation region or a shape in which the annular shape is interrupted. 6.

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