JP6169928B2 - Gate drive circuit and power conversion device - Google Patents

Description

  Embodiments described herein relate generally to a gate drive circuit and a power conversion device that drive a voltage-driven transistor on and off.

  For example, an inverter circuit that converts an AC voltage of a power supply system into a DC voltage and converts it to an arbitrary power supply frequency is configured by combining a plurality of voltage-driven transistors such as IGBTs and MOSFETs, and each transistor is driven by a gate drive circuit. ing. In recent years, the switching speed of transistors has been increased in order to reduce the loss of the transistors, and problems such as an increase in EMI noise and surge voltage during switching have become serious.

JP-A-6-253529

  In order to reduce EMI noise and surge voltage, the switching speed is designed to be optimal by adjusting the value of the gate resistance while considering the element temperature (element loss) of the transistor. In order to further reduce EMI noise and surge voltage, it is effective to adaptively control the switching speed (dV / dt) in accordance with the operation status of the power converter. However, in the conventional design method, it is not easy to change the gate resistance once mounted on the circuit board or the like by adjustment work, and it is difficult to control the switching speed according to the operation state of the power converter.

  Therefore, a gate drive circuit and a power conversion device that can easily control the switching speed of a voltage-driven transistor are provided.

  The gate drive circuit of the embodiment uses the source or emitter potential of the voltage-driven transistor as a reference potential, and drives the voltage-driven transistor on and off according to the gate drive signal. The on-drive constant current circuit, the off-drive constant current circuit, It has.

  The on-drive constant current circuit is provided between the first drive voltage line having the first drive voltage higher than the threshold voltage of the voltage-driven transistor and the gate of the voltage-driven transistor, and the gate drive signal is on level. At this time, a constant current is output in the direction in which the gate capacitance of the voltage-driven transistor is charged, and the output constant current value can be changed according to the on-drive control voltage.

The off drive constant current circuit is provided between a second drive voltage line having a second drive voltage lower than a reference potential and the gate of the voltage drive transistor, and the voltage drive transistor when the gate drive signal is at an off level. A constant current is output in the direction in which the gate capacitance is discharged, and the output constant current value can be changed according to the off drive control voltage.
The on-drive constant current circuit is connected between the first and second transistors constituting the current mirror circuit connected to the first drive voltage line, and the on-drive control voltage line having the on-drive control voltage. The first switch circuit and the first reference resistor are connected in series to each other, and the first switch circuit is configured to be turned on when the gate drive signal is at the on level.

Configuration diagram of main part of gate drive circuit showing first embodiment Configuration diagram of conversion circuit Configuration diagram of power converter Operation explanation diagram at turn-on Illustration of operation at turn-off Simulation waveform diagram The figure which shows the flow of adjustment work of surge voltage reduction about 3rd Embodiment FIG. 1 equivalent view showing the fourth embodiment FIG. 1 equivalent diagram showing the fifth embodiment

(First embodiment)
The first embodiment will be described with reference to FIGS. As shown in FIG. 3, the power conversion device 1 includes a DC power supply circuit 2, an inverter circuit 3, a gate drive circuit 4, a control unit 5, and the like. The DC power supply circuit 2 includes a three-phase diode bridge (not shown) and a capacitor (not shown) connected between the DC power supply lines 6 and 7, and rectifies and smoothes a three-phase AC voltage supplied from a commercial AC power supply to generate a DC. Convert to voltage Vdc.

  The inverter circuit 3 includes IGBTs 8up, 8vp, 8wp, 8un, 8vn, and 8wn (voltage driven transistors) connected to a three-phase bridge and a freewheeling diode 9up, 9vp, 9wp, 9un, 9vn, and 9wn. IGBTs 8up to 8wn and freewheeling diodes 9up to 9wn are one pair each (1 IGBT and 1 diode), elements constituting the upper and lower arms of each phase (2 IGBTs and 2 diodes) or all elements (6 IGBTs and 6 diodes) Is modularized. A three-phase load such as a motor 11 is connected to the output nodes 10 u, 10 v, and 10 w of the inverter circuit 3. The IGBTs 8up to 8wn are driven by the gate drive circuit 4 having the same configuration.

  The control unit 5 is configured mainly with a microcomputer, and is a control unit that controls the operation of the power conversion device 1 including the inverter circuit 3. The control unit 5 detects a phase current by a current detection unit (not shown), detects a voltage signal by a voltage detection unit (not shown), and calculates a phase voltage command signal from these and a frequency command signal. The control unit 5 compares the phase voltage command signal obtained by the calculation with the carrier signal, and outputs gate drive signals Gup to Gwn by PWM control to each gate drive circuit 4.

  The control unit 5 generates voltage control signals for generating an on-drive control voltage V3 and an off-drive control voltage V4, which will be described later, for the gate drive circuit 4 that drives the IGBT 8xp (x: u, v, w) of the upper arm, respectively. Sxp and Txp are output. The control unit 5 generates a common voltage control signal Sn for generating an on drive control voltage V3 and an off drive control voltage V4 for the gate drive circuit 4 that drives the IGBT 8xn (x: u, v, w) of the lower arm. , Tn are output.

  FIG. 1 shows the configuration of the main part of the gate drive circuit 4. For example, the gate drive circuit 4 of the U-phase upper arm uses the emitter potential of the IGBT 8up as a reference potential, and drives the IGBT 8up on and off according to the gate drive signal Gup after being insulated by a photocoupler or the like.

  The gate drive circuit 4 includes an on-drive constant current circuit 12 and an off-drive constant current circuit 13 having a symmetrical circuit structure. The on-drive constant current circuit 12 is provided between the first drive voltage line 14 having the first drive voltage V1 (for example, + 15V) higher than the threshold voltage Vth of the IGBT 8up and the gate of the IGBT 8up. The off drive constant current circuit 13 is provided between the second drive voltage line 15 having the second drive voltage V2 (for example, −15V) lower than the reference potential and the gate of the IGBT 8up.

  The on-drive constant current circuit 12 includes PNP-type first and second transistors Q1 and Q2 having an emitter connected to the first drive voltage line 14 and constituting a current mirror circuit. The off-drive constant current circuit 13 includes NPN-type third and fourth transistors Q3 and Q4 whose emitters are connected to the second drive voltage line 15 and constitute a current mirror circuit. The collectors and bases of the transistors Q1 and Q3 are connected to each other.

  The on-drive control voltage line 16 and the off-drive control voltage line 17 are respectively supplied with an on-drive control voltage V3 and an off-drive control voltage V4 output from a conversion circuit 18 described later. Between the collector of the transistor Q1 and the ON drive control voltage line 16, the emitter-collector of the PNP transistor Q5 and the first reference resistor R1 are connected in series. Between the collector of the transistor Q3 and the off drive control voltage line 17, the emitter-collector of the NPN transistor Q6 and the second reference resistor R2 are connected in series. The transistors Q5 and Q6 function as a first switch circuit and a second switch circuit, respectively.

  A gate drive signal Gup is supplied to the bases of the transistors Q5 and Q6 via resistors R3 and R4, respectively. The resistors R3 and R4 limit the base currents of the transistors Q5 and Q6.

  Gate resistors R5 and R7 are connected in series between the collector of the transistor Q2 and the gate of the IGBT 8up. Gate resistors R6 and R7 are connected in series between the collector of the transistor Q4 and the gate of the IGBT 8up. The on-drive constant current circuit 12 outputs (sources) a constant current I1 in a direction in which the gate capacitance of the IGBT 8up is charged when the gate drive signal Gup is on level (V2 as an example). The off drive constant current circuit 13 outputs (sinks) a constant current I2 in a direction in which the gate capacitance of the IGBT 8up is discharged when the gate drive signal Gup is at an off level (V1 as an example).

  The conversion circuit 18 illustrated in FIG. 2 constitutes a part of the gate drive circuit 4. The conversion circuit 18 receives the voltage control signal S (Sup, Svp, Swp, Sn) given from the control unit 5, and generates an on drive control voltage V3 having a magnitude corresponding to the duty ratio. Although not shown, the conversion circuit 18 that receives the voltage control signal T (Tup, Tvp, Twp, Tn) and generates the off drive control voltage V4 having a magnitude corresponding to the duty ratio is similarly configured.

  The conversion circuit 18 includes a photocoupler 19 to insulate the control unit 5 from the IGBTs 8up to 8wn. A resistor R8 is connected between the output port of the controller 5 and the input terminal of the photocoupler 19. The emitter of the phototransistor built in the photocoupler 19 is connected to the emitter of any of the IGBTs 8up to 8wn serving as the reference potential. The collector of this phototransistor is connected to the first drive voltage line 14 via a resistor R9, and is connected to the base of the transistor Q7 via a resistor R10.

  The collector of the transistor Q7 is connected to the first drive voltage line 14 via the resistor R11. A resistor R12 and a capacitor C1 are connected in series between the collector and emitter of the transistor Q7. The voltage of the capacitor C1 becomes the ON drive control voltage V3. According to this configuration, the transistor Q7 is turned off while the voltage control signal S is at the H level (5V as an example) to charge the capacitor C1, and the transistor Q7 is turned on while the voltage control signal S is at the L level (0V as an example). Thus, the capacitor C1 is discharged.

  As a result, the on-drive control voltage V3 becomes a voltage within the range of 0V to V1 with respect to the reference potential in proportion to the duty ratio of the voltage control signal S. The off drive control voltage V4 also becomes a voltage within the range of 0V to V2 with respect to the reference potential in proportion to the duty ratio of the voltage control signal T.

  Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 4 is an operation explanatory diagram when the IGBT 8up is turned on. When the gate drive signal Gup becomes an on level (V2; −15V), a base current flows through the transistor Q5 as shown in FIG. 4A, and the transistor Q5 is turned on. At this time, the transistor Q6 is turned off. When the transistor Q5 is turned on, a base current flows through the transistors Q1 and Q2 as shown in FIG. 4B, and the transistors Q1 and Q2 are turned on. As a result, the collector current I1 flows through the transistor Q2 as shown in FIG. The constant current I1 charges the gate capacitance of the IGBT 8up through the gate resistors R5 and R7, and turns on the IGBT 8up.

The current I1 can be adjusted by the voltage applied to the reference resistor R1. Assuming that the mirror ratio of the current mirror circuit composed of the transistors Q1 and Q2 is 1, the current I1 is expressed by the equation (1).
I1 = (V1-V3-VBE (Q1) -VCE (Q5)) / R1 (1)

  Here, the resistance values of the drive voltage V1 and the reference resistor R1 are constant, and the transistors VBE (Q1) and VCE (Q5) are also substantially constant. Therefore, by varying the ON drive control voltage V3, the magnitude of the gate current I1 that charges the gate capacitance of the IGBT 8up can be adjusted, and the turn-on time of the IGBT 8up, that is, the switching speed can be controlled. Specifically, the gate current I1 increases as the ON drive control voltage V3 is lower than the drive voltage V1. As described above, the control unit 5 can control the on-drive control voltage V3 by controlling the duty ratio of the voltage control signal Sup.

  FIG. 5 is an operation explanatory diagram when the IGBT 8up is turned off. When the gate drive signal Gup becomes an off level (V1; + 15V), a base current flows through the transistor Q6 as shown in FIG. 5A, and the transistor Q6 is turned on. At this time, the transistor Q5 is turned off. When the transistor Q6 is turned on, a base current flows through the transistors Q3 and Q4 as shown in FIG. 5B, and the transistors Q3 and Q4 are turned on. As a result, the collector current I2 flows through the transistor Q4 as shown in FIG. The constant current I2 discharges the gate capacitance of the IGBT 8up through the gate resistors R6 and R7, and turns off the IGBT 8up.

The current I2 can be adjusted by the voltage applied to the reference resistor R2. Assuming that the mirror ratio of the current mirror circuit composed of the transistors Q3 and Q4 is 1, the current I2 is expressed by equation (2).
I2 = (V4-V2-VBE (Q3) -VCE (Q6)) / R2 (2)

  Here, the resistance values of the drive voltage V2 and the reference resistor R2 are constant, and the transistors VBE (Q3) and VCE (Q6) are also substantially constant. Therefore, by varying the off drive control voltage V4, the magnitude of the gate current I2 that discharges the gate capacitance of the IGBT 8up can be adjusted, and the turn-off time, that is, the switching speed of the IGBT 8up can be controlled. Specifically, the gate current I2 increases as the off drive control voltage V4 is higher than the drive voltage V2. As described above, the control unit 5 can control the off drive control voltage V4 by controlling the duty ratio of the voltage control signal Tup.

  In FIG. 6, DC voltage Vdc = 500V, drive voltage V1 = + 15V, drive voltage V2 = −15V, on drive control voltage V3 is changed to three types of 0V, 5V, and 7V, and off drive control voltage V4 is set to 0V. It is a simulation waveform when it changes into three types, -5V and -7V. From the top, the gate drive signal Gup, the gate current I1 or I2, and the collector-emitter voltage VCE of the IGBT 8up are shown.

  At turn-on, it can be seen that the higher the on-drive control voltage V3 (that is, the lower V1-V3), the smaller the magnitude of the gate current I1, and the slower the switching speed of the IGBT 8up at turn-on. Similarly, at the time of turn-off, the lower the off drive control voltage V4 (that is, the lower V4-V2), the smaller the magnitude of the gate current I2 is, and the lower the switching speed of the IGBT 8up at turn-off is. .

  As the output current of the inverter circuit 3 decreases, the control unit 5 increases the duty ratio of the voltage control signal S (Sup, Svp, Swp, Sn) to increase the on-drive control voltage V3, and the gate current I1 decreases. To control. At the same time, the control unit 5 increases the duty ratio of the voltage control signal T (Tup, Tvp, Twp, Tn) to lower the off drive control voltage V4 and controls the gate current I2 to be smaller. In order to perform this control, it is necessary to prepare in advance a relational expression of the loss of the IGBT 8up to 8wn, the inverter output current, the carrier frequency fc, and the gate currents I1 and I2. As a result, EMI noise and surge voltage associated with switching can be reduced while limiting the temperature rise of the IGBTs 8up to 8wn within an allowable value.

  As described above, the gate drive circuit 4 of the present embodiment changes the IGBT 8up by changing the on drive control voltage V3 and the off drive control voltage V4 without changing the components including the gate resistors R5 to R7. The switching speed (dV / dt) of ˜8 wn can be controlled. Thereby, the control part 5 becomes easy to adjust the switching speed according to the driving | running state of the inverter circuit 3. FIG.

(Second Embodiment)
A second embodiment of the power conversion device 1 using the gate drive circuit 4 will be described. The control unit 5 shown in FIG. 3 lowers the carrier frequency fc under a predetermined condition in order to reduce EMI noise or reduce a surge voltage generated at the motor end. When the carrier frequency fc is lowered, the EMI noise and the surge voltage are reduced, the switching loss is reduced, and the temperature of the IGBT module is lowered.

  Since the control unit 5 controls the temperature of the IGBT module to be equal to or lower than an allowable value, there is a margin in the loss of the IGBT module when the carrier frequency fc is lowered. Therefore, the control unit 5 uses the loss reduction to reduce the gate currents I1 and I2 described above, thereby reducing the IGBT switching speed and further reducing EMI noise and surge voltage. Specifically, as described below, the gate currents I1 and I2 are controlled so that the loss of the IGBT module before and after the decrease of the carrier frequency fc is constant (the temperature of the IGBT module is constant).

  Saturation loss Psat, on-loss Pon, and off-loss Poff occur in the IGBT that constitutes the IGBT module, and forward loss Pf and recovery loss Prr occur in the free wheel diode. The sum of these losses is the loss of the IGBT module. Saturation loss Psat and forward loss Pf depend on collector current Ic, and on-loss Pon, off-loss Poff and recovery loss Prr depend on collector current Ic, carrier frequency fc, and gate current Ig. The gate current Ig is an integrated representation of the above-described gate currents I1 and I2. For example, when the absolute values of the gate currents I1 and I2 are controlled to be equal, the gate current Ig becomes the absolute value.

  When the collector current Ic is constant, the saturation loss Psat and the forward loss Pf are constant even if other factors change. The on loss Pon, the off loss Poff, and the recovery loss Prr are proportional to the carrier frequency fc. Each loss becomes a function shown in the following equations (3) to (7), for example. α is a constant. The control unit 5 stores these functions in advance.

Psat = fpsat (Ic) (3)
Pf = fpf (Ic) (4)
Pon = α · fc · fpon (Ic, Ig) (5)
Poff = α · fc · fpoff (Ic, Ig) (6)
Prr = α · fc · fprr (Ic, Ig) (7)

When the collector current is Ic1, the carrier frequency is fc1, and the gate current is Ig1, the loss P Loss1 per IGBT module is expressed by equation (8).
PLoss1 = fpsat (Ic1) + fpf (Ic1) + αfc1 (fpon (Ic1, Ig1) + fpoff (Ic1, Ig1) + fpr (Ic1, Ig1)) (8)

When the collector current is Ic1, the carrier frequency is fc2 (<fc1), and the gate current is Ig2 (<Ig1), the loss P Loss2 per IGBT module is expressed by equation (9).
PLoss2 = fpsat (Ic1) + fpf (Ic1) + αfc2 (fpon (Ic1, Ig2) + fpoff (Ic1, Ig2) + fprr (Ic1, Ig2)) (9)

In order to keep the temperature of the IGBT module constant, it is sufficient that PLoss1 = PLoss2. Here, let us consider a case where the loss does not change for each loss as shown in the equations (10) to (12).
fc1 · fpon (Ic1, Ig1) = fc2 · fpon (Ic1, Ig2) (10)
fc1 · fpoff (Ic1, Ig1) = fc2 · fpoff (Ic1, Ig2) (11)
fc1 · fprr (Ic1, Ig1) = fc2 · fprr (Ic1, Ig2) (12)

If β = fc1 / fc2 is defined, equations (10) to (12) become equations (13) to (15), respectively.
β · fpon (Ic1, Ig1) = fpon (Ic1, Ig2) (13)
β · fpoff (Ic1, Ig1) = fpoff (Ic1, Ig2) (14)
β · fprr (Ic1, Ig1) = fprr (Ic1, Ig2) (15)

  As described above, when the carrier frequency fc is lowered from fc1 to fc2, the gate current Ig can be reduced from Ig1 to Ig2 so that the on-loss Pon, the off-loss Poff, and the recovery loss Prr are each β times.

  When the carrier frequency fc is changed from fc1 to fc2 by the parameter, the control unit 5 obtains the gate current Ig2, that is, the gate currents I1 and I2 satisfying the expressions (13) to (15) using the above-mentioned function stored in advance. . Subsequently, the control unit 5 determines the on drive control voltage V3 and the off drive control voltage V4 using the equations (1) and (2), and has a duty ratio for generating the drive control voltages V3 and V4. Voltage control signals S and T are output to the gate drive circuit 4.

  According to the present embodiment described above, when the carrier frequency fc is lowered, the switching loss of the IGBT module is reduced together with the EMI noise. Therefore, under the control condition in which the temperature of the IGBT module is constant, the switching speed is reduced by the loss reduction amount. Can be lowered. Since the gate drive circuit 4 can dynamically control the switching speed while continuing the operation by changing the gate currents I1 and I2 by the voltage control signals S and T, the EMI noise can be further reduced. it can.

(Third embodiment)
A third embodiment of the power converter 1 using the gate drive circuit 4 will be described with reference to FIG. If the cable connecting the power conversion device 1 and the motor 11 shown in FIG. 3 is long and dV / dt at the time of switching is large, an excessive surge voltage exceeding the surge resistance of the motor 11 may be generated at the motor terminal. is there. Therefore, the control unit 5 uses the gate drive circuit 4 to lower the IGBT switching speed and reduce dV / dt to mitigate the surge voltage generated at the motor end.

  The surge voltage at the motor end varies depending on the type of the inverter circuit 3, the type of the motor 11, the type of the cable between the inverter and the motor, the length, the wiring route, and the like. Therefore, it is necessary to adjust with the actual machine to which the motor 11 is connected when the power conversion apparatus 1 is introduced. FIG. 7 shows an adjustment procedure performed by an operator during installation. The power converter 1 can change the gate currents I1 and I2 according to parameters.

  The power converter 1 is operated in a state where the assumed maximum load is applied, and the surge voltage at the motor end is measured (step S1). It is determined whether or not the measured surge voltage is higher than the voltage level allowed from the surge tolerance of the motor 11 (step S2). If it is determined to be high (YES), the gate currents I1 and I2 are lowered according to the parameters, and the switching speed is lowered (step S3). Steps S1 to S3 are repeated, and if it is determined in step S2 that the surge voltage is lower than the allowable voltage level (NO), the process proceeds to step S4.

  In step S4, it is determined whether or not the adjusted parameters (gate currents I1 and I2) are larger than a limit level at which the temperature of the IGBT module can be maintained below the allowable value. If the parameter is larger than the limit level, the temperature of the IGBT module may exceed the allowable value, so the carrier frequency fc is lowered to reduce the loss (step S5). As described above, lowering the carrier frequency fc can also reduce the EMI noise.

  According to this embodiment described above, the surge voltage at the motor end is set to be equal to or lower than the allowable voltage level by changing the set values of the parameters (gate currents I1 and I2) when installing the power converter 1. Can be adjusted easily.

(Fourth and fifth embodiments)
8 and 9 show the configuration of the gate drive circuits 21 and 22 according to the fourth and fifth embodiments, respectively. The IGBTs 8up to 8wn shown in FIG. 3 are driven by gate drive circuits 21 or 22 having the same configuration. The gate drive circuit 21 includes an on drive constant current circuit 12 and an off drive circuit 23. The off drive circuit 23 is provided between the second drive voltage line 15 and the gate of the IGBT 8up, and discharges the gate capacitance of the IGBT 8up when the gate drive signal Gup is at the off level (V1). The voltage of the second drive voltage line 15 is lower than the reference potential (the emitter potential of the IGBT 8up).

  The gate drive circuit 22 includes an off drive constant current circuit 13 and an on drive circuit 24. The on drive circuit 24 is provided between the first drive voltage line 14 and the gate of the IGBT 8up, and charges the gate capacitance of the IGBT 8up when the gate drive signal Gup is on level (V2). The voltage of the first drive voltage line 14 is equal to or higher than the threshold voltage Vth of the IGBT 8up.

  The off drive circuit 23 and the on drive circuit 24 are configured by a switch circuit, a constant voltage circuit, a constant current circuit, and the like that are turned on and off according to the gate drive signal Gup. Also in the fourth and fifth embodiments, the on-drive constant current circuit 12 or the off-drive constant current circuit 13 operates at turn-on or turn-off, respectively. Therefore, the same effects as those of the first to third embodiments are obtained. It is done.

(Other embodiments)
In addition to the plurality of embodiments described above, the following configuration may be adopted.
The transistors constituting the inverter circuit 3 are not limited to IGBTs, and may be voltage driven transistors such as FETs. The inverter circuit is not limited to three phases, and may have a single phase configuration.

The transistors Q1 to Q7 constituting the gate drive circuit 4 may be replaced with FETs.
The second and third embodiments can also be applied to the fourth and fifth embodiments.
According to the embodiment described above, the switching speed of the voltage driven transistor can be easily controlled.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof in the same manner as included in the scope and gist of the invention.

  In the drawings, 1 is a power conversion device, 3 is an inverter circuit, 4 is a gate drive circuit, 5 is a control unit (control means), 8up to 8wn are IGBTs (voltage drive type transistors), 12 is an on-drive constant current circuit, 13 Is an off drive constant current circuit, 14, 15 are first and second drive voltage lines, 16 is an on drive control voltage line, 17 is an off drive control voltage line, Q1, Q2, Q3, and Q4 are first, second, The third and fourth transistors, Q5 and Q6 are transistors (first and second switch circuits), and R1 and R2 are first and second reference resistors.

Claims (5)

In a gate drive circuit that uses the source or emitter potential of a voltage-driven transistor as a reference potential and drives the voltage-driven transistor on and off according to a gate drive signal,
Provided between a first drive voltage line having a first drive voltage higher than a threshold voltage of the voltage-driven transistor and a gate of the voltage-driven transistor, and when the gate drive signal is on level, An on-drive constant current circuit capable of outputting a constant current in a direction to charge the gate capacitance of the voltage-driven transistor and changing the output constant current value according to the on-drive control voltage;
A gate capacitance of the voltage-driven transistor is provided between a second drive voltage line having a second drive voltage lower than the reference potential and the gate of the voltage-driven transistor, and when the gate drive signal is at an off level. A constant current is output in the direction of discharging, and the constant current value to be output is provided with an off drive constant current circuit that can be changed according to the off drive control voltage ,
The on-drive constant current circuit includes first and second transistors that are connected to the first drive voltage line to form a current mirror circuit, an on-drive control voltage line having the first transistor and the on-drive control voltage, A first switch circuit and a first reference resistor connected in series between the first switch circuit and the first switch circuit, which is turned on when the gate drive signal is on level . In a gate drive circuit that uses the source or emitter potential of a voltage-driven transistor as a reference potential and drives the voltage-driven transistor on and off according to a gate drive signal,
Provided between a first drive voltage line having a first drive voltage higher than a threshold voltage of the voltage-driven transistor and a gate of the voltage-driven transistor, and when the gate drive signal is on level, An on-drive constant current circuit capable of outputting a constant current in a direction to charge the gate capacitance of the voltage-driven transistor and changing the output constant current value according to the on-drive control voltage;
A gate capacitance of the voltage-driven transistor is provided between a second drive voltage line having a second drive voltage lower than the reference potential and the gate of the voltage-driven transistor, and when the gate drive signal is at an off level. A constant current is output in the direction of discharging, and the constant current value to be output is provided with an off drive constant current circuit that can be changed according to the off drive control voltage ,
The off drive constant current circuit includes third and fourth transistors that are connected to the second drive voltage line to form a current mirror circuit, and an off drive control voltage line having the third transistor and the off drive control voltage. A second switch circuit and a second reference resistor connected in series, and the second switch circuit is turned on when the gate drive signal is at an off level . In a gate drive circuit that uses the source or emitter potential of a voltage-driven transistor as a reference potential and drives the voltage-driven transistor on and off according to a gate drive signal,
Provided between a first drive voltage line having a first drive voltage higher than a threshold voltage of the voltage-driven transistor and a gate of the voltage-driven transistor, and when the gate drive signal is on level, An on-drive constant current circuit capable of outputting a constant current in a direction to charge the gate capacitance of the voltage-driven transistor and changing the output constant current value according to the on-drive control voltage;
Provided between a second drive voltage line having a second drive voltage equal to or lower than the reference potential and the gate of the voltage-driven transistor, and the gate capacitance of the voltage-driven transistor when the gate drive signal is off level. An off-drive circuit for discharging ,
The on-drive constant current circuit includes first and second transistors that are connected to the first drive voltage line to form a current mirror circuit, an on-drive control voltage line having the first transistor and the on-drive control voltage, A first switch circuit and a first reference resistor connected in series between the first switch circuit and the first switch circuit, which is turned on when the gate drive signal is on level . In a gate drive circuit that uses the source or emitter potential of a voltage-driven transistor as a reference potential and drives the voltage-driven transistor on and off according to a gate drive signal,
The voltage driving transistor is provided between a first driving voltage line having a first driving voltage equal to or higher than a threshold voltage of the voltage driving transistor and a gate of the voltage driving transistor, and the voltage when the gate driving signal is on level. An on-drive circuit that charges the gate capacitance of the drive transistor;
A gate capacitance of the voltage-driven transistor is provided between a second drive voltage line having a second drive voltage lower than the reference potential and the gate of the voltage-driven transistor, and when the gate drive signal is at an off level. A constant current is output in the direction of discharging, and the constant current value to be output is provided with an off drive constant current circuit that can be changed according to the off drive control voltage ,
The off drive constant current circuit includes third and fourth transistors that are connected to the second drive voltage line to form a current mirror circuit, and an off drive control voltage line having the third transistor and the off drive control voltage. A second switch circuit and a second reference resistor connected in series, and the second switch circuit is turned on when the gate drive signal is at an off level . The power converter device provided with the gate drive circuit as described in any one of Claim 1 to 4 .

Images