JP6180398B2 - Memory access device - Google Patents

Description

  The present invention relates to a memory access device.

  In general, a data storage area of an SDRAM (Synchronous Dynamic Random Access Memory) is divided into a plurality of banks, and each of the banks is divided into a plurality of pages. The SDRAM is activated in units of pages by the memory access device, and the activated pages can be accessed.

  In the SDRAM, it is possible to independently activate the pages of the different banks. Therefore, when access to different banks continues, a large overhead does not occur, and continuous high-speed access is possible.

  On the other hand, if access to different pages in one bank continues, a relatively large overhead due to bank contention occurs. That is, in the access within one bank, a step of activating the next page after completion of the closing process of the previously activated page is necessary, and this step is an overhead due to the bank contention. It becomes.

  In general, access for writing and reading data to and from a memory such as the SDRAM is controlled by a memory access device. Further, the memory access device divides an access request transaction including a sequence of access requests to the memory input from the master into access requests in units of banks, and after changing the order of the divided access requests, It is known to issue a command corresponding to the access request to the SDRAM (see, for example, Patent Document 1). In this case, a part of the overhead due to the bank contention is concealed by optimizing the order of issuing the commands.

JP 2006-260472 A

  By the way, in the memory access device, consistency between the read access request order from the master and the read data output order to the master may be required. Further, when a plurality of read access commands are issued, a read data string in which each data is arranged corresponding to the issuing order of the read access commands is obtained.

  Accordingly, when the memory access device issues a plurality of the read access commands in an order different from the input order of the read access requests, the memory access device includes a first read data string corresponding to the issue order of the read access commands, It is necessary to hold the second read data string after being rearranged in the order. In this case, an additional resource such as a data buffer is required in the memory access device. Further, due to the rearrangement of the read data sequence, the latency from the input of the access request to the output of the read data sequence increases.

  The object of the present invention is to avoid the addition of resources and increase in latency while avoiding the addition of resources and the increase in latency even when the consistency between the read access request order and the read data output order is required when accessing a memory such as SDRAM. An object of the present invention is to provide a memory access device that can conceal the overhead caused by the above.

  A memory access device according to one aspect of the present invention is a memory access device that issues an access command to a memory. The memory has a data storage area which is divided into a plurality of banks and each bank is divided into a plurality of pages. The memory access device includes an access request sorting unit, a first queuing buffer, a second queuing buffer, a read queue sorting unit, a write queue sorting unit, and a command issuing unit. The access request sequence sorting unit sorts an access request transaction including a sequence of access requests to the memory input from the outside into a read access queue in which read access requests are arranged and a write access queue in which write access requests are arranged. The first queuing buffer temporarily stores the read access queue. The second queuing buffer temporarily stores the write access queue. The read queue sorting unit sorts the read access queue into a plurality of unit read queues each including one or more read access requests. The read queue sorting unit sorts the read access queue between two consecutive read access requests that have different pages in the same bank in the memory as access destinations. The write queue sorting unit sorts the write access queue into a plurality of unit write queues each including one or more write access requests. The write queue sorting unit sorts the write access queue between two consecutive write access requests that have different pages in the same bank in the memory as access destinations. The command issuing unit sequentially selects each unit read queue according to the order of the read access requests in the access request transaction. Further, the command issuing unit sequentially selects each of the unit write queues. Further, the command issuing unit issues at least a command corresponding to all the unit read queues in the first queuing buffer or a command corresponding to all the unit write queues in the second queuing buffer. The unit read queue and the unit write queue selected up to are issued to the memory alternately.

  According to the present invention, even when the consistency between the read access request order and the read data output order is required in access to a memory such as an SDRAM, it is possible to avoid the addition of resources and increase in latency while avoiding the increase in latency. It becomes possible to provide a memory access device capable of concealing overhead.

FIG. 1 is a block diagram of an image processing apparatus including a memory access apparatus according to the first embodiment of the present invention. FIG. 2 is a block diagram of the memory access apparatus according to the first embodiment of the present invention. FIG. 3 shows commands when the command corresponding to each access request of the access request transaction is issued as it is and when the memory access device according to the first embodiment of the present invention issues a command corresponding to each access request. It is a time chart which shows an example of an execution situation typically. FIG. 4 is a diagram schematically illustrating an example of a read access queue and a write access queue temporarily stored in the memory access device according to the first embodiment of the present invention. FIG. 5 is a block diagram of a memory access apparatus according to the second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the following embodiment is an example which actualized this invention, Comprising: It does not have the character which limits the technical scope of this invention.

[First Embodiment]
First, a schematic configuration of an image processing apparatus 100 including a memory access device 10 according to the first embodiment of the present invention will be described with reference to FIG. The image processing apparatus 100 is one application example of the memory access apparatus 10.

  An image processing apparatus 100 shown in FIG. 1 is a multifunction machine that has both a function of an image reading apparatus that reads an image from a document and a function of an image forming apparatus that forms an image on a recording sheet. Note that the image processing apparatus 100 is the image forming apparatus, the image reading apparatus, the image forming apparatus, a copying machine having the functions of the image reading apparatus, or a facsimile apparatus having the functions of the image reading apparatus and the image transmission function. There is also a possibility.

  The image processing apparatus 100 includes an SDRAM 9, a memory access device 10, a scan unit 20, a scan control unit 30, a print unit 40, a print control unit 50, a communication control unit 60, an image processing unit 70, and the like. The memory access device 10, the scan control unit 30, the print control unit 50, the communication control unit 60, and the image processing unit 70 are each connected to a bus 80 and can exchange data with each other through the bus 80.

  The scanning unit 20 includes an optical system (not shown) that scans the original with light, an image sensor (not shown) that detects the amount of reflected light from the original for each pixel, and outputs original image data.

  The scan control unit 30 controls the scan unit 20 to acquire the original image data. Further, the scan control unit 30 also executes a process of writing the original image data into the SDRAM 9 through the memory access device 10. For example, the scan control unit 30 may deliver the document image data to another device such as the image processing unit 70, the print control unit 50, or the communication control unit 60 via the SDRAM 9.

  The print unit 40 forms an image on the recording sheet by a known electrophotographic image forming process. The print unit 40 includes an image carrier (not shown) and its peripheral devices, and transfers an image of the developer from the image carrier to the recording sheet and fixes the image on the recording sheet.

  The print control unit 50 controls the print unit 40. The print control unit 50 acquires recording image data from another device, and causes the printing unit 40 to execute processing for forming an image based on the recording image data on the recording sheet.

  The communication control unit 60 transmits / receives data to / from an external device such as a personal computer, and exchanges data with other devices via the bus 80. For example, the communication control unit 60 receives image data from the external device, and delivers the image data to the print control unit 50 as the recording image data.

  Further, the communication control unit 60 acquires the document image data from the scan control unit 30 and transmits data including the document image data to the external device.

  The image processing unit 70 performs image processing on image data obtained from another device via the bus 80. The target of image processing by the image processing unit 70 is, for example, image data transmitted from the scan control unit 30 to the external device through the communication control unit 60 or the original document delivered from the scan control unit 30 to the print control unit 50. For example, image data. For example, the image processing unit 70 performs image processing such as image rotation processing, halftone processing, or size cut processing on the image data obtained from another device.

  The SDRAM 9 is a memory capable of writing and reading data at high speed. The SDRAM 9 records data in the data area and outputs the data recorded in the data area according to the contents of the access command issued from the device connected to the bus 80.

  The data storage area of the SDRAM 9 is divided into a plurality of banks, and each of the banks is divided into a plurality of pages. The SDRAM 9 is activated in units of pages by the memory access device 10, and the activated pages can be accessed.

  In the SDRAM 9, it is possible to independently activate the page in one bank and the page in another bank. Therefore, when access to different banks continues, a large overhead does not occur, and continuous high-speed access is possible.

  On the other hand, if access to different pages in one bank continues, a relatively large overhead due to bank contention occurs.

  For example, consider a case where read access commands to the first page and the second page in the same bank are issued successively. In this case, a step of activating the second page after the closing process of the previously activated first page is necessary. In this step, since the time required for the closing process of the first page is relatively long, the waiting time until the activation command for the second page becomes an overhead due to the bank contention.

  Further, in the general SDRAM 9, when one of the read access and the write access is continuous regardless of the access destination, an overhead due to switching of the access type occurs. This overhead is comparatively large as the bank contention overhead.

  In the present embodiment, the memory access device 10 mainly issues the access command to the SDRAM 9. In this case, each of the scan control unit 30, the print control unit 50, the communication control unit 60, and the image processing unit 70 outputs an access request transaction including an access request sequence to the SDRAM 9 to the memory access device 10 through the bus 80. To do. In general, the memory access device 10 is called a DMAC (Direct Memory Access Controller) or the like. One of the access requests is a read access request, and the corresponding access command is a read access command. Another one of the access requests is a write access request, and the access command corresponding to this is a write access command.

  In the following description, a device that outputs the access request transaction to the memory access device 10 is referred to as a master for the memory access device 10. The master in the present embodiment is each of the scan control unit 30, the print control unit 50, the communication control unit 60, and the image processing unit 70. The master may be referred to as a client.

  The memory access device 10 is a device that issues the access command to the SDRAM 9. The memory access device 10 rearranges the access request queue included in the access request transaction input from the master so as to reduce the overhead, and issues the access command to the SDRAM 9 in the order after the rearrangement. The access request queue is a sequence of the access requests for the SDRAM 9.

  Incidentally, there is a case where consistency between the read access request order from the master and the read data output order to the master is required. Further, when a plurality of read access commands are issued, a read data string in which each data is arranged corresponding to the issuing order of the read access commands is obtained.

  Therefore, when a plurality of the read access commands are issued in an order different from the order of the read access requests in the access request transaction, the first read data string arranged in the order of issuing the read access commands and the original order It is necessary to hold the second read data string after the rearrangement. In this case, additional resources such as a data buffer are required. Further, due to the rearrangement of the read data sequence, the latency from the input of the access request to the output of the read data sequence increases.

  The memory access device 10 has a configuration to be described later, so that in the access to the SDRAM 9, even when consistency between the read access request order and the read data output order is required, the addition of the resource and the increase of the latency are performed. The overhead due to the bank contention can be concealed.

[Memory access device]
Next, the memory access device 10 will be described with reference to FIG. The memory access device 10 includes a request transaction input unit 1, an access request sorting unit 2, a first queuing buffer 3, a second queuing buffer 4, an access queue sorting unit 5, a command issuing unit 6, a memory And an access unit 7.

  The access queue sorting unit 5 includes a read queue sorting unit 51 and a write queue sorting unit 52. The command issuing unit 6 includes a unit read queue selecting unit 61, a unit write queue selecting unit 62, and a command alternate issuing unit 63.

  The memory access unit 7 includes a command issue adjustment unit 71, a read data buffer 72, a data output unit 73, a write data buffer 74, and a data input unit 75.

  The memory access device 10 is configured by, for example, an application specific integrated circuit (ASIC) or a digital signal processor (DSP).

  The request transaction input unit 1 executes a process of acquiring an access request transaction including a sequence of the access request to the SDRAM 9 from the master. The access request transaction is input from the master to the request transaction input unit 1 through the bus 80.

  The access request transaction requests the SDRAM 9 to read the data stored in the data storage area, and requests the SDRAM 9 to record data in the data storage area. Including write access. The read access request and the write access request include information on the type of the request, and row address information and column address information specifying an address in the data storage area.

  The access request sorting unit 2 sorts the access request transaction for memory access input from the master into a read access queue and a write access queue. The read access queue is a queue in which the read access requests are arranged, and is a queue in which the write access requests are arranged.

  The access request sorting unit 2 generates the read access queue without changing the order of the plurality of read access requests in the access request transaction. The access request sorting unit 2 generates the write access queue without changing the order of the plurality of write access requests in the access request transaction.

  In other words, the access request sorting unit 2 divides the access request transaction between the read access request and the write access request that are consecutive. Further, the access request sorting unit 2 organizes the plurality of read access requests obtained by the division as the read access queue in the order in the access request transaction. Further, the access request sorting unit 2 organizes the plurality of write access requests obtained by the division as the write access queue in the order in the access request transaction.

  As described above, when one and the other of the read access request and the write access request are continuous, that is, when one and the other of the read access command and the write access command are continuous, the type of access is switched. Causes overhead. Hereinafter, this overhead is referred to as access switching overhead. The access request sorting unit 2 divides the access request transaction at a position where the access switching overhead occurs.

  The first queuing buffer 3 is a buffer for temporarily storing the read access queue. The second queuing buffer 4 is a buffer for temporarily storing the write access queue. That is, the access request sorting unit 2 records the read access queue in the first queuing buffer 3 and records the write access queue in the second queuing buffer 4.

  The access queue sorting unit 5 executes a process of sorting each of the read access queue and the write access queue into a plurality of unit access queues, each of which is a group of the access requests issued to the SDRAM 9. .

  The read queue sorting unit 51 sorts the read access queue into a plurality of unit read queues each including one or more read access requests. The write queue sorting unit 52 sorts the write access queue into a plurality of unit read queues each including one or more write access requests.

  The read queue sorting unit 51 sorts the read access queue between two consecutive read access requests that have different pages in the same bank in the SDRAM 9 as access destinations. As described above, an overhead due to the bank conflict occurs between two consecutive read access requests to which different pages in the same bank are accessed as the corresponding commands are issued. To do.

  Similarly, the write queue sorting unit 52 sorts the write access queue between two consecutive write access requests that have different pages in the same bank in the memory as access destinations. Between two consecutive write access requests that have different pages in the same bank as access destinations, overhead due to bank contention occurs when commands corresponding to them are issued.

  Hereinafter, the overhead due to bank contention is referred to as bank contention overhead. The access queue sorting unit 5 sorts each of the read access queue and the write access queue at a position where the bank contention overhead occurs.

  The access queue sorting unit 5 can calculate the overhead time that occurs when a command corresponding to each of the plurality of access requests in the access request transaction is issued according to a predetermined calculation rule.

  For example, the read queue sorting unit 51 accumulates the time of the bank contention overhead that occurs when commands corresponding to each of the read access requests in the read access queue are sequentially issued from the head side. Then, the read queue sorting unit 51 sorts the read access request column as the unit read queue for each read access request column in which the accumulation result of the bank conflict overhead time falls within a predetermined allowable range. .

  Similarly, the write queue sorting unit 52 accumulates the time of the bank contention overhead that occurs when commands corresponding to the write requests in the write access queue are successively issued in order from the head side. Then, the write queue sorting unit 52 sorts the write access request column as the unit write queue for each column of the write access request in which the accumulation result of the bank conflict overhead time falls within a predetermined allowable range. .

  Information about the division position of each unit read queue in the read access queue is notified from the read queue division unit 51 to the unit read queue selection unit 61. Similarly, information on the division position of each unit write queue in the write access queue is notified from the write queue division unit 52 to the unit write queue selection unit 62.

  The unit read queue selection unit 61 of the command issuing unit 6 executes a process of selecting the unit read queues stored in the first queuing buffer 3 one by one. At that time, the unit read queue selection unit 61 sequentially selects each of the unit read queues according to the order of the read access requests in the access request transaction.

  The unit write queue selection unit 62 of the command issuing unit 6 executes a process of selecting the unit write queues stored in the second queuing buffer 4 one by one. At that time, the unit write queue selection unit 62, when the unit read queues sequentially selected by the unit read queue selection unit 61 and the unit write queues sequentially selected by the unit write queue selection unit 62 are issued alternately, The unit write queues are sequentially selected under the condition that cache coherency is maintained.

  The command alternate issuing unit 63 of the command issuing unit 6 includes a command corresponding to the unit read queue sequentially selected by the unit read queue selecting unit 61 and a command corresponding to the unit write queue sequentially selected by the unit write queue selecting unit 62. Are issued to the SDRAM 9 alternately. In the present embodiment, the command alternate issue unit 63 at least commands corresponding to all the unit read queues in the first queuing buffer 3 or commands corresponding to all the unit write queues in the second queuing buffer 4. Until the command is issued, the command corresponding to the unit read queue and the command corresponding to the unit write queue are alternately issued to the SDRAM 9. At this time, the command alternate issue unit 63 issues commands corresponding to each of the unit read queue and the unit write queue to the SDRAM 9 via a command issue adjustment unit 71 described later.

  After selection and issuance of the opposite command are performed for all of one of the unit read queue and the unit write queue, the command alternate issue unit 63 is not selected in the first queuing buffer 3 or the second queuing buffer 4. The unit read queue or the unit write queue that remains is sequentially selected, and commands corresponding to the selected queue are sequentially issued.

  The constraint condition is to maintain the relationship before and after the request transaction when the unit read queue and the unit write queue that access the same address of the data storage area of the SDRAM 9 exist.

  In the following description, the last read access command in the last issued unit read queue command is referred to as the latest read access command.

  For example, it is conceivable that the unit write queue selection unit 62 selects the unit write queue according to a selection rule based on a comparison of overhead times as described below, with the constraint that the cache coherency is maintained.

  In the selection rule, the time of the access switching overhead occurring between the most recent read access command corresponds to the first read access request in the unit read queue to be issued next and the most recent read access command. The rule is to select the unit write queue closest to the time of the bank contention overhead occurring between commands.

  The command issuance adjustment unit 71 issues the read access command and the write access command corresponding to the unit read queue and the unit write queue, which are sequentially issued from the command issuing unit 6, in the issue order from the command issuing unit 6. Issue to SDRAM9. At this time, the command issuance adjustment unit 71 also issues an activation command and a precharge command necessary for the read access command and the write access command to the SDRAM 9.

  More specifically, the command issue adjustment unit 71 issues the read access command or the write access command including the column address information after issuing the activation command including the row address information, and Issue a charge command. The command issue adjustment unit 71 issues each command at a timing determined in advance by the specification of the SDRAM 9.

  Each of the unit read queue and the unit write queue issued by the command issuing unit 6 is erased from each of the first queuing buffer 3 and the second queuing buffer 4.

  The read data buffer 72 is a buffer for temporarily storing read data read from the SDRAM 9 in response to the issue of the read access command. The data output unit 73 is an interface for transferring the read data in the read data buffer 72 to the master through the bus 80.

  The transfer destination of the read data is the master that has output the access request transaction including the read access command issued from the command issuing unit 6 to the SDRAM 9 through the command issue adjusting unit 71. The read data transferred to the master is erased from the read data buffer 72.

  The data input unit 75 is an interface for acquiring write data output together with the access request transaction including the write access request from the master through the bus 80. The write data buffer 74 is a buffer that temporarily stores the write data acquired by the data input unit 75.

  The SDRAM 9 records the write data at the address of the data storage area designated when the write access command is received. The write data recorded in the SDRAM 9 is erased from the write data buffer 74.

[Specific example of access command issue order]
Next, a specific example of a command issue order corresponding to each access request in the access request transaction will be described with reference to FIGS. FIG. 3 is a time chart schematically showing an example of the execution status of the command corresponding to the access request in the access request transaction.

  A first time chart Tc1 shown in FIG. 3 is a time chart schematically showing an example of a command execution situation when commands corresponding to each access request of the access request transaction are issued in the original order. The second time chart Tc2 is a time chart schematically showing an example of a command execution situation when the memory access device 10 that has received the request transaction issues the access command.

  The access request transaction that is the basis of each of the first time chart Tc1 and the second time chart Tc2 is the same. In the following description, the access request transaction is referred to as a sample request transaction.

  In FIG. 3, R1 to R6 represent the read access request, WI to W3 represent the write access request, and X1 to X8 represent the overhead.

  In the first time chart Tc1, the first read access request R1 and the second read access request R2 are access requests to different pages in the same bank. Therefore, the first overhead X1, which is the bank contention overhead, is generated by sequentially issuing the commands of the first read access request R1 and the second read access request R2. The fourth overhead X4 occurring between the command of the fourth read access request R4 and the command of the fifth read access request R5 is also the bank contention overhead.

  In the first time chart Tc1, the second read access request R2 and the third read access request R3 are the access requests to the different banks. For this reason, the commands of the second read access request R2 and the third read access request R3 are issued in succession, so that a large overhead does not occur and continuous high speed access is possible.

  In the first time chart Tc1, the different commands of the third read access request R3 and the first write access request W1 are successively issued. Therefore, the second overhead X2 that is the access switching overhead occurs.

  Between the command of the first write access request W1 and the command of the fourth read access request R4, the fifth read access request R5, the second write access request W2, the sixth read access request R6, and the third write access request W3. The second overhead X2, the third overhead X3, the fifth overhead X5, the sixth overhead X6, the seventh overhead X7, and the eighth generated between the respective commands and after the execution of the command of the third write access request W3. The overhead is also the access switching overhead.

  On the other hand, the memory access device 10 rearranges the plurality of access request queues included in the sample request transaction input from the master so as to reduce the overhead, and each of the access requests in the order after the rearrangement. A command corresponding to is issued to the SDRAM 9.

  FIG. 4 is a diagram schematically illustrating an example of the read access queue Rq and the write access queue Wq that are temporarily stored in the memory access device 10 that has received the sample request transaction.

  In the memory access device 10, the access request sorting unit 2 divides the sample request transaction into the read access queue Rq in which the read access requests R1 to R6 are arranged and the write access queue Wq in which the write access requests W1 to W3 are arranged. Sort.

  In FIG. 4, the read queue sorting unit 51 divides the read access queue Rq into a plurality of unit read queues Ru1 to Ru5, and the write queue sorting unit 52 divides the write access queue Wq into the plurality of unit write queues Wu1. The example divided into ~ Wu3 is shown.

  For convenience, FIG. 4 shows an example in which the read access queue Rq is all divided between two consecutive read access requests to which different pages in the same bank in the SDRAM 9 are accessed. It is an example.

  Similarly, in the example shown in FIG. 4, the write access queue Wq is all divided between two consecutive write access requests to which different pages in the same bank in the SDRAM 9 are accessed. This is an example.

  As shown in the second time chart Tc2 of FIG. 3, the command issuing unit 6 alternately issues commands corresponding to the unit read queues Ru1 to Ru6 and commands corresponding to the unit write queues Wu1 to Wu3. . At this time, the command issuance order corresponding to the unit read queues Ru1 to Ru6 is in accordance with the order of the read access requests R1 to R6 in the sample request transaction.

  For convenience, in the example shown by the second time chart Tc2 in FIG. 3, the command issue order corresponding to the unit write queues Wu1 to Wu3 is also in the order of the write access requests W1 to W3 in the sample request transaction. It is in order.

  When the sample request transaction is processed, the access switching overhead (X2, X3, X5, X6, X7, X8) is necessarily generated overhead.

  In the memory access device 10, the read access queue Rq is divided into the unit read queues Ru1 to Ru6 at positions between the access requests where the bank contention overhead (X1, X4) occurs.

  Further, in the memory access device 10, the unit read queues Ru1 to Ru6 and the unit write queues Wu1 to Wu3 are issued alternately. Therefore, the bank conflict overhead (X1, X4) overlaps with a part of the access switching overhead (X2, X3, X5, X6, X7, X8).

  In the example shown by the second time chart Tc2 of FIG. 3, the first overhead X1 overlaps with the second overhead X2, and the fourth overhead X4 overlaps with the seventh overhead X7. Therefore, a portion of the bank conflict overhead that overlaps with the access switching overhead is hidden. As a result, the access efficiency to the SDRAM 9 is improved.

  Here, an example of a situation where the unit write queue selection unit 62 of the command issuing unit 6 selects the next unit write queue when the command corresponding to the first read access request R1 is the latest read access command will be described. To do. In this situation, it is conceivable that the unit write queue selection unit 62 selects the unit write queue (Wu1) according to the selection rule based on the overhead time comparison as described above, with the maintenance of the cache coherency as a constraint. .

  If the unit write queue (Wu1) is selected according to the selection rule, the bank contention overhead (X1) having the longest overlap time with the access switching overhead (X2) is selected. As a result, the concealing time of the bank conflict overhead becomes longer, and the access efficiency to the SDRAM 9 is further improved.

  Further, the read access command corresponding to each of the read access requests in the access request transaction is issued in an order according to the order inputted to the memory access device 10, that is, without changing the context. . In this case, the read data sequence in the original order is recorded in the read data buffer 72.

  Therefore, if the memory access device 10 is adopted, the read data need not be rearranged even when the consistency between the read access request order for the SDRAM 9 and the read data output order is required. As a result, it is not necessary to add resources such as the read data buffer 72 for rearranging the read data. Further, the latency is not increased due to the rearrangement of the read data.

  Further, if the unit read queue and the unit write queue are classified for each of the one or more access requests in which the bank contention overhead falls within a predetermined allowable range, the number of times of occurrence of the access switching overhead is suppressed. be able to.

[Second Embodiment]
Next, a memory access device 10A according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a schematic configuration of the memory access device 10A. In FIG. 5, the same components as those shown in FIGS. 1 to 4 are given the same reference numerals.

  The memory access device 10A has a configuration in which some components are added as compared to the memory access device 10 shown in FIG. Hereinafter, differences of the memory access device 10A from the memory access device 10 will be described.

  The memory access device 10 </ b> A has a configuration in which a priority determination unit 8 is added to the configuration of the memory access device 10. Further, the memory access device 10A includes a plurality of first queuing buffers 3 and a plurality of second queuing buffers 4. In the example shown in FIG. 5, the access request classification unit 2 includes a priority determination unit 8.

  In the present embodiment, the request transaction input to the request transaction input unit 1 includes priority information. The priority information is, for example, information included in the request transaction by the master. It is also conceivable that the priority determination unit 8 stores information on the correspondence between each of the masters and the priority in advance. In this case, the priority information is information for identifying the master that requested the request transaction.

  A first queuing buffer 3 and a second queuing buffer 4 are provided for each priority candidate. For example, when the priority candidates are two types, ie, the first priority and the second priority having a lower priority than the first priority, the memory access device 10 has two first queuing buffers 3 and two second priorities. A queuing buffer 4 is provided. The example shown in FIG. 5 is an example in which two first queuing buffers 3 and two second queuing buffers 4 are provided.

  The priority determination unit 8 determines the priority for each request transaction by referring to the priority information included in the input request transaction.

  Then, the access request classification unit 2 classifies the read access queue and the write access queue for each access request transaction having the same priority determined by the priority determination unit 8.

  Each of the first queuing buffers 3 temporarily stores only the read access queues sorted for the access request transactions having the same priority. Similarly, each of the second queuing buffers 4 temporarily stores only the write access queue sorted for the access request transactions having the same priority.

  That is, the memory access device 10A has, for each access request transaction having the same priority, the plurality of first queuing buffers 3 that store the read access queue and the plurality of second queues that store the write access queue. Ing buffer 4 is provided.

  In the memory access device 10A, the read queue sorting unit 51 and the write queue sorting unit 52 classify the unit read queue and the unit write queue for each priority. Similarly, the command issuing unit 6 selects and issues the unit read queue and the unit write queue in order from the highest priority.

  If the memory access device 10A is employed, the issuance order of the read access command is maintained in the original context for each request transaction, and the access request transactions with the highest priority are processed in order.

  Therefore, even when the request transactions having different priorities are input in a mixed manner, the read access request order and the read data for each request transaction are avoided for each request transaction while avoiding the addition of the resource and the increase in the latency. Consistency with the output order can be ensured.

<Application example>
It is also conceivable that the memory access devices 10 and 10A are applied to an information processing device other than the image processing device 100 such as a portable information terminal.

  The memory access device according to the present invention can be freely combined with the above-described embodiments and application examples within the scope of the invention described in each claim, or can be modified as appropriate. Alternatively, it may be configured by omitting a part.

1: Request transaction input unit 2: Access request sorting unit 3: First queuing buffer 4: Second queuing buffer 5: Access queue sorting unit 6: Command issuing unit 7: Memory access unit 8: Priority determining unit 9: SDRAM
10, 10A: Memory access device 20: Scan unit 30: Scan control unit 40: Print unit 50: Print control unit 51: Read queue classification unit 52: Write queue classification unit 60: Communication control unit 61: Unit read queue selection unit 62 : Unit write queue selection unit 63: Command alternate issue unit 70: Image processing unit 71: Command issue adjustment unit 72: Read data buffer 73: Data output unit 74: Write data buffer 75: Data input unit 80: Bus 100: Image processing Devices R1 to R6: Read access request Rq: Read access queue Ru1 to Ru6: Unit read queue Tc1: First time chart Tc2: Second time chart W1 to W3: Write access request Wq: Write access queue Wu1 to Wu3: Unit write Queues X1-X7: overhead

Claims (4)

A memory access device for issuing an access command to a memory having a data storage area divided into a plurality of banks and each of the banks being divided into a plurality of pages,
An access request sorting unit for sorting an access request transaction including a column of access requests to the memory input from the outside into a read access queue in which read access requests are arranged and a write access queue in which write access requests are arranged;
A first queuing buffer for temporarily storing the read access queue;
A second queuing buffer for temporarily storing the write access queue;
A plurality of read access requests each including one or more read access requests by partitioning the read access queue between two consecutive read access requests that are accessed by different pages in the same bank in the memory; A read queue sorting section that divides the unit read queue into
A plurality of write access requests each including one or more write access requests by partitioning the write access queue between two consecutive write access requests to which different pages in the same bank in the memory are accessed A light queue sorting section for sorting into unit light queues of
Each of the unit read queues is sequentially selected according to the order of the read access requests in the access request transaction, and each of the unit write queues is sequentially selected, and at least all the unit read queues in the first queuing buffer are selected. Or a command corresponding to the selected unit read queue and a command corresponding to the unit write queue until a command corresponding to the unit write queue or a command corresponding to all the unit write queues in the second queuing buffer is issued. A memory access device comprising: a command issuing unit that alternately issues to the memory.   When the command issuing unit selects the unit write queue to be issued next from the write access queue, the last read access in the last issued unit read queue with the maintenance of cache coherency as a constraint condition The overhead time due to switching of the type of access that occurs between the latest read access command that is a command corresponding to the request is the first read access request in the unit read queue that is scheduled to be issued next. The memory access device according to claim 1, wherein a memory access device that is closest to an overhead time due to a bank contention occurring with a command corresponding to is selected. The read queue sorting unit includes a column of the read access request for each column of the read access request in which the overhead due to bank competition falls within a predetermined allowable range when corresponding commands are continuously issued to the memory. As the unit read queue,
The write queue sorting unit includes a write access request column for each write access request column in which overhead due to bank competition falls within a predetermined allowable range when corresponding commands are continuously issued to the memory. The memory access device according to claim 1, wherein the memory access device is classified as the unit write queue. A determination unit for determining a priority of the access request transaction;
The access request classification unit classifies the read access queue and the write access queue for each access request transaction having the same priority determined by the determination unit,
A plurality of first queuing buffers for storing the read access queue and a plurality of second queuing buffers for storing the write access queue for each access request transaction having the same priority;
The read queue sorting unit and the write queue sorting unit perform the unit read queue sorting and the unit write queue sorting for each priority,
4. The memory access according to claim 1, wherein the command issuing unit selects the unit read queue and the unit write queue and issues a command in order from the highest priority. 5. apparatus.

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