JP6204042B2 - Delay circuit element and delay circuit device - Google Patents

Description

  The present invention relates to a delay circuit element and a delay circuit device used for delaying a signal in electronic devices such as computers, communication devices, and communication devices.

  In an electronic device such as a computer, a communication device, and a communication device, when a plurality of electric signals transmitted separately in a plurality of transmission lines are combined, in order to align the phases between the plurality of electric signals, There is a case where a delay process for a predetermined time is performed on the electric signal. In such a case, a circuit board for delay provided with a delay circuit (delay line) corresponding to a required delay time is used.

  Conventionally used circuit boards for delay include those in which a delay circuit corresponding to a predetermined delay time is provided on a substrate such as a ceramic substrate (see Patent Documents 1 and 2, etc.). Such a circuit board for delay has an insulating substrate and a delay circuit provided inside the substrate, and is formed by electrically leading both ends of the delay circuit to the main surface of the substrate. ing. After an electrical signal is input from one end of the both ends of the delay circuit led to the main surface of the substrate and subjected to delay processing for a predetermined time by the delay circuit, from the other end of both ends of the delay circuit An electrical signal is output.

JP-A-6-152208 Japanese Patent Laid-Open No. 10-22709

  In the conventional circuit board for delay, it is necessary to prepare a circuit board by providing a delay circuit having such a delay time on an insulating plate in accordance with a required delay time. For example, it is necessary to prepare a plurality of delay circuit boards corresponding to a plurality of types of delay times. For this reason, the productivity and economy as an electronic device having a delay circuit element may be lowered.

The delay circuit element according to one aspect of the present invention includes an insulating substrate having a first main surface and a second main surface opposite to the first main surface, and the first main surface and the second main surface of the insulating substrate. Three or more electrodes provided in a plane, overlapping in a plan view and electrically connected to each other between the first main surface and the second main surface, and the insulating substrate, the plurality of electrodes A delay circuit provided so as to connect between a pair of electrodes, and the plurality of electrodes along a circumference of a virtual circle that overlaps the insulating substrate in a plan view. The adjacent gaps between the respective electrodes are arranged so as to have the same length , and the upper pair of the upper and lower electrodes are stacked when the insulating substrate is rotated up and down around the center of the virtual circle. One of the electrodes is a pair of the lower pair of electrodes. Overlaps with the other electrode, the other electrode of the upper side of the pair of electrodes, wherein the overlap with Rukoto and other electrodes other than the pair of electrodes of the lower.

Also, in the delay circuit device according to one aspect of the present invention, the plurality of delay circuit elements having the above-described configuration are stacked vertically with the first main surface facing down, and the two delay circuit elements adjacent vertically Among the pair of electrodes of the lower delay circuit element, the other electrode on the second main surface side and the first main surface side of the pair of electrodes of the upper delay circuit element One of the electrodes is electrically connected to each other.

According to the delay circuit element of one aspect of the present invention, because of the above configuration, a plurality of the delay circuit elements are stacked one above the other, and the delay circuits of the respective delay circuit elements are sequentially electrically connected to each other for a predetermined time. The delay circuit device having the delay circuit can be easily formed. Since the plurality of delay circuit elements have the same configuration, the production and lamination of the plurality of delay circuit elements are easy. For example, when one electrode of a pair of electrodes included in one delay circuit element and the other electrode of a pair of electrodes included in the lower delay circuit element are connected to each other, both delay circuit elements The delay circuits are connected in series with each other. Therefore, it is possible to easily form a delay circuit device having a total delay time in the delay circuits of these delay circuit elements.

  In the delay circuit device, if the input terminal and the output terminal provided on the first main surface of the lowermost delay circuit element are electrically connected to an external transmission line, the transmission line is transmitted. The incoming electric signal can be delayed through a delay circuit for a predetermined time and then output to the transmission line again. Therefore, for example, it is possible to provide a delay circuit element and a delay device that are advantageous in increasing the productivity of an electronic device having a delay element.

(A) is a top view which shows the delay circuit element of embodiment of this invention, (b) is sectional drawing in the AA of (a), (c) is the delay circuit element shown to (a). FIG. FIG. 2 is a schematic diagram (top view) for illustrating positions of through conductors in the delay circuit element shown in FIG. 1. It is a disassembled perspective view which shows the delay circuit apparatus of embodiment of this invention. (A) is a top view showing a first modification of the delay circuit element shown in FIG. 1, and (b) is an exploded perspective view showing the main part of the delay circuit device manufactured by the delay circuit element of (a). It is. (A) And (b) is a top view which shows the 2nd and 3rd modification of the delay circuit element shown in FIG. (A) is a top view which shows the 4th modification of the delay circuit element shown in FIG. 1, (b) is sectional drawing in the AA of (a). FIG. 10 is a top view showing a fifth modification of the delay circuit element shown in FIG. 1. FIG. 10 is a top perspective view showing a sixth modification of the delay circuit element shown in FIG. 1. FIG. 10 is a cross-sectional view showing a seventh modification of the delay circuit element shown in FIG. 1.

  A delay circuit element and a delay device according to embodiments of the present invention will be described with reference to the accompanying drawings. Note that the distinction between the upper and lower sides in the following description is for convenience in the description with reference to the above drawings, and does not specify the upper and lower sides when the delay circuit element is actually used.

  1A is a top view showing a delay circuit element according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line AA in FIG. 1A, and FIG. FIG. 2 is a bottom view of the delay circuit element shown in FIG.

  A delay circuit element 9 includes a flat insulating substrate 1, a plurality of through conductors 2 provided on the insulating substrate 1, and a delay circuit 3 connecting a pair of through conductors 2 among the plurality of through conductors. Is basically formed. In FIG. 1 and each of the following figures, line-shaped conductors such as the delay circuit 3 are shown as lines having no width in order to make the drawing easier to see. Actually, these delay circuits 3 and the like have a predetermined line width (for example, about 50 to 500 μm).

  In the example shown in FIG. 1, the insulating substrate 1 has a quadrangular shape such as a square shape in plan view, and a flat plate shape. The insulating substrate 1 may have a shape other than a square shape, such as a square shape, as long as a plurality of delay circuit elements 9 can be stacked on top of each other.

  That is, the insulating substrate 1 is a flat plate having a first main surface (lower surface in the example of FIG. 1) 11 and a second main surface (upper surface in the example of FIG. 1) 12 opposite to the first main surface. Shape. The first main surface 11 and the second main surface 12 are preferably parallel to each other so that the plurality of delay circuit elements 9 are stacked without tilting. In this case, a concave portion (not shown) or the like may be included in at least one of the first main surface 11 and the second main surface 12 that are parallel to each other. In other words, the first main surface 11 and the second main surface 12 do not have to be completely parallel to each other as long as the plurality of delay circuit elements 9 are within the range where stacking is not hindered. The concave portion can be used as a space for storing electronic components such as a capacitive element and a resistor, for example.

  The insulating substrate 1 is formed by laminating a plurality of insulating layers 1a made of ceramic sintered bodies such as aluminum oxide sintered bodies, aluminum nitride sintered bodies, mullite sintered bodies, and glass ceramic sintered bodies. ing.

  For example, if each insulating layer 1a is made of an aluminum oxide sintered body, the insulating substrate 1 includes a plurality of ceramics obtained by forming raw material powders such as aluminum oxide and silicon oxide into a sheet shape together with an appropriate organic binder and organic solvent. It is manufactured by firing after laminating green sheets.

  The insulating substrate 1 may be formed of an organic resin material such as an epoxy resin, a polyimide resin, and a polyamideimide resin. In this case, for example, the insulating substrate 1 can be manufactured by forming an uncured epoxy resin into a predetermined shape of the insulating substrate 1 using a mold or the like, and curing it by heating. An inorganic additive (filler) such as glass powder may be added to the organic resin material.

  The insulating substrate 1 is provided with a plurality of through conductors 2 penetrating from the first main surface 11 to the second main surface 12, that is, in the thickness direction. Each of the plurality of through conductors 2 is a conductive path that conducts between the first main surface 11 and the second main surface 12 of the insulating substrate 1. When the plurality of delay circuit elements 9 are stacked one above the other, a conductive path is formed by the plurality of through conductors 2 from the uppermost delay circuit element 9 to the lowermost delay circuit element 9.

  The electrical continuity between the first main surface 11 and the second main surface 12 of the insulating substrate 1 is not limited to the through conductor 2 and may be another form of conductor. That is, the insulating substrate 1 only needs to be provided with a wiring conductor that conducts between the first main surface 11 and the second main surface 12, and one form of the wiring conductor is the through conductor 2. As such wiring conductors, in addition to the through conductors 2, side conductors (so-called castoration conductors and the like) provided on the outer surface of the insulating substrate 1, via conductors penetrating a part in the thickness direction of the insulating substrate 1, and plural Examples thereof include a conductor such as an internal wiring provided between the insulating layers 1a. The wiring conductor may be a combination of a plurality of such conductors.

  The insulating substrate 1 is provided with a delay circuit 3 so as to connect any one of the plurality of through conductors 2 between the pair of through conductors 2. The delay circuit 3 is for delaying a signal input to the delay circuit element 9 for a predetermined time. The delay time T by the delay circuit 3 can be calculated by the following equation.

(Formula) T = L × √ (ε _r ) / c
Where, L is the length of the delay circuit 3 (m), ε _r the relative dielectric constant of the insulating substrate 1, c is the speed of light in vacuum (m / s).

In other words, the delay circuit 3 having a predetermined delay time can be provided on the insulating substrate 1 by adjusting the length of the delay circuit or the relative dielectric constant of the insulating substrate 1. For example, the predetermined time is preferably a unit time (for example, 0.01 ns, 0.1 ns, 0.5 ns, 1 ns, etc.). If the delay time is a unit time, the required number of delay circuit elements can be easily calculated with respect to the required delay time in the electronic device in which the delay circuit element 9 is used.

  Since the delay circuit 3 connects the pair of through conductors 2 as described above, a predetermined delay time occurs between the pair of through conductors 2. If one through conductor 2 (2a) of the pair of through conductors 2 is used as an input side conductor and the other through conductor 2 (2b) is used as an output side conductor, the input side conductor and the output side conductor are used. Can be used as the delay circuit element 9 that generates a predetermined delay time between the two.

  That is, the end portion of the through conductor 2 is electrically connected between the upper and lower delay circuit elements 9 or an electrical connection between a delay circuit device (described later) in which a plurality of delay circuit elements 9 are laminated and an external electric circuit. Functions as an electrode for connection or the like. In the example shown in FIG. 1, lands 4 which will be described later are provided connected to the end portions of the through conductors 2, and the end portions of these through conductors 2 and the lands 4 constitute electrodes. The electrode may be composed only of the end portion of the through conductor 2. The electrodes of the plurality of electrodes on the first main surface side and the electrodes of the plurality of electrodes on the second main surface side overlap with each other in plan view and are electrically connected to each other. There is a need. Thereby, a plurality of delay circuit elements 9 can be easily stacked and electrically connected to each other.

  The through conductor 2 (wiring conductor) and the delay circuit 3 are made of, for example, a metal material such as tungsten, molybdenum, manganese, copper, silver, palladium, gold, or platinum, or an alloy of these metal materials. If the through conductor 2 and the delay circuit 3 are made of tungsten, for example, a predetermined position on the main surface of the ceramic green sheet that becomes the insulating layer 1a is a metal paste prepared by mixing tungsten powder with an organic solvent and an organic binder. The insulating layer 1a (insulating substrate 1) is provided in a predetermined pattern by a method such as screen printing and printing. In the case of the through conductor 2, a through hole is provided in advance in the ceramic green sheet, and a metal paste is filled in the through hole. In filling the metal paste into the through hole, means such as vacuum suction may be used in combination.

  The through conductor 2 and the delay circuit 3 may be formed by depositing a metal material such as copper on an insulating base made of a resin material in the form of a thin film such as a vapor deposition layer, a plating layer, or a metal foil. it can.

  Further, for example, when the delay circuit 3 is made of copper and the insulating substrate 1 is made of an organic resin material, the delay circuit 3 made of copper is replaced with an organic resin by means such as vapor deposition, plating, or copper foil bonding. It may be provided on the main surface of the insulating substrate 1 made of a material. In this case, means such as masking and etching can be used in combination.

  Further, when seen in a plan view, the plurality of through conductors 2 are located along the circumference of a virtual circle that overlaps the insulating substrate 1 and have the same adjacent interval. In other words, as shown in FIG. 2, for example, the plurality of through conductors 2 are located at the ends of a plurality of (four in the example of FIG. 2) virtual arcs B having the same central angle and radius. ing. The plurality of arcs B are continuous with each other to form the circle C. FIG. 2 is a schematic diagram (plan view) showing the arrangement of the through conductors 2 in the delay circuit element 9 of the embodiment. In FIG. 2, portions other than the insulating substrate 1 and the through conductor 2 are omitted for easy viewing.

The virtual circle C overlaps with the insulating substrate 1 in plan view. Insulating substrate 1 in plan view
The virtual circle C that overlaps with the circle may be a circle in which the plurality of through conductors 2 positioned along the circumference of the circle C are accommodated in the insulating substrate 1.

  In plan view, the central angles θ of the arcs B between two adjacent through conductors 2 are the same as each other. In other words, the plurality of through conductors 2 are arranged on the circumference of the virtual circle C at substantially constant intervals (same radians). That is, the interval between the adjacent through conductors 2 is the same.

  It should be noted that the adjacent interval between adjacent through conductors 2 (center angles θ of the plurality of arcs B) may not be completely the same value, or may be different from each other by several degrees. These through conductors 2 are for connecting the delay circuits 3 of the upper and lower delay circuit elements 9 to each other when a plurality of delay circuit elements 9 are stacked one above the other. If so, the central angles may be slightly different from each other.

  In the example shown in FIG. 1, a land 4 is provided from each of the first main surface 11 and the second main surface 12 of the insulating substrate 1 to the end surface of the through conductor 2. The land 4 is for facilitating electrical connection between the through conductors 2 of the upper and lower delay circuit elements 9 when, for example, a plurality of delay circuit elements 9 are stacked one above the other. It has become a part of. Since the area of the land 4 is larger than the area of the end face of the through conductor 2, the electrodes are easier to electrically connect between the through conductors 2 of the upper and lower delay circuit elements 9.

  The land 4 can be provided by the same method using the same metal material as that of the delay circuit 3, for example. The land 4 has an exposed surface coated with one or more plating layers, which are appropriately selected from metal materials such as nickel, cobalt, gold and copper, and alloys of these metal materials. Also good.

  The land 4 (4a) provided on the first main surface 11 side of the end surface of the through conductor 2 (2a) serving as the input-side conductor functions as an input electrode (no symbol) of the delay circuit element 9. . The land 4 (4b) provided on the second main surface 12 side of the end surface of the through conductor 2 (2b) serving as the output-side conductor serves as an output electrode (no symbol) of the delay circuit element 9.

  For example, a delay circuit device 10 as shown in FIG. 3 can be manufactured by stacking a plurality of such delay circuit elements 9 in the vertical direction. When a plurality of delay circuit elements 9 are stacked one above the other, one through conductor (input side) 2 (2a) of the pair of through conductors 2 included in the upper delay circuit element 9 and the lower delay circuit element The other through conductor (output side) 2 (2b) of 9 is electrically connected to each other. In other words, the output electrode of the lower delay circuit element and the input electrode of the upper delay circuit element are electrically connected to each other.

  As a result, the delay circuits 3 included in the upper and lower delay circuit elements 9 are connected in series, and a group of delay circuits (no sign) having a total delay time of the delay times of the individual delay circuits 3 is obtained. It is formed. This is repeated to form the delay circuit device 10 having a predetermined delay time.

  In this case, since the adjacent intervals of the plurality of through conductors 2 are the same and are located at the ends of the arc B having the same central angle, the upper and lower delay circuit elements 9 can be rotated relatively by 90 degrees. For example, one through conductor (input side) 2 (2a) of the upper delay circuit element 9 and the other through conductor (output side) 2 (2b) of the lower delay circuit element 9 can be easily and electrically connected. Can connect. The relative rotation angle is changed according to the number of through conductors 2. For example, if there are six through conductors 2 (not shown), the upper and lower delay circuit elements 9 may be rotated by 60 degrees relatively. That is, the rotation angle is 360 × 1 / n (degrees) (where n is the number of through conductors 2).

In the delay circuit device 10, the lowermost delay circuit element 3 is a layer for performing input / output with respect to an external electric circuit (not shown). The end portion (actually land 4) of the through conductor 2 located on the first main surface 11 of the lowermost delay circuit element 3 (that is, the lowermost surface of the delay circuit device 10) is a conductive connecting material 8 such as solder. (Not shown) and electrically and mechanically connected to a predetermined position of the external electric circuit. Thereby, the delay circuit device 10 is mounted on the external electric circuit. An electrical signal is input from the external electrical circuit to the delay circuit device 10 mounted on the external electrical circuit, and after being delayed by the delay circuit device 10 for a predetermined time, the electrical signal is output from the delay circuit device 10 to the external electrical circuit. The

  FIG. 4A is a top view showing a first modification of the delay circuit element 9, and FIG. 4B shows a delay circuit device 10 manufactured by the delay circuit element 9 of FIG. 4A. It is a disassembled perspective view which shows the principal part. 4, parts similar to those in FIGS. 1 and 2 are denoted by the same reference numerals.

  In the example shown in FIG. 4, the insulating substrate 1 has a rectangular shape in plan view. Even in such a case, if the plurality of through conductors 2 are positioned so as to be adjacent to the end of the virtual arc B, the same effects as those of the delay circuit element 9 and the delay circuit device 10 shown in FIG. Can do.

  When the insulating substrate 1 has a rectangular shape (having a long side and a short side) as in this example, when a plurality of delay circuit elements 9 are stacked one above the other, Are not continuous with each other (so-called not flush). Therefore, unevenness is generated on the outer surface of the manufactured delay circuit device. In such a case, this concavo-convex portion is likely to cause mechanical breakage of the insulating substrate 1, and the concavo-convex portion is likely to be caught by jigs and devices (not shown) used when mounted on an external electric circuit. There is a possibility that the practical handling will be reduced.

  That is, the insulating substrate 1 is preferably a regular polygon or a circle. In this case, when a plurality of delay circuit elements 9 are stacked, the outer surfaces of the delay circuit elements 9 are vertically continuous (become flush with each other), so that the delay circuit element 9 and the delay circuit are better in practicality and the like. Device 10 can be provided.

  The regular polygonal shape is not limited to a square shape as shown in FIG. 1, and includes a regular triangular shape, a regular pentagonal shape, a regular hexagonal shape, a regular octagonal shape, and the like. In this case, the insulating substrate 1 is not limited to a perfect regular polygon. For example, the insulating substrate 1 has a square shape and its corners are formed in a circular arc shape (so-called chamfering), or a part of the side is recessed inward. It may be one having By chamfering, for example, mechanical destruction such as cracks of the insulating substrate 1 at the corners can be more effectively suppressed. Further, the inward dent in a part of the side can be used as, for example, a holding position when the insulating substrate 1 is lifted by a jig or the like.

  FIGS. 5A and 5B are top views showing second and third modifications of the delay circuit element shown in FIG. 1, respectively. FIG. 5A shows an example in which the insulating substrate 1 is a regular octagon. FIG. 5B shows an example where the insulating substrate is circular.

  As shown in FIG. 5A, when the insulating substrate 1 has a regular polygonal shape such as a regular octagon, when the plurality of delay circuit elements 9 are stacked, the corners of the upper and lower delay circuit elements 9 are connected to each other. It is easy to align.

In addition, when the through conductors 2 are located at the corners of the regular polygonal insulating substrate 1, the ends (or lands 4) of the upper and lower through conductors 2 are aligned together with the alignment of the corners. It is also possible to easily carry out and confirm the alignment of these. Therefore, the delay circuit element 9 with higher practicality can be provided. Further, in this case, it is advantageous to increase the distance between the plurality of through conductors 2 and reduce electromagnetic interference between the through conductors 2.

  Further, when the insulating substrate 1 is circular, there are no (or few) corner portions where cracks or the like are likely to occur, and therefore the delay circuit element 9 and the mechanical breakdown such as cracks in the insulating substrate 1 are less likely to occur. The delay circuit device 10 can be provided.

  Moreover, as shown in FIG.5 (b), the regular polygonal through-hole 5 may be provided in the center part of the insulated substrate in planar view. In this case, when a plurality of delay circuit elements 9 are stacked, a predetermined position such as a corner of the through hole 5 can be used for alignment between the upper and lower delay circuit elements 9. For example, if two delay circuit elements 9 are stacked one above the other and the corners of the through holes 5 of the upper and lower delay circuit elements 9 are aligned, the through conductors 2 (lands) 4 of the upper and lower delay circuit elements 9 are connected to each other. Can be easily aligned. Therefore, it is possible to provide the delay circuit element 9 with higher workability and productivity when the delay circuit device 10 in which the plurality of delay circuit elements 9 are laminated is manufactured.

  In this case, any one of the plurality of corners of the through-hole 5 can be distinguished from the other, and the land 4 as the output electrode (the two delay circuit elements 9 to be stacked) It is also possible to make it easier to align the position of one of them) and the land as the input electrode (of the other delay circuit element 9). As such identification means, for example, printing of a mark for identification on the first or second main surface 11, 12 of the insulating substrate 1 using a coloring material such as dye or pigment, or the first or second main Means such as formation of recesses in the surfaces 11 and 12 can be mentioned.

  In this case, each of the plurality of through conductors 2 may be positioned on a virtual straight line passing through the corner from the center of the through hole 5 in plan view. In this case, the alignment and electrical connection between the through conductors 2 (lands 4) of the upper and lower delay circuit elements 9 can be made easier and more reliable.

  6A is a top view showing a fourth modification of the delay circuit element shown in FIG. 1, and FIG. 6B is a cross-sectional view taken along the line AA in FIG. 6A. In the example shown in FIG. 6, the ground conductor layer 6 is provided on the second main surface 12 of the insulating substrate 1. If such a ground conductor layer 6 is provided, when a plurality of delay circuit elements 9 are stacked one above the other, electromagnetic interference between the delay circuits 3 of the delay circuit elements 9 adjacent to each other in the vertical direction is prevented. It can be effectively reduced.

  The ground conductor layer 6 is desirably provided in a range that covers the entirety of the delay circuit 3 in a plan view in order to sufficiently obtain the electromagnetic shielding effect. When the ground conductor layer 6 is provided on the first main surface 11 or the second main surface 12 of the insulating substrate 1, the delay circuit 3 is electrically connected to the ground conductor layer 6 of the other delay circuit element 9. In order to avoid a short circuit, it is provided so as to be located inside the insulating substrate 1. The ground conductor layer 6 can be provided by the same method using, for example, the same metal material as that of the delay circuit 3.

If the ground conductor layer 6 is provided on at least one main surface of the first main surface 11 and the second main surface 12 of the insulating substrate 1, a certain shielding effect can be obtained. Furthermore, if the ground conductor layer 6 is provided on both the first and second main surfaces 11 and 12 of the insulating substrate 1, the electromagnetic shielding effect can be obtained more sufficiently. Further, if the ground conductor layer 6 is provided on both the first and second main surfaces 11 and 12 of the insulating substrate 1, for example, the insulating substrate 1 made of an aluminum oxide sintered body and the metallization of tungsten or the like. When the ground conductor layer 6 composed of layers is formed by simultaneous firing, deformation of the insulating substrate 1 such as warpage can be more reliably suppressed. That is, when the metal paste that becomes the ground conductor layer 6 is printed and fired on the first and second main surfaces 11 and 12 of the ceramic green sheet (laminated body or the like) that becomes the insulating substrate 1, the ceramic green sheet and the metal paste The stress caused by the difference in shrinkage during firing cancels out between the upper and lower sides of the ceramic green sheet. Therefore, the warp of the insulating substrate 1 is effectively suppressed.

  FIG. 7 is a top view showing a fifth modification of the delay circuit element shown in FIG. In FIG. 7, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. In the example shown in FIG. 7, a plurality of through conductors 2 are respectively provided in the central part of the side of the square insulating substrate 1. As described above, the plurality of through conductors 2 may not be located at corners of the insulating substrate 1 such as a regular polygonal shape.

  For example, as shown in FIG. 7, the positions of the plurality of through conductors 6 may be appropriately adjusted according to the arrangement space of the delay circuit 3 on the insulating substrate 1 or the like. When the penetrating conductor 2 is on the side portion, the penetrating conductor 2 is separated from a corner portion of the insulating substrate 1 where mechanical breakage such as a crack is likely to occur. Therefore, for example, even if a crack occurs at the corner, it is more effectively suppressed that the influence reaches the through conductor 2 (partial destruction of the through conductor 2 and the like).

  FIG. 8 is a top perspective view showing a sixth modification of the delay circuit element shown in FIG. In FIG. 8, the same parts as those in FIG. In the example shown in FIG. 8, the ground line 7 is provided adjacent to the delay circuit 3. The ground line 7 is separated from the delay circuit 3. In this example, the delay circuit 3 and the ground line 7 adjacent to each other are provided between the same insulating layers 1a. In FIG. 6, for the sake of clarity, the insulating layer 1a above the layer where the delay circuit 3 and the ground line 7 are provided is omitted from the perspective view.

  The delay circuit 3 and the ground line 7 may be separated from the upper surface or the lower surface of the insulating substrate 1. However, in this case, the delay circuit 3 and the ground line 7 are arranged at a position where an electrical short circuit does not occur between the upper and lower delay circuit elements 3 when the plurality of delay circuit elements 3 are stacked. Need to be.

  When the ground line 7 is provided adjacent to the delay circuit 3, the effect of electromagnetic shielding on the external electric circuit of the delay circuit 3 can be enhanced. Therefore, for example, electromagnetic interference between the delay circuit 3 of the delay circuit device 10 and the external electric circuit on which the delay circuit device 10 is mounted can be effectively reduced. Such a ground line 7 can be provided by the same method using the same metal material as the delay circuit 3, for example.

  In order to sufficiently obtain the above-described electromagnetic shielding effect, the ground line 7 is desirably provided adjacent to the entire length of the delay circuit 3. When the delay circuit 3 and the ground line 7 which are adjacent to each other are located between the plurality of insulating layers 1a, that is, inside the insulating substrate 1, for example, a plurality of delay circuit devices 10 are stacked. Sometimes, the electrical short circuit in the delay circuit 3 or the ground line 7 is suppressed between the delay circuit devices 10. Therefore, for example, in consideration of practicality when a plurality of delay circuit devices 10 are stacked and used, it is preferable that the delay circuit 3 and the ground line 7 are located inside the insulating substrate 1.

  The ground line 7 may be electrically connected to the ground conductor layer 6 in a delay circuit element 9 having the ground conductor layer 6 as shown in FIG. In this case, the ground potential in the ground line 7 is further stabilized, and the effect of electromagnetic shielding by the ground line 7 on the delay circuit 3 is further enhanced.

  The electrical connection between the ground line 7 and the ground conductor layer 6 is made, for example, via a ground via conductor 7a that penetrates the insulating layer 1a in the thickness direction. The grounding via conductor 7a can be formed by using the same metal material as that of the through conductor 2, for example, by the same method.

  In the example of FIG. 8, the delay circuit 3 has a meander pattern, and a plurality of straight (line segment) ground lines 7 are provided adjacent to the delay circuit 3. The plurality of ground lines 7 are electrically connected to the ground conductor layer 6 through the via conductors 7a, so that they are more reliably at the same potential.

  FIG. 9 is a sectional view showing a seventh modification of the delay circuit element shown in FIG. 9, parts similar to those in FIG. 1 are denoted by the same reference numerals. In the example shown in FIG. 9, the delay circuit 3 is located between a plurality of stacked insulating layers 1a. Further, between the layers, a filling layer 8 is filled in portions other than the delay circuit 3. The filling layer 8 is made of a dielectric material having a relative dielectric constant higher than that of the insulating layer 1a. In this example, an insulating substrate 1A is formed by a plurality of insulating layers 1a and a filling layer 8 between the insulating layers 1a.

  In such a case, since the portion other than the delay circuit 3 between the layers is filled with the filling layer 8, there is a possibility that a gap is generated between the upper and lower insulating layers 1a according to the thickness of the delay circuit 3. Reduced. Therefore, it is possible to provide the delay circuit element 9 and the delay circuit device 10 including the insulating substrate 1A in which the adhesion between the plurality of insulating layers 1a is improved.

In addition, a large effect when the filling layer 8 having the above-described configuration is included is effective in shortening the length (L) of the delay circuit 3, and downsizing as the delay circuit element 9 and the delay circuit device 10 is effective. It is easy to mention. That is, when the same delay time T is obtained in (Expression) T = L × √ (ε _r ) / c, the filling layer 3 having a relative dielectric constant (root) √ (ε _r ) larger than that of the insulating layer 1a is delayed. If it is adjacent to the circuit 3, the length L of the delay circuit 3 can be small, which is advantageous for miniaturization.

  The filling layer 8 may have a thickness (not shown) larger than the thickness of the delay circuit 3. In this case, the filling layer 8 is filled between the layers so as to cover the entire delay circuit 3.

  The filling layer 8 is formed of, for example, a ceramic sintered body having a glass content smaller than that of the insulating layer 1a. For example, when the insulating layer 1a is made of a glass ceramic sintered body, the filling layer 8 is made of a ceramic paste having a glass content smaller than that of the ceramic green sheet to be the glass ceramic sintered body, and the ceramic paste is insulated. It can be formed by printing on the surface of the ceramic green sheet to be the layer 1a and co-firing. In this case, the ceramic paste is printed by a screen printing method using a printing plate provided with a pattern that avoids a portion where the metal paste to be the delay circuit 3 is printed.

  In addition, the relative dielectric constant of the filling layer 8 can be appropriately adjusted according to the glass content as described above. For example, if the insulating layer 1a is made of a glass ceramic sintered body having a glass content of about 60% by mass and a relative dielectric constant of about 7, the filler layer 8 has a glass content of about 50% by mass. % And a glass ceramic sintered body having a relative dielectric constant of about 8 can be used.

  In addition, the relative dielectric constant of the filling layer 8 can be adjusted by means other than the glass content, such as the ratio or composition of the voids inside. For example, the relative permittivity of the entire filling layer 8 can be increased as the proportion of the voids in the filling layer 8 is reduced.

  The filling layer 8 can be formed, for example, by printing a ceramic paste as described above. Further, the ceramic paste does not need to be formed into a sheet shape unlike the ceramic green sheet that becomes the insulating layer 1a. Therefore, formation of the filling layer 8 is easy. Moreover, adjustment of the glass content rate of the filling layer 8 is easier than adjustment of the glass content rate of the insulating layer 1a.

1 (1A) .. Insulating substrate
11 ・ ・ ・ First surface
12 ... 2nd main surface 1a .... Insulating layer 2 ... Through conductor (wiring conductor)
3 ... Delay circuit 4 ... Land (electrode)
5 ... through hole 6 ... grounding conductor layer 7 ... grounding line 8 ... filling layer 9 ... delay circuit element
10 ... Delay circuit device

Claims (10)

An insulating substrate having a first main surface and a second main surface opposite to the first main surface;
The insulation is provided on the first main surface and the second main surface of the substrate, between said first major surface and said second major surface, 3, which are electrically connected to each other with overlap in a plan view Two or more electrodes,
A delay circuit provided on the insulating substrate so as to connect between any one of the plurality of electrodes;
The plurality of electrodes are arranged along the circumference of a virtual circle that overlaps the insulating substrate in plan view so that adjacent intervals between the electrodes have the same length .
When the insulating substrate is rotated around the center of the virtual circle and stacked vertically, one electrode of the upper pair of electrodes is connected to the other electrode of the lower pair of electrodes. overlap, the delay circuit elements other electrode of the upper side of the pair of electrodes, wherein the overlap with Rukoto and other electrodes other than the pair of electrodes of the lower. The delay circuit element according to claim 1, wherein the insulating substrate has a regular polygonal shape or a circular shape in a plan view. The delay circuit element according to claim 2, wherein the insulating substrate has a regular polygonal shape in a plan view, and the plurality of electrodes are respectively positioned at corners of the insulating substrate. 3. The delay circuit element according to claim 2, wherein a through-hole having a regular polygonal shape in a plan view is provided at a central portion of the insulating substrate. 5. The delay circuit element according to claim 4, wherein each of the plurality of electrodes is positioned on an imaginary straight line passing through a corner from the center of the through hole in plan view. The delay circuit is located inside the insulating substrate, and a ground conductor layer is provided on at least one main surface of the first main surface and the second main surface of the insulating substrate. The delay circuit element according to any one of claims 1 to 5. The delay circuit element according to claim 1, further comprising a ground line provided adjacent to the delay circuit and spaced from the delay circuit. 8. The delay circuit element according to claim 7, wherein the delay circuit and the ground line are located inside the insulating substrate. The insulating substrate includes a plurality of insulating layers stacked on each other, and the delay circuit is located between the plurality of insulating layers,
2. The method according to claim 1, further comprising a filling layer made of a dielectric material having a relative dielectric constant higher than that of the insulating layer and filled in a portion other than the delay circuit between the layers where the delay circuit is located. The delay circuit element described. The delay circuit element according to claim 1, wherein a plurality of the delay circuit elements are vertically stacked with the first main surface facing downward, and the lower delay circuit element has between the two delay circuit elements adjacent vertically. and said other side of the electrode of the second main surface side of the pair of electrodes, and the electrodes of the hand of the first main surface side of the pair of electrodes of the upper side of the delay circuit elements, electrical Delay circuit device, characterized in that the delay circuit devices are connected in a connected manner.

Images