JP6204313B2 - Electronics - Google Patents

Description

  The present invention relates to an electronic device.

  A certain information processing apparatus executes a specific process by dedicated hardware such as an ASIC (Application Specific Integrated Circuit) and also executes a specific process by software processing by a SIMD (Single Instruction Multiple Data stream) processor (for example, Patent Document 1).

JP 2011-191903 A

  FIG. 4 is a block diagram illustrating an example of a data flow in the electronic device. Assuming that a series of processes to be processed sequentially is a process block, as shown in FIG. 4, for example, in an electronic device, a plurality of process blocks are executed by three processes by four ASICs and one SIMD processor. For example, in the process block # 0, first, after the processing by the ASIC # 0 is performed on the band data in the image data (a set of line data for a certain width), the process # 0 by the SIMD processor is performed. Thereafter, processing by another ASIC # 1 is executed. The plurality of process blocks may be executed in parallel or sequentially.

  Specifically, for example, in an image forming apparatus such as a multifunction machine, as a certain process block, first, acquisition of image data by image reading is executed by an ASIC, and a spatial filter is applied to the image data in the SIMD process. In addition, as another process block, image processing such as color conversion is performed on the image data, and then halftoning is performed by the ASIC.

  FIG. 5 is a diagram for explaining a data processing band required for the ASIC by the process blocks (PB) # 0 to # 2 shown in FIG. Generally, when a process block is interrupted and another process block is executed, a context switch occurs and overhead is generated. Therefore, as shown in FIG. 5, process blocks # 0 to # 2 are executed sequentially. . Therefore, when the data processing speed of the SIMD process is higher than the data processing speed by the ASIC, depending on the type of processing, a specific ASIC may require a wide bandwidth (that is, high throughput) as in the ASIC # 2 in FIG. As a result, the cost of the apparatus increases to realize the bandwidth, or the processing speed is reduced without achieving the required bandwidth.

  The present invention has been made in view of the above problems, and leveling the required bandwidth of each of a plurality of hardware processing units such as an ASIC in the time axis direction while suppressing a decrease in the overall data processing speed. Thus, it is an object to obtain an electronic device that keeps the maximum required bandwidth low.

  An electronic device according to the present invention is an electronic device that sequentially performs hardware processing and software processing on data, and includes a hardware processing unit that performs the hardware processing and a software processing unit that performs the software processing An internal memory for the software processing unit, a read direct memory access controller that reads data for one subline obtained by dividing a line into a predetermined number in the main scanning direction from an external memory, the hardware processing unit, and the Among the read direct memory access controllers, a load transfer unit for transferring data for one subline from the transmission source corresponding to the process identifier to the internal memory, and a write direct memory access controller for writing data for one subline to the external memory. A roller, a store transfer unit that transfers data for one subline stored in the internal memory to a destination corresponding to a process identifier among the hardware processing unit and the write direct memory access controller, and the load transfer And a controller for designating the process identifier to the store transfer unit and transferring data for one subline. The internal memory has a plurality of buffer areas, the load transfer unit writes data to the buffer areas, and the software processing unit is multi-threaded and data for one subline from the plurality of buffer areas. Is read and the process is executed. The controller performs exclusive control of the plurality of buffer areas, locks the buffer area until the use of the data in the buffer area by the software processing unit is completed, and the buffer area specified by a certain process identifier When there is no buffer area that is not locked, the load transfer unit does not transfer the data specified by the process identifier to the internal memory, and is specified by another process identifier. If there is an unlocked buffer area among the buffer areas to be transferred, the load transfer unit is caused to transfer the data specified by the another process identifier to the internal memory.

  According to the present invention, since the granularity of data and processing is reduced while suppressing the overhead of context switching, each of a plurality of hardware processing units such as ASICs is suppressed while suppressing a decrease in the overall data processing speed. By leveling the required bandwidth in the time axis direction, the maximum required bandwidth can be kept low.

FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an operation of the electronic device illustrated in FIG. FIG. 3 is a diagram showing an example of a format of a process identifier used in the electronic device shown in FIG. FIG. 4 is a block diagram illustrating an example of a data flow in the electronic device. FIG. 5 is a diagram for explaining a data processing band required for the ASIC by the process blocks # 0 to # 2 shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to an embodiment of the present invention. The electronic device illustrated in FIG. 1 sequentially performs hardware processing and software processing on data. For example, the electronic device is an image forming apparatus such as a multifunction peripheral, and performs image processing on image data by hardware processing and software processing.

  The electronic device shown in FIG. 1 includes a plurality of ASICs 1 as hardware processing units, and also includes a SIMD processor 2 as a software processing unit. The SIMD processor 2 has a higher data processing speed than each ASIC 1.

  Each of the plurality of ASICs 1 performs predetermined hardware processing (that is, specific data processing by dedicated hardware), and the SIMD processor 2 operates in a multi-thread, and each thread corresponding to a plurality of process blocks includes: Perform software processing (ie, programmed data processing by software).

  In this embodiment, the SIMD processor 2 executes image processing and includes at least the same number of processing elements as the number of pixels of the subline. That is, processing for all the pixels in one subline is performed in parallel by the plurality of processing elements.

  A read DMAC (Direct Memory Access Controller) 3 reads data for one subline from the external memory 102. One subline is a data amount obtained by dividing one line of data into a predetermined number in the main scanning direction.

  The read DMAC 3 includes a built-in memory (for example, SRAM (Static RAM), DRAM, etc.), stores context information for each process identifier in the built-in memory, and incorporates context information corresponding to the process identifier specified by the controller 31. After reading from the memory and switching the context, data corresponding to the designated process identifier is read based on the context information after the switching. By doing so, the delay due to the reading of the context information can be reduced as compared with the case where the context information is stored in the external memory 102.

  The write DMAC 4 writes data for one subline to the external memory 102. The write DMAC 4 also has a built-in memory, stores context information for each process identifier in the built-in memory, reads the context information corresponding to the process identifier specified by the controller 31 from the built-in memory, switches the context, and then switches. Based on the subsequent context information, data writing corresponding to the designated process identifier is executed.

  In FIG. 1, the routing unit 11 performs static routing between the ASICs 1 and between the ASIC 1 and the buffer 12. The buffer 12 is provided corresponding to the ASIC 1 and receives and temporarily stores data transferred to the ASIC 1 and data transferred from the ASIC 1 by FIFO (First-In First-Out). However, the number of buffers 12 may be the same as that of ASIC1, but may be less than ASIC1.

  In FIG. 1, an internal memory 21 is an internal memory for the SIMD processor 2 (that is, a shared memory of processing elements in the SIMD processor 2), and is a RAM (Random Access Memory). Read / write to the internal memory 21 is executed.

  The internal memory 21 has a plurality of buffer areas, and the SIMD processor 2 operates in a multi-thread manner, reads data for one subline from the plurality of buffer areas, and executes processing. For example, the internal memory 21 has a ring buffer area for each process block (that is, for each thread of the SIMD processor 2), and the SIMD processor 2 reads and processes data sequentially from the ring buffer area in each thread. Run.

  The load transfer unit 23 transfers data for one subline from the transmission source corresponding to the process identifier of the ASIC 1 and the read DMAC 3 to the internal memory 21 using the memory interface 22. Specifically, the load transfer unit 23 writes data in the buffer area.

  The store transfer unit 24 transfers data for one subline stored in the internal memory 21 to a destination corresponding to the process identifier of the ASIC 1 and the write DMAC 4.

  The routing unit 25 routes the data for one subline from the read DMAC 3 to either the ASIC 1 (specifically, the corresponding buffer 12) or the load transfer unit 23, and stores the data for one subline. Routing is performed from the unit 24 to either the ASIC 1 (specifically, the corresponding buffer 12) or the write DMAC 4. Specifically, a channel to the destination is determined corresponding to the process identifier, and the data is transferred to the destination through the channel. At this time, data for one subline is burst transferred to the destination.

  The controller 31 uses an I / O (Input / Output) bus 32 to perform inter-processor communication with the SIMD processor 2, and to read DMAC 3, write DMAC 4, load transfer unit 23, store transfer unit 24, etc. Output the command.

  The controller 31 designates a process identifier for the load transfer unit 23 and the store transfer unit 24 and causes the data transfer for one subline to be executed.

  In addition, the controller 31 designates a process identifier and causes the read DMAC 3 to read data for one subline. Furthermore, the controller 31 designates a process identifier and writes data for one subline in the write DMAC 4.

  Further, the controller 31 performs exclusive control of a plurality of buffer areas in the internal memory 21 and locks the buffer areas until the use of data in the buffer area by the SIMD processor 2 is completed. When there is no unlocked buffer area among the buffer areas specified by a certain process identifier, the controller 31 sends the data specified by the process identifier to the internal memory 21 to the load transfer unit 23. If there is an unlocked buffer area among the buffer areas specified by another process identifier, the load transfer unit 23 receives the data specified by the other process identifier. The transfer to the internal memory 21 is executed.

  The host interface 33 performs communication between a main CPU (Central Processing Unit) 101 and the controller 31. For example, the main CPU 101 generates band data from image data, further generates sub-band data obtained by dividing the band data in the main scanning direction, and stores it in the external memory 102. Note that the main CPU 101 does not intervene in the controller 31 during execution of the above-described process block. The external memory 102 is a DRAM that is a main memory of the main CPU 101. The main CPU 101 and the external memory 102 belong to the system clock domain, and the SIMD processor 2 belongs to a clock domain different from the system clock domain.

  Next, the operation of the electronic device will be described.

  FIG. 2 is a diagram illustrating an operation of the electronic device illustrated in FIG. FIG. 3 is a diagram showing an example of a format of a process identifier used in the electronic device shown in FIG.

  First, the main CPU 101 prepares subband data in the external memory 102.

  Then, as described below, data is read from the external memory 102 one subline at a time, and a plurality of program blocks are executed in parallel at a granularity of one subline.

  The controller 31 exclusively controls the buffer area of the internal memory 21, selects one process block (thread) having an empty buffer area by a predetermined arbitration method, and processes corresponding to the selected process block (thread). The identifier is designated and a command is output to the read DMAC 3 and the load transfer unit 23.

  As shown in FIG. 3, the process identifier has a process block ID unique to the process block and a local process ID indicating the process type. A local process ID value is assigned to each of a predetermined series of processes, and a process to be executed in the process block specified by the process block ID based on the local process ID included in the process identifier The order is specified.

  When the read DMAC 3 accepts the command, it sets context information (such as a read address of data for one subline) corresponding to the process identifier specified by the command, and then reads data for one subline from the external memory 102. , Update context information. The load transfer unit 23 transfers the data for one subline to the buffer area corresponding to the process identifier in the internal memory 21. At this time, the process block ID in the process identifier is used as a context ID, and context information is stored for each process block ID.

  When the transfer is completed, the load transfer unit 23 notifies the controller 31 of the transfer completion. When the notification of transfer completion is received, when the processing by the SIMD processor 2 is executed on the transferred data, the controller 31 immediately sends a command to the SIMD processor 2 to execute the processing on the data. The processed data is stored in a buffer area corresponding to the process identifier. When the data processing for one subband is completed, the SIMD processor 2 notifies the controller 31 of the completion of processing.

  The controller 31 selects the data to be transferred from the internal memory 21 after the processing by the SIMD processor 2 is completed, designates the process identifier of the selected data, and outputs a command to the store transfer unit 24. . Upon receipt of the command, the store transfer unit 24 reads the data from the buffer area of the internal memory 21 corresponding to the designated process identifier, designates the process identifier, and sends the read data to the routing unit 25. To do. The data is received via the routing unit 25 at a destination (the buffer 12 of the ASIC 1 or the write DMAC 4) corresponding to the process identifier.

  When data is stored in the external memory 102, the destination is the write DMAC 4. In that case, the controller 31 designates a process identifier and outputs a command to the write DMAC 4. When the write DMAC 4 receives the command, the write DMAC 4 sets the context information (such as the write address of data for one subline) corresponding to the process identifier specified by the command, and then receives the data via the routing unit 25. The received data is written into the external memory 102.

  When data is input to the buffer 12, the ASIC 1 executes processing on the data and writes the processed data to the buffer 12. Further, when the processing of the data is completed, the ASIC 1 notifies the controller 31 of the completion of the processing. When the controller 31 receives the notification, if there is an empty buffer area corresponding to the process identifier corresponding to the data, the controller 31 designates the process identifier and outputs a command to the load transfer unit 23, and the load transfer unit 23 reads the data from the buffer 12 according to the command and transfers it to the buffer area of the internal memory 21.

  If the data processed by the ASIC 1 is to be stored in the external memory 102 without being processed by the SIMD processor 2, the data processed by the ASIC 1 is first stored by the load transfer unit 23 as described above. The data is transferred to the memory 21, and thereafter transferred from the internal memory 21 to the write DRAM 4 by the store transfer unit 24 without being processed by the SIMD processor 2 and written to the external memory 102. At this time, when the data transfer by the store transfer unit 24 is completed, the controller 31 is notified of the end of the data transfer, and the controller 31 releases the lock of the buffer area in the internal memory 21 used by this data.

  When data stored in the external memory 102 is to be transferred to the ASIC 1 without being processed by the SIMD processor 2, the data is first stored in the internal memory by the read DMAC 3 and the load transfer unit 23 as described above. Then, without being processed by the SIMD processor 2, the data is transferred from the internal memory 21 to the ASIC 1 (via the routing unit 25 and the buffer 12) by the store transfer unit 24. At this time, when the data transfer by the store transfer unit 24 is completed, the controller 31 is notified of the end of the data transfer, and the controller 31 releases the lock of the buffer area in the internal memory 21 used by this data.

  In this way, a program block having an empty buffer area in the internal memory 21 is subjected to software processing by the SIMD processor 2 with a granularity of one subline, and before or after that, hardware processing by the ASIC 1 is executed. . At this time, since a series of processes to be executed on the data is specified by a process identifier added to the data, the controller 31 does not need to specify a process to be executed for each data one by one. .

  Therefore, since the processing by the SIMD processor 2 in a plurality of program blocks is performed in a multithreaded manner in parallel, the processing by the SIMD processor 2 in the plurality of program blocks is executed while being distributed along the time axis. The processing of the ASIC 1 executed before or after is also distributed and executed along the time axis.

  When a series of processing for all the sub-block data is completed and the processed sub-block data is stored in the external memory 102, the main CPU 101 combines the processed sub-block data into one band data. To do.

  As described above, according to the above-described embodiment, as described below, each requested bandwidth of the ASIC 1 is set with the processing granularity as one subline while suppressing a decrease in the overall data processing speed due to context switching. By leveling in the time axis direction, the maximum required bandwidth can be kept low.

  Generally, when hardware processing is cascade-connected to software processing with a short instruction step number, the size of the data buffer between software processing and hardware processing is smaller than the processing granularity (context switching granularity) of software processing. When it is not sufficient, if the speed of the subsequent hardware processing is not sufficient for the software processing, the software processing is made to wait. In this regard, in the above embodiment, since the processing granularity is one subline and is sufficiently small, a data buffer between software processing and hardware processing is sufficiently secured.

  In general, when the processing granularity is reduced, the overhead due to context switching increases. Regarding this point, in the above embodiment, the read DMAC 3 and the write DMAC 4 are provided with a local built-in memory, and the context switching is performed using the memory, and the SIMD processor 2 switches the processing in a multi-thread. The overhead of context switching is reduced.

  Furthermore, when software processing is multi-threaded, when one hardware processing unit is used by a plurality of threads (corresponding to a plurality of process blocks in this case), the hardware processing unit is generally shared. Therefore, complicated control is required. With regard to this point, in the above embodiment, since the processing order of each data is determined with the granularity of one subline based on the above-described process identifier, one ASIC 1 is connected to a plurality of process blocks with relatively simple control. Can be shared on

  The above-described embodiments are preferred examples of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. is there.

  For example, in the above-described embodiment, in the above-described arbitration, a backward process may be prioritized in order to avoid deadlock.

  The present invention is applicable to, for example, an image forming apparatus.

1 ASIC (an example of a hardware processing unit)
2 SIMD processor (example of software processing unit)
3 Lead DMAC
4 Write DMAC
21 Internal memory 23 Load transfer unit 24 Store transfer unit 31 Controller

Claims (5)

In an electronic device that sequentially performs hardware processing and software processing on data,
A hardware processing unit for performing the hardware processing;
A software processing unit for performing the software processing;
An internal memory for the software processor;
A read direct memory access controller for reading out data for one subline obtained by dividing a line into a predetermined number in the main scanning direction from an external memory;
Among the hardware processing unit and the read direct memory access controller, a load transfer unit that transfers data for one subline from the transmission source corresponding to the process identifier to the internal memory,
A write direct memory access controller that writes data for one subline to the external memory;
A store transfer unit that transfers data for one subline stored in the internal memory to a destination corresponding to a process identifier among the hardware processing unit and the write direct memory access controller;
A controller for specifying the process identifier for the load transfer unit and the store transfer unit, and transferring data for one subline,
The internal memory has a plurality of buffer areas,
The load transfer unit writes data to the buffer area,
The software processing unit is multi-threaded and executes processing by reading data for one subline from the plurality of buffer areas,
The controller performs exclusive control of the plurality of buffer areas, locks the buffer area until the use of the data in the buffer area by the software processing unit is completed, and the buffer area specified by a certain process identifier When there is no buffer area that is not locked, the load transfer unit does not transfer the data specified by the process identifier to the internal memory, and is specified by another process identifier. If there is an unlocked buffer area among the buffer areas to be transferred, the load transfer unit is caused to execute transfer of the data specified by the another process identifier to the internal memory. ,
Electronic equipment characterized by   When the transmission source is the read direct memory access controller, the controller links data read by the read direct memory access controller together with data transfer by the load transfer unit, and the destination is the write direct memory access controller 2. The electronic device according to claim 1, wherein data writing by the write direct memory access controller is linked with data transfer by the store transfer unit. The read direct memory access controller includes a built-in memory, stores context information in the built-in memory for each process identifier, reads out the context information corresponding to the process identifier specified by the controller from the built-in memory, and stores the context information. After switching, executing reading of the data corresponding to the specified process identifier based on the context information after the switching,
The electronic device according to claim 1. The data is image data,
The hardware processing and the software processing include image processing on the image data;
The electronic device according to any one of claims 1 to 3, wherein The software processing unit is a SIMD processor,
The data for the one subline is image data,
The SIMD processor includes at least the same number of processing elements as the number of pixels of a subline, and the processing element processes data for one subline in parallel;
The electronic device according to any one of claims 1 to 4 , wherein

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