JP6207213B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus that provides processing data in response to an external request.

  Conventionally, in the computer field, when performing certain processing, a part of the processing is executed by hardware (hereinafter referred to as H / W) to improve the processing efficiency of the CPU and the processing speed of the entire device. It was. The following three processes can be considered as a certain process here.

  The first is management processing of various resources such as a memory area. Here, an example of memory resource management using H / W having an ID management function will be described. Whether an ID is assigned to each of the logically or physically distributed memory areas by the H / W or CPU, and whether the corresponding ID (memory area corresponding to the H / W) is used Centrally manage whether or not. When the CPU wants to use the ID (memory area associated with the ID), it sends an ID acquisition request to the H / W. The H / W that has received the acquisition request transmits an ID that has not been used from the H / W to the CPU, thereby giving the CPU permission to use the ID (memory area associated with the CPU). At the same time, the H / W holds the corresponding ID as a use-prohibited state for other CPUs. Further, when it is desired to release the memory used by the CPU, an ID release request associated with the memory is transmitted to the H / W. The received H / W manages the ID again as an available ID.

  The second is random number generation processing. The CPU requests the H / W to generate a random number, and the H / W generates a random number having a higher randomness than the CPU and returns the result to the CPU.

  The third is timer processing. This is a process in which the start of the timer is notified to the H / W, and when an inquiry is made as to how much time has elapsed from the start to the H / W after a certain time has elapsed, the elapsed time is returned from the H / W.

  What is applicable to any of the above three examples is that the CPU once transmits a request to the H / W and then receives desired data from the H / W as a response.

  As H / W for managing resources, Patent Document 1 discloses a resource management apparatus that accepts a temporary reservation request for resources. The resource management apparatus that has received the provisional reservation request discloses provisional reservation identification information as a response method to the provisional reservation request.

  Patent Document 2 discloses a resource management method. Specifically, it is a resource management method for software applications developed in a client / server system. Describes how to determine whether a resource group required to adapt to a request is stored locally on the client computer, and if it is not stored locally, obtain it from the server system Yes.

  Patent Document 3 discloses a memory resource management method. In the data processing device, in order to respond to the request for acquiring the space to be used, an empty space is confirmed. If there is not enough empty space, the space acquisition request is put in a wait state and processing is performed when the space is released. It describes how to do this.

JP 2004-302748 A Special table 2003-536133 gazette JP-A-63-201826

  In a configuration in which processing is executed by H / W and the result is received by the CPU, there are the following problems. When the CPU transmits a processing result acquisition request to the H / W, if it takes time until the processing result is obtained by the H / W, the CPU is waiting. Then, the CPU cannot shift to the next process. For example, it is desirable that the CPU can promptly move to the next process if there is another process to be performed even if the process result is not obtained.

In order to solve this problem, for example, an information processing apparatus of the present invention has the following configuration. That is,
An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit ;
The memory unit notifies the control unit of a storage state of the processing data;
The control unit controls whether to cause the response unit to transmit a response signal including the processing data to the request unit or to transmit a response signal including the predetermined value to the request unit based on the storage state. It is characterized by doing .

  According to the present invention, when there is a request for obtaining processing data via at least the bus, the preset pseudo data is used as the processing response result until the processing data of the processing result corresponding to the request is obtained. As a result, the request source can promptly move to the next process. Even when processing data acquisition requests are executed from a plurality of request sources, one request source does not occupy the bus for accessing the apparatus, so other request sources can quickly access the apparatus. it can.

1 is an overall block diagram of an information processing apparatus. FIG. 2 is an overall block diagram of a processing unit in the first embodiment. The flowchart of a control part. The flowchart of IF part and a register part. 6 is a timing chart of the information processing apparatus. 1 is an overall block diagram of an information processing apparatus. The block diagram in the reservation process of a control part. The figure which shows the process data in an embodiment, and the list of pseudo data.

  Hereinafter, preferred embodiments to which the present invention is applied will be described. First, a common part in all the embodiments will be described, and a different part will be described in each embodiment. FIG. 1 is a block diagram of an information processing apparatus 101 to which the present invention can be applied. The information processing apparatus includes a processing unit 107 and has a function of providing processing data output from the processing unit 107 in response to a request from a request source. This will be described in detail below.

  Reference numeral 102 denotes a Clock signal (clock signal). Each functional unit of the information processing apparatus 101 is supplied with the clock signal 102, and operates with the detection of the rising edge as a trigger. Reference numeral 103 denotes a Request signal. When the request source (CPU 121 to 123) requests the information processing apparatus 101 to acquire processing data, the request source outputs (asserts to “1”) the signal. Reference numeral 104 denotes a response signal. When the request signal 103 is received from the request source, the response signal 104 is output (asserted to “1”) as a response. Reference numeral 105 is Response Data. This data is output at the same time when the response signal 104 is output to the request source.

  Reference numeral 106 denotes a control unit that controls the entire apparatus. It manages and controls the status of various functional units of the information processing apparatus 101. Details will be described later (described in FIGS. 3 and 4). Reference numeral 107 denotes a processing unit. Processing data that is a part having a unique function of the information processing apparatus 106 and that has an acquisition request from the request source is generated by the processing unit 107. The processing unit 107 outputs the status of the processing unit 107 (Unit Status signal 114) to the control unit 106. In this description, it is assumed that Unit Status outputs a status (Empty or Not Empty) indicating whether or not processing data is stored in the processing unit 107. When processing data (processing result) is transmitted to the outside of the processing unit 107 (FIFO Input Data 117), a processing data output notification signal (FIFO Input Enable signal 116) is also transmitted. The processing unit 107 is configured to accept an external status signal (FIFO Status signal 115) as a guideline for determining whether to generate processing data. Specific examples of the processing unit 107 will be described in the first to third embodiments.

  Reference numeral 108 denotes a FIFO unit. Process data (FIFO Input Data 117) is received from the processing unit 107. Further, in accordance with an instruction (FIFO Output Enable) from the control unit 106, the stored processing data is output (FIFO Output Data 119). The FIFO unit 108 has a function of outputting FIFO storage status information (FIFO Status signal 115). Specifically, one of the three states (1) Empty / (2) Not Empty (≠ Full) / (3) Full is output.

  Reference numeral 109 denotes an IF unit that functions as a receiving unit that receives a request and a response unit that responds. It has a function of receiving a processing data acquisition request from a request source and returning a response to the request source. The response unit 110 controls the response (Response signal 104). In addition, the IF unit 111 includes the register unit 111, and when the response signal 104 is output, data stored in the register unit 111 is output at the same time. The IF unit 109 has a function of outputting a data value (Reg Value 112) stored in the register unit 111. The IF unit 109 has a function of receiving data (Reg In Data 113) to be input to the register unit 111 from the outside of the IF unit 109.

  The processing of the IF unit 109 will be described in detail with reference to FIG. FIG. 4B is a flowchart showing the processing of the response signal 104 and the response data 105. Each signal / data undergoes a state change according to a predetermined condition when the clock signal 102 rises. Until the rising edge of the clock signal 102, the signal / data is held in the previous state (S409). When the clock signal 102 rises (Yes in S409), the state of the Request signal 103 is confirmed (S410). At this time, if the Request signal 103 is “1” (Yes in S410), the Response signal 104 is set to “1” and a response is returned. At the same time, the Response Data 105 outputs the data held in the register unit 111 (S411). When the Request signal 103 is not “1” (No in S410), the Response signal 104 is set to “0”, and at the same time, the Response Data 105 is set to High impedance (S412). This is to prevent damage to the device due to output collision even if the connection destination of the Response Data 105 outputs data. The above is the description of FIG. As can be easily understood from the above, since the I / F unit 109 always performs the process of S411 when the request signal 103 is “1”, the response signal 104 is output regardless of the presence or absence of the processing data. Set to '1' to return a response.

  Returning to the description of FIG. Reference numeral 110 denotes a switch unit. The switch unit 110 has a function of selecting and outputting data to be output to the register unit 111 in the I / F unit 109 based on an instruction (Data Select signal 120) from the control unit 106. The selection is made from processing data output from the processing unit 107 or pseudo data that is not processing data. The pseudo data is stored in the switch unit 110. In the information processing apparatus 101, when the processing unit 107 cannot generate processing data and the FIFO unit 108 does not contain processing data, the empty code (empty code) is output as pseudo data. . In addition, when there is no data in the FIFO unit 108, but processing is being performed in the processing unit 107, the Busy Code (busy code) is output as pseudo data. The above is the outline of the information processing apparatus 101.

  Next, a request source that makes a processing request to the information processing apparatus 101 will be described. Reference numerals 121, 122, and 123 denote CPUs. In this specification, a case where three CPUs are request sources to the information processing apparatus 101 will be described as an example. The CPUs 121 to 123 and the information processing apparatus 101 are connected by a bus 124. The above is the description regarding FIG.

  Next, the control unit 106 provided in the information processing apparatus 101 will be described. There are two main processes of the control unit 106. The first is the data output instruction from the FIFO, that is, the control of the FIFO Output Enable signal 118. The second is the selection of data to be input to the register unit 111, that is, the control of the Data Select signal 120. Each control is performed by monitoring the state of the data stored in the register unit 111, the processing unit 107, and the FIFO unit 108. That is, monitoring of Reg Value 112, Unit Status 114, and FIFO Status 115 is performed. The two processes will be described with reference to FIGS. 3 (a) and 3 (b).

First, the control of the FIFO Output Enable signal 118 will be described with reference to FIG. This figure is a flowchart showing the processing of the FIFO Output Enable signal 118. The FIFO Output Enable signal 118 also changes its state depending on a predetermined condition when the Clock signal 102 rises (Yes in S301). When all the conditions (1) to (3) described below are met on condition that the clock signal 102 has risen, the FIFO Output Enable signal 118 is set to “1”, and the processing data from the FIFO unit 108 is set. Is requested (S305). When any of the conditions (1) to (3) is not satisfied, the process data is not prompted to be output as “0” (S306). The conditions (1) to (3) will be described below.
(1) The FIFO Status signal 115 is not Empty (No in S302). When the FIFO Status signal 115 is Empty, the processing data cannot be taken out from the FIFO unit 108, so the processing data output is not requested.
(2) The Reg Value signal 112 is Empty or Busy (Yes in S303). If the Reg Value 112 is processing data that is neither Empty nor Busy, the data is already ready to be passed, so the data output to the FIFO unit 108 is not prompted. However, this is not the case for the case where it is desirable that the register unit 111 always contains the latest processing data from the processing unit 107 (described in the third embodiment).
(3) The FIFO Output Enable signal 118 is “0” (S304). If the FIFO Output Enable signal 118 is “1” before, the processing data has already been output from the FIFO unit 108, and the processing is stopped once. However, when the FIFO unit 108 accepts burst read, this is not the case when it is desirable to store the latest processing data in the register unit 111.

  The above is the control of the FIFO Output Enable signal 118. Next, the control of the Data Select signal 120 will be described with reference to FIG. The figure is a flowchart showing the processing of the Data Select signal 120. The state of the Data Select signal 120 also changes according to a predetermined condition when the Clock signal 102 rises (Yes in S311).

  First, the case where the FIFO Output Enable signal 118 is “1” (Yes in S312) will be described. At this time, since the processing data is output from the FIFO unit 108, the Data Select signal 120 is set to ‘0’ in order to store the processing data in the register unit 111.

  In the case of No in S312, the Data Select signal 120 can take a plurality of values depending on various conditions. When the current Data Select signal 120 is “0” and the Request signal 103 is “0”, the processing data is stored in the register unit 111 and is not output to the request source. . This means that it is not necessary to select and store the next processing data or pseudo data. Therefore, there is no need to switch the Data Select signal 120 (as a result, the Data Select signal 120 maintains “0”). In the case of No in S314, the value of the Data Select signal 120 differs depending on the state of the FIFO Status signal 115 and the Unit Status signal 114. If both states are Empty (Yes in S315), the Data Select signal 120 is set to '2' (S317). If either is not Empty (No in S315), the Data Select signal 120 is set to ‘1’ (S316). The above is the method for controlling the Data Select signal 120.

  The control method of the two signals, (1) FIFO Output Enable signal 118 / (2) Data Select signal 120, executed by the control unit 106 has been described above. How the data stored in the register unit 111 is changed by this control will be described with reference to FIG. This figure is a flowchart showing the processing of Reg Value 112 which is data stored in the register unit 111. The Reg Value 112 also changes its state depending on a predetermined condition when the Clock signal 102 rises (Yes in S401).

  First, processing is switched according to the state of the Request signal 103. When the Request signal 103 is “0” (No in S402) and the Reg Value 112 is neither Busy nor Empty (No in S405), the current processing data is held as it is. When the Request signal 103 is “1” or the Reg Value 112 is pseudo data (Busy or Empty), the process proceeds to the condition of S403. After S403, the Reg Value 112 is updated according to the value of the DataSelect signal 120. If the Data Select signal 120 is “0”, the processing data output from the FIFO unit 108 is present, so the Reg Value 112 is updated to the processing data output from the FIFO unit 108 (S404). When the Data Select signal 120 is “1” or “2”, the Reg Value 112 is updated to Busy (S407) or Empy (S408), respectively. The above is the processing of Reg Value 112. The configuration and processing in the main part of FIG. 1 excluding the processing unit 107 has been described above.

  Next, FIG. 5 shows a timing chart of main data / signals inside and outside including the request signal 103 which is a request from the request source. This figure shows how the signal / data in the outside and inside of the information processing apparatus 101 transition in time. Reference numeral 501 indicates the Clock signal 102 in FIG. 1, reference numeral 502 indicates the Request signal 103, reference numeral 503 indicates the Response signal 104, and reference numeral 504 indicates the Response Data 105. Reference numeral 505 denotes the Reg Value 112 in FIG. 1, reference numeral 506 denotes the Data Select signal 120, reference numeral 507 denotes the FIFO Output Data 119, and reference numeral 508 denotes the FIFO Output Enable signal 118. Reference numeral 509 corresponds to the FIFO Status signal 115 in FIG. 1, and reference numeral 510 corresponds to the Unit Status signal 114. When it is detected that the Request signal 103 is “1”, it is understood that the Response Data 105 is output together with the Response signal 104 immediately. Also, it can be seen that the state of Reg Value 112 is updated in the background depending on the value of Reg Value 112, regardless of the state of Request signal 103. It can be seen that the FIFO Output Data 119 and the Reg Value 112 are updated under the control of the Data Select signal 120 and the FIFO Output Enable signal 118.

  In this description, the register unit 111 is provided, and the FIFO unit 108 has been described using a FIFO that does not read the next cycle after outputting one clock cycle. However, the FIFO unit 108 may use a burst read, that is, the FIFO output enable signal 118 can output the processing data even if it becomes ‘1’ in a continuous clock cycle. In this case, the request signal 103 may be gated as necessary by the control unit 106 and directly input to the FIFO unit 108 as a FIFO Output Enable signal. By doing so, it is possible to provide the data output from the Response Data 105 with responsiveness regarding the state of the information processing apparatus 101 and the processing result.

[First Embodiment]
Next, a first embodiment will be described. In the present embodiment, a case where the information processing apparatus 101 is applied to an ID management apparatus will be described. Since the outline of the operation of the ID management apparatus has been described in the background art, it is omitted here. In order to apply the information processing apparatus 101 to the ID management apparatus, the processing unit 107 may be responsible for the main part of the ID management process. The processing unit 107 when applied to an ID management apparatus will be described in detail. FIG. 2 is an internal block diagram of the processing unit 107. In the case of accepting an ID release request from the request source, it is omitted because it is not the main part of the present invention.

  201 is a processing control unit. The FIFO Status signal 115 is monitored, and specific instructions are given to the processing search unit 204 and the ID operation unit 206. In addition, the internal status is transmitted to the outside by the Unit Status signal 114. Reference numeral 202 denotes a search unit. In response to an instruction from the processing control unit 201, the memory unit 204 is searched for an unused ID. A memory read operation necessary for the search is transmitted to the memory management unit 205. Further, the processing result is transmitted to the processing control unit 201. Note that the search unit 202 may have a function of checking the number of unused IDs. Reference numeral 203 denotes an ID operation unit. A process of outputting an unused ID to the outside, making the unused ID used, and a process of returning the unused ID to the unused state by the information from the processing control unit 201 for the ID requested to be released from the request source . Further, the processing result is transmitted to the processing control unit 201. A memory read / write operation necessary for the ID operation is transmitted to the memory management unit 205. Further, when the registered ID is output as processing data to the outside, the acquired memory value is transmitted to the conversion unit 210.

  Reference numeral 204 denotes a memory unit. Regarding the ID uniquely assigned to each memory area, which is a resource of the system, in each bit in the memory unit 204, the memory area indicated by the ID is unused (value is “1”) or used (value is “ 0 ′) is stored. One address is assigned 32 bits, and each bit position corresponds to an ID number. Therefore, 32 bits of Address 0x0000 — 0000 are for managing ID numbers “0” to “31”. 0b01000100_00000000_00000000_00010001 (the leading 0b indicates a binary number) is stored in the address “0x0000 — 0000”. Therefore, among ID numbers 0 to 31, four IDs are unused (the number of 1s is four). The 32 bits of Address 0x0000 — 0004 are for managing the subsequent IDs “32” to “63”. The same applies hereinafter. Thus, by associating the ID with each bit of each address, there is an effect that the memory can be reduced rather than managing by using the ID number as it is.

  Reference numeral 205 denotes a memory management unit. In response to an instruction from the search unit 202 or the ID operation unit 203, necessary memory access (Read / Write) is executed for the memory unit 204. The memory unit 204 is provided with an R / W signal 206 indicating the type of access as Read or Write, and a CS (Chip Select) signal 207 indicating the occurrence of access. Further, the memory unit 204 includes an address 208 indicating an access destination address and a memory data 209 in which data to be read / written appears.

  Reference numeral 210 denotes a conversion unit. As described above, since the memory unit 204 manages each ID by assigning it to the bit of each address, it is responsible for the process of converting the actual ID value and bit data into both. In addition, an interface for outputting the ID as processing data to the outside is provided. Specifically, the FIFO Input Enable signal 116 and the FIFO Input Data 117. The above is the processing outline of the processing unit 107 in the first embodiment. Thus, it has been described that the information processing apparatus 101 can be applied as an ID management apparatus by applying the processing unit 107 as an ID management processing function part.

[Second Embodiment]
In the first embodiment, the case where the information processing apparatus 101 is applied to an ID management apparatus has been described. In the first embodiment, the request source is not specified for a plurality of request sources, and if there is an ID that can be provided at the time of receiving the request, the value is provided as processing data. Provide status as pseudo data. In other words, it can be applied to a plurality of request sources. However, depending on the processing timing of the processing unit 107 and the request reception timing from the request source, the pseudo data is provided to the request destination that has been requested earlier, and the processing data is provided to the request destination that has been requested later. Can happen. Therefore, a method of accepting as a reservation when processing data cannot be provided to a request destination that has previously obtained an acquisition request (that is, pseudo data is provided) will be described.

  Reference numeral 601 in FIG. 6 denotes an information processing apparatus that supports reservation processing. A difference from the information processing apparatus 101 will be described.

  First, in order to deal with a reservation, the information processing apparatus 601 needs to specify a request source in order to determine which request source to make a reservation. Therefore, Req ID 602, which is a signal for specifying the request source, is used. A Req ID is assigned when a request signal 103 is issued from each request source (CPU 121 to 123). The Req ID 602 may be assigned by either the bus 603 or the request source (CPU 121 to 123). In the following description, the case where the Req ID 602 is applied will be continued. However, any method may be used as long as the request source can be basically identified. For example, when each request source issues the request signal 103 in advance, the address information is used if negotiations such as using different addresses for the areas specified in the read of the acquired data have been established. May be.

  Reference numeral 604 denotes an IF unit corresponding to the reservation. In order to respond to the reservation, since it is necessary to switch the Response Data 105 to be returned by requesting from which request source, a register is provided for each request source.

  Reference numeral 608 denotes a control unit corresponding to the reservation. In order to cope with the reservation, Req ID 602 and Reg1 Value / Reg2 Value / Reg3 Value which are data values stored in the respective register units 605 to 607 are received. In addition, for each of the register units 605 to 607, three Data Select signals are output in order to select data to be input to the register unit (612, 613, 614). Details of the control unit 608 will be described later. The information processing apparatus 601 includes three switch units 110 in order to correspond to each register unit. Each switch unit 110 operates according to a Data Select signal assigned to each switch unit 110 from the control unit 608. The above is the overall outline of the information processing apparatus 601.

  Next, details of the control unit 608 will be described with reference to FIG. A reservation function that is a large difference from the control unit 106 will be described here. Other parts are omitted because they can be applied as they are or with slight changes in the control unit 106.

  The control unit 608 has as many tags as the number of request sources. In FIG. 8, TAG1 (701), TAG2 (702), and TAG3 (703) are used for managing reservation processing of CPU1 (121), CPU2 (122), and CPU3 (123), respectively. Hereinafter, how the tag is used and the reservation process is performed will be described.

  Reference numeral 704 denotes a request source pool. If no reservation process is required, all tags are stored (recorded) in the request source pool 704. When reservation processing is necessary, that is, when a Reserve Request 706 is received, a tag associated with a request source that requires reservation is output from the To Do Tag 707 from the request source pool, and the reservation processing is started. . Note that nothing is done in particular when the requested tag from the reserve request 706 has already entered the reservation process and does not exist in the request source pool 704. When the reservation process is completed or when the reservation is no longer necessary, the corresponding tag is returned to the request source pool from Done Tag 711.

Reference numeral 705 denotes a reservation issuing unit. A Reserve Request 706 that is a reservation request is transmitted to the request source pool. A reservation request is issued under the following conditions. That is, when it is detected that the Request signal 103 is “1”, a reservation is established if the value of the register corresponding to the Req ID (602) is pseudo data. Specifically, when the acquisition request is detected, if the request source is identified as CPU1 (121) from the Req ID 602, and the Reg1 Value 609 of the register unit 1 (605) at that time is pseudo data, TAG1 (701) ) Is booked.
This information is transmitted to the reserve request 706.

  Reference numeral 708 denotes a reservation source FIFO. This is the place where the tag for which reservation processing is determined is stored first. It is used as a buffer when reservation processing is already in progress, and includes FIFOs corresponding to the number of stages (number of request destinations-1). When the tag of the reservation source register 710 is removed, or when the reservation source register 710 is empty, the Next Do Tag 709 transmits one of the tags stored in the reservation source register 703.

  Reference numeral 710 denotes a reservation source register. A tag for executing the reservation process is stored. In the figure, TAG3 (703) is stored. The reservation process is executed by the reservation control unit 712, and the process is performed with reference to the tag stored in the reservation source register 711.

  Reference numeral 712 denotes a reservation control unit. The request source to be reserved is confirmed based on the tag stored in the reservation source register 703. Then, a signal (Switch Select signal 715) for specifying to which switch unit 110 of which three switch units 110 the processing data from the FIFO unit 108 is propagated to the register unit is sent to the data select unit 716. Output. Further, the register unit 1 (605) to the register unit 3 (607) are monitored, and when it is confirmed that valid data is stored, the reservation is withdrawn. Further, the FIFO Output Enable signal 118 and the Switch Select signal 715 are monitored, and the reservation is canceled when it is determined that the reservation processing is completed. When canceling the reservation, a process of returning the tag stored in the reservation source register 710 to the request source pool is performed. The data selection unit 716 basically performs the process of FIG. 3B, but since the Data Select signal is three, three processes are performed. Whether there is a branch to the process of setting the Data Select of S313 to '0' depending on the use / unuse status of the Switch Select signal 715 and the output value at the time of use (which request source is performing the reservation process) Is changed. The above is the description of the reservation method in the second embodiment. In the first embodiment, application to an ID management device is taken as an example. However, the reservation method described in the second embodiment is not particularly applicable to an ID management device so far. It is clear in the explanation.

[Third Embodiment]
In the first embodiment and the second embodiment, the case where the present invention is applied to an ID management apparatus has been described. At this time, the processing data output from the processing unit 107 and the pseudo data generated by the switch unit 110 instead of the data from the processing unit 107 are as indicated by reference numeral 801 in FIG. In FIG. 8, ID values that can be managed by the ID management apparatus are 65535 examples in the range of 0 to 65535, but IDs that can be managed as long as the data allowed as ID values and the pseudo data do not overlap. The maximum number of values is applicable as a variable.

  Further, the present invention can be applied to devices other than the ID management device. For example, it can be applied to a timer device. Here, an example will be described in which a timer value is subtracted from a certain timer value set in the timer device until the time set in the timer is reached. Specifically, the processing unit 107 in FIG. 1 is a timer processing unit and has the following functions. The timer processing unit sets a preset timer value in the counter, and subtracts it until the counter value becomes zero every elapse of a certain time or a certain clock cycle. The timer processing unit outputs the count value every time the count value is updated. Due to the nature of the timer device, it is necessary to output a real timer value after receiving an inquiry. Therefore, the FIFO unit 108 is arranged in a single stage, or the FIFO unit is eliminated, and the processing unit 107 is directly connected to the data input unit of the switch unit 110. A configuration in which the output IF is connected is desirable. When the FIFO unit 108 is not installed, the FIFO Output Enable signal 118 may be input to the processing unit 107 and the processing unit 107 may prompt the processing data to be output. In addition, since it is desirable that the latest processing data is always included, even if the condition of S303 in FIG. 3 and processing data is included in the Reg Value 112, the condition that does not set the FIFO Output Enable to “0” may be deleted. Good.

  When the timer is not set, the switch unit 110 may be configured to output data representing Null Code to the register unit. Reference numeral 802 in FIG. 8 describes processing data and pseudo data when applied to the timer device. FIG. 8 shows that if the period of the Timer clock is 1 second, the timer device can measure a maximum time of 65535 seconds. Similar to the ID management apparatus, it is possible to handle a larger counter value by setting the switch unit 110 and the processing unit 107 so that the pseudo data and the processing data do not overlap.

  Furthermore, the present invention can be applied to an apparatus that performs random number generation processing. Here, it is assumed that the processing unit 107 is a random number generator and has a function of outputting to the FIFO unit 108 every time a random number is generated. If the random number generator is configured to generate a random number until the FIFO unit 108 becomes Full, data can be stored as long as processing data remains in the FIFO unit 108 even if the request timing from the request source continues. It is possible to provide a random number without running out. Reference numeral 803 in FIG. 8 describes processing data and pseudo data when applied to a random number generator. In the example of FIG. 8, this random number generator indicates that random numbers from 0 to 65535 can be generated. In addition, during the calculation of the random number, the Busy Code is output.

  Similar to the ID management apparatus, it is possible to handle a larger counter value by setting the switch unit 110 and the processing unit 107 so that the pseudo data and the processing data do not overlap.

  Here, in addition to the ID management device, an application example of the present invention is shown with respect to a timer device and a random number generation device. However, the present invention is not particularly limited to these applications. In other words, any processing that the information processing apparatus is responsible for is applicable as long as it provides processing data from the processing unit 107 based on a data acquisition request from a request source.

Claims (8)

An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit ;
The memory unit notifies the control unit of a storage state of the processing data;
The control unit controls whether to cause the response unit to transmit a response signal including the processing data to the request unit or to transmit a response signal including the predetermined value to the request unit based on the storage state. An information processing apparatus characterized by: An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit;
In the first case where there is no processing data to be output to the processing unit and no processing data is stored in the memory unit, the response unit has processing data to be output to the processing unit. and, between the case where the second processing data in the memory unit is not stored, information processing apparatus a response signal including a different value and transmits to the requesting unit. The response unit, according to claim 2 wherein, when the first transmits a response signal including a value indicating empty, in the case of the second, characterized in that the transmitting the response signal including a value indicating the busy The information processing apparatus described in 1. An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit;
Wherein the processing unit, in accordance with the storage state of processing data in the memory unit, information processing apparatus and executes the predetermined processing. An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit;
Wherein the predetermined processing, timer processing, or information processing device which is a process that generates random numbers. An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit;
Wherein the processing unit is further to each of the plurality of memory areas, in use, or, a bit indicating that it is not used, information which is characterized in that correspondingly manages the ID indicating the memory area Processing equipment. An information processing apparatus,
A processing unit for executing a predetermined process;
A memory unit that is connected to the processing unit and stores processing data obtained by the predetermined processing by the processing unit;
Connected to a bus that operates when a clock signal is supplied, and a request unit that requests the processing data;
When the processing data is requested by the request unit when connected to the bus and the processing data is stored in the memory unit, a response signal including the processing data is transmitted to the request unit, A response unit that transmits a response signal including a predetermined value to the request unit instead of the process data when the processing data is not stored in the memory unit;
It said request unit, information processing apparatus characterized by including a plurality of CPU. The memory unit, FIFO, or the information processing apparatus according to any one of claims 1 to 7, characterized in that it comprises one of the registers.

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