JP6209892B2 - Timing adjustment program for competition test, timing adjustment method for competition test, and timing adjustment apparatus for competition test - Google Patents

Description

  The present invention relates to a competitive adjustment timing adjustment program for a semiconductor device, a competitive adjustment timing adjustment method, and a competitive adjustment timing adjustment apparatus.

  A semiconductor device such as an LSI verifies a logic circuit described in a hardware description language using a function verification device. As one of the function verifications, there is a competition verification of LSI internal signals due to timing dependency of a plurality of signals.

  In the conflict verification, for example, there is a technique for checking whether a condition to be conflicted among conditions generated during a simulation in which a plurality of programs operate in parallel is referred to by referring to a table in which the condition for the conflict is registered. In this technique, simulation execution is stopped when some conditions are matched, and simulation execution is restarted when all conditions are matched (see, for example, Patent Document 1 below).

Japanese Patent Laid-Open No. 11-236002

  However, in the conventional technology, it is difficult to grasp all the time differences for each of the multiple data paths at the time of verifying the conflict at the competitive point located deeper from the data input side, and the conflict verification is difficult. It took time and effort.

  For example, in order to confirm the arbitration operation (priority output) of the competition point (arbiter) inside the core as a competition point, verification when two signals (data 1 and data 2) are simultaneously input to this arbiter I do. At this time, the time required to reach the competition point (arbiter) may be different between the two data respectively input from the outside to the core. For example, when a predetermined event occurs in a circuit block (for example, a flip-flop (FF)) before a competing point (arbiter) on two data paths, until a request reaches the competing point (arbiter) that needs to be verified. The (delay) time will be different.

  FIG. 10 is a diagram for explaining the occurrence of competition. The horizontal axis represents time, and the vertical axis represents two data (data 1 and data 2). First, as shown in (a), it is assumed that data 1 and 2 are input simultaneously (time t = 0). It is assumed that the time until the request for the arbiter at this time is t = 1 for data 1 and t = 2 for data 2. In this case, the request time difference Δ between the data 1 and 2 is confirmed by a waveform or the like. Thereafter, as shown in (b), if the input timing of data 2 is delayed by an amount corresponding to the time difference Δ, requests for data 1 and 2 can compete at the competition point (arbiter).

  However, even if the input timing shown in (b) is delayed, the request timings of the data 1 and 2 may not compete at the competition point (arbiter). For example, as shown in (c), even if the time difference Δ is given to the data 2 and input, the time until the request is actually generated at the competing point (arbiter) becomes t = 2 ′ and the expected t = May differ from 2.

  This difference is caused by integration of delay amounts based on occurrence of a predetermined event in a plurality of circuit blocks (FF) on the data path. Conventionally, the verification apparatus updates the time difference Δ to determine whether the competition condition is satisfied by a predetermined number of times without grasping the order control of individual circuit blocks (FF) on a large-scale LSI. . When the competition condition by the verification device is not satisfied, the designer needs to manually update the time difference Δ, and it takes time and effort to converge to the competition condition. In addition, even if it is performed manually, the result may not converge to the competition condition.

  Here, since there are an enormous number of circuit blocks (FF) on the data path, it is difficult to grasp all the delay amounts for the operation of each circuit block, and the timing of contention at the contention point (arbiter) is difficult. There is a demand for a concrete solution on how to adjust the optimum. At a competition point (arbiter) at a deep position in the data path as viewed from the data input side, there are a number of blocks in front, and it is difficult to obtain an input timing at which a plurality of data compete.

  In one aspect, an object of the present invention is to optimally adjust the contention timing at an arbitrary contention point of a plurality of data.

  In one proposal, by specifying a pair of events to be competing, a plurality of the transactions related to the pair of events are selected for each set based on the transactions and events of the input of the semiconductor device, and the selected set The input timing of one transaction is adjusted so that the times of the pair of events included in the transaction of the other transaction match, and the time of the other event included in the one transaction whose input timing is adjusted is the other transaction. As a timing adjustment result for a pair of events for which a set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are made to conflict with each other Output.

  According to one embodiment, it is possible to optimally adjust the contention timing at an arbitrary contention point of a plurality of data.

FIG. 1 is a block diagram illustrating functions of the competition test timing adjusting apparatus according to the embodiment. FIG. 2 is a chart showing event table information stored in the event table. FIG. 3 is a flowchart illustrating an example of a processing procedure for generating an event table. FIG. 4 is a chart for explaining an example of selecting a transaction for generating a conflict scenario. FIG. 5 is a flowchart illustrating an example of a transaction selection process for generating a conflict scenario. FIG. 6 is a flowchart illustrating an example of a conflict scenario generation process. FIG. 7 is a block diagram illustrating an example of a hardware configuration of the competition test timing adjustment device. FIG. 8 is a diagram showing an arrangement example of the competition test timing adjusting device. FIG. 9 is a diagram illustrating an example of timing conflict at a competition point. FIG. 10 is a diagram for explaining the occurrence of competition.

(Embodiment)
Hereinafter, preferred embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating functions of the competition test timing adjusting apparatus according to the embodiment. The competition test timing adjustment apparatus 100 includes an event table generation unit 101, an event table 102, and a competition scenario generation unit 103.

  The event table generation unit 101 generates an event based on information (Tr1, Tr2,..., Trn) 110 on a set of input transactions for the core and internal event list information (Ev1, Ev2,..., Evm) 111 inside the core. Table information 112 is generated and stored in the event table 102. The internal event list information 111 includes an event to be competed (competition target) at a competition point (arbiter or the like) inside the core.

  The conflict scenario generation unit 103 generates the conflict scenario information 121 for the event to be competed based on the event table information 112 stored in the event table 102 and the designation input of the event set information 113 to be competed. To do. The event set information 113 to be competed is prepared as a subset from the internal event list information 111 and can be designated and input. For example, when the competing point is a predetermined block (for example, arbiter) in the core, a pair of blocks (for example, FF) that outputs a request (Req) to this block (arbiter) is designated as event set information. Is done.

(About event table generation)
FIG. 2 is a chart showing event table information stored in the event table. The event table generation unit 101 performs simulation execution of a plurality of transactions (Tri) in the input transaction set information 110 using a simulator. When this simulation is executed, the event table generation unit 101 stores, in the event table 102, event table information 112 that lists times (Tk) at which events (Evj) registered in the internal event list information 111 occur. In the event table information 112, the vertical axis stores each transaction Tri, and the horizontal axis stores each event Evj for each time Tk (time elapses in the right direction).

  For example, each event Evj corresponds to each FF on the data path inside the core. In FIG. 2, for example, when the transaction Tr3 indicated by 112a in the figure is executed, the events Ev1, Ev3 do not occur, and the times when the events Ev2, Ev4, Ev5 occur are T = 50, 80, 100, respectively. Is shown.

  FIG. 3 is a flowchart illustrating an example of a processing procedure for generating an event table. The generation contents of the event table information 112 performed by the event table generation unit 101 will be described. First, the event table generation unit 101 sets an initial value i = 0 of the transaction Tri execution (step S301). Next, the event table generation unit 101 causes the simulator to execute the transaction Tri indicated by the input transaction set information 110 (step S302).

  Thereafter, the event table generation unit 101 records the time (Tk) at which the event (Evj) registered in the internal event list information 111 occurs in the corresponding event (Evj) in the event table information 112 (step S303). . Then, the variable i is incremented.

  Then, the event table generation unit 101 determines whether the simulation execution of the n last transactions (Trn) has been completed (i <n) (step S304). If there is an unexecuted transaction (step S304: No), the process returns to step S302. If all the transactions have been executed (step S304: Yes), the process of generating the event table information 112 is terminated.

(About generation of competitive scenarios)
The conflict scenario generation unit 103 performs the following processes (1) and (2).
(1) Time adjustment for simultaneous occurrence of competing events and assignment of transaction group priorities. In this process, based on the event table information 112, all transaction pairs in which an event to be competed at a competition point occurs are generated. Then, the start time of the transaction is determined so that the events to be competed with each other occur simultaneously. Also, due to the possibility of competition of other events, a priority is given to the generated transaction set.

(2) Confirmation of the presence or absence of conflict by simulation execution of each combination of transactions in order of priority given in (1) above, and generation of a conflict scenario. In this process, the conflict scenario generation unit 103 confirms whether or not competition actually occurs at the competition point by executing simulation by the simulator in order of priority for each combination of transactions, and determines the combination where the conflict has occurred. A scenario 121 is output.

(1: Explanation of processing contents of time adjustment for simultaneous occurrence of conflict events and assigning priority of transaction pairs)
FIG. 4 is a chart for explaining an example of selecting a transaction for generating a conflict scenario. A processing example performed by the competitive scenario generation unit 103 will be described using an example of the event table information 112 similar to FIG. Here, it is assumed that a set of events to be competed at a competition point (arbiter or the like) is Ev4 and Ev5.

  First, as shown in (a), the conflict scenario generation unit 103 (1) searches for a transaction Tr that generates the event Ev4. Then, (2) the transaction Tr1 including the event Ev4 is selected. Thereafter, (3) a transaction that generates the event Ev5 is searched, and the transaction Tr2 is selected.

  Thereafter, as shown in (b), (4) the time at which the event Ev4 (T = 50) of the selected transaction Tr1 and the event Ev5 (T = 80) of the transaction Tr2 are simultaneously generated is determined. In this case, the conflict scenario generation unit 103 determines that the start time of the transaction Tr1 is +30 based on the difference Δ between the times of the transactions Tr1 and Tr2.

  Thereafter, as shown in (c), (5) the time of event Ev2 of transaction Tr1 becomes 50 (20 + 30), which is the same as time 50 of event Ev2 of transaction Tr2. As a result, arbitration due to competition in the event Ev2 works, and there is a possibility that the processing of either the transaction Tr1 or Tr2 is awaited (delay occurs).

  Since the occurrence of the event Ev2 is a position before the events Ev4 and Ev5 to be made to compete (before the data path), the contention scenario generation unit 103 determines that the events Ev4 and Ev5 are simultaneously generated as a result of the arbitration in the event Ev2. Judge that it may not occur (compete). In such a case, the conflict scenario generation unit 103 sets the combination of the transactions Tr1 and Tr2 to a low priority.

  Then, as shown in (d), (6) the priority of the other transaction Tr2 when combined with one transaction Tr1 is lowered, and the storage order of the table is lowered accordingly. Thereafter, (7) the conflict scenario generation unit 103 searches for the transaction Tr that generates the event Ev5 again, and (8) selects the transaction Tr3.

  Thereafter, it is determined when to simultaneously generate the event Ev4 (T = 50) of the selected transaction Tr1 and the event Ev5 (T = 100) of the transaction Tr3. In this case, the conflict scenario generation unit 103 determines that the start time of the transaction Tr1 is +50 based on the difference Δ between the times of the transactions Tr1 and Tr3.

  In this case, as shown in (e), for the transaction Tr1, (9) the start time of the event Ev2 is 70 (20 + 50), and since it is different from the time 50 of the transaction Tr3, it is determined that they do not occur at the same time (no conflict). Also, (10) it is determined that the event Ev3 does not occur simultaneously because there is no event on the transaction Tr3 side. (11) The start time of the event Ev4 is 100 (50 + 50), which is different from the time 80 of the transaction Tr3. Therefore, it is determined that they do not occur at the same time (no conflict).

  As described above, the conflict scenario generation unit 103 sets (12) the combination of the transactions Tr1 and Tr3 as a high priority.

  Thereafter, the competition scenario generation unit 103 confirms whether or not competition actually occurs at the competition point by executing simulation with the simulator for each combination of transactions, and outputs the combination in which competition has occurred as the competition scenario 121. To do. At this time, the simulation is performed with priority given to the combination of the event Ev4 of the high priority transaction Tr1 and the event Ev5 of the transaction Tr3 shown in FIG.

  FIG. 5 is a flowchart illustrating an example of a transaction selection process for generating a conflict scenario. The processing contents performed by the competition scenario generation unit 103 shown in the processing example of FIG. 4 will be described. In the following processing, a set of transactions including an event to be conflicted is selected, and a set of transactions that do not cause a conflict for a plurality of other (other than the competition points) events included in the set of transactions is selected. . The conflict scenario generation unit 103 changes and reads the transaction set from the event table information 112 of the event table 102, and performs the following processing for each transaction set.

  First, the conflict scenario generation unit 103 reads the event table information 112 of the event table 102 and selects a transaction Tri including the event Evj at the conflict point (step S501). Next, it is determined whether or not all the events Evj included in the selected transaction Tri have been extracted (step S502). If there is an unextracted portion remaining (step S502: No), the remaining events Evj are extracted (step S503). ), The process returns to step S501. If all have been extracted (step S502: Yes), the process proceeds to step S504.

  Through the processing in steps S501 to S503, all the events Evj of all the transactions Tri included in the event table information 112 are extracted. The extracted information is held in a memory (not shown). For example, in the example shown in FIG. 4A, each event Ev included in the transactions Tr1 to Tr3 is extracted.

  In the following processing, the conflict scenario generation unit 103 adjusts the timing (time) for each pair of transactions Tri for all transactions Tri including a plurality of events Evj that cause a conflict at the conflict point, and performs the conflict. Check for conflicts in events other than points.

  First, the conflict scenario generation unit 103 selects a set of transactions Tri (step S504). For example, the transactions Tr1 and Tr2 shown in FIG. 4 are selected. Next, an event Evj having the maximum time Tij is searched for from the selected set of transactions Tri (step S505). The event at the time Tij of the maximum value indicates contention in a block (such as an arbiter) located at the innermost part in the data path on the core. For example, in the example shown in FIG. 4B, the maximum time Tij of the pair of transactions Tr1 and Tr2 is 80.

  In this example, the maximum value of the time is searched for as the block with the competition point located farthest, but the competition point is set to an arbitrary block in front of the data path and the corresponding time is searched. It is good.

  Next, the conflict scenario generation unit 103 changes the start time of one transaction Tri of the selected set of transactions Tri (step S506). At this time, the competition scenario generation unit 103 obtains a difference Δ at which the time at the competition point in the set of transactions Tri is the same, and adds the difference Δ to the start time of one transaction Tri. For example, in the example shown in FIG. 4C, 30 is added as the difference Δ to the start time of the transaction Tr1.

  Next, the conflict scenario generation unit 103 adds the difference Δ to the time of each event Evj included in the transaction Tri to which the difference Δ is added (step S507). In the example shown in FIG. 4C, a difference Δ of 30 is added to the time of each event Ev2, Ev3, Ev4 of the transaction Tr1.

  Next, the conflict scenario generation unit 103 performs processing for confirming whether or not there is a conflict in each event Evj in the selected pair of transactions Tri. At this time, the confirmation processing is performed on condition that the times of the event Evj corresponding to the desired competition point coincide and the times in the other events Evj do not coincide.

  The process of step S508 is a process of updating a set of transactions Tri, but the conflict scenario generation unit 103 selects the set of transactions Tri selected in step S504 for the first time (step S508).

  In the subsequent processing, the set of transactions Tri that competes at the competition point is changed by incrementing the variable k. That is, since there is a possibility that there are a plurality of data inputs for the competition point (arbiter), not only one set, a plurality of sets of transactions Tri corresponding to the plurality of data inputs are sequentially selected. For example, in the example of FIG. 4, after the set of transactions Tr1 and Tr2, the transaction Tr3 is selected without changing the transaction Tr1, and the transactions Tr1 and Tr3 are set as one set.

  After step S508, the conflict scenario generation unit 103 determines whether or not the time Tij in each event Evj is inconsistent for one set of transactions Tri (step S509). For example, in the example shown in FIG. 4C, it is determined whether the transactions Tr1 and Tr2 have different times in the events Ev2, Ev3, and Ev4.

  As a result, when the time coincidence occurs in the event Evj (step S509: No), the conflict scenario generating unit 103 lowers the priority of the corresponding transaction Tri and changes the position to the lowest level of the event table information 112. (Step S510). For example, as shown in FIG. 4D, the priority of one transaction Tr2 of one set of transactions Tri is lowered and the position is changed to the lowest level of the event table information 112. As a result, in the event table information 112, a transaction Tri having a higher priority is stored in the upper stage.

  Next, the conflict scenario generation unit 103 changes one transaction of the set of transactions Tri to a new transaction Tri (step S511). At this time, the transaction selects the transaction including the event (time) at the competition point. In the example of FIG. 4D, the transaction Tr3 is selected as the new transaction Tri, and the transactions Tr1 and Tr3 become a new set of transactions.

  Next, the conflict scenario generation unit 103 confirms whether or not the timing adjustment process using the new set of transactions Tri has been executed (step S512). If it is an unexecuted group (step S512: No), the process returns to step S509, but if it is already executed (step S512: Yes), as a result of timing adjustment in all combinations of transactions Tri, Therefore, it is determined that the timing adjustment (following competition scenario creation) is impossible (step S513), and the above timing adjustment processing is terminated.

  In step S509, when the time mismatch in the event Evj is confirmed (step S509: Yes), the conflict scenario generation unit 103 determines whether there is another set of transactions Tri at the conflict point (step S509). S514). If another set of transactions Tri remains (step S514: Yes), the conflict scenario generation unit 103 increments the variable k (step S515), returns to step S508, and uses a new transaction Tri + k. Timing adjustment processing is performed in one set of transactions.

  On the other hand, when there is no other set of transactions Tri (step S514: No), the competitive scenario generation unit 103 is effective in timing adjustment for all sets of transactions Tri at the competition point, and creates subsequent competitive scenarios. The timing adjustment process is terminated.

(2: Confirmation of the occurrence of conflict by simulation execution of each combination of transactions in order of priority and explanation of processing for generating a conflict scenario)
FIG. 6 is a flowchart illustrating an example of a conflict scenario generation process. The processing content performed by the competition scenario generation unit 103 will be described. 6, the conflict scenario generation unit 103 executes the processing shown in FIG. 5 and causes the simulator to execute a conflict simulation for each selected set of transactions. Then, a combination of transactions in which competition occurs is generated as a competition scenario.

  First, the conflict scenario generation unit 103 performs initial setting (step S601). The transaction Tr1 is d1, and the other transactions Tr2 and subsequent are d2 to dn. In addition, the flag is set to an initial value (0). The flag is changed to 1 when the event start time is changed.

  Next, the competitive scenario generation unit 103 outputs a combination of the transactions d1 to dn to the simulator and executes a simulation (step S602). At this time, by the selection process described with reference to FIGS. 4 and 5, a set of transactions having a high priority is first selected, and the simulation is executed by the simulator. Then, the competition scenario generation unit 103 determines whether the simulation result actually satisfies the competition condition in a desired pair of events (step S603).

  When a simulation result that actually satisfies the competition condition is obtained by executing the simulation (step S603: Yes), the competition scenario generation unit 103 determines that the competition test timing adjustment is successful. Then, the conflict scenario generation unit 103 generates a conflict scenario indicating information on the combination of transactions executed in step S602 (step S604), and ends the process.

  On the other hand, in the case of a simulation result in which the competition condition is not satisfied by the simulation execution (step S603: No), the competition scenario generation unit 103 determines each event for the transaction d (d2 to dn) other than one transaction d1 of each combination. A predetermined time difference Δ is added to Evj (step S605). As described above, the start time of the event Evj is changed by the time difference Δ.

  Next, the competition scenario generation unit 103 determines whether the flag is 1 (step S606). If the flag is not 1 (step S606: No), the flag is changed to 1 in response to the change of the start time (step S607), the process returns to step S602, and the processes after step S602 are executed again. If the competition condition is satisfied by executing the simulation after changing the start time (step S603: Yes), it can be determined that the timing adjustment is successful (step S604). The processing in steps S602 to S607 is equivalent to the existing conflict timing verification.

  On the other hand, if the flag is 1 in step S606 (step S606: Yes), the assertion generation unit provided in the competitive scenario generation unit 103 generates an assertion (step S608). This assertion is information on a set of possible conflicts in each event. For example, (e1 |->! E2) || (e1 |->! E3) ... (e1 |->! En) It includes information related to each request (Req) from each event e1, e2,. Then, this assertion is passed to the formal verification tool, and formal analysis at the time of simulation by the simulator is executed (step S609). The formal verification tool returns to the competitive scenario generation unit 103 whether or not the assertion has been proved as the analysis result.

  Then, when the assertion is proved (step S610: Yes), the competition scenario generation unit 103 proceeds to step S612. When the assertion is not proved (step S610: No), the conflict scenario generation unit 103 selects the next highest priority transaction pair (step S611: Yes), and returns to step S601.

  In step S611, when there is no next highest priority transaction set (step S611: No), the process proceeds to step S612. In step S612, it is determined that a conflict scenario cannot be generated and has failed (step S612), and the above-described conflict scenario generation process ends.

(Hardware configuration of competitive timing adjustment device)
FIG. 7 is a block diagram illustrating an example of a hardware configuration of the competition test timing adjustment device. In FIG. 7, the competition test timing adjustment device 700 includes a CPU 701, a read-only memory (ROM) 702, and a random access memory (RAM) 703. Further, a storage unit 704 such as a semiconductor memory or a disk drive, a display 708, a communication interface (I / F) 709, a keyboard 710, a mouse 711, a scanner 712, and a printer 713 may be provided. These CPU 701 to printer 713 are connected by a bus 714.

  The CPU 701 is an arithmetic processing unit that performs overall control of the competitive test timing adjustment apparatus 700. The ROM 702 is a non-volatile memory that stores a competition test timing adjustment program of the competition test timing adjustment apparatus 700. A RAM 703 is a volatile memory used as a work area when the CPU 701 executes arithmetic processing.

  The communication interface 709 serves as an internal interface with the network 715 and controls data input / output from an external device. Specifically, the communication interface 709 is connected to a local area network (LAN), a wide area network (WAN), the Internet, or the like, which becomes the network 715 through a communication line, and is connected to another device via the network 715. As the communication interface 709, for example, a modem or a LAN adapter can be employed.

  The display 708 is a device that displays data such as a cursor, an icon, or a tool box, a document, an image, function information, and the like regarding a setting screen for timing adjustment processing for competition test and a timing adjustment result. As the display 708, for example, a Thin Film Transistor (TFT) liquid crystal display, a plasma display, an organic EL display, or the like can be employed.

  The competition test timing adjustment function (event table generation unit 101, competition scenario generation unit 103) described with reference to FIG. 1 described above is executed by the CPU 701 illustrated in FIG. It can be obtained through execution processing.

(Figure showing layout of competitive test timing adjustment device)
FIG. 8 is a diagram showing an arrangement example of the competition test timing adjusting device. As an interface between the formal verification tool 801 and the simulator 802, the competition test timing adjustment apparatus 100 (competition scenario generation unit 103) is arranged.

  As described above, the conflict scenario generation unit 103 receives information on a set of events (for example, Ev4 and Ev5) to be competed at the competition point in order to confirm the competition at the competition point. The conflict scenario generation unit 103 generates a transaction set corresponding to the event based on the information on the event set by the processes (1) and (2) described above. Then, the timing adjustment for the transaction data d1... Dn is updated so that the events that are desired to compete at the competition point occur simultaneously.

  This update is executed by the data input sequence update processing unit 103a of FIG. 8, adjusts the timing to the simulator 802, and outputs the updated transactions d1. The simulator 802 returns simulation results t1 to tn to the data input sequence update processing unit 103a.

  Further, the assertion generation unit 103b creates an assertion and outputs it to the formal verification tool 801. The formal verification tool 801 returns the formal analysis result to the assertion generation unit 103b.

  Then, the conflict scenario generation unit 103, based on the responses from the data input sequence update processing unit 103a and the assertion generation unit 103b, simultaneously causes an event to be competed at the competition point, and other events (more than the competition point). A conflict scenario for avoiding a conflict in a block on the previous data path is generated and output. The conflict scenario is output to the simulator 802, and describes a competing data input sequence for the simulator 802 in text or the like.

(Example of timing conflict at the competition point)
FIG. 9 is a diagram illustrating an example of timing conflict at a competition point. A plurality of data paths are arranged in the core 901, and a plurality of blocks (FF1 to FFn) on the data path 1 (902a) and a plurality of blocks (FF1 to FFm) on the data path 2 (902b) are arranged. ing. Assume that an arbiter 903 is arranged as a block at the back as viewed from the input side of these data paths 1 and 2. In order to verify the operation at the time of data input competition in the arbiter 903, it is necessary to simultaneously generate requests (Req) from FFn and FFm immediately before the arbiter 903.

  Therefore, the test bench 910 adjusts the input timing of the driver 1 (911a) and the driver 2 (911b) that input data to the data paths 1 and 2. The test bench 910 includes the formal verification tool 801, the simulator 802, and the competition test timing adjustment apparatus 100 (competition scenario generation unit 103) described above. Then, data is input with the timing adjusted optimally by the competitive scenario generation unit 103, and the arbiter 903 can simultaneously generate requests (Req) from the immediately preceding FFn and FFm.

  As a result, even a block such as the arbiter 903 located at the back of the core 901 can generate a conflict, and the operation of the block when the conflict occurs (arbiter operation of the arbiter 903) can be monitored. It becomes possible to confirm. If an arbitrary block (event) on the data path is designated and input to the competition test timing adjusting device, the operation at the time of competition can be confirmed in the same manner.

  Further, the maximum time among the events of the input transaction may be extracted and a block in which a pair of events are input may be specified. Then, referring to the event table 112, it is possible to automatically search for a competition point using a block (for example, arbiter 903) located at the innermost part of the data path as a competition point. As a result, it is possible to omit the designation input of a pair of events to be made to compete.

  According to the embodiment described above, it is possible to adjust the input timing of a transaction so that events to be competed at a competition point can occur simultaneously. At this time, it is confirmed whether or not there is contention in an event other than the contention point in the transaction whose input timing is adjusted. As a result, it is possible to confirm the possibility of occurrence of a delay due to the occurrence of an event in the preceding block on the data path other than the competition point, and it is possible to optimally adjust the input timing of the event desired to compete at the competition point.

  As a result, when the transaction input timing (start time) is simply delayed, the timing of the competition is shifted at the competition point due to the occurrence of an event in another block, and no competition occurs. Can be avoided. Then, a competition timing test (competition verification) can be performed by using a transaction in which an event to be competed at a competition point occurs simultaneously.

  The program described in this embodiment can be realized by executing a program prepared in advance by a computer. The program is recorded on a computer-readable recording medium such as a semiconductor memory, a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be distributed through a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) In a competition test timing adjustment program for adjusting a competition timing for competing internal signals of a semiconductor device with an arbitrary event,
On the computer,
By specifying a pair of events to be competed, a plurality of transactions related to the pair of events are selected for each set based on the input transaction of the semiconductor device and the event,
Adjusting the input timing of one transaction so that the times of the pair of events included in the selected set of transactions match,
Determine whether the time of the other event included in one transaction whose input timing is adjusted does not match the time of the same event included in the other transaction,
A set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are output as a timing adjustment result for a pair of events desired to compete,
A competitive test timing adjustment program characterized by causing a process to be executed.

(Additional remark 2) The event table which linked | related the transaction of the input of the said semiconductor device, and the said event is produced | generated,
The competition test according to appendix 1, wherein a plurality of transactions related to the pair of events are selected for each set with reference to the event table based on a pair of events to be competed Timing adjustment program.

(Supplementary note 3) The competition test timing adjustment program according to supplementary note 1 or 2, wherein a low priority is assigned to the one transaction in which a match has occurred as the determination result.

(Supplementary note 4) After a match has occurred as a result of the determination, it is determined that the timing adjustment for the pair of events is impossible when the transaction pair related to the pair of events does not remain. The timing adjustment program for competitive test according to any one of appendices 1 to 3.

(Supplementary note 5) The competitive test timing adjustment program according to any one of supplementary notes 2 to 4, wherein the simulator executes the transaction and records the time when the event occurs in the event table.

(Appendix 6) The simulator outputs a plurality of sets of transactions obtained from the timing adjustment result,
Based on the simulation result of the simulator, when a competition condition in the pair of events is satisfied, information on timing adjustment for the pair of events is output as a competition scenario.
The timing adjustment program for competitive test according to any one of appendices 1 to 5, characterized in that:

(Supplementary note 7) The contention test according to any one of Supplementary notes 2 to 6, wherein the one transaction for which a match has occurred as a result of the determination is changed to a storage location having a low priority in the event table. Timing adjustment program.

(Supplementary note 8) The input timing of one transaction is adjusted so that the time of the event having the maximum time among the times of the pair of events included in the selected pair of transactions is matched. The timing adjustment program for competitive test according to any one of appendices 1 to 7.

(Supplementary Note 9) In a competitive test timing adjustment method for adjusting a competitive timing for competing internal signals of a semiconductor device with an arbitrary event,
Computer
By specifying a pair of events to be competed, a plurality of the transactions related to the pair of events are selected for each set based on the input transaction of the semiconductor device and the event,
Adjust the input timing of one transaction so that the times of the pair of events included in the selected set of transactions match,
Determine whether the time of another event included in one transaction whose input timing has been adjusted does not match the time of the same event included in the other transaction,
Outputting as a timing adjustment result for a pair of events for which a set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are to be made to compete with each other;
A timing adjustment method for competitive testing, characterized by executing processing.

(Supplementary Note 10) In a competitive test timing adjusting device for adjusting a competitive timing for competing internal signals of a semiconductor device with an arbitrary event,
An event table in which the semiconductor device input transaction is associated with the event;
Based on the input of a pair of events to be competed, referring to the event table, select a plurality of the transactions related to the pair of events for each set,
Adjust the input timing of one transaction so that the times of the pair of events included in the selected set of transactions match,
Determine whether the time of another event included in one transaction whose input timing has been adjusted does not match the time of the same event included in the other transaction,
A conflict scenario generation unit that outputs as a timing adjustment result for a pair of events for which a set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are to be made to compete with each other;
A timing adjustment device for competitive test, comprising:

(Additional remark 11) The event which produces | generates the said event table which linked | related the transaction of the input of the said semiconductor device and the said event by making the simulator perform the said transaction and recording the time when the said event occurred in the said event table Table generator,
The timing adjustment device for competitive test according to appendix 10, further comprising:

DESCRIPTION OF SYMBOLS 100 Competition adjustment timing adjustment apparatus 101 Event table production | generation part 102 Event table 103 Competitive scenario production | generation part 901 Core 903 Arbiter 910 Test bench

Claims (10)

In the competition test timing adjustment program that adjusts the competition timing to compete the internal signal of the semiconductor device at any event,
On the computer,
By specifying a pair of events to be competed, a plurality of transactions related to the pair of events are selected for each set based on the input transaction of the semiconductor device and the event,
Adjusting the input timing of one transaction so that the times of the pair of events included in the selected set of transactions match,
Determine whether the time of the other event included in one transaction whose input timing is adjusted does not match the time of the same event included in the other transaction,
A set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are output as a timing adjustment result for a pair of events desired to compete,
A competitive test timing adjustment program characterized by causing a process to be executed. Generating an event table associating the input transaction of the semiconductor device with the event;
2. The contention test according to claim 1, wherein a plurality of the transactions related to the pair of events are selected for each set with reference to the event table based on an input of a pair of events to be conflicted. Timing adjustment program.   The competitive adjustment timing adjustment program according to claim 1, wherein a low priority is assigned to the one transaction in which a match occurs as the determination result.   2. The timing adjustment for the pair of events is determined to be impossible when there is no remaining transaction pair related to the pair of events after the determination result is a match. The timing adjustment program for competitive tests according to any one of to 3. 3. The competitive test timing adjustment program according to claim 2 , wherein the simulator executes the transaction and records the time when the event occurred in the event table. Causing the simulator to output a plurality of sets of transactions obtained from the timing adjustment results;
Based on the simulation result of the simulator, when a competition condition in the pair of events is satisfied, information on timing adjustment for the pair of events is output as a competition scenario.
6. The competitive test timing adjustment program according to claim 1, wherein the program is a competitive test timing adjustment program. 6. The competitive test timing adjustment program according to claim 2 , wherein the one transaction having a match as the determination result is changed to a storage position having a low priority in the event table.   2. The input timing of one transaction is adjusted so that the time of the event having the maximum time among the times of the pair of events included in the selected pair of transactions matches. The timing adjustment program for competitive testing as described in any one of -7. In a competition test timing adjustment method for adjusting a competition timing for competing internal signals of a semiconductor device at an arbitrary event,
Computer
By specifying a pair of events to be competed, a plurality of the transactions related to the pair of events are selected for each set based on the input transaction of the semiconductor device and the event,
Adjust the input timing of one transaction so that the times of the pair of events included in the selected set of transactions match,
Determine whether the time of another event included in one transaction whose input timing has been adjusted does not match the time of the same event included in the other transaction,
Outputting as a timing adjustment result for a pair of events for which a set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are to be made to compete with each other;
A timing adjustment method for competitive testing, characterized by executing processing. In a competition test timing adjustment device that adjusts a competition timing for competing internal signals of a semiconductor device at an arbitrary event,
An event table in which the semiconductor device input transaction is associated with the event;
Based on the input of a pair of events to be competed, referring to the event table, select a plurality of the transactions related to the pair of events for each set,
Adjust the input timing of one transaction so that the times of the pair of events included in the selected set of transactions match,
Determine whether the time of another event included in one transaction whose input timing has been adjusted does not match the time of the same event included in the other transaction,
A conflict scenario generation unit that outputs as a timing adjustment result for a pair of events for which a set of transactions in which a mismatch is obtained as a determination result and the adjusted input timing are to be made to compete with each other;
A timing adjustment device for competitive test, comprising:

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