JP6231291B2 - Motor drive device - Google Patents

Description

  The present invention relates to a motor drive device.

  FIG. 12 is a block diagram showing a conventional example of an optical disc apparatus. With the increase in capacity of optical discs (for example, the practical application of BD [blu-ray (registered trademark) disc]), in recent optical disc apparatuses, an optical pickup 400 is equipped with an LVDS (low voltage differential signaling) receiving unit 410. However, there is one that performs high-speed data communication via the LVDS transmitter 200 between the microcomputer 100 and the optical pickup 400 (particularly, the laser diode driving unit 420 that drives the laser diode 430 when data is recorded on the optical disk).

  On the other hand, the conventional optical disk apparatus is also provided with a motor driving apparatus 300 (system motor driver IC) that integrally drives various motors and servos mounted on the optical disk apparatus in response to an instruction from the microcomputer 100. The driving target of the motor driving device 300 includes a spindle motor, a loading motor, a thread motor (feed motor), various servos incorporated in the optical pickup 400, a spherical aberration motor 440, and the like.

  For example, the conventional motor driving device 300 receives a linear voltage from the microcomputer 100, generates a two-channel differential signal, and outputs each signal to the optical pickup 400 as a driving signal for the spherical aberration motor 440. 310.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2009-261122 A (FIG. 7 etc.)

  However, in the conventional optical disk apparatus, in order to perform high-speed data communication between the microcomputer 100 and the optical pickup 400, the LVDS transmitter 200 must be provided, which increases the size and cost of the set.

  In recent years, in order to further reduce the size of the optical pickup 400 (port reduction), control signals other than the write data (for example, a drive signal for the spherical aberration motor 440) can be received via the LVDS receiver 410. It is being considered.

  However, since the conventional motor driving device 300 does not have a technique for outputting an LVDS signal, when the above-described new method is adopted in the optical pickup 400, a part of the driving target incorporated in the optical pickup 400 ( For example, there is a problem that it becomes impossible to directly control the spherical aberration motor 440).

  In view of the above-described problems found by the inventors of the present application, an object of the present invention is to provide a motor drive device capable of directly controlling a drive target by the LVDS method.

  To achieve the above object, a motor driving device disclosed in the present specification includes a driving unit that drives a motor or a servo, an LVDS transmission processing unit that transmits a pair of positive and negative LVDS output signals to the outside of the device, and an apparatus And a logic unit that sets a logic level of the LVDS output signal in accordance with a register value stored from the outside (first configuration).

  In the motor drive device having the first configuration, the LVDS transmission processing unit includes a plurality of LVDS transmission units that independently generate the LVDS output signal in accordance with each input signal given from the logic unit. A reference voltage generation unit that generates a reference voltage of the plurality of LVDS transmission units in a unified manner, and a reference current generation unit that generates a reference current of the plurality of LVDS transmission units in a unified manner (second Configuration).

  In the motor drive device having the second configuration, the LVDS transmission processing unit may include a mute unit (third configuration) that performs mute control of the input signal according to a mute signal.

  Further, in the motor drive device having the second or third configuration, the plurality of LVDS transmission units and the reference current generation unit are configured to control whether or not their operations are performed according to a power save signal (fourth configuration). ).

  Further, in the motor drive device having any one of the second to fourth configurations, each of the plurality of LVDS transmission units receives the input of the reference current and differentially outputs the LVDS output signal. And an intermediate voltage generation unit that generates an intermediate voltage of the LVDS output signal, and a feedback unit that controls the differential output unit so that the intermediate voltage matches the reference voltage (fifth configuration) ).

  In the motor drive device having any one of the first to fifth configurations, the LVDS transmission processing unit may have a configuration (sixth configuration) arranged away from the power transistor of the drive unit. .

  In the motor drive device having any one of the first to sixth configurations, the plurality of LVDS transmission units may be configured to have a pair property (seventh configuration).

  The optical disk device disclosed in the present specification includes an optical pickup for reproducing or recording / reproducing an optical disk, a spindle motor for rotationally driving the optical disk, a loading motor for taking in and out the optical disk or a disk tray, and the optical disk device. A sled motor that drives the pickup in the radial direction of the optical disc, a motor driving device having any one of the first to seventh configurations, and a microcomputer that controls the motor driving device. The driving control of the spherical aberration motor is performed according to the LVDS output signal from the motor driving device (eighth configuration).

  In the optical disk apparatus having the eighth configuration, the optical pickup performs drive control of the spherical aberration motor in accordance with the LVDS output signal when the optical disk is mounted, and the LVDS when data is recorded on the optical disk. A configuration (ninth configuration) for performing drive control of the laser diode in accordance with the output signal is preferable.

  Further, the car AV device disclosed in the present specification has a configuration (tenth configuration) including the optical disk device having the eighth or ninth configuration.

  ADVANTAGE OF THE INVENTION According to this invention, the motor drive device which can directly control a drive object by LVDS system can be provided.

Block diagram showing a configuration example of an optical disk device Correlation diagram between register value DSAx and LVDS output signal SAOx Output timing chart of LVDS output signal SAOx Correlation diagram between register value SA_OUTEN and LVDS output operation Correlation diagram between register value SA_PSB and LVDS power save operation The block diagram which shows the example of 1 structure of the LVDS transmission process part 14. The circuit diagram which shows the example of 1 structure of the mute part 143 The circuit diagram which shows the example of 1 structure of the reference current production | generation part 146 The circuit diagram which shows the example of 1 structure of the LVDS transmission part 141 Plan layout diagram of the motor drive device 10 External view of car AV equipment Block diagram showing a conventional example of an optical disk device

<Optical disk device>
FIG. 1 is a block diagram illustrating a configuration example of an optical disc apparatus. The optical disc device 1 of this configuration example includes a motor driving device 10, an optical pickup 20, a spindle motor 30, a loading motor 40, a thread motor 50, and a microcomputer 60.

  The motor drive device 10 is a semiconductor integrated circuit device (so-called system motor driver IC) that integrally drives various motors and servos mounted on the optical disc device 1 in response to an instruction from the microcomputer 60. The internal configuration of the motor drive device 10 will be described in detail later.

  The optical pickup 20 is means for reproducing or recording / reproducing the optical disc D, and includes focus / tilt servos 21 and 22, a tracking servo 23, an LVDS reception processing unit 24, a spherical aberration motor driving unit 25, and a spherical aberration motor ( SA [spherical aberration] motor) 26, laser diode drive unit 27, and laser diode 28.

  The focus / tilt servos 21 and 22 use an actuator to drive an objective lens (not shown) to adjust the focal position of the laser beam to the recording surface of the optical disc D, or to record the optical axis of the laser beam on the optical disc D. Keep perpendicular to the surface.

  The tracking servo 23 drives the objective lens (not shown) using an actuator to cause the focal position of the laser beam to follow the track of the optical disc D.

  The LVDS reception processing unit 24 receives the two-channel LVDS output signals input from the motor driving device 10 and receives the LVDS output signals received by the LVDS reception units 241 and 242, respectively. And a logic unit 243 that generates control signals for the aberration motor driving unit 25 and the laser diode driving unit 27.

  In particular, the logic unit 243 generates a control signal for the spherical aberration motor driving unit 25 so as to control the driving of the spherical aberration motor 26 using both of the two-channel LVDS output signals when the optical disc D is mounted. By performing such an operation, it is possible to correct the spherical aberration according to the type of the optical disc D (BD or DVD and CD) when the optical disc D is mounted.

  On the other hand, after correcting the spherical aberration when the optical disc D is mounted, it is not necessary to drive the spherical aberration motor 26 until another optical disc D is mounted. Therefore, the logic unit 243 generates a control signal for the laser diode driving unit 27 so as to control the driving of the laser diode 28 using one of the two-channel LVDS output signals when recording data on the optical disc D.

  With such a configuration, it is possible to control both the spherical aberration motor 26 and the laser diode 28 via the motor driving device 10 without separately providing an LVDS transmitter between the microcomputer 60 and the optical pickup 20. Therefore, it is possible to reduce the size and cost of the set.

  The spherical aberration motor drive unit 25 performs drive control of the spherical aberration motor 26 in accordance with a control signal input from the logic unit 243.

  The spherical aberration motor 26 corrects the spherical aberration due to the difference in substrate thickness of the optical disc D by driving a collimator lens (not shown). By this correction, it becomes possible to perform recording and reproduction of various optical disks D regardless of the type of optical disk D and the number of recording layers.

  The laser diode drive unit 27 performs drive control (light on / off control) of the laser diode 28 in accordance with a control signal (write data) input from the logic unit 243.

  The laser diode 28 writes data by irradiating the recording surface of the optical disc D with a laser beam.

  The spindle motor 30 drives the optical disk D to rotate. The loading motor 40 takes in and out the optical disc D (or a disc tray on which the optical disc D is placed). The thread motor 50 drives the optical pickup 20 in the radial direction of the optical disc D. Since the loading motor 40 and the sled motor 50 are not used at the same time, they can be shared as a sled / loading motor.

  The microcomputer 60 is a main body that comprehensively controls the entire operation of the optical disk device 1, and communicates with the motor drive device 10 mainly in accordance with the SPI [Serial Peripheral Interface] standard (serial data input signal SDI, serial Data output signal SDO, serial clock signal SCLK, serial slave signal SLE, etc.) are input / output.

<Motor drive device>
The motor driving device 10 includes a focus / tilt servo driving unit 11 and 12, a tracking servo driving unit 13, an LVDS transmission processing unit 14, a spindle motor driving unit 15, a loading motor driving unit 16, and a thread motor driving unit 17. , A logic unit 18 and a serial interface unit 19.

  The focus / tilt servo drive unit 11 generates drive signals (FCTLO1 +, FCTLO1-) for the focus / tilt servo 21 in accordance with the control signal from the logic unit 18.

  The focus / tilt servo drive unit 12 generates drive signals (FCTLO2 +, FCTLO2-) for the focus / tilt servo 22 in accordance with a control signal from the logic unit 18.

  The tracking servo drive unit 13 generates a drive signal (TKO +, TKO−) for the tracking servo 23 according to the control signal from the logic unit 18.

  The LVDS transmission processing unit 14 is similar to the LVDS transmission unit 141 that transmits a pair of positive and negative LVDS output signals (SAO1 +, SAO1-) to the optical pickup 20 according to the input signal (SAIN1) given from the logic unit 18, and the logic unit 18 similarly. And an LVDS transmission unit 142 that transmits a pair of positive and negative LVDS output signals (SAO2 +, SAO2-) to the optical pickup 20 in accordance with an input signal (SAIN2) given from the signal.

  As described above, if the motor driving apparatus 10 includes the LVDS transmission processing unit 14, it is possible to directly control the drive target using the LVDS method. In particular, if the configuration outputs LVDS output signals for two channels, it is possible to support not only drive control of the laser diode 28 but also drive control of the spherical aberration motor 26.

  The spindle motor drive unit 15 generates drive signals (U_OUT, V_OUT, W_OUT) for the spindle motor 30 in accordance with a control signal from the logic unit 18.

  The loading motor driving unit 16 generates driving signals (LDO +, LDO−) for the loading motor 40 in accordance with a control signal from the logic unit 18.

  The sled motor driving unit 17 generates a driving signal (SLO1 +, SLO1-, SLO2 +, SLO2-) of the sled motor 50 according to the control signal from the logic unit 18.

  The logic unit 18 sets the logic level of the LVDS output signals (SAO1 +, SAO1-, SAO2 +, SAO2-) according to the register value stored in the register 181 from the microcomputer 60. The register 181 stores a 1-bit register value DSAx (x = 1, 2), a register value SA_OUTEN, and a register value SA_PSB as register values related to the LVDS transmission processing unit 14.

  The interface unit 19 inputs and outputs communication signals (serial data input signal SDI, serial data output signal SDO, serial clock signal SCLK, serial slave signal SLE, etc.) compliant with the SPI standard with the microcomputer 60.

<Register>
FIG. 2 is a correlation diagram between the register value DSAx and the LVDS output signal SAOx. The register value DSAx is a register value for setting the logic level of the LVDS output signals SAOx + and SAOx−. When the register value DSAx is “0”, the logic unit 18 generates the input signal SAINx to the LVDS transmission output unit 14 so that the LVDS output signal SAOx + is at a low level and the LVDS output signal SAOx− is at a high level. To do. On the other hand, when the register value DSAx is “1”, the logic unit 18 sets the LVDS output signal SAOx + to the high level and the LVDS output signal SAOx− to the low level, and the input signal SAINx to the LVDS transmission output unit 14. Is generated.

  Thus, the logic levels of the LVDS output signals SAOx + and SAOx− are uniquely determined by the register value DSAx. Therefore, the microcomputer 60 can transmit arbitrary LVDS output signals SAOx + and SAOx− to the optical pickup 20 via the motor driving device 10 by rewriting the register value DSAx of the register 181.

  FIG. 3 is an output timing chart of the LVDS output signal SAOx (x = 1, 2). As shown in the figure, the LVDS output signals SAO1 and SAO2 can be controlled independently for each channel. The differential signal level VODx of the LVDS output signal SAOx can be calculated by VODx = | V (SAOx +) − V (SAOx−) |. Further, the intermediate voltage VOCx of the LVDS output signal SAOx can be calculated by VOCx = {V (SAOx +) + V (SAOx −)} / 2.

  FIG. 4 is a correlation diagram between the register value SA_OUTEN and the LVDS output operation. The register value SA_OUTEN is a register value for setting whether or not the LVDS transmission processing unit 14 can output. When the register value SA_OUTEN is “0”, the logic unit 18 sets the mute signal MUTEB to the LVDS transmission processing unit 14 to a high level (LVDS output operation: enable) so as to permit the output operation of the LVDS transmission processing unit 14. And On the other hand, when the register value SA_OUTEN is “1”, the logic unit 18 sets the mute signal MUTEB to a low level (LVDS output operation: disabled) so as to prohibit the output operation of the LVDS transmission processing unit 14. Details of the mute signal MUTEB will be described later.

  As described above, whether or not the LVDS transmission processing unit 14 can output is uniquely determined by the register value SA_OUTEN. Therefore, the microcomputer 60 can arbitrarily set the output permission of the LVDS transmission processing unit 14 by rewriting the register value SA_OUTEN of the register 181.

  FIG. 5 is a correlation diagram between the register value SA_PSB and the LVDS power saving operation. The register value SA_PSB is a register value for turning on / off the internal circuit of the LVDS transmission processing unit 14. When the register value SA_PSB is “0”, the logic unit 18 sets the power save signal PSB to the LVDS transmission processing unit 14 to a low level (power saving operation: enable) so as to turn off the internal circuit of the LVDS transmission processing unit 14. ). On the other hand, when the register value SA_PSB is “1”, the logic unit 18 sets the power save signal PSB to a high level (power save operation: disabled) so as to turn on the internal circuit of the LVDS transmission processing unit 14. Details of the power save signal PSB will be described later.

  Thus, the on / off state of the internal circuit included in the LVDS transmission processing unit 14 is uniquely determined by the register value SA_PSB. Therefore, the microcomputer 60 can arbitrarily turn on / off the internal circuit of the LVDS transmission processing unit 14 by rewriting the register value SA_PSB of the register 181. For example, the power consumption of the motor drive device 10 can be greatly reduced by turning off the internal circuit of the LVDS transmission processing unit 14 except when the optical disk D is mounted and when data is written.

<LVDS transmission processing unit>
FIG. 6 is a block diagram illustrating a configuration example of the LVDS transmission processing unit 14. In addition to the LVDS transmission units 141 and 142, the LVDS transmission processing unit 14 of the present configuration example includes mute units 143 and 144, a reference voltage generation unit 145, and a reference current generation unit 146.

  The mute unit 143 basically generates control signals V1P and V1N having opposite logics according to the input signal SAIN1 from the logic unit 18 and outputs them to the LVDS transmission unit 141. Similarly, the mute unit 144 basically generates control signals V2P and V2N having opposite logics according to the input signal SAIN2 from the logic unit 18 and outputs them to the LVDS transmission unit 142. The mute units 143 and 144 have a function of performing mute control of the input signals SAIN1 and SAIN2 according to the mute signal MUTEB from the logic unit 18, respectively. The mute control will be described in detail later together with the circuit configurations of the mute units 143 and 144.

  The reference voltage generation unit 145 generates the reference voltage VREF of the LVDS transmission units 141 and 142 in an integrated manner. As the reference voltage generation unit 145, for example, a flat band gap reference voltage source with flat temperature characteristics and power supply characteristics can be used.

  The reference current generation unit 146 generates the reference currents IREF1 and IREF2 of the LVDS transmission units 141 and 142 in an integrated manner. The circuit configuration of the reference current generation unit 146 will be described later with a specific example.

  As described above, in the LVDS transmission processing unit 14 of this configuration example, the reference voltage generation unit 145 and the reference current generation unit 146 are shared by the LVDS transmission units 141 and 142 for two channels. By adopting such a configuration, the differential signal level VODx and the intermediate voltage VOCx of each channel can be made to coincide with each other, so that the LVDS output accuracy can be increased.

  Further, in the LVDS transmission processing unit 14 of this configuration example, the LVDS transmission units 141 and 142 and the reference current generation unit 146 are all controlled according to the power save signal PSB. This power saving control will be described in detail later together with the circuit configurations of the LVDS transmitters 141 and 142 and the reference current generator 146.

  FIG. 7 is a circuit diagram illustrating a configuration example of the mute unit 143. The mute unit 143 of this configuration example includes an inverter 143a and selectors 143b and 143c. Both the input terminal of the inverter 143a and the first input terminal (H) of the selector 143b are connected to the application terminal of the input signal SAIN1. The output terminal of the inverter 143a is connected to the first input terminal (H) of the selector 143c. The second input terminals (L) of the selectors 143b and 143c are both connected to the ground terminal. The output terminal of the selector 143b is connected to the application terminal of the control signal V1P. The output terminal of the selector 143c is connected to the application terminal of the control signal V1N. The control ends of the selectors 143b and 143 are both connected to the application end of the mute signal MUTEB. Note that the mute unit 144 basically has the same configuration as described above, and a duplicate description is omitted.

  In the mute unit 143 of this configuration example, when the mute signal MUTEB is at a high level (LVDS output operation: enable), the selectors 143b and 143c conduct the first input terminal (H) and the output terminal. Therefore, when the input signal SAIN1 is at a high level, the control signal V1P is at a high level and the control signal V1N is at a low level. Conversely, when the input signal SAIN1 is at a low level, the control signal V1P is at a low level and the control signal V1N is at a high level. As described above, when the mute signal MUTEB is at the high level, the control signals V1P and V1N have the logic level corresponding to the input signal SAIN1, and the LVDS transmission unit 141 that receives the input receives the LVDS corresponding to the input signal SAIN1. Output signals SAO1 + and SAO1- are generated.

  On the other hand, when the mute signal MUTEB is at a low level (LVDS output operation: disabled), the selectors 143b and 143c conduct the respective second input terminals (L) and output terminals. Therefore, the control signals V1P and V1N are both at a low level regardless of the logic level of the input signal SAIN1, and the LVDS transmitter 141 that receives the input is in an output high impedance state.

  FIG. 8 is a circuit diagram illustrating a configuration example of the reference current generation unit 146. The reference current generator 146 of this configuration example includes a current source 146a that generates a predetermined reference current IREF0 and a current mirror that generates a reference current IREF1 and IREF2 (for example, 20 μA each) by mirroring the reference current IREF0 (for example, 10 μA). 146b and an N-channel MOS field effect transistor 146c that conducts / cuts off a current path through which the reference current IREF0 flows in response to the power save signal PSB.

  In the reference current generation unit 146 of this configuration example, when the power save signal PSB is at a high level (power save operation: enable), the transistor 146c is turned on, so that the current path through which the reference current IREF0 flows is conducted, The reference currents IREF1 and IREF2 are output from the current mirror 146b.

  On the other hand, when the power save signal PSB is at the low level (power save operation: disabled), the transistor 146c is turned off, so that the current path through which the reference current IREF0 flows is cut off, and the reference current IREF1 and IREF2 is not output.

  FIG. 9 is a circuit diagram illustrating a configuration example of the LVDS transmission unit 141. The LVDS transmission unit 141 of this configuration example includes a differential output unit 141a, an intermediate voltage generation unit 141b, a feedback unit 141c, current mirrors 141d and 141e, and a power save control unit 141f.

  The differential output unit 141a is a circuit unit that receives an input of a mirror current IM4 (for example, 4 mA) and differentially outputs LVDS output signals SAO1 + and SAO1-, and includes N-channel MOS field effect transistors a1 to a4. The drains of the transistors a1 and a2 are both connected to the application end of the mirror current IM4. The source of the transistor a1 and the drain of the transistor a3 are both connected to the application end of the LVDS output signal SAO1 +. The source of the transistor a2 and the drain of the transistor a4 are both connected to the application terminal of the LVDS output signal SAO1-. The sources of the transistors a4 and a4 are both connected to the ground terminal via the feedback unit 141c. The gates of the transistors a1 and a4 are both connected to the application terminal for the control signal V1P. The gates of the transistors a2 and a3 are both connected to the application terminal for the control signal V1N.

  In the differential output unit 141a of this configuration example, when the control signal V1P is at a high level and the control signal V1N is at a low level, the transistors a1 and a4 are turned on and the transistors a2 and a3 are turned off. Accordingly, the mirror current IM4 flows to the LVDS receiver 241 (for example, a 100Ω resistor) through a current path through the transistors a1 and a4. As a result, the LVDS output signal SAO1 + becomes a high level (for example, VOC1 + 200 mV), and the LVDS output signal SAO1- becomes a low level (for example, VOC1-200 mV).

  On the other hand, when the control signal V1P is at a low level and the control signal V1N is at a high level, the transistors a1 and a4 are turned off and the transistors a2 and a3 are turned on. Therefore, the mirror current IM4 flows to the LVDS receiver 241 through a current path through the transistors a2 and a3. As a result, the LVDS output signal SAO1 + becomes a low level (for example, VOC1-200 mV), and the LVDS output signal SAO1- becomes a high level (for example, VOC1 + 200 mV).

  The intermediate voltage generation unit 141b is a circuit unit that generates an intermediate voltage VOC1 of the LVDS output signals SAO1 + and SAO1-, and includes resistors b1 and b2 having the same resistance value. The resistors b1 and b2 are connected in series between the application terminal of the LVDS output signal SAO1 + and the application terminal of the LVDS output signal SAO1-, and form a voltage dividing circuit that outputs the intermediate voltage VOC1 from each connection node. Yes.

  The feedback unit 141c is a circuit unit that controls the differential output unit 141a so that the intermediate voltage VOC1 matches the reference voltage VREF, and includes an operational amplifier c1 and an N-channel MOS field effect transistor c2. The non-inverting input terminal (+) of the operational amplifier c1 is connected to the application terminal for the reference voltage VREF. The inverting input terminal (−) of the operational amplifier c1 is connected to the application terminal for the intermediate voltage VOC1. The positive power supply terminal of the operational amplifier c1 is connected to the application terminal of the mirror current IM3 (for example, 160 μA). The negative power supply terminal of the operational amplifier c1 is connected to the ground terminal. The output terminal of the operational amplifier c1 is connected to the gate of the transistor c2. The drain of the transistor c2 is connected to the sources of the transistors a3 and a4. The source of the transistor c2 is connected to the ground terminal.

  In the feedback unit 141c of this configuration example, the operational amplifier c1 controls the conductivity of the transistor c2 so that the intermediate voltage VOC matches the reference voltage VREF.

  The current mirror 141d is a circuit unit that receives a reference current IREF1 (for example, 20 μA) and generates mirror currents IM1 and IM2 (for example, 80 μA each), and includes N-channel MOS field effect transistors d1 to d6. The drain of the transistor d1 is connected to the application end of the reference current IREF1. The gates of the transistors d1 to d3 are all connected to the drain of the transistor d1. The drain of the transistor d2 is connected to the application end of the mirror current IM2. The drain of the transistor d3 is connected to the application end of the mirror current IM3. The drain of the transistor d4 is connected to the source of the transistor d1. The gates of the transistors d4 to d6 are all connected to the drain of the transistor d4. The drain of the transistor d5 is connected to the source of the transistor d2. The drain of the transistor d6 is connected to the source of the transistor d3. The sources of the transistors d4 to d6 are all connected to the ground terminal.

  The current mirror 141e is a circuit unit that receives mirror currents IM1 and IM2 and generates mirror currents IM3 and IM4, and includes P-channel MOS field effect transistors e1 to e7. The source of the transistor e1 is connected to the power supply terminal. The gates of the transistors e1 to e4 are all connected to the drain of the transistor e1. The drain of the transistor e1 is connected to the drain of the transistor d2. The drain of the transistor e2 is connected to the drain of the transistor d3. The drain of the transistor e3 is connected to the positive power supply terminal of the operational amplifier c1. The drain of the transistor e4 is connected to the drains of the transistors a1 and a2. The source of the transistor e2 is connected to the drain of the transistor e5. The source of the transistor e3 is connected to the drain of the transistor e6. The source of the transistor e4 is connected to the drain of the transistor e7. The sources of the transistors e5 to e7 are all connected to the power supply terminal. The gates of the transistors e5 to e7 are all connected to the drain of the transistor e2.

  As described above, since the current mirrors 141d and 141e of this configuration example are both of the cascade type, it is possible to increase the accuracy of each mirror.

  The power save control unit 141f is a circuit unit that controls the operation of the current mirrors 141d and 141e in accordance with the power save signal PSB, and includes P channel type MOS field effect transistors f1 and f2, and an N channel type MOS field effect transistor f3. And including. The sources of the transistors f1 and f2 are both connected to the power supply terminal. The gates of the transistors f1 and f2 are both connected to the application end of the power save signal PSB. The drain of the transistor f1 is connected to the drain of the transistor e2. The drain of the transistor f2 is connected to the drain of the transistor e1. The drain of the transistor f3 is connected to the drain of the transistor d1. The source of the transistor f3 is connected to the ground terminal. The gate of the transistor f3 is connected to the application terminal of the inverted power save signal XPSB (the logic inverted signal of the power save signal PSB).

  In the power save control unit 141f of this configuration example, when the power save signal PSB is at a high level and the inverted power save signal XPSB is at a low level, all of the transistors f1 to f3 are turned off. Therefore, the current mirrors 141d and 141e are both in a state in which mirror operation is possible, and current is supplied to the differential output unit 141a and the feedback unit 141c.

  On the other hand, when the power save signal PSB is at a low level and the inverted power save signal XPSB is at a high level, all of the transistors f1 to f3 are turned on. Accordingly, the current mirrors 141d and 141e are both in a state in which the mirror operation is prohibited, and the current supply to the differential output unit 141a and the feedback unit 141c is stopped.

  Note that the LVDS transmission unit 142 basically has the same configuration as described above, and a duplicate description is omitted.

<Planar layout>
FIG. 10 is a plan layout view of the motor drive device 10. When driving a large number of motors and servos, the power transistors forming the output stages of the various drive units generate heat. Therefore, in the motor driving device 10, the power transistors are separately disposed on both ends of the IC, and the logic unit and the analog unit are provided so as to be sandwiched between the power transistors. By adopting such a planar layout, it is possible to reduce the influence of the heat generation of the power transistor on the signal processing of the logic unit and the analog unit.

  In particular, the LVDS transmission processing unit 14 is arranged near the center of the analog unit so as to be as far as possible from the power transistor of the driving unit. The LVDS transmission units 141 and 142 for two channels included in the LVDS transmission processing unit 14 are arranged in parallel so as to have a pair property. By adopting such a planar layout, it is possible to realize highly accurate LVDS transmission processing without depending on the heat generation of the power transistor.

<Car AV [audio / visual] equipment>
FIG. 11 is an external view of a car AV device. The car AV device X of this configuration example includes an optical disc device 1 that plays back an optical disc D (CD, DVD, BD, etc.), a disc slot X1 that is an insertion / extraction port of the optical disc D, and an optical disc D from the disc slot X1 It has an eject button X2 for ejecting, and a display panel X3 for displaying a playback video and content information (playback track number, playback time, etc.) of the optical disc D or a touch panel UI [user interface] screen.

<Other variations>
In the embodiment described above, the system motor driver IC for car AV equipment has been described as an example of the application of the present invention. However, the application of the present invention is not limited to this, and other It can also be incorporated into a motor drive device (for example, a system motor driver IC for a DVD drive or a BD recorder) used for the above-described applications.

  In addition to the above-described embodiments, the invention disclosed in the present specification can be variously modified without departing from the spirit of the technical creation. For example, mutual replacement of a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used, for example, in a system motor driver IC incorporated in an optical disk device for in-vehicle AV equipment.

DESCRIPTION OF SYMBOLS 1 Optical disk apparatus 10 Motor drive device 11, 12 Focus / tilt servo drive part (1ch, 2ch)
13 Tracking servo drive unit 14 LVDS transmission processing unit 141, 142 LVDS transmission unit (1ch, 2ch)
141a differential output unit a1 to a4 N channel type MOS field effect transistor 141b intermediate voltage generation unit b1 and b2 resistance 141c feedback unit c1 operational amplifier c2 N channel type MOS field effect transistor 141d current mirror d1 to d6 N channel type MOS field effect transistor 141e Current mirror e1 to e7 P channel type MOS field effect transistor 141f Power save control unit f1, f2 P channel type MOS field effect transistor f3 N channel type MOS field effect transistor 143, 144 Mute unit (1ch, 2ch)
143a Inverter 143b, 143c Selector 145 Reference voltage generator 146 Reference current generator 146a Current source 146b Current mirror 146c N-channel MOS field effect transistor 15 Spindle motor driver 16 Loading motor driver 17 Thread motor driver 18 Logic unit 181 Register 19 Serial interface section 20 Optical pickup 21, 22 Focus / tilt servo (actuator coil)
23 Tracking servo (actuator coil)
24 LVDS reception processing unit 241 242 LVDS reception unit (1ch, 2ch)
243 Logic unit 25 Spherical aberration motor drive unit 26 Spherical aberration motor 27 Laser diode drive unit 28 Laser diode 30 Spindle motor 40 Loading motor 50 Thread motor 60 Microcomputer X Car AV device X1 Disc slot X2 Eject button X3 Display panel D Optical disc

Claims (9)

An optical pickup for reproducing or recording / reproducing an optical disc;
A spindle motor that rotationally drives the optical disc;
A loading motor for taking in and out the optical disc or the disc tray;
A thread motor that drives the optical pickup in the radial direction of the optical disc;
A motor drive device;
A microcomputer for controlling the motor driving device;
Have
The motor driving device is
The spindle motor, the loading motor, the thread motor, or a drive unit that drives the servo of the optical pickup;
A pair of positive and negative LVDS (low voltage differential signaling) LVDS transmission processing units for transmitting output signals to the outside of the device;
A logic unit for setting a logic level of the LVDS output signal according to a register value stored from the outside of the device;
Have
The optical pickup performs drive control of the spherical aberration motor according to the LVDS output signal from the motor drive device, and controls the drive of the spherical aberration motor according to the LVDS output signal when the optical disc is mounted. On the other hand, at the time of recording data on the optical disc, the optical disc apparatus controls driving of the laser diode in accordance with the LVDS output signal. The LVDS transmission processing unit includes a plurality of LVDS transmission units that independently generate the LVDS output signal according to each input signal given from the logic unit,
Each of the plurality of LVDS transmission units includes an intermediate voltage generation unit that generates an intermediate voltage of the LVDS output signal;
The intermediate voltage generator includes a first resistor and a second resistor connected in series between a positive LVDS output signal application terminal and a negative LVDS output signal application terminal, and outputting the intermediate voltage from the connection nodes. The optical disk apparatus according to claim 1, comprising: The LVDS transmission processing unit
A reference voltage generation unit that generates the reference voltages of the plurality of LVDS transmission units in an integrated manner;
A reference current generation unit that generates a reference current of the plurality of LVDS transmission units in an integrated manner;
The optical disc apparatus according to claim 2, comprising:   4. The optical disc apparatus according to claim 3, wherein the LVDS transmission processing unit includes a mute unit that performs mute control of the input signal in accordance with a mute signal.   5. The optical disc apparatus according to claim 3, wherein whether or not the plurality of LVDS transmission units and the reference current generation unit are operated is controlled according to a power save signal. The plurality of LVDS transmission units are respectively
A differential output unit for receiving the reference current and differentially outputting the LVDS output signal;
A feedback unit that controls the differential output unit such that the intermediate voltage matches the reference voltage;
The optical disc apparatus according to claim 3, comprising:   The optical disk apparatus according to any one of claims 1 to 6, wherein the LVDS transmission processing unit is disposed apart from a power transistor of the driving unit. The optical disc apparatus according to any one of claims 2 to 6 , wherein the plurality of LVDS transmission units are arranged in parallel.   A car AV device comprising the optical disc device according to any one of claims 1 to 8.

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