JP6231969B2 - Voltage equalization apparatus and voltage equalization method - Google Patents

Description

  Embodiments described herein relate generally to a voltage equalization apparatus and a voltage equalization method.

  A hybrid electric vehicle (HEV) and an electric vehicle (EV) are equipped with a lithium ion secondary battery as a power source. The output voltage of one lithium ion secondary battery is, for example, Since it is 3.6 V, in order to obtain a voltage required for the drive motor, it is necessary to connect several tens of them in series and use them as an assembled battery.

By the way, in the initial state, the voltage characteristics of the secondary batteries constituting the assembled battery are uniform, but the state of charge (voltage) of each cell differs due to repeated charge and discharge during use. .
In this case, in order to avoid overcharging when charging, it is necessary to stop charging according to the secondary battery with the highest voltage, so other secondary batteries can still be charged, Charging is stopped.

In addition, in order to avoid overdischarge even at the time of discharge, it is necessary to stop discharge in accordance with the secondary battery with the lowest voltage, so other secondary batteries can still be discharged, Discharging is stopped.
As a result, there arises a problem that the available stored power is reduced.

  Therefore, in the conventional assembled battery, a capacitor is provided, and a switch group is provided between the secondary battery and the capacitor constituting the assembled battery, and the secondary battery having a higher voltage is controlled by controlling the switch group. A voltage equalizing apparatus has been proposed in which voltage is equalized by repeating the operation of transferring the electric charge to another secondary battery having a low voltage through a capacitor.

JP 2014-050269 A JP-A-10-225005

By the way, at the start of equalization, no charge is stored in the capacitor. In such a state, if a switch group is controlled to connect the capacitor to the secondary battery and a charging current is passed, a large inrush current is generated. Will occur.
In order to cope with this, it is necessary to increase the current capacity of the switches and wirings constituting the switch group, which may increase the size of the device.

  The present invention has been made in view of the above, and an object of the present invention is to provide a voltage equalizing apparatus and a voltage equalizing method that can be miniaturized.

  The voltage equalization apparatus according to the embodiment repeats the process of transferring the charge of any one of the plurality of battery cells connected in series to the other battery cell to equalize the voltage of the plurality of battery cells. A voltage equalizing apparatus that performs the above-described operation, the first capacitor having a capacity smaller than the capacity of the battery cell, and the first capacitor can be connected in parallel, and has a capacity larger than the capacity of the first capacitor. Prior to transferring the charge of the second capacitor and the transfer source battery cell to the transfer destination battery cell via the second capacitor, the storage voltage of the second capacitor is changed to the voltage of the transfer source battery cell. A switching control unit that repeats the process of transferring the charge of the transfer source battery cell to the second capacitor via the first capacitor.

  In this case, the switching control unit includes a plurality of switches capable of selectively simultaneously connecting any one of the plurality of battery cells, the first capacitor, or the second capacitor. You may make it provide the provided connection switching part and the control part which controls a connection switching part.

  The connection switching unit includes a plurality of battery cells as a first battery block and a plurality of battery cells to be voltage equalized by another voltage equalization device on the high potential side of the first battery block. When the second battery block is connected, the battery cell on the lowest potential side among the battery cells constituting the second battery block may be selected.

  In addition, the first capacitor is provided with a voltage measuring unit capable of measuring the voltage of the battery cell, and when the voltage of each of the plurality of battery cells is measured, the charge of each battery cell is transferred to the first capacitor. It may be used for voltage measurement of each battery cell.

  In the voltage equalization method of the embodiment, the plurality of battery cells are repeatedly processed by transferring the charge of any one of the plurality of battery cells connected in series to the other battery cell. A voltage equalization method executed by a voltage equalization apparatus that performs voltage equalization of the first capacitor having a capacity smaller than the capacity of the battery cell and the first capacitor. And a second capacitor having a capacity larger than that of the first capacitor, and the transfer source battery until the stored voltage of the second capacitor becomes the voltage of the transfer source battery cell. The process of repeating the process of transferring the cell charge to the second capacitor through the first capacitor and the charge of the transfer source battery cell until the voltage of the transfer destination battery cell becomes the voltage of the transfer source battery cell The second Of and a process for repeating the process of transferring the transfer destination of the battery cell via a capacitor.

  According to the voltage equalization apparatus and the voltage equalization method of the embodiment, the voltage equalization apparatus, and thus the battery system can be reduced in size.

FIG. 1 is a schematic configuration block diagram of the battery system of the first embodiment. FIG. 2 is a schematic configuration diagram of the assembled battery system of the first embodiment. FIG. 3 is a process flowchart of the cell voltage detection / balance circuit according to the embodiment. FIG. 4 is a process flowchart of the cell voltage measurement process. FIG. 5 is a process flowchart of the cell balance process. FIG. 6 is a schematic configuration block diagram of the battery system of the second embodiment. FIG. 7 is a schematic configuration diagram of the assembled battery system of the second embodiment.

Next, embodiments will be described with reference to the drawings.
[1] First Embodiment FIG. 1 is a schematic configuration block diagram of a battery system according to a first embodiment.
The battery system 10 is charged by receiving power from the external device 11 such as a charger via the high potential side terminal TH and the low potential side terminal TL, and also stores the power stored in the external device 11 such as a load. And an assembled battery system 12 that is supplied via a high potential side terminal TH and a low potential side terminal TL.

  The assembled battery system 12 detects a voltage of a battery block 21 having a plurality of battery cells and the voltage of the battery cells constituting the battery block 21, and eliminates a bias in the storage capacity (remaining storage capacity) of the battery cells. A cell voltage detection / balance circuit 22 that performs balance processing, and a battery cell voltage detection / balance circuit 22 that is externally attached to the cell voltage detection / balance circuit 22 and has a capacity smaller than that of the battery cells constituting the battery block 21. And a capacitor C2 having a larger capacity than the capacitor C1.

  Here, in the capacitor C1, the capacity smaller than the capacity of the battery cells constituting the battery block 21 means that the empty capacitor C1 is connected to the fully charged battery cells constituting the battery block 21. Even so, the capacity is such that a large current called inrush current does not flow into the connection wiring, and is set appropriately.

  In the above configuration, the cell voltage / balance circuit 22, the connection switching unit 31, which will be described later, the controller 39, which will be described later, the first capacitor C1, and the second capacitor C2 constitute a voltage equalizing device.

FIG. 2 is a schematic configuration diagram of the assembled battery system of the first embodiment.
For example, as shown in FIG. 2, the battery block 21 of the assembled battery system 12 includes battery cells CL1 to CL5 between the low potential side terminal TL and the high potential side terminal TH from the low potential side toward the high potential side. Are connected in series.

A connection point between the low potential side terminal TL and the negative electrode terminal of the battery cell CL1 is grounded via the VSS terminal TVSS of the cell voltage detection / balance circuit 22.
A connection point between the positive terminal of the battery cell CL1 and the negative terminal of the battery cell CL2 is connected to the first input terminal VIN1 of the cell voltage detection / balance circuit 22 via the current limiting resistor R.
A connection point between the positive terminal of the battery cell CL2 and the negative terminal of the battery cell CL3 is connected to the second input terminal VIN2 of the cell voltage detection / balance circuit 22 via the current limiting resistor R.

A connection point between the positive terminal of the battery cell CL3 and the negative terminal of the battery cell CL4 is connected to the third input terminal VIN3 of the cell voltage detection / balance circuit 22 via the current limiting resistor R.
A connection point between the positive terminal of the battery cell CL4 and the negative terminal of the battery cell CL5 is connected to the fourth input terminal VIN4 of the cell voltage detection / balance circuit 22 via the current limiting resistor R.
A connection point between the positive electrode terminal of the battery cell CL5 and the high potential side terminal TH is connected to the fifth input terminal VIN5 of the cell voltage detection / balance circuit 22 through the current limiting resistor R. Furthermore, the connection point between the positive electrode terminal of the battery cell CL5 and the high potential side terminal TH is connected to the power supply terminal VCC of the cell voltage detection / balance circuit 22 through a wire parallel to the current limiting resistor R.

The cell voltage detection / balance circuit 22 broadly categorizes and outputs a signal corresponding to the temperature of the battery block 21 and a connection switching unit 31 that selectively switches and connects the battery cells to be measured, charged or discharged. A temperature sensor 32 that detects the temperature of the battery block 21 based on an output signal of the temperature sensor 32, a booster circuit 34 that boosts the voltage of the supplied power supply VCC and outputs the boosted voltage to each unit, and a power supply A VDD regulator 35 that stabilizes the voltage VCC and outputs it to each unit as a stabilized power supply VDD, a buffer amplifier 36 that outputs a voltage corresponding to the stored voltage of the capacitor C1, and an internal reference voltage generated from the power supply voltage VCC and outputs it. Based on the internal reference voltage source 37 and the internal reference voltage output from the internal reference voltage source 37, the output voltage of the buffer amplifier 36 is analyzed. An AD converter 38 that performs voltage / digital conversion and outputs voltage data; a controller 39 that controls the entire cell voltage detection / balance circuit 22 including control of the connection switching unit 31 based on the output of the AD converter 38; A first communication interface 40 and a second communication interface 41 that communicate with each other.
In the above configuration, the buffer amplifier 36, the internal reference voltage source 37, and the AD converter 38 constitute a voltage measuring unit.

  In the above configuration, the connection switching unit 31 includes the first high potential side switch SH1 to the fifth high potential side switch SH5, the first low potential side switch SL1 to the fourth low potential side switch SL4, the ground switch SL0, and the current limiting resistor R1. And a voltage detection switch SAD and a cell balance switch SCB.

The capacitor C1 is connected between the capacitor connection terminal HCP and the capacitor connection terminal HCN.
Similarly, the capacitor C2 is connected between the capacitor connection terminal HCN and the capacitor connection terminal BC. As a result, the capacitor C1 and the capacitor C2 are connected in parallel.
Furthermore, the controller 39 functions as a control unit that controls the connection switching unit 31 and is configured as a logic circuit.

Next, the operation of the embodiment will be described.
FIG. 3 is a process flowchart of the cell voltage detection / balance circuit according to the embodiment.
In the initial state, the first high potential side switch SH1 to the fifth high potential side switch SH5, the first low potential side switch SL1 to the fifth low potential side switch SL5, the ground switch SL0, the voltage detection switch SAD, and the cell balance switch SCB are , All are in the open state (off state).

Further, it is assumed that the capacitor C1 and the capacitor C2 are in an uncharged state (charge = 0 state).
First, the controller 39 of the cell voltage detection / balance circuit 22 performs a cell voltage measurement process (step S11).

FIG. 4 is a process flowchart of the cell voltage measurement process.
First, the controller 39 sets parameter n = 1 for specifying any one of the battery cells CL1 to CL5 that are voltage measurement targets (step S21).
Next, the controller 39 connects the n-th battery cell CL1 from the low potential side, that is, the first battery cell CL1 to the capacitor C1 represented as a small capacitor in FIG. 4 (step S22).
Specifically, the controller 39 closes the first high potential side switch SH1 and the ground switch SL0 (on state).

Subsequently, the controller 39 determines whether or not a settling time sufficient for the capacitor C1 to be charged by the battery cell CL1 has elapsed (step S23).
If it is determined in step S23 that the settling time sufficient for the capacitor C1 to be charged by the battery cell CL1 has not elapsed (step S23; No), a standby state is entered.

If it is determined in step S23 that the settling time sufficient for the capacitor C1 to be charged by the battery cell CL1 has elapsed (step S23; Yes), the controller 39 disconnects the capacitor C1 from the battery cell CL1 (step S24). ).
Specifically, the controller 39 opens the first high potential side switch SH1 and the ground switch SL0 (off state).

Subsequently, the controller 39 connects the capacitor C1 to the buffer amplifier 36, and measures a voltage corresponding to the voltage of the battery cell CL1 (step S25).
Specifically, the controller 39 closes the voltage detection switch SAD and the ground switch SL0 (ON state). As a result, the voltage at the non-inverting input terminal of the buffer amplifier 36 becomes equal to the storage voltage of the capacitor C1, that is, the voltage of the battery cell CL1. At this time, since the input resistance of the buffer amplifier 36 is set high, an output voltage corresponding to the input voltage is output to the AD converter 38 without causing an error. Accordingly, the AD converter 38 performs analog / digital conversion of the voltage of the battery cell CL1 based on the internal reference voltage output from the internal reference voltage source 37, and outputs the digital voltage data (voltage measurement data) to the controller 39.

As a result, the controller 39 stores the digital voltage data in a built-in memory (not shown) (step S26).
Subsequently, the controller 39 adds 1 to the parameter n (step S27), and determines whether or not the value of the parameter n exceeds the number of battery cells (step S28).

In this case, since the parameter n = 2 and the number of battery cells does not exceed 5 (step S28; No), the controller 39 opens the voltage detection switch SAD and the ground switch SL0 (off state), The process again proceeds to step S22.
That is, the controller 39 connects the second battery cell CL2 to the capacitor C1 with the second high potential side switch SH2 and the ground switch SL0 closed (on state) (step S22).

  By the way, in this case, the capacitor C1 has a voltage corresponding to the voltage of the battery cell CL1. However, since the capacity of the battery cell CL2 is sufficiently larger than the capacity of the capacitor C1 (capacity of the battery cell CL2 >> capacitance of the capacitor C1), the voltage of the battery cell CL2 is temporarily higher than the voltage of the battery cell CL1. Is low, the influence of the charging power by the capacitor C1 on the voltage measurement of the battery cell CL2 is negligible (the same applies hereinafter).

  Then, the controller 39 determines whether or not the settling time sufficient for the capacitor C1 to be charged by the battery cell CL2 has elapsed (step S23), and is sufficient for the capacitor C1 to be charged by the battery cell CL2. When the settling time has elapsed (step S23; Yes), the controller 39 opens the second high potential side switch SH2 and the ground switch SL0 (off state) to disconnect the capacitor C1 from the battery cell CL2 (step S24). ).

  Subsequently, the controller 39 closes the voltage detection switch SAD and the ground switch SL0 (ON state), connects the capacitor C1 to the buffer amplifier 36, and measures a voltage corresponding to the voltage of the battery cell CL1 (step S25). The digital voltage data is stored in a built-in memory (not shown) (step S26).

  Subsequently, the controller 39 adds 1 to the parameter n (step S27), determines whether or not the value of the parameter n exceeds the number of battery cells (5 in this embodiment) (step S28). Since the number of battery cells does not exceed 5 (step S28; No), the controller 39 opens the voltage detection switch SAD and the ground switch SL0 (off state), and the process returns to step S22.

  Thereafter, similarly, the third high potential side switch SH3, the ground switch SL0, and the voltage detection switch SAD are sequentially controlled to measure the voltage of the battery cell CL3 as the third battery cell and store the digital voltage data. The fourth high potential side switch SH4, the ground switch SL0, and the voltage detection switch SAD are sequentially controlled to measure the voltage of the battery cell CL4, which is the fourth battery cell, and store the digital voltage data. The high potential side switch SH5, the ground switch SL0, and the voltage detection switch SAD are sequentially controlled to measure the voltage of the battery cell CL5, which is the fifth battery cell, and store the digital voltage data (step S26).

Subsequently, the controller 39 adds 1 to the parameter n (step S27), and determines whether or not the value of the parameter n exceeds the number of battery cells (step S28).
In this case, since parameter n = 6 and the number of battery cells exceeds 5 (step S28; Yes), the controller 39 opens the voltage detection switch SAD and the ground switch SL0 (off state). Then, the cell voltage measurement process is terminated, and it is determined whether or not the cell balance process is completed (step S12).
In this case, since the cell balance process has not been completed yet (step S12; No), the controller 39 shifts the process to the cell balance process (step S13).

FIG. 5 is a process flowchart of the cell balance process.
Here, the cell balance process shown in FIG. 5 corresponds to a voltage equalization method.
First, based on the stored digital voltage data, the controller 39 sets the battery cell having the highest voltage as the charge transfer source battery cell and the battery cell having the lowest voltage as the charge transfer destination battery cell among all the battery cells CL1 to CL5. (Step S31).

In the following description, it is assumed that the battery cell with the highest voltage is the battery cell CL2, and the battery cell with the lowest voltage is the battery cell CL4.
Therefore, it is assumed that the battery cell CL2 is a charge transfer source battery cell and the battery cell CL4 is a charge transfer destination battery cell.

First, the controller 39 connects the battery cell CL2, which is a charge transfer source battery cell, to the capacitor C1, which is a small-capacitance capacitor (step S32).
Specifically, the second high potential side switch SH2 and the ground switch SL0 are closed (on) and connected to the capacitor C1.
Subsequently, the controller 39 determines whether or not a settling time sufficient for the capacitor C1 to be charged by the battery cell CL2 has elapsed (step S33).

If it is determined in step S33 that the settling time sufficient for the capacitor C1 to be charged by the battery cell CL2 has not elapsed (step S33; No), a standby state is entered.
In the determination of step S33, when the settling time sufficient for the capacitor C1 to be charged by the battery cell CL2 has elapsed (step S33; Yes), the controller 39 opens all the switches (off state), The capacitor C1 is disconnected from the battery cell CL2 (step S34).

Subsequently, the controller 39 connects the capacitor C2 that is a large-capacitance capacitor and the capacitor C1 that is a small-capacitance capacitor (step S35). As a result, the capacitor C2 is initially charged while suppressing the inrush current.
Next, the controller 39 connects the capacitor C2, which is a large-capacity capacitor, to the buffer amplifier 36, and performs voltage measurement (step S36).
Specifically, the controller 39 closes the voltage detection switch SAD and the ground switch SL0 (on state), connects the capacitor C2 to the buffer amplifier 36, and measures the voltage of the capacitor C2.

Subsequently, the controller 39 determines whether or not the charging of the capacitor C2 that is a large-capacity capacitor by the capacitor C1 is completed, that is, the voltage of the capacitor C2 becomes equal to the voltage of the battery cell CL2 measured in the cell voltage measurement process S11. It is determined whether or not there is (step S37). That is, it is determined whether or not the initial charging of the capacitor C2 has been completed.
If it is determined in step S37 that the charging (initial charging) of the capacitor C2 that is a large-capacity capacitor by the capacitor C1 is not yet completed (step S37; No), the controller 39 shifts the process to step S32 again. Continue charging (initial charging).

  In the determination in step S37, when the charging (initial charging) of the capacitor C2 that is a large-capacity capacitor by the capacitor C1 is completed (step S37; Yes), the controller 39 determines the battery cell CL4 that is the charge transfer destination battery cell. The capacitor C2 that is a large capacity capacitor is connected (step S38).

  Specifically, the controller 39 opens all the switches (off state) and closes the third low potential side switch SL3, the fourth high potential side switch SH4, and the cell balance switch SCB (on state). Thereby, the electric charge of the capacitor C2 is transferred to the battery cell CL4 which is the charge transfer destination battery cell, and the voltage of the battery cell CL4 increases according to the capacity difference and the voltage difference between the battery cell CL4 and the capacitor C2.

Subsequently, the controller 39 determines whether or not a settling time sufficient for the battery cell CL4 to be charged by the capacitor C2 has elapsed (step S39).
If it is determined in step S39 that the settling time sufficient for the battery cell CL4 to be charged by the capacitor C2 has not elapsed (step S39; No), the controller 39 enters a standby state.

  In the determination in step S39, when the settling time sufficient for the battery cell CL4 to be charged by the capacitor C2 has elapsed (step S39; Yes), the controller 39 opens all the switches (off state), Voltage measurement is performed on the battery cell CL2 that is the charge transfer source battery cell and the battery cell CL4 that is the charge transfer destination battery cell (step S40).

Specifically, the process of step S22 to step S25 of FIG. 4 is performed for each of the battery cell CL2 and the battery cell CL4.
Subsequently, the controller 39 stores the digital voltage data corresponding to the battery cell CL2 which is the charge transfer source battery cell and the battery cell CL4 which is the charge transfer destination battery cell, as measurement results in a built-in memory (not shown) (step S41). .

Subsequently, the controller 39 compares the voltage of the battery cell CL2, which is the charge transfer source battery cell, with the voltage of the battery cell CL4, which is the charge transfer destination battery cell, and determines whether or not the voltage difference is equal to or less than a predetermined value. It discriminate | determines (step S42).
If it is determined in step S42 that the voltage difference between the voltage of the battery cell CL2 that is the charge transfer source battery cell and the voltage of the battery cell CL4 that is the charge transfer destination battery cell exceeds a predetermined value (step S42; No), since the transfer of charges has not been completed, the controller 39
The capacitor C2 is connected to the battery cell CL2 that is the charge transfer source battery cell (step S43).

Specifically, the controller 39 opens all the switches (off state) and closes the first low potential side switch SL1, the second high potential side switch SH2, and the cell balance switch SCB (on state).
Therefore, thereafter, the capacitor C2 is charged directly by the battery cell CL2 without going through the capacitor C1. In this case, the initial voltage of the capacitor C2 is the same as the voltage of the battery cell CL4. Therefore, unlike the initial state in which the capacitor C2 is empty, there is no possibility of inrush current.

Subsequently, the controller 39 determines whether or not a sufficient settling time has elapsed for the capacitor C2 as a large-capacity capacitor to be charged by the battery cell CL2 as the charge transfer source cell (step S44).
If it is determined in step S44 that the settling time sufficient for the capacitor C2 to be charged by the battery cell CL2 has not elapsed (step S44; No), the controller 39 enters a standby state.

  If it is determined in step S44 that the settling time sufficient for the capacitor C2 to be charged by the battery cell CL2 has passed (step S44; Yes), the controller 39 again transfers the charge by the capacitor C2, which is a large-capacitance capacitor. In order to charge the battery cell CL4 that is the destination cell, the battery cell CL4 that is the charge transfer destination battery cell is connected to the capacitor C2 that is a large-capacitance capacitor (step S38).

  As a result, the charge of the capacitor C2 is again transferred to the battery cell CL4, which is the charge transfer destination battery cell, and the voltage of the battery cell CL4 rises according to the capacity difference and the voltage difference between the battery cell CL4 and the capacitor C2.

Subsequently, the controller 39 determines whether or not a settling time sufficient for the battery cell CL4 to be charged by the capacitor C2 has elapsed (step S39).
If it is determined in step S39 that the settling time sufficient for the battery cell CL4 to be charged by the capacitor C2 has not elapsed (step S39; No), the controller 39 enters a standby state.

  In the determination in step S39, when the settling time sufficient for the battery cell CL4 to be charged by the capacitor C2 has elapsed (step S39; Yes), the controller 39 opens all the switches (off state), Voltage measurement is performed on the battery cell CL2 that is the charge transfer source battery cell and the battery cell CL4 that is the charge transfer destination battery cell (step S40).

  Subsequently, the controller 39 stores the digital voltage data corresponding to the battery cell CL2 which is the charge transfer source battery cell and the battery cell CL4 which is the charge transfer destination battery cell, as measurement results in a built-in memory (not shown), respectively (step S41). .

Next, the controller 39 compares the voltage of the battery cell CL2, which is the charge transfer source battery cell, with the voltage of the battery cell CL4, which is the charge transfer destination battery cell, and determines whether or not the voltage difference is equal to or less than a predetermined value. It discriminate | determines (step S42).
If it is determined in step S42 that the voltage difference between the voltage of the battery cell CL2 that is the charge transfer source battery cell and the voltage of the battery cell CL4 that is the charge transfer destination battery cell exceeds a predetermined value, the process is performed again. The process proceeds to step S43, and the same processing (step S43, step S44, step S38 to step S42) is repeated thereafter.

  On the other hand, if it is determined in step S42 that the voltage difference between the voltage of the battery cell CL2 that is the charge transfer source battery cell and the voltage of the battery cell CL4 that is the charge transfer destination battery cell is equal to or less than the predetermined value (step S42). Yes), since the cell balance process between the battery cell CL2 which is the charge transfer source battery cell and the battery cell CL4 which is the charge transfer destination battery cell is completed, the process returns to step S11 again.

  Then, the same processing (step S11 to step S13) is repeated, and when the cell balance processing end condition that the voltage difference of all the battery cells CL1 to CL5 is equal to or less than the specified value (step S12; Yes), the processing is performed. finish.

As described above, according to the first embodiment, when the initial capacitor C2 is empty, charging (initial charging) is performed by the charge transfer source battery cell via the capacitor C1, and the capacitor C2 is temporarily set. Since the capacitor C2 is directly charged by the charge transfer source battery cell after being charged, no inrush current is generated, so the first high potential side switches SH1 to SH5 There is no need to use the potential side switch SH5, the first low potential side switch SL1 to the fifth low potential side switch SL5, the ground switch SL0, the voltage detection switch SAD, the cell balance switch SCB, etc., and the wiring having a large current capacity, It is possible to reduce the size of the cell voltage detection / balance circuit 22 and, consequently, the size of the assembled battery system 12 as a whole.
Further, since the capacitor for initial charging of the large-capacitance capacitor C2 and the capacitor used for measuring the voltage of the battery cell are shared by the small-capacitance capacitor C1, the apparatus can be miniaturized and the cell balance processing can be achieved. The processing time can be shortened.

[2] Second Embodiment In the first embodiment, the battery system 10 having one battery block 21 has been described. However, when a higher voltage is required, a plurality of battery blocks are connected in series. It is conceivable to construct a battery system.

In this case, the cell balance processing is performed for each battery block from the relationship of the withstand voltage of the switch to be used.
However, when such a configuration is simply adopted, voltage balance cannot be achieved between the battery blocks, and in order to balance the voltage of the entire battery system, it is possible to discharge the block having a high voltage value. In addition, it is necessary to provide a passive block balance circuit separately, which increases the cost of the apparatus and is not desirable from the viewpoint of energy saving.

Therefore, the second embodiment is an embodiment in which cell balance can be actively performed between battery blocks.
FIG. 6 is a schematic configuration block diagram of the battery system of the second embodiment.
The battery system 50 is charged by receiving power from the external device 11 such as a charger via the high potential side terminal TH and the low potential side terminal TL, and also stores the power stored in the external device 11 such as a load. An assembled battery system 55 is provided through a high potential side terminal TH and a low potential side terminal TL.

  The assembled battery system 55 detects a plurality of battery blocks 51-1 and 51-2 having a plurality of battery cells, and the voltages of the battery cells constituting the battery blocks 51-1 and 51-2. A plurality of cell voltage detection / balance circuits 52-1 and 52-2 that perform cell balance processing to eliminate a bias in the storage capacity (remaining power storage amount) and a plurality of cell voltage detection / balance circuits 52-1 and 52-2. And a capacitor C1 used for voltage detection of the battery cell with a relatively small capacity compared to the capacity of the battery cell constituting each of the battery blocks 51-1, 51-2, and the capacitor C1. And a large-capacity capacitor C2.

Here, the battery block 51-1 which is the first battery block and the battery block 51-2 which is the second battery block are connected in series.
In the above configuration, the cell voltage detection / balance circuit 52-1, the connection switching unit 61, the controller 69, the first capacitor C1 and the second capacitor C2 connected to the cell voltage detection / balance circuit 52-1, Is configured.

  The cell voltage detection / balance circuit 52-2, the connection switching unit 81, the controller 89, and the first capacitor C1 and the second capacitor C2 connected to the cell voltage detection / balance circuit 52-1, Another voltage equalizing apparatus is configured.

FIG. 7 is a schematic configuration diagram of the assembled battery system of the second embodiment.
For example, as shown in FIG. 7, the battery block 51-1 of the assembled battery system 55 includes a battery cell CL1 between the low potential side terminal TL and the high potential side terminal TH from the low potential side toward the high potential side. ~ CL5 are connected in series.

A connection point between the low potential side terminal TL and the negative terminal of the battery cell CL1 is grounded via the VSS terminal VSSa of the cell voltage detection / balance circuit 52-1.
A connection point between the positive electrode terminal of the battery cell CL1 and the negative electrode terminal of the battery cell CL2 is connected to the first input terminal VIN1a of the cell voltage detection / balance circuit 52-1, via the current limiting resistor R.

A connection point between the positive electrode terminal of the battery cell CL2 and the negative electrode terminal of the battery cell CL3 is connected to the second input terminal VIN2a of the cell voltage detection / balance circuit 52-1 through the current limiting resistor R.
A connection point between the positive terminal of the battery cell CL3 and the negative terminal of the battery cell CL4 is connected to the third input terminal VIN3a of the cell voltage detection / balance circuit 52-1 via the current limiting resistor R.

  A connection point between the positive terminal of the battery cell CL4 and the negative terminal of the battery cell CL5 is connected to the fourth input terminal VIN4a of the cell voltage detection / balance circuit 52-1 through the current limiting resistor R.

  A connection point between the positive terminal of the battery cell CL5 and the negative terminal of the battery cell CL6 is connected to the fifth input terminal VIN5a of the cell voltage detection / balance circuit 22 via the current limiting resistor R. Furthermore, the connection point between the positive electrode terminal of the battery cell CL5 and the high potential side terminal TH is connected to the power supply terminal VCCa of the cell voltage detection / balance circuit 52-1 through a wire parallel to the current limiting resistor R.

  Similarly, the battery block 51-2 of the assembled battery system 55 is, for example, as shown in FIG. 7, between the low potential side terminal TL and the high potential side terminal TH, from the low potential side toward the high potential side. Battery cells CL6 to CL10 are connected in series. The negative terminal of the battery cell CL6 is connected to the positive terminal of the battery cell CL5 of the battery block 51-1.

A connection point between the negative electrode terminal of the battery cell CL6 and the positive electrode terminal of the battery cell CL5 is grounded via the VSS terminal VSSb of the cell voltage detection / balance circuit 52-2.
A connection point between the positive terminal of the battery cell CL6 and the negative terminal of the battery cell CL7 is connected to the first input terminal VIN1b of the cell voltage detection / balance circuit 52-2 via the current limiting resistor R.

A connection point between the positive terminal of the battery cell CL7 and the negative terminal of the battery cell CL8 is connected to the second input terminal VIN2b of the cell voltage detection / balance circuit 52-2 via the current limiting resistor R.
A connection point between the positive terminal of the battery cell CL8 and the negative terminal of the battery cell CL9 is connected to the third input terminal VIN3b of the cell voltage detection / balance circuit 52-2 via the current limiting resistor R.

  A connection point between the positive terminal of the battery cell CL9 and the negative terminal of the battery cell CL10 is connected to the fourth input terminal VIN4b of the cell voltage detection / balance circuit 52-2 via the current limiting resistor R.

  A connection point between the positive electrode terminal of the battery cell CL10 and the high potential side terminal TH is connected to the fifth input terminal VIN5b of the cell voltage detection / balance circuit 52-2 via the current limiting resistor R. Furthermore, the connection point between the positive electrode terminal of the battery cell CL5 and the high potential side terminal TH is connected to the power supply terminal VCCb of the cell voltage detection / balance circuit 52-2 via a wire parallel to the current limiting resistor R.

  The cell voltage detection / balance circuit 52-1 can be broadly classified according to the temperature of the battery block 51-1 and the connection switching unit 61 that selectively switches and connects the battery cells to be measured, charged, or discharged. A temperature sensor 62 that outputs the detected signal, a temperature detection circuit 63 that detects the temperature of the battery block 51-1 based on the output signal of the temperature sensor 62, and a booster that boosts the supplied power supply voltage VCCa and outputs the boosted voltage to each unit. A circuit 64; a VDD regulator 65 that stabilizes the power supply voltage VCCa and outputs the stabilized power supply VDDa to each unit; a buffer amplifier 66 that outputs a voltage corresponding to the storage voltage of the capacitor C1; and an internal reference voltage from the power supply voltage VCCa. An internal reference voltage source 67 that is generated and output, and a buffer amplifier 6 based on the internal reference voltage output from the internal reference voltage source 67 AD converter 68 that performs analog / digital conversion of the output voltage of the output voltage and outputs it as voltage data, and controls the entire cell voltage detection / balance circuit 52-1 including control of the connection switching unit 31 based on the output of the AD converter 68. The controller 69 to perform and the 1st communication interface 70 and the 2nd communication interface 71 which communicate between the exterior are provided.

In the above configuration, the connection switching unit 61 includes the first high potential side switch SH1a to the sixth high potential side switch SH6a, the first low potential side switch SL1a to the fifth low potential side switch SL5a, the ground switch SL0a, and the current limiting resistor R1a. A voltage detection switch SADa and a cell balance switch SCBa are provided.
The buffer amplifier 66, the internal reference voltage source 67, and the AD converter 68 constitute a voltage measuring unit.
The capacitor C1 is connected between the capacitor connection terminal HCPa and the capacitor connection terminal HCNa, and the capacitor C2 is connected between the capacitor connection terminal HCNa and the capacitor connection terminal BCa. As a result, the capacitor C1 and the capacitor C2 Are connected in parallel.

  Similarly, the cell voltage detection / balance circuit 52-2 can be broadly divided into a connection switching unit 81 that selectively switches and connects battery cells to be voltage-measured, charged or discharged, and a battery block 51-2. A temperature sensor 82 that outputs a signal corresponding to the temperature, a temperature detection circuit 83 that detects the temperature of the battery block 51-2 based on the output signal of the temperature sensor 82, and the voltage of the supplied power supply VCCb are boosted. From the power supply voltage VCCb, a VDD regulator 85 that stabilizes the power supply voltage VCCb and outputs it to each unit as a stabilized power supply VDDb, a buffer amplifier 86 that outputs a voltage corresponding to the storage voltage of the capacitor C1, and the power supply voltage VCCb. An internal reference voltage source 87 that generates and outputs an internal reference voltage, and a buffer based on the internal reference voltage output from the internal reference voltage source 87 An AD converter 88 that performs analog / digital conversion of the output voltage of the amplifier 86 and outputs it as voltage data, and the entire cell voltage detection / balance circuit 52-2 including control of the connection switching unit 81 based on the output of the AD converter 88 A controller 89 that performs control, and a first communication interface 90 and a second communication interface 91 that perform communication with the outside are provided.

In the above configuration, the connection switching unit 81 includes the first high potential side switch SH1b to the sixth high potential side switch SH6b, the first low potential side switch SL1b to the fifth low potential side switch SL5b, the ground switch SL0b, and the current limiting resistor R1b. A voltage detection switch SADb and a cell balance switch SCBb are provided.
The buffer amplifier 86, the internal reference voltage source 87, and the AD converter 88 constitute a voltage measuring unit.
The capacitor C1 is connected between the capacitor connection terminal HCPb and the capacitor connection terminal HCNb, and the capacitor C2 is connected between the capacitor connection terminal HCNb and the capacitor connection terminal BCb. As a result, the capacitor C1 and the capacitor C2 are connected. Are connected in parallel.

Next, the operation of the second embodiment will be described.
Since the operation of the second embodiment is basically the same as the operation of the first embodiment, only the main operation portion will be described with reference to FIGS. 4 and 5 again.
The cell voltage detection / balance circuit 52-1 measures the voltages of the battery cells CL1 to CL5 according to the processing procedure shown in FIG. 4 and stores the digital voltage data.

  Further, the cell voltage detection / balance circuit 52-1 sequentially controls the sixth high potential side switch SH6a, the ground switch SL0a, and the voltage detection switch SADa, and is the battery cell that is the first battery cell of the battery block 51-2. Measure CL6 voltage and store digital voltage data.

On the other hand, the cell voltage detection / balance circuit 52-2 measures the voltages of the battery cells CL6 to CL10 according to the processing procedure shown in FIG. 4 and stores the digital voltage data.
Then, the cell voltage detection / balance circuit 52-1 and the cell voltage detection / balance circuit 52-2 shift to the cell balance process (step S13) because the cell balance process has not been completed yet.

Next, the cell balance process will be described with reference to FIG. 5 again.
In the following description, only the operation of the cell voltage detection / balance circuit 52-1 will be mainly described.
First, based on the stored digital voltage data, the controller 69 of the cell voltage detection / balance circuit 52-1 has the highest voltage among all the battery cells CL1 to CL5 and the battery cell CL6 of the battery block 51-2. Is the charge transfer source battery cell, and the battery cell having the lowest voltage is the charge transfer destination battery cell (step S31).

In the following description, it is assumed that the battery cell having the highest voltage is the battery cell CL2, and the battery cell having the lowest voltage is the battery cell CL6.
Therefore, it is assumed that the battery cell CL2 is a charge transfer source battery cell and the battery cell CL6 is a charge transfer destination cell.

  First, the controller 69 of the cell voltage detection / balance circuit 52-1 connects the battery cell CL2, which is a charge transfer source battery cell, to the capacitor C1, which is a small-capacitance capacitor (step S32).

  Subsequently, the controller 69 performs the processing from step S32 to step S37, and when the charging of the capacitor C2 which is a large-capacity capacitor by the capacitor C1 is completed (step S37; Yes), the controller 69 performs the charge transfer destination battery. The battery cell CL6 of the battery block 51-2 that is a cell is connected to the capacitor C2 that is a large-capacity capacitor (step S38).

  Specifically, the controller 69 opens all the switches (off state) and closes the fifth low potential side switch SL5a, the sixth high potential side switch SH6a, and the cell balance switch SCBa (on state). Thereby, the electric charge of the capacitor C2 is transferred to the battery cell CL6 which is the charge transfer destination battery cell, and the voltage of the battery cell CL6 rises according to the capacity difference and the voltage difference between the battery cell CL6 and the capacitor C2.

  Subsequently, the controller 69 determines whether or not the settling time sufficient for the battery cell CL6 to be charged by the capacitor C2 has elapsed (step S39), and is sufficient for the battery cell CL6 to be charged by the capacitor C2. When the settling time has elapsed (step S39; Yes), the controller 69 opens all the switches (off state), and the battery cell CL2 that is the charge transfer source battery cell and the battery cell that is the charge transfer destination battery cell. The voltage of CL6 is measured (step S40).

Subsequently, the controller 69 stores the digital voltage data corresponding to the battery cell CL2 which is the charge transfer source battery cell and the battery cell CL6 which is the charge transfer destination battery cell in the built-in memory (not shown) as a measurement result (step S41). .
Subsequently, the controller 69 compares the voltage of the battery cell CL2, which is the charge transfer source battery cell, with the voltage of the battery cell CL6, which is the charge transfer destination battery cell, and determines whether or not the voltage difference is equal to or less than a predetermined value. It discriminate | determines (step S42).

If it is determined in step S42 that the voltage difference between the voltage of the battery cell CL2 that is the charge transfer source battery cell and the voltage of the battery cell CL6 that is the charge transfer destination battery cell exceeds a predetermined value (step S42; No) Since the charge transfer is not completed, the controller 69
The capacitor C2 is connected to the battery cell CL2 that is the charge transfer source battery cell (step S43).

Next, the controller 69 shifts the process to step S36 again, connects the capacitor C2 which is a large-capacitance capacitor to the buffer amplifier 36, and performs voltage measurement (step S36).
Subsequently, the controller 69 determines whether or not the charging of the capacitor C2 that is a large-capacity capacitor by the capacitor C1 is completed, that is, whether or not the voltage of the capacitor C2 is equal to the voltage of the battery cell CL2 measured in step S40. Is discriminated (step S37).

If it is determined in step S37 that the charging of the capacitor C2, which is a large-capacity capacitor, by the battery cell CL2 has not been completed, the controller 69 enters a standby state.
In the determination in step S37, when the charging of the capacitor C2 that is a large-capacity capacitor by the battery cell CL2 is completed (step S37; Yes), the controller 69 replaces the battery cell CL6 that is the charge transfer destination battery cell with the large-capacity capacitor. Is connected to the capacitor C2 (step S38).

Thereby, the electric charge of the capacitor C2 is transferred to the battery cell CL6 which is a transfer destination cell, and the voltage of the battery cell CL6 increases according to the capacity difference and the voltage difference between the battery cell CL6 and the capacitor C2.
Subsequently, the controller 69 determines whether or not the settling time sufficient for the battery cell CL6 to be charged by the capacitor C2 has elapsed (step S39), and is sufficient for the battery cell CL6 to be charged by the capacitor C2. When the settling time has elapsed (step S39; Yes), the controller 69 opens all the switches (off state), and the battery cell CL2 that is the charge transfer source battery cell and the battery cell that is the charge transfer destination battery cell. The voltage of CL6 is measured (step S40).

  Subsequently, the controller 69 stores the digital voltage data corresponding to the battery cell CL2 which is the charge transfer source battery cell and the battery cell CL6 which is the charge transfer destination battery cell in the built-in memory (not shown) as a measurement result (step S41). .

Subsequently, the controller 69 compares the voltage of the battery cell CL2, which is the charge transfer source battery cell, with the voltage of the battery cell CL6, which is the charge transfer destination battery cell, and determines whether or not the voltage difference is equal to or less than a predetermined value. It discriminate | determines (step S42).
In the determination of step S42, if the voltage difference between the voltage of the battery cell CL2 that is the charge transfer source battery cell and the voltage of the battery cell CL6 that is the charge transfer destination battery cell exceeds a predetermined value, step S43, After the capacitor C2 is directly charged by the battery cell CL2 through the process of step S44, the process proceeds to step S38 again, and the same process is repeated thereafter.

  On the other hand, if it is determined in step S42 that the voltage difference between the voltage of the battery cell CL2 that is the charge transfer source battery cell and the voltage of the battery cell CL6 that is the charge transfer destination battery cell is equal to or less than the predetermined value (step S42). Yes), since the cell balance process between the battery cell CL2 which is the charge transfer source battery cell and the battery cell CL6 which is the charge transfer destination battery cell is completed, the process returns to step S11 again.

  Thereafter, the same processing (steps S11 to S13) is repeated, and the cell balance processing end condition is satisfied in which the voltage difference between all the battery cells CL1 to CL5 and the battery cell CL6 of the battery block 51-2 is equal to or less than a specified value. (Step S12; Yes), the process is terminated.

However, in parallel with this, the battery block 51-2 also has its own cell balance processing. Therefore, when the voltage difference of the battery cell CL6 of the battery block 51-2 occurs again, the cell balance processing is performed. Will be continued.
That is, the cell balance process works across the blocks even between the battery block 51-1 and the battery block 51-2.

  As a result, the cell balance process proceeds, and the voltage difference between the battery cells CL1 to CL5 constituting the battery block 51-1 and the battery cells CL6 to CL10 constituting the battery block 51-2 is equal to or less than the specified value. If the cell balance process end condition is satisfied (step S12; Yes), the process ends.

  As described above, according to the second embodiment, in addition to the effects of the first embodiment, even when a plurality of battery blocks are provided, it is possible to achieve cell balance of the entire battery block.

  As described above, the present invention has been described based on the embodiments. However, these embodiments are exemplifications, and various modifications can be made to the respective components and combinations thereof, and such modifications are also included in the present invention. It will be understood by those skilled in the art that it is in the range.

  In the above description, when the capacitor C2 is initially charged using the capacitor C1 as a small-capacitance capacitor, the capacitor C1 is charged by the high-voltage side battery cell as the charge transfer source battery cell, and the capacitor C2 However, it is also possible to use a configuration in which the capacitor C1 is charged by a low-voltage side battery cell as a charge transfer destination and the capacitor C2 is initially charged.

  In the above description, the battery cell having the highest voltage and the battery cell having the lowest voltage are connected via the capacitor C2 to achieve cell balance. The cell balance is taken in order via the capacitor C2, the battery cell with the maximum voltage → the battery cell with the minimum voltage, the battery cell with the second highest voltage → the battery cell with the second lowest voltage, and so on. It is also possible to configure such that a predetermined order is determined in advance in the wind and cell balance is achieved via the capacitor C2.

  In the above description, the controllers 39, 69, and 89 are configured as logic circuits. However, the controllers 39, 69, and 89 are configured as a microprocessor unit (MPU) equipped with a CPU, ROM, RAM, communication interface, input / output port, and the like. It can also be configured to operate by a program.

In the above description, a plurality of switches constituting the connection switching units 31, 61, 81, that is, any one of the plurality of battery cells, the capacitor C1 (first capacitor), or the capacitor C2 ( Although the configuration of each of the plurality of switches that can selectively connect any two of the second capacitors) has not been described in detail, it is configured to use a semiconductor switch like a MOSFET. Is also possible. According to this configuration, the device can be further reduced in size.
Furthermore, the entire cell voltage detection / balance circuit 22, 52-1, 52-2 (= corresponding to the connection switching unit and the control unit) can be configured as a semiconductor IC. According to this configuration, the device can be further reduced in size.

10, 50 Battery system 11 External device 12, 55 Assembly battery system 21 Battery block 22, 52-1, 52-2 Cell voltage detection / balance circuit (voltage equalization device)
31, 61, 81 Connection switching unit (switching control unit, voltage equalization device)
32, 62, 82 Temperature sensor 36, 66, 86 Buffer amplifier (voltage measuring unit)
37, 67, 87 Internal reference voltage source (voltage measurement unit)
38, 68, 88 AD converter (voltage measurement unit)
39, 69, 89 Controller (control unit, switching control unit, voltage equalization device)
51-1 battery block (first battery block)
51-2 battery block (second battery block)
C1 capacitor (first capacitor [small capacitor], voltage equalization device)
C2 capacitor (second capacitor [capacitor], voltage equalization device)
CL1 to CL10 Battery cells SH1 to SH5 First high potential side switch to fifth high potential side switch SH1a to SH6a First high potential side switch to sixth high potential side switch SH1b to SH6b First high potential side switch to sixth high Potential side switches SL1 to SL4 First low potential side switch to fourth low potential side switch SL1a to SL5a First low potential side switch to fifth low potential side switch SL1b to SL5b First low potential side switch to fifth low potential side Switch SL0, SL0a, SL0b Ground switch SAD, SADA, SADb Voltage detection switch SCB, SCBa, SCBb Cell balance switch

Claims (5)

Voltage equalization for performing voltage equalization of the plurality of battery cells by repeating the process of transferring the charge of any one of the plurality of battery cells connected in series to the other battery cell A device,
A first capacitor having a capacity smaller than the capacity of the battery cell;
A second capacitor capable of being connected in parallel to the first capacitor and having a capacity greater than that of the first capacitor;
Prior to transferring the charge of the transfer source battery cell to the transfer destination battery cell via the second capacitor, the storage voltage of the second capacitor is equal to the voltage of the transfer source battery cell. A switching control unit that repeats the process of transferring the charge of the battery cell of the transfer source to the second capacitor through the first capacitor until
A voltage equalization apparatus comprising: The switching control unit includes a plurality of switches capable of selectively simultaneously connecting any one of the plurality of battery cells, the first capacitor, or the second capacitor. A connection switching unit provided;
A control unit for controlling the connection switching unit;
The voltage equalizing apparatus according to claim 1, further comprising: The connection switching unit includes the plurality of battery cells as a first battery block, and is configured by a plurality of battery cells to be voltage equalized by another voltage equalization device on the high potential side of the first battery block. When the second battery block is connected, the battery cell on the lowest potential side among the battery cells constituting the second battery block can be selected.
The voltage equalization apparatus according to claim 2. A voltage measuring unit capable of measuring the voltage of the battery cell;
When measuring the voltage of each of the plurality of battery cells, the first capacitor is used to measure the voltage of each battery cell by transferring the charge of each battery cell,
The voltage equalization apparatus as described in any one of Claims 1 thru | or 3. Voltage equalization for performing voltage equalization of the plurality of battery cells by repeating the process of transferring the charge of any one of the plurality of battery cells connected in series to the other battery cell A voltage equalization method performed in the apparatus,
The voltage equalization apparatus is capable of being connected in parallel to a first capacitor having a capacity smaller than the capacity of the battery cell, and a capacity larger than the capacity of the first capacitor. 2 capacitors,
Until the stored voltage of the second capacitor reaches the voltage of the transfer source battery cell, the process of transferring the charge of the transfer source battery cell to the second capacitor through the first capacitor is repeated. Process,
The charge of the transfer source battery cell is transferred to the transfer destination battery cell via the second capacitor until the voltage of the transfer destination battery cell becomes the voltage of the transfer source battery cell. The process of repeating the process,
A voltage equalization method comprising:

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