JP6232836B2 - Capacitor element - Google Patents

Description

  The present invention relates to a capacitor element as an electronic component, and more specifically to a capacitor element in which dielectric layers and internal electrode layers are alternately stacked along a predetermined direction.

  Conventionally, a capacitor element has been used as an electronic component for removing noise superimposed on an electronic circuit. This type of capacitor element is called a bypass capacitor or a decoupling capacitor, and is provided in an electronic circuit so as to connect a power supply line and a ground (ground line).

  For example, a DC / DC converter mounted on an electronic device converts a direct current voltage into a predetermined direct current voltage suitable for each electronic device and supplies it as electric power. A capacitor element represented by a multilayer ceramic capacitor is connected to the circuit in order to reduce noise generated based on the switching operation.

  A general capacitor element is also called a two-terminal capacitor, and connects one of a pair of internal electrode layers adjacent to each other in the stacking direction to one of a pair of external electrodes and the other of a pair of external electrodes. Connected to the other of the two. In the two-terminal capacitor, a capacitor element is configured by the pair of internal electrode layers, and the capacitor element is electrically connected in parallel to increase the capacitance.

  One of the structures that can improve the reliability of the capacitor element is a so-called series structure. In the series structure, each of a plurality of capacitor elements electrically connected in parallel inside the capacitor element is composed of a plurality of capacitor elements electrically connected in series. By using a capacitor element having such a series structure, even when dielectric breakdown occurs in one of the capacitor elements connected in series, electrical insulation is maintained by the other capacitor element. High reliability will be obtained. As a document disclosing a capacitor element having the series structure, there is, for example, Japanese Patent Laid-Open No. 8-37126 (Patent Document 1).

  Furthermore, as a capacitor element in which ESL (equivalent series inductance) which is a parasitic component of the capacitor element is reduced, there is a so-called feedthrough capacitor. The ESL which is a parasitic component can be reduced by shortening the wiring part included in the capacitor element or the wiring part of the wiring board connected to the capacitor element. One of a pair of internal electrode layers adjacent along the stacking direction is an internal electrode layer (through electrode layer) electrically connected in series to the power supply line, and the other is an internal electrode connected to the ground By forming the layers, the capacitor element constituted by the pair of internal electrode layers and the power supply line (that is, the through electrode layer) are arranged as close as possible to reduce unnecessary wiring, thereby reducing the ESL. It has been. In addition, as a document in which the feedthrough capacitor is disclosed, for example, there is JP-A-2005-44871 (Patent Document 2).

JP-A-8-37126 JP 2005-44871 A

  Conventionally, as a circuit configuration for obtaining the advantages of both the above-described high reliability and low ESL, the above-described ordinary two-terminal capacitor is interposed between the external electrode connected to the ground of the feedthrough capacitor and the ground. Some of the configurations are used.

  However, since the circuit configuration is such that a two-terminal capacitor is installed between the feedthrough capacitor and the ground, the wiring portion included in the two-terminal capacitor and the feedthrough capacitor and the two-terminal capacitor are connected. Therefore, the wiring portion of the wiring board is provided as an extra wiring portion between the power supply line and the ground, and as a result, the low ESL cannot be sufficiently achieved, and the through-type capacitor has a low There has been a problem that the ESL characteristics are greatly impaired.

  In order to realize the above circuit configuration, a feedthrough capacitor and at least one two-terminal capacitor need to be mounted on the wiring board, so that a space for mounting these becomes large. There is also a problem that leads to an increase in the size of the wiring board.

  Therefore, the present invention has been made to solve the above-described problems, and an object thereof is to provide a capacitor element that achieves both high reliability and low ESL.

The capacitor element according to the present invention has a substantially rectangular parallelepiped laminated body including dielectric layers and internal electrode layers alternately laminated along a first direction, and a second direction perpendicular to the first direction. A first external electrode provided on one of a pair of first side surfaces of the laminated body positioned, a second external electrode provided on the other, and a third direction orthogonal to the first direction and the second direction. And a third external electrode provided on at least one of the pair of second side surfaces of the laminated body positioned opposite to each other. The internal electrode layer includes a first internal electrode layer connected to the first external electrode and the second external electrode and not connected to the third external electrode; the first external electrode; the second external electrode; A second internal electrode layer not connected to any of the third external electrodes; and a third internal electrode layer connected to the third external electrode and not connected to the first external electrode and the second external electrode. It is out. In the capacitor element according to the present invention, the first capacitor element is configured by disposing the first internal electrode layer and the second internal electrode layer so as to face each other along the first direction. The second capacitor element is configured by arranging the second internal electrode layer and the third internal electrode layer to face each other along the first direction, whereby the first external electrode and the second internal electrode layer are formed. The first capacitor element and the second capacitor element are electrically connected in series between the external electrode and the third external electrode. Here, the internal electrode layer includes a through electrode layer formed so as to penetrate the stacked body along the second direction or the third direction, and the through electrode layer includes two or less types. is there.

  In the capacitor element according to the present invention, the first internal electrode layer and the third internal electrode layer may be provided on the same plane orthogonal to the first direction. The first internal electrode layer overlaps a part of the second internal electrode layer when viewed along the first direction, and the third internal electrode layer extends along the first direction. When viewed, it preferably overlaps with the other part of the second internal electrode layer.

  In the capacitor element according to the present invention, the second internal electrode layer may be provided between the first internal electrode layer and the third internal electrode layer along the first direction. In this case, it is preferable that the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer overlap each other when viewed along the first direction.

  In the capacitor element according to the present invention, it is preferable that the third external electrode is provided on either of the pair of second side surfaces of the multilayer body.

  In the capacitor element according to the present invention, the dielectric layer is preferably made of a ceramic material.

  According to the present invention, it is possible to provide a capacitor element that achieves both high reliability and low ESL.

1 is a perspective view of a multilayer ceramic capacitor in Embodiment 1 of the present invention. It is a figure which shows the equivalent circuit of the multilayer ceramic capacitor in Embodiment 1 of this invention. It is a disassembled perspective view which shows the structure of the laminated body shown in FIG. It is a cross-sectional view of a portion including a signal internal electrode layer and a ground internal electrode layer of the multilayer ceramic capacitor in accordance with the first exemplary embodiment of the present invention. It is a cross-sectional view of the portion including the floating internal electrode layer of the multilayer ceramic capacitor in Embodiment 1 of the present invention. FIG. 6 is a longitudinal sectional view of the multilayer ceramic capacitor according to the first embodiment of the present invention, taken along line VI-VI shown in FIGS. 4 and 5. It is a disassembled perspective view which shows the structure of the laminated body of the laminated ceramic capacitor which concerns on the modification based on Embodiment 1 of this invention. It is a disassembled perspective view which shows the structure of the laminated body of the laminated ceramic capacitor in Embodiment 2 of this invention. It is a cross-sectional view of the portion including the signal internal electrode layer of the multilayer ceramic capacitor in the second embodiment of the present invention. It is a cross-sectional view of the portion including the floating internal electrode layer of the multilayer ceramic capacitor in the second embodiment of the present invention. It is a cross-sectional view of the portion including the grounding internal electrode layer of the multilayer ceramic capacitor in the second embodiment of the present invention. It is a longitudinal cross-sectional view along the XII-XII line | wire shown to FIG. 9 thru | or FIG. 11 of the laminated ceramic capacitor in Embodiment 2 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Examples of the capacitor element to which the present invention can be applied include a multilayer ceramic capacitor using a ceramic material as a dielectric material and a multilayer metallized film capacitor using a resin film as a dielectric material. In this embodiment, a case where the present invention is applied to a multilayer ceramic capacitor will be described as an example. In the following embodiments, the same or common parts are denoted by the same reference numerals in the drawings, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a perspective view of the multilayer ceramic capacitor according to Embodiment 1 of the present invention, and FIG. 2 is a diagram showing an equivalent circuit of the multilayer ceramic capacitor shown in FIG. FIG. 3 is an exploded perspective view showing the structure of the laminate shown in FIG. 4 is a cross-sectional view of the portion including the signal internal electrode layer and the ground internal electrode layer of the multilayer ceramic capacitor shown in FIG. 1, and FIG. 5 is a cross-sectional view of the portion including the floating internal electrode layer. . FIG. 6 is a longitudinal sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line VI-VI shown in FIGS.

  As shown in FIG. 1, the multilayer ceramic capacitor 1 </ b> A in the present embodiment is an electronic component having a substantially rectangular parallelepiped shape as a whole, and includes a multilayer body 10 </ b> A, a signal first external electrode 15 as a first external electrode, It has the signal 2nd external electrode 16 as a 2nd external electrode, and a pair of grounding external electrodes 17 and 17 as a 3rd external electrode.

  As shown in FIG. 2, the first signal external electrode 15 and the second signal external electrode 16 are electrically connected inside the multilayer ceramic capacitor 1A, and no capacitor element is interposed therebetween. On the other hand, a first capacitor element 18A and a second capacitor element 18B are interposed between the first signal external electrode 15 and the second signal external electrode 16 and the pair of ground external electrodes 17 and 17, respectively. The first capacitor element 18A and the second capacitor element 18B are electrically connected in series.

  Here, in the multilayer ceramic capacitor 1A according to the present embodiment, for example, the first external electrode for signal 15 and the second external electrode for signal 16 are electrically connected in series to the power line, and a pair of ground externals Each of the electrodes 17 and 17 is connected to the ground (ground line).

  Thereby, the multilayer ceramic capacitor 1A becomes a through-type multilayer ceramic capacitor having a series structure. Hereinafter, the detailed structure of the multilayer ceramic capacitor 1A in the present embodiment will be described.

  As shown in FIGS. 1 and 4 to 6, the laminated body 10 </ b> A has a substantially rectangular parallelepiped shape, and is a pair of main bodies positioned relative to each other along the Z-axis direction shown in the drawing as the first direction. A pair of first side surfaces 3 and 3 that are positioned relative to each other along the X-axis direction shown in the figure as a second direction perpendicular to the first direction, and the first direction and the second direction. It has a pair of 2nd side surfaces 4 and 4 located facing along the Y-axis direction shown in the figure as the orthogonal | vertical 3rd direction.

  As shown in FIG. 6, the stacked body 10 </ b> A includes dielectric layers 11 and internal electrode layers 12, 13, and 14 that are alternately stacked along the first direction (that is, the Z-axis direction). As shown in FIG. 3, the laminated body 10A is manufactured using a material sheet group 20A composed of a plurality of material sheets 21A, 21B, and 21C having different configurations, and more specifically, a plurality of material sheets 21A having different configurations. , 21B, 21C are laminated in a predetermined order, and are manufactured by pressure bonding and firing. The details will be described later.

  Dielectric layer 11 is made of, for example, a ceramic material mainly composed of barium titanate. In addition, the dielectric layer 11 may contain a Mn compound, Mg compound, Si compound, Co compound, Ni compound, rare earth compound, and the like as subcomponents of ceramic powder that is a raw material of the ceramic sheet described later. On the other hand, the internal electrode layers 12, 13, and 14 are made of, for example, Ni which is a metal material.

The material of the dielectric layer 11 is not limited to the above-described ceramic material mainly composed of barium titanate, and other high dielectric constant ceramic materials (for example, CaTiO ₃ , SrTiO ₃ , CaZrO _3, etc.) are mainly used. May be selected as the material of the dielectric layer 11. The material of the internal electrode layers 12, 13, 14 is not limited to Ni described above, and other conductive materials such as Cu, Ag, Pd, Ag—Pd alloy, Au, etc., which are metal materials, are used as the internal electrode layers 12, 13. , 14 may be selected.

  As shown in FIGS. 1, 4 and 5, the signal first external electrode 15 and the signal second external electrode 16 are provided apart from each other so as to cover the first side surfaces 3 and 3 of the multilayer body 10A. ing. More specifically, the signal first external electrode 15 includes one first side surface 3 of the laminated body 10 </ b> A and the one first side surface 3 of the pair of main surfaces 2, 2 and the pair of second side surfaces 4, 4. The signal second external electrode 16 includes the other first side surface 3 of the multilayer body 10A, the pair of main surfaces 2 and 2, and the pair of second side surfaces 4 and 4. Is provided so as to cover the portion of the other side closer to the first side surface 3.

  On the other hand, as shown in FIGS. 1 and 4 to 6, the pair of grounding external electrodes 17, 17 are provided so as to be separated from each other so as to cover the second side surfaces 4, 4 of the multilayer body 10 </ b> A. More specifically, one of the pair of grounding external electrodes 17, 17 includes a central portion along the X-axis direction of one second side surface 4 of the laminated body 10 </ b> A and the pair of main surfaces 2, 2. One of the pair of grounding external electrodes 17 and 17 is provided so as to cover the central portion along the X-axis direction near one second side surface 4, and the other second side surface of the stacked body 10A. 4 is provided so as to cover the central portion along the X-axis direction and the central portion along the X-axis direction near the other second side surface 4 of the pair of main surfaces 2 and 2.

  The first signal external electrode 15, the second signal external electrode 16, and the pair of ground external electrodes 17, 17 are each formed of a conductive film, for example, a sintered metal layer and a metal film of a plating layer Composed. A sintered metal layer is formed by baking pastes, such as Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, for example. A plating layer is comprised by the Ni plating layer and the Sn plating layer which covers this, for example. Instead of this, the plated layer may be a Cu plated layer or an Au plated layer. Further, the first signal external electrode 15, the second signal external electrode 16, and the pair of ground external electrodes 17 and 17 may be formed of only a plating layer or a conductive resin paste. Also good.

  Here, as shown in FIG. 1, the first direction (that is, the Z-axis direction) that is the stacking direction of the dielectric layer 11 and the internal electrode layers 12, 13, and 14 in the stacked body 10 </ b> A is usually as the thickness direction T. The second direction (that is, the X-axis direction) that is defined and is the direction in which the first signal external electrode 15 and the second signal external electrode 16 are arranged is usually defined as the length direction L, and a pair of ground external electrodes The third direction (that is, the Y-axis direction), which is the direction in which 17 and 17 are arranged, is usually defined as the width direction W. The monolithic ceramic capacitor 1 </ b> A in the present embodiment has an elongated substantially rectangular parallelepiped shape that is configured such that the outer dimension along the length direction L is the longest.

  As representative values of the outer dimension in the length direction L and the outer dimension in the width direction W of the multilayer ceramic capacitor 1A (normally, the outer dimension in the thickness direction T is the same as the outer dimension in the width direction W), For example, 3.2 [mm] × 1.6 [mm], 2.0 [mm] × 1.25 [mm], 1.6 [mm] × 0.8 [mm], 1.0 [mm] × 0.5 [mm], 0.8 [mm] × 0.4 [mm], 0.6 [mm] × 0.3 [mm], 0.4 [mm] × 0.2 [mm], etc. Can be mentioned.

  As shown in FIG. 6, the internal electrode layers 12, 13, and 14 provided in the stacked body 10 </ b> A are provided across a plurality of layers by being separated by the dielectric layer 11. As shown in FIGS. 4 to 6, the internal electrode layers 12, 13, and 14 include a signal internal electrode layer 12 as a first internal electrode layer, a floating internal electrode layer 13 as a second internal electrode layer, It includes a pair of grounding internal electrode layers 14 and 14 as third internal electrode layers.

  Here, the signal internal electrode layer 12 and the pair of grounding internal electrode layers 14 and 14 are provided side by side on a single plane orthogonal to the stacking direction (Z-axis direction). The internal electrode layer 12 and the pair of ground internal electrode layers 14 and 14 are positioned on the same plane. More specifically, the signal internal electrode layer 12 is provided so as to extend along the X-axis direction shown in the drawing at the center position in the Y-axis direction shown in the drawing, and a pair of grounding internal electrodes The layers 14 are provided at positions near both ends in the Y-axis direction shown in the figure so as to sandwich the signal internal electrode layer 12 therebetween.

  On the other hand, the floating internal electrode layer 13 is provided on a plane different from the plane on which the signal internal electrode layer 12 and the pair of ground internal electrode layers 14 and 14 are provided. Are arranged so as to face each of the grounding internal electrode layers 14, 14, so that when viewed in the stacking direction (Z-axis direction), the signal internal electrode layer 12 is a floating internal electrode. The grounding internal electrode layer 14 overlaps a part of the layer 13 and the grounding internal electrode layer 14 overlaps another part of the floating internal electrode layer 13.

  The signal internal electrode layer 12 is connected to the signal first external electrode 15 and the signal second external electrode 16 and is not connected to the pair of ground external electrodes 17 and 17. Specifically, as shown in FIG. 4, in the signal internal electrode layer 12, the connection portions 12a and 12a located at both ends in the X-axis direction are exposed at the pair of first side surfaces 3 and 3 of the laminate 10A. Thus, the signal is connected to the signal first external electrode 15 and the signal second external electrode 16 covering the first side surfaces 3 and 3. Note that both ends in the Y-axis direction of the signal internal electrode layer 12 are covered with the dielectric layer 11 and are not exposed on the pair of second side surfaces 4 and 4 of the stacked body 10A. The layer 12 is not connected to the pair of grounding external electrodes 17 and 17.

  The floating internal electrode layer 13 is not connected to any of the signal first external electrode 15, the signal second external electrode 16, and the pair of grounding external electrodes 17 and 17. Specifically, as shown in FIG. 5, both ends of the floating internal electrode layer 13 in the X-axis direction are covered with the dielectric layer 11 so as to be exposed at the pair of first side surfaces 3 and 3 of the stacked body 10A. Thus, the floating internal electrode layer 13 is not connected to the signal first external electrode 15 and the signal second external electrode 16. Further, both ends of the floating internal electrode layer 13 in the Y-axis direction are covered with the dielectric layer 11 so that they are not exposed at the pair of second side surfaces 4 and 4 of the stacked body 10A. Are not connected to the pair of grounding external electrodes 17, 17.

  Each of the pair of grounding internal electrode layers 14 and 14 is connected to the corresponding grounding external electrode 17 of the pair of grounding external electrodes 17 and 17, and the signal first external electrode 15, The signal external electrode 16 and the pair of ground external electrodes 17, 17 are not connected to the non-corresponding ground external electrode 17. Specifically, as shown in FIG. 4, each of the pair of grounding internal electrode layers 14, 14 includes a pair of first side surfaces 3 of the stacked body 10 </ b> A having a connection portion 14 a located at one end in the Y-axis direction. 3 is exposed and is connected to the corresponding grounding external electrode 17 of the pair of grounding external electrodes 17 and 17 covering the first side surfaces 3 and 3. On the other hand, the other end in the Y-axis direction of the pair of grounding internal electrode layers 14, 14 is covered with the dielectric layer 11 so as to be exposed at the other of the pair of first side surfaces 3, 3 of the laminate 10A. Thus, each of the grounding internal electrode layers 14 is disconnected from the non-corresponding grounding external electrode 17 of the pair of grounding external electrodes 17, 17. Note that both ends in the X-axis direction of the pair of grounding internal electrode layers 14 and 14 are covered with the dielectric layer 11 so that they are not exposed on the pair of second side surfaces 4 and 4 of the stacked body 10A. Each of the pair of grounding internal electrode layers 14 is not connected to the signal first external electrode 15 and the signal second external electrode 16.

  Here, in the multilayer ceramic capacitor 1A according to the present embodiment, the signal internal electrode layer 12, the floating internal electrode layer 13, and the pair of ground internal electrode layers 14 and 14 described above constitute a set of internal electrode layers. Thus, the internal electrode layer group is stacked and arranged in a plurality of sets along the stacking direction (Z-axis direction), thereby increasing the capacitance.

  With the above configuration, as shown in FIG. 6, the signal internal electrode layer 12 and the floating internal electrode layer 13 that are arranged to face each other and the dielectric layer 11 that is located between them are formed as shown in FIG. The first capacitor element 18A shown in FIG. 2 is configured, and the floating internal electrode layer 13 and the grounding internal electrode layer 14 that are disposed opposite to each other and the dielectric layer 11 that is positioned between them are formed as shown in FIG. The second capacitor element 18B shown in FIG. 4 is configured, and further, the first capacitor element 18A and the second capacitor element 18B are electrically connected in series via the floating internal electrode layer 13. It will be.

  Therefore, by using the monolithic ceramic capacitor 1A in the present embodiment, a through-type monolithic ceramic capacitor having a so-called series structure can be obtained. Therefore, even when dielectric breakdown occurs in one of the first capacitor element 18A and the second capacitor element 18B connected in series, electrical insulation is maintained by the other capacitor element, which is high. Reliability is obtained, and the first capacitor element 18A and the second capacitor element 18B are connected to the signal internal electrode layer 12 connected to the signal first external electrode 15 and the signal second external electrode 16. Since the extra wiring is greatly reduced by the close arrangement, the ESL can be reduced.

  The pair of grounding internal electrode layers 14 and 14 and the pair of grounding external electrodes 17 and 17 preferably have a symmetrical shape. By configuring in this way, these wiring inductances can be reduced, so that further ESL reduction can be achieved.

  Here, the multilayer ceramic capacitor 1A having the above-described configuration can be realized by manufacturing the multilayer body 10A using the material sheet group 20A as shown in FIG. As shown in FIG. 3, a plurality of three types of material sheets, ie, a first material sheet 21A, a second material sheet 21B, and a third material sheet 21C are prepared.

  The first material sheet 21A is composed only of the ceramic substrate 22 on which the conductive pattern is not formed, and the first material sheet 21A becomes a part of the dielectric layer 11 after firing.

  In the second material sheet 21B, the conductive pattern 23 having a shape corresponding to the signal internal electrode layer 12 and the conductive patterns 23 and 23 having a shape corresponding to the pair of grounding internal electrode layers 14 and 14 are formed on the surface of the ceramic substrate 22. The second material sheet 21 </ b> B becomes the signal internal electrode layer 12 and the pair of grounding internal electrode layers 14 and 14 and a part of the dielectric layer 11 after firing.

  The third material sheet 21 </ b> C is formed by forming a conductive pattern 23 having a shape corresponding to the floating internal electrode layer 13 on the surface of the ceramic substrate 22, and the third material sheet 21 </ b> C is formed after the firing. And becomes part of the dielectric layer 11.

  Here, the conductive pattern 23 can be formed by attaching a conductive paste to the surface of the ceramic substrate 22 (that is, the green sheet) by a printing method or the like.

  At the time of lamination, one second material sheet 21B and one third material sheet 21C are taken as a set, and a plurality of sets are laminated along the lamination direction (Z-axis direction), and these are sandwiched between them. In addition, the first material sheets 21A are laminated so as to be inserted between them as necessary. And the laminated body 10A is manufactured by crimping | bonding and baking the raw material sheet group 20A after lamination | stacking.

  As described above, in the case of the multilayer ceramic capacitor 1A according to the present embodiment, two types of shapes are sufficient for the conductive pattern formed on the ceramic substrate 22 in order to form the internal electrode layers 12, 13, and 14. Therefore, a through-type multilayer ceramic capacitor having a so-called series structure can be manufactured at a lower cost, and the size in the stacking direction (Z-axis direction) can be reduced.

  In the above, the case where one second material sheet 21B and one third material sheet 21C are set as one set has been illustrated, but the present invention is not limited to this. For example, from the viewpoint of reducing the DC resistance of the signal internal electrode layer 12, a plurality of second material sheets 21B and one third material sheet 21C may be combined.

  In the above description, the first material sheet 21A, the second material sheet 21B, and the third material sheet 21C are prepared and laminated, and then a manufacturing example in which this is crimped and baked is described as an example. Preparing a plurality of mother sheets including a plurality of first material sheets 21A, a mother sheet including a plurality of second material sheets 21B, and a mother sheet including a plurality of third material sheets 21C, and laminating and crimping the plurality of mother sheets. It is also possible to manufacture the mother block, and then cut the mother block into individual chips, which are then baked to produce the laminate 10A.

(Modification)
FIG. 7 is an exploded perspective view showing the structure of the multilayer body of the multilayer ceramic capacitor according to the modification based on Embodiment 1 of the present invention.

  As shown in FIG. 7, the multilayer ceramic capacitor 1 </ b> B according to this modification differs mainly in the configuration and layout of the grounding internal electrode layer 14 when compared with the multilayer ceramic capacitor 1 </ b> A in the first embodiment described above. Yes. Specifically, in the multilayer ceramic capacitor 1B according to the present modification, a laminated body 10B is formed using a raw material sheet group 20B as shown in place of the raw material sheet group 20A shown in the first embodiment. Is done. Here, the material sheet group 20B is obtained by replacing the second material sheet 21B included in the material sheet group 20A shown in the first embodiment described above with a second material sheet 21B1 as illustrated.

  The second material sheet 21 </ b> B <b> 1 includes a conductive pattern 23 that becomes the signal internal electrode layer 12 and a conductive pattern 23 that becomes the four grounding internal electrode layers 14. When the laminated body 10B is manufactured using the material sheet group 20B including the second material sheet 21B1, the signal internal electrode layer 12 has the X axis shown in the drawing at the center position in the Y axis direction shown in the drawing. The four grounding internal electrode layers 14 are provided at positions close to both ends in the Y-axis direction shown in the drawing so as to sandwich the signal internal electrode layer 12 therebetween. Two each are provided along the Y-axis direction.

  Although not shown in the multilayer ceramic capacitor 1B according to the present modification, two are provided on each of the second side surfaces 4 and 4 of the multilayer body 10B corresponding to the four grounding internal electrode layers 14. The grounding external electrode 17 is formed.

  Even when configured in this manner, a through-type multilayer ceramic capacitor having a so-called series structure can be obtained as in the case of the first embodiment.

(Embodiment 2)
FIG. 8 is an exploded perspective view showing a structure of the multilayer body of the multilayer ceramic capacitor according to Embodiment 2 of the present invention. FIG. 9 is a cross-sectional view of a portion including a signal internal electrode layer of the multilayer ceramic capacitor in the present embodiment, FIG. 10 is a cross-sectional view of a portion including a floating internal electrode layer, and FIG. It is a cross-sectional view of a portion including a grounding internal electrode layer. FIG. 12 is a longitudinal sectional view taken along line XII-XII shown in FIGS. 9 to 11 of the multilayer ceramic capacitor in the present embodiment.

  As shown in FIG. 8, the monolithic ceramic capacitor 1C in the present embodiment differs mainly in the configuration and layout of the grounding internal electrode layer 14 when compared with the monolithic ceramic capacitor 1A in the first embodiment described above. Yes. Specifically, in the multilayer ceramic capacitor 1C according to the present embodiment, a laminated body 10C is formed by using a raw material sheet group 20C as shown in place of the raw material sheet group 20A shown in the first embodiment. Is done. Here, the material sheet group 20C replaces the second material sheet 21B included in the material sheet group 20A shown in the first embodiment described above with a second material sheet 21B2 as shown in the drawing, and further a fourth material sheet. 21D is added.

  The second material sheet 21B2 is obtained by forming a conductive pattern 23 having a shape corresponding to the signal internal electrode layer 12 on the surface of the ceramic substrate 22, and the second material sheet 21B2 is a signal internal electrode after firing. It becomes the layer 12 and part of the dielectric layer 11. Here, the conductive pattern 23 to be the grounding internal electrode layer 14 is not formed on the second material sheet 21B2.

  The fourth material sheet 21D is obtained by forming a conductive pattern 23 having a shape corresponding to the grounding internal electrode layer 14 on the surface of the ceramic substrate 22, and the fourth material sheet 21D is a grounding internal electrode after firing. It becomes the layer 14 and part of the dielectric layer 11.

  At the time of stacking, one second material sheet 21B2, one third material sheet 21C and one fourth material sheet 21D are set as a set, and a plurality of sets are set along the stacking direction (Z-axis direction). While laminating, the first material sheets 21A are laminated so as to sandwich them and, if necessary, to be inserted between them. And the laminated body 10C is manufactured by crimping | bonding and baking the raw material sheet group 20C after lamination | stacking.

  As shown in FIG. 12, in the multilayer ceramic capacitor 1 </ b> C including the multilayer body 10 </ b> C manufactured in this way, the internal electrode layers 12, 13, and 14 provided inside the multilayer body 10 </ b> C are formed by the dielectric layer 11. By being separated, it is provided over a plurality of layers. The appearance structure of the multilayer ceramic capacitor 1C is the same as that of the multilayer ceramic capacitor 1A in the first embodiment described above (see FIG. 1).

  As shown in FIGS. 9 to 12, these internal electrode layers 12, 13, and 14 include a signal internal electrode layer 12 as a first internal electrode layer, a floating internal electrode layer 13 as a second internal electrode layer, The third internal electrode layer includes a grounding internal electrode layer 14.

  Here, the floating internal electrode layer 13 is provided between the signal internal electrode layer 12 and the ground internal electrode layer 14 along the stacking direction (Z-axis direction), and the stacking direction (Z-axis direction). , The signal internal electrode layer 12, the floating internal electrode layer, and the ground internal electrode layer 14 are positioned so as to overlap each other.

  The signal internal electrode layer 12 is connected to the signal first external electrode 15 and the signal second external electrode 16 and is not connected to the pair of ground external electrodes 17 and 17. Specifically, as shown in FIG. 9, in the signal internal electrode layer 12, the connection portions 12a and 12a located at both ends in the X-axis direction are exposed at the pair of first side surfaces 3 and 3 of the laminated body 10C. Thus, the signal is connected to the signal first external electrode 15 and the signal second external electrode 16 covering the first side surfaces 3 and 3. Note that both ends of the signal internal electrode layer 12 in the Y-axis direction are covered with the dielectric layer 11 and are not exposed on the pair of second side surfaces 4 and 4 of the stacked body 10C. The layer 12 is not connected to the pair of grounding external electrodes 17 and 17.

  The floating internal electrode layer 13 is not connected to any of the signal first external electrode 15, the signal second external electrode 16, and the pair of grounding external electrodes 17 and 17. Specifically, as shown in FIG. 10, both ends of the floating internal electrode layer 13 in the X-axis direction are covered with the dielectric layer 11 so as to be exposed at the pair of first side surfaces 3 and 3 of the stacked body 10C. Thus, the floating internal electrode layer 13 is not connected to the signal first external electrode 15 and the signal second external electrode 16. Further, both ends of the floating internal electrode layer 13 in the Y-axis direction are covered with the dielectric layer 11 so as not to be exposed at the pair of second side surfaces 4 and 4 of the stacked body 10C. Are not connected to the pair of grounding external electrodes 17, 17.

  The grounding internal electrode layer 14 is connected to the pair of grounding external electrodes 17 and 17 and is not connected to the signal first external electrode 15 and the signal second external electrode 16. Specifically, as shown in FIG. 11, in the grounding internal electrode layer 14, the connection portions 14a and 14a located at both ends in the Y-axis direction are exposed at the pair of second side surfaces 4 and 4 of the laminated body 10C. Thus, the connection is made to the pair of grounding external electrodes 17 and 17 covering the second side surfaces 4 and 4. Note that both ends of the grounding internal electrode layer 14 in the X-axis direction are covered with the dielectric layer 11 and are not exposed on the pair of first side surfaces 3 and 3 of the stacked body 10C. The layer 14 is not connected to the first signal external electrode 15 and the second signal external electrode 16.

  Here, in the multilayer ceramic capacitor 1C according to the present embodiment, the signal internal electrode layer 12, the floating internal electrode layer 13, and the ground internal electrode layer 14 described above are configured as a set of internal electrode layers, and Capacitance is increased by arranging a plurality of internal electrode layer groups in a stacking direction along the stacking direction (Z-axis direction).

  With the above-described configuration, as shown in FIG. 12, the signal internal electrode layer 12 and the floating internal electrode layer 13 that are disposed to face each other and the dielectric layer 11 that is positioned between them are formed as shown in FIG. The first capacitor element 18A shown in FIG. 2 is configured, and the floating internal electrode layer 13 and the grounding internal electrode layer 14 that are disposed opposite to each other and the dielectric layer 11 that is positioned between them are formed as shown in FIG. The second capacitor element 18B shown in FIG. 4 is configured, and further, the first capacitor element 18A and the second capacitor element 18B are electrically connected in series via the floating internal electrode layer 13. It will be.

  Therefore, by using the monolithic ceramic capacitor 1C in the present embodiment, a through-type monolithic ceramic capacitor having a so-called series structure can be obtained, and the same effects as those described in the first embodiment can be obtained. Can do.

  In the monolithic ceramic capacitor 1C according to the present embodiment, the signal internal electrode layer 12 and the ground internal electrode layer 14 are formed on non-coplanar surfaces, so that each of them can be formed larger. In this respect, the capacitance can be increased.

  The above-described embodiment and its modifications disclosed herein are illustrative in all respects and are not restrictive. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1A to 1C multilayer ceramic capacitor, 2 main surface, 3st side surface, 4th side surface, 10A to 10C multilayer body, 11 dielectric layer, 12 signal internal electrode layer, 12a connecting portion, 13 floating internal electrode layer, 14 Ground internal electrode layer, 14a connecting portion, 15 signal first external electrode, 16 signal second external electrode, 17 ground external electrode, 18A first capacitor element, 18B second capacitor element, 20A to 20C material sheet group , 21A First material sheet, 21B, 21B1, 21B2 Second material sheet, 21C Third material sheet, 21D Fourth material sheet, 22 Ceramic substrate, 23 Conductive pattern.

Claims (5)

A substantially rectangular parallelepiped laminate including dielectric layers and internal electrode layers alternately laminated along the first direction;
A first external electrode provided on one of a pair of first side surfaces of the laminate and a second external electrode provided on the other side, which are positioned opposite to each other in a second direction orthogonal to the first direction;
A third external electrode provided on at least one of a pair of second side surfaces of the laminate that is positioned relative to each other in a third direction orthogonal to the first direction and the second direction;
The internal electrode layer includes a first internal electrode layer connected to the first external electrode and the second external electrode and not connected to the third external electrode, the first external electrode, the second external electrode, and the A second internal electrode layer not connected to any of the third external electrodes; and a third internal electrode layer connected to the third external electrode and not connected to the first external electrode and the second external electrode. ,
The first internal electrode layer and the second internal electrode layer are disposed to face each other along the first direction to form a first capacitor element, and the second internal electrode along the first direction. A second capacitor element is configured by opposingly arranging the layer and the third internal electrode layer, whereby the first external electrode and the first external electrode between the second external electrode and the third external electrode are formed. A capacitor element and the second capacitor element are electrically connected in series ;
The internal electrode layer includes a through electrode layer formed so as to penetrate the stacked body along the second direction or the third direction;
The capacitor element , wherein the through electrode layer has two or less types . The first internal electrode layer and the third internal electrode layer are provided on the same plane orthogonal to the first direction;
When viewed along the first direction, the first internal electrode layer overlaps a part of the second internal electrode layer, and the third internal electrode layer is another layer of the second internal electrode layer. The capacitor | condenser element of Claim 1 which overlaps with a part. The second internal electrode layer is provided between the first internal electrode layer and the third internal electrode layer along the first direction;
2. The capacitor element according to claim 1, wherein the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer overlap each other when viewed along the first direction.   4. The capacitor element according to claim 1, wherein the third external electrode is provided on either of the pair of second side surfaces of the multilayer body. 5.   The capacitor element according to claim 1, wherein the dielectric layer is made of a ceramic material.

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