JP6233210B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device having a trench.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage, low loss, and use in a high temperature environment, silicon carbide is being adopted as a material constituting the semiconductor device. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve high breakdown voltage of the semiconductor device, reduction of on-resistance, and the like. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  As a semiconductor device adopting silicon carbide as a material, for example, there is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A MOSFET is a semiconductor device that conducts or cuts off current by controlling whether or not an inversion layer is formed in a channel region with a predetermined threshold voltage as a boundary. For example, Japanese Patent Laying-Open No. 2010-258294 (Patent Document 1) discloses a trench MOSFET in which a channel region is formed along a side wall surface of a trench.

  In a trench MOSFET employing silicon carbide as a material, a trench is formed on the main surface of the silicon carbide layer by etching the silicon carbide layer on which the mask layer having an opening is formed. Then, by thermally oxidizing the silicon carbide layer in which the trench is formed, a gate insulating film (silicon dioxide film) is formed so as to extend from the inner wall of the trench to the upper surface of the silicon carbide layer.

  In such a trench MOSFET, the upper corner formed by the sidewall of the trench and the main surface of the silicon carbide layer has a shape close to a right angle, so that the gate insulation formed near the upper corner of the trench. The film thickness is locally reduced. On the other hand, the upper corner portion of the trench is a portion where a high electric field is likely to be applied, so when an electric field is locally concentrated on the upper corner portion, a leak current is generated in the gate insulating film formed near the upper corner portion, The insulation reliability of the gate insulating film is lowered.

  In Patent Document 1, a trench is formed by etching on a substrate on which a silicon carbide epitaxial layer is formed, and then in an argon (Ar) atmosphere in a range of 1600 ° C. to 1800 ° C. under a pressure of 10 Torr or less for 10 minutes to 10 minutes. Heat treatment for a minute. Thereby, silicon (Si) atoms are evaporated from the silicon carbide surface, and the silicon carbide surface is changed to 95 at% or more carbon (C) atoms. By graphitizing the silicon carbide surface, deformation of the silicon carbide etching shape is suppressed.

JP 2010-258294 A

  However, according to the manufacturing method described in Patent Document 1 described above, there is a problem that the sidewall surface of the trench becomes rough due to migration of silicon atoms by heat treatment. When the side wall surface of the trench is rough, the carrier mobility is lowered in the channel region formed along the side wall surface, so that it is difficult to reduce the channel resistance (that is, reduce the on-resistance).

  Further, step bunching occurs on the main surface of the silicon carbide layer connected to the side wall surface of the trench, thereby increasing the surface roughness of the main surface. As a result, when the gate insulating film is formed by thermal oxidation, the portion where the gate insulating film is locally thin due to the fact that the thermal oxidation rate differs depending on the crystal plane of silicon carbide (plane orientation dependence) Will occur. As a result, there is a possibility that a leakage current is induced in the gate insulating film starting from the portion.

  An object of one embodiment of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of ensuring a sufficient insulation reliability of a gate insulating film while realizing a low channel resistance.

  A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention includes a first main surface that is a carbon surface or a surface that is turned off by 8 degrees or less from the carbon surface, and a second main surface opposite to the first main surface. And a step of preparing a silicon carbide substrate having a surface. The silicon carbide substrate includes a first impurity region forming a second main surface and having a first conductivity type, and a second impurity having a second conductivity type provided on the first impurity region. And a third impurity region provided on the second impurity region so as to be separated from the first impurity region, forming a first main surface, and having the first conductivity type. The manufacturing method further includes a step of forming a mask layer having an opening on the first main surface of the silicon carbide substrate, a third impurity region, a second impurity region through the opening of the mask layer, Removing a part of the first impurity region by etching to form a trench in the first main surface of the silicon carbide substrate; and removing the mask layer and then thermally oxidizing the trench and silicon carbide Forming a gate insulating film covering the first main surface of the substrate; and forming a gate electrode on the gate insulating film. The step of forming the mask layer includes a step of forming a first film covering the first main surface, a step of forming a second film having a lower density than the first film on the first film, And patterning the first and second films so as to have an opening corresponding to the position where the trench is formed. The step of forming the trench includes a step of chemically etching the first main surface of the silicon carbide substrate exposed at the opening while heating the silicon carbide substrate. In the step of applying chemical etching, the stress applied to the first film due to the thermal contraction of the second film is caused between the edge surrounding the opening of the first film and the first main surface of the silicon carbide substrate. A gap is formed. The first main surface of the silicon carbide substrate exposed at the opening and the gap is removed by etching.

  According to the above, it is possible to manufacture a silicon carbide semiconductor device that can secure a sufficient insulation reliability of the gate insulating film while realizing a low channel resistance.

It is a fragmentary sectional view for demonstrating schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. FIG. 2 is a perspective view schematically showing a shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1. It is an enlarged view of FIG. FIG. 5 is a flowchart for schematically illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 2 is a flowchart for schematically illustrating a method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 2 is a flowchart for schematically illustrating a method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 12 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 12 is a partial cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. FIG. 12 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention. FIG. 12 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention. FIG. 12 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 2 of this invention.

[Description of Embodiment of the Present Invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding “-” (bar) on a number, but in this specification, a sign is attached before the number. The angle is described using a system in which the omnidirectional angle is 360 degrees.

First, embodiments of the present invention will be listed and described.
(1) A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present invention includes a first main surface 10a that is a carbon surface or a surface that is off by 8 degrees or less from the carbon surface, and a side opposite to the first main surface 10a. A step of preparing silicon carbide substrate 10 having the second main surface 10b. Silicon carbide substrate 10 is provided on first impurity regions 80, 81 forming second main surface 10 b and having the first conductivity type, and on first impurity regions 80, 81, A second impurity region 82 having a conductivity type, provided on the second impurity region 82 so as to be separated from the first impurity regions 80 and 81, to form a first main surface 10a; And a third impurity region 83 having a conductivity type. The manufacturing method further includes a step of forming mask layer 100 having opening OP on first main surface 10a of silicon carbide substrate 10; third impurity region 83 through opening OP of mask layer 100; The step of forming trench TR in first main surface 10a of silicon carbide substrate 10 by removing second impurity region 82 and a part of first impurity region 81 by etching, and mask layer 100 After removing, a step of forming gate insulating film 91 covering trench TR and first main surface 10a of silicon carbide substrate 10 by thermal oxidation and a step of forming gate electrode 92 on gate insulating film 91 are provided. . The step of forming the mask layer 100 includes a step of forming the first film 110 covering the first main surface 10a, and a second density lower than that of the first film 110 on the first film 110. A step of forming the film 120 and a step of patterning the first film 110 and the second film 120 so as to have the opening OP corresponding to the position where the trench TR is formed are included. The step of forming trench TR includes a step of performing chemical etching on first main surface 10a of silicon carbide substrate 10 exposed at opening OP while heating silicon carbide substrate 10. In the step of performing chemical etching, the edge surrounding the opening OP of the first film 110 and the first of the silicon carbide substrate 10 due to the stress applied to the first film 110 due to the thermal contraction of the second film 120. A gap GP is formed between the main surface 10a. First main surface 10a of silicon carbide substrate 10 exposed at opening OP and gap GP is removed by etching.

  According to the method for manufacturing a silicon carbide semiconductor device according to (1) above, a trench MOSFET is manufactured. In the method for manufacturing a trench MOSFET, the mask layer 100 used for forming the trench TR in the first main surface 10a of the silicon carbide substrate 10 which is the carbon surface or a surface that is off by 8 degrees or less from the carbon surface, A two-layer structure of the film 110 and the second film 120 formed on the first film 110 and having a lower density than the first film 110 is employed. Thereby, when chemical etching is performed while heating silicon carbide substrate 10, first film 110 can be warped using stress generated by contraction of second film 120. Since the gap GP is formed between the first film 110 and the first main surface 10a of the silicon carbide substrate 10 due to the warp of the first film 110, side etching in the gap GP is promoted. As a result, the tilt angle with respect to the carbon surface is smaller than that of the first side surface SW1 that is tilted with respect to the carbon surface and includes the channel region, and is located near the upper corner of the trench TR and that of the first side surface SW1. A trench TR having the second side surface SW2 is formed.

  Gate insulating film 91 formed by thermally oxidizing silicon carbide substrate 10 having trench TR formed thereon is thinned on first side surface SW1 in accordance with the plane orientation dependence of the thermal oxidation rate of silicon carbide. Thus, the second side surface SW2 is thickened. That is, it is possible to increase the thickness of the gate insulating film 91 formed in the vicinity of the upper corner portion of the trench TR while reducing the thickness of the gate insulating film 91 in contact with the channel region. By forming the thin gate insulating film 91 over the channel region, carrier mobility is improved, so that channel resistance can be reduced. Further, since the thick gate insulating film 91 is formed in the vicinity of the upper corner portion of the trench TR, the electric field concentration on the upper corner portion of the trench TR is greatly relieved, so that leakage current is generated near the upper corner portion. Can be suppressed. As a result, it is possible to ensure the insulation reliability of the gate insulating film while realizing a low channel resistance.

  (2) Preferably in the method for manufacturing a silicon carbide semiconductor device according to (1) above, sidewall surface SW of trench TR is formed of first impurity region 81 and second impurity region 82, and is 50% from the carbon surface. The first side surface SW1 is inclined at an angle of not less than 50 degrees, and the second side surface SW2 is formed of the third impurity region 83 and is inclined at an angle smaller than 50 degrees with respect to the carbon surface. Thereby, gate insulating film 91 formed by thermally oxidizing silicon carbide substrate 10 in which trench TR is formed is thinned on first side surface SW1 in accordance with the plane orientation dependency of the thermal oxidation rate of silicon carbide. On the other hand, the thickness is increased on the second side surface SW2. Thus, by utilizing the plane orientation dependence of the thermal oxidation rate in silicon carbide, a trench MOSFET having low channel resistance and high insulation reliability can be manufactured by a simplified process.

  (3) Preferably in the method for manufacturing a silicon carbide semiconductor device according to (2) above, first side surface SW1 is inclined at 50 ° or more and 65 ° or less with respect to the carbon surface. Thereby, since the channel resistance in the first side surface SW1 can be reduced, the on-resistance of the trench MOSFET can be reduced.

  (4) Preferably in the method for manufacturing a silicon carbide semiconductor device according to (3) above, first side surface SW1 includes a surface having a plane orientation {0-33-8}. Thereby, the channel resistance in the first side surface SW1 can be further reduced, so that the on-resistance can be reduced.

  (5) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (1) to (4) above, in the step of performing chemical etching, in an atmosphere containing a reactive gas having at least one or more types of halogen atoms To heat silicon carbide substrate 10. Thereby, the first side surface SW1 and the second side surface SW2 of the trench TR can be formed at a time by thermal etching, and thus the process can be simplified.

  (6) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (1) to (5) above, in the step of forming first film 110, oxide film 110 is formed by thermal oxidation. Thereby, first film 110 that is dense and has high adhesion to first main surface 10a of silicon carbide substrate 10 can be easily formed, so that the process can be simplified.

  (7) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (1) to (6) above, in the step of forming second film 120, oxide film 120 is formed by deposition. Accordingly, since the second film 120 that covers the first film 110 and has a lower density than the first film 110 can be easily formed, the process can be simplified.

  (8) Preferably, in the method for manufacturing a silicon carbide semiconductor device according to any one of (1) to (7), the step of patterning first film 110 and second film 120 includes first film 110 and A step of removing a part of second film 120 by etching to form opening OP and removing a part of first main surface 10a of silicon carbide substrate 10 exposed at opening OP by etching. Including. Thereby, since first main surface 10a of silicon carbide substrate 10 is over-etched when patterning mask layer 100, first film 110 and second film remaining in opening OP of mask layer 100 are used. 120 is reliably removed. By chemically etching the first main surface 10a through the opening OP of the mask layer 100, the sidewall surface SW and the bottom portion BT of the trench TR can be flattened (stabilized).

  (9) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (1) to (8), the step of forming trench TR is exposed at opening OP before the step of performing chemical etching. The method further includes a step of performing dry etching on the first main surface 10a of the silicon carbide substrate 10 to be performed. As a result, the first side surface SW1 that is inclined substantially at right angles to the carbon surface and includes the channel region, and that is located near the upper corner of the trench TR and that is inclined relative to the carbon surface as compared to the first side surface SW1. A trench TR having a second side surface SW2 having a small angle is formed. While gate insulating film 91 formed by thermally oxidizing silicon carbide substrate 10 in which trench TR is formed is thinned on first side surface SW1 in accordance with the plane orientation dependency of the thermal oxidation rate of silicon carbide, The thickness is increased on the second side surface SW2. Therefore, the insulation reliability of the gate insulating film can be ensured while realizing a low channel resistance.

[Details of the embodiment of the present invention]
(Embodiment 1)
<Configuration of silicon carbide semiconductor device>
First, the structure of a trench MOSFET as a silicon carbide semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  The trench MOSFET according to the present embodiment includes silicon carbide substrate 10, gate insulating film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, source wiring layer 95, and drain electrode 98. Prepare.

  Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. First main surface 10a of silicon carbide substrate 10 is a surface that is off by 8 degrees or less from the {000-1} plane or {000-1} plane. Specifically, the first major surface 10a is a (000-1) plane (carbon plane) or a plane that is off by 8 degrees or less from the (000-1) plane (carbon plane), and the second major surface 10b. Is a plane off by 8 degrees or less from the (0001) plane (silicon plane) or the (0001) plane (silicon plane).

  Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 80 and a silicon carbide epitaxial layer provided on silicon carbide single crystal substrate 80. Silicon carbide single crystal substrate 80 has, for example, a polytype 4H hexagonal crystal structure. Silicon carbide single crystal substrate 80 contains an impurity (donor) such as nitrogen (N), for example, and has n type (first conductivity type).

  The silicon carbide epitaxial layer includes a drift region 81, a body region 82, a source region 83, and a contact region 84.

Drift region 81 is an n-type region containing an impurity such as nitrogen, for example. The impurity concentration (donor concentration) of drift region 81 is preferably lower than the impurity concentration of silicon carbide single crystal substrate 80. The concentration of the n-type impurity in the drift region 81 is, for example, about 5 × 10 ¹⁵ cm ⁻³ . Silicon carbide single crystal substrate 80 and drift region 81 are n-type regions (first impurity regions), and form second main surface 10b of silicon carbide substrate 10.

Body region 82 (second impurity region) is provided on drift region 81. Body region 82 is a p-type (second conductivity type) region containing an impurity such as aluminum (Al) or boron (B). The concentration of the p-type impurity in body region 82 is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

Source region 83 (third impurity region) is an n-type region that forms first main surface 10a of silicon carbide substrate 10 and contains an impurity such as phosphorus (P). Source region 83 is provided on body region 82 so as to be separated from drift region 81 by body region 82. The concentration of the n-type impurity included in the source region 83 is higher than the concentration of the n-type impurity included in the drift region 81. The concentration of the n-type impurity contained in the source region 83 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

Contact region 84 is a p-type region containing a p-type impurity such as aluminum or boron. Contact region 84 is formed to connect first main surface 10a of silicon carbide substrate 10 and body region 82. The concentration of the p-type impurity included in contact region 84 is higher than the concentration of the p-type impurity included in body region 82. The concentration of the p-type impurity contained in contact region 84 is, for example, about 1 × 10 ²⁰ cm ⁻³ . The depth of contact region 84 along the normal direction of first main surface 10 a of silicon carbide substrate 10 may be deeper than the depth of source region 83.

  Trench TR is provided in first main surface 10a of silicon carbide substrate 10. Trench TR has side wall surface SW and bottom portion BT. Sidewall surface SW passes through source region 83 and body region 82 and reaches drift region 81. Side wall surface SW is inclined with respect to first main surface 10a of silicon carbide substrate 10, whereby trench TR extends in a tapered shape toward the opening. In the present embodiment, as shown in FIG. 2, a number of mesa structures are formed on the upper surface of silicon carbide single crystal substrate 80. Specifically, the mesa structure has a hexagonal shape at the top and bottom, and its side wall is inclined with respect to the top surface of silicon carbide single crystal substrate 80.

  Side wall surface SW has side surface SW1 and side surface SW2. Side surface SW <b> 1 includes drift region 81 and body region 82. Side surface SW <b> 1 includes a channel surface of the MOSFET on body region 82. Side SW1 is preferably inclined at an angle of 50 degrees or more with respect to the (000-1) plane (carbon plane). Preferably, the side surface SW1 is inclined at an angle of not less than 50 degrees and not more than 65 degrees with respect to the (000-1) plane (carbon plane). Thereby, since the channel resistance in the side surface SW1 can be reduced, the on-resistance of the trench MOSFET can be reduced.

  Such side surface SW1 includes a first surface having a plane orientation {0-33-8}. More preferably, the side surface SW1 microscopically includes a first surface, and the side surface SW1 further microscopically includes a second surface having a plane orientation {0-11-1}. Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As an observation method of such a microscopic structure, for example, a TEM (Transmission Electron Microscope) can be used.

  Preferably, the first surface and the second surface of the side surface SW1 constitute a composite surface having a surface orientation {0-11-2}. That is, the composite surface is configured by periodically repeating the first surface and the second surface. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy).

  The side surface SW2 is composed of a source region 83. Side SW2 is preferably inclined at an angle smaller than 50 degrees with respect to the (000-1) plane (carbon plane). Preferably, the side surface SW2 is inclined at an angle of 30 degrees or more and less than 50 degrees with respect to the (000-1) plane (carbon plane). In other words, the side surface SW2 is located in the vicinity of the opening of the trench TR, and is inclined with respect to the (000-1) plane (carbon surface) at an angle smaller than the side surface SW1. That is, in the trench MOSFET, the upper corner portion of the trench TR formed by the extension line of the side surface SW1 and the extension line of the first main surface 10a is substantially rounded, so that the side surface is located near the upper corner portion. A side surface SW2 having a smaller inclination angle with respect to the (000-1) plane (carbon surface) than SW1 is formed.

  Bottom BT is located on drift region 81. In the present embodiment, bottom portion BT is a surface substantially parallel to first main surface 10a of silicon carbide substrate 10. The bottom BT may be a surface or a line. When the bottom portion BT is a line, the shape of the trench TR is V-shaped when viewed in cross section.

  Gate insulating film 91 is provided in contact with side wall surface SW and bottom portion BT of trench TR and first main surface 10a of silicon carbide substrate 10. Gate insulating film 91 is in contact with source region 83 at first main surface 10a of silicon carbide substrate 10 and side surface SW2 of trench TR, and is in contact with body region 82 at side surface SW1 of trench TR, and the side surface of trench TR Each of SW1 and bottom BT is in contact with drift region 81. A channel region can be formed in part of the body region 82 in contact with the gate insulating film 91. The gate insulating film 91 is a silicon dioxide film and is formed by thermal oxidation. The thickness of the gate insulating film 91 is, for example, about 40 nm to 60 nm.

  Referring to FIG. 3, gate insulating film 91 includes a side surface portion 910 that covers side surface SW1, a side surface portion 911 that covers side surface SW2, and a flat portion 912 that covers a part of first main surface 10a connected to side surface SW2. including. The side surface portion 910 has a thickness d1. The side part 911 has a thickness d2. The flat portion 912 has a thickness d3. The thickness of the side surface portion 911 continuously changes between the portion having the thickness d1 and the portion having the thickness d3. The thickness d2 is, for example, an average value of the thickness of the side surface portion 911.

  Regarding the thickness of the gate insulating film 91 described above, at least d2> d1 is satisfied. Preferably, d3> d2> d1 is satisfied. Such a magnitude relationship in the thickness of the gate insulating film 91 can be formed by using the plane orientation dependence of the thermal oxidation rate in silicon carbide, as will be described later.

  The gate electrode 92 is provided on the gate insulating film 91. Source electrode 94 is in contact with each of source region 83 and contact region 84. The source wiring layer 95 is in contact with the source electrode 94. Source wiring layer 95 is, for example, an aluminum layer. The interlayer insulating film 93 insulates between the gate electrode 92 and the source wiring layer 95. Drain electrode 98 is arranged in contact with second main surface 10b (silicon carbide single crystal substrate 80) of silicon carbide substrate 10.

<Method for Manufacturing Silicon Carbide Semiconductor Device>
Next, with reference to FIGS. 4-16, the manufacturing method of the trench type MOSFET which concerns on this Embodiment is demonstrated.

(1) Silicon carbide substrate preparation process First, a silicon carbide substrate preparation process (S10: FIG. 4) is implemented. The silicon carbide substrate preparation step includes a silicon carbide single crystal substrate preparation step (S101: FIG. 5), an epitaxial layer formation step (S102: FIG. 5), and an ion implantation step (S103: FIG. 5).

  Specifically, in the silicon carbide single crystal substrate preparation step (S101: FIG. 5), a silicon carbide single crystal substrate 80 is obtained by slicing an ingot made of hexagonal silicon carbide having polytype 4H formed by a sublimation method. Is prepared.

Next, an epitaxial layer forming step (S102: FIG. 5) is performed. Specifically, referring to FIG. 6, a silicon carbide epitaxial layer is formed on silicon carbide single crystal substrate 80. The silicon carbide epitaxial layer includes an n type drift region 81 (first impurity region). For example, the silicon carbide epitaxial layer is formed by CVD (Chemical Vapor Deposition) using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen (H ₂ ) gas as a carrier gas. ) Method. During the epitaxial growth, for example, nitrogen (N) is introduced as an impurity.

  Next, an ion implantation step (S103: FIG. 5) is performed. Specifically, referring to FIG. 7, body region 82 (second impurity region) in contact with drift region 81 is formed by ion implantation of a p-type impurity such as aluminum into drift region 81. It is formed. Next, n-type impurity such as phosphorus is ion-implanted into body region 82 to form source region 83 (third impurity region). Next, a p-type impurity such as aluminum is ion-implanted into source region 83, so that contact region 84 extending from first main surface 10a to body region 82 is formed. In place of ion implantation, epitaxial growth with impurity addition may be used.

  Next, heat treatment (activation annealing) for activating the impurities added by ion implantation is performed. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon atmosphere.

  As described above, silicon carbide substrate 10 having first main surface 10a and second main surface 10b opposite to first main surface 10a is prepared. First main surface 10a of silicon carbide substrate 10 is a surface that is off by 8 degrees or less from (000-1) plane (carbon plane) or (000-1) plane (carbon plane). Silicon carbide substrate 10 has a drift region 81 having n type, a body region 82 in contact with drift region 81 and having a p type, and a source region having an n type and separated from drift region 81 by body region 82. 83, and a contact region 84 having a p-type and connecting first main surface 10a and body region 82. In the above description, the contact region 84 is formed after the source region 83 is formed. However, the source region 83 may be formed after the contact region 84 is formed.

(2) Etching mask layer formation process Next, an etching mask layer formation process (S20: FIG. 4) is implemented. For example, the etching mask layer 100 (FIG. 11) having the opening OP is formed on the first main surface 10 a composed of the source region 83 and the contact region 84. The opening OP is formed corresponding to the position of the trench TR (FIG. 1).

  As shown in FIG. 8, the etching mask layer forming step includes a thermal oxide film forming step (S201), a deposited oxide film forming step (S202), and a patterning step (S203).

First, a thermal oxide film forming step (S201: FIG. 8) is performed. Specifically, referring to FIG. 9, first main surface 10a of silicon carbide substrate 10 is thermally oxidized. The thermal oxidation is performed, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes. Thus, a thermal oxide film 110 (first film) made of silicon dioxide (SiO ₂ ) is formed on the first main surface 10a. The thickness of the thermal oxide film 110 is preferably 100 angstroms or more and 1000 angstroms or less.

  Next, a deposited oxide film forming step (S202: FIG. 8) is performed. Referring to FIG. 10, deposited oxide film 120 (second film) is formed on thermal oxide film 110. Specifically, for example, TEOS (Tetraethylortosilicate) gas is supplied to silicon carbide substrate 10 at a temperature of about 600 ° C. to 800 ° C. for about 6 hours. In addition, it is preferable that the heat processing temperature in this process is lower than the heat processing temperature in the thermal etching process implemented at the trench formation process (S30: FIG. 4) mentioned later. Thus, the deposited oxide film 120 is formed so as to cover the thermal oxide film 110. The thickness of the deposited oxide film 120 is preferably 5000 angstroms or more and 20000 angstroms or less.

  The deposited oxide film 120 has a feature that the density of silicon dioxide is lower than that of the thermal oxide film 110. Therefore, the deposited oxide film 120 has a larger volume shrinkage rate during heating than the thermal oxide film 110. In the present embodiment, the thickness of the deposited oxide film 120 is made sufficiently larger than the thickness of the thermal oxide film 110. Thereby, the volume shrinkage amount of the deposited oxide film 120 during heating is sufficiently larger than the volume shrinkage amount of the thermal oxide film 110. As a result, the compressive stress generated by the volume contraction is larger in the deposited oxide film 120 than in the thermal oxide film 110.

  Next, a patterning step (S203: FIG. 8) is performed. Referring to FIG. 11, thermal oxide film 110 and deposited oxide film 120 are patterned so as to have an opening OP corresponding to the position where trench TR (FIG. 1) is formed. Specifically, first, a resist layer (not shown) having an opening corresponding to the position of trench TR is formed on deposited oxide film 120 by photolithography. Next, the etching mask layer 100 is formed by etching the thermal oxide film 110 and the deposited oxide film 120. As an etching method, for example, dry etching is used, and more specifically, inductively coupled plasma reactive ion etching (ICP-RIE) can be used.

  In the etching of the thermal oxide film 110 and the deposited oxide film 120 described above, a part of the first main surface 10a exposed at the opening OP may be over-etched. That is, the thermal oxide film 110 and the deposited oxide film 120 are etched, and a part of the first main surface 10a is etched. By over-etching the first main surface 10a, the etching mask layer 100 located in the opening OP is reliably removed. When thermal etching is performed with etching mask layer 100 remaining on first main surface 10a of silicon carbide substrate 10, the surface of the silicon carbide epitaxial layer that forms sidewall surface SW and bottom portion BT of trench TR is uneven. It will occur. In the present embodiment, etching mask layer 100 located in opening OP can be surely removed by overetching first main surface 10a, and therefore, a silicon carbide epitaxial layer that forms sidewall surface SW and bottom portion BT of trench TR. Can be flattened (stabilized).

  As described above, the thermal oxide film 110 (first film), the deposited oxide film 120 (second film) formed on the thermal oxide film 110 and having a lower density than the thermal oxide film 110, and a trench are formed. An etching mask layer 100 having an opening OP corresponding to the position where TR is formed is formed.

(3) Trench formation process Next, a trench formation process (S30: Drawing 4) is carried out. Specifically, trench TR is formed in first main surface 10a of silicon carbide substrate 10 by removing part of silicon carbide substrate 10 by etching through opening OP of etching mask layer 100.

The trench formation step includes a step of performing chemical etching on first main surface 10a of silicon carbide substrate 10 exposed at opening OP of etching mask layer 100 while heating silicon carbide substrate 10. Specifically, thermal etching is performed on first main surface 10a of silicon carbide substrate 10 through opening OP of etching mask layer 100. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCl ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas and a heat treatment temperature of, for example, about 800 ° C. to 1000 ° C.

Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. In thermal etching, etching mask layer 100 made of a silicon dioxide film has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide.

  Here, in the above thermal etching, first main surface 10a of silicon carbide substrate 10 is etched in opening OP of etching mask layer 100 as shown in FIG. Further, during etching, the deposited oxide film 120 contracts due to the heat treatment. The white arrows in FIG. 12 schematically show the behavior of the deposited oxide film 120 contracting. On the other hand, the thermal oxide film 110 under the deposited oxide film 120 is denser than the deposited oxide film 120 and has a sufficiently small thickness, so that the contraction amount is sufficiently small. Note that the heat treatment time required for the shrinkage of the deposited oxide film 120 is, for example, about 5 seconds to 20 minutes at 900 ° C.

  As the deposited oxide film 120 shrinks as described above, compressive stress is generated in the deposited oxide film 120. In response to this compressive stress, the thermal oxide film 110 is distorted. Specifically, as shown in FIG. 13, thermal oxide film 110 warps in a convex shape toward silicon carbide substrate 10 side. The black arrows in FIG. 13 schematically show the behavior of the thermal oxide film 110 being distorted. In the present embodiment, in the deposited oxide film forming step (S202: FIG. 8), the stress applied to the thermal oxide film 110 is effectively increased by setting the thickness of the deposited oxide film 120 to 5000 angstroms or more and 20000 angstroms or less. Can be generated. Further, by setting the thickness of the thermal oxide film 110 to 100 angstroms or more and 1000 angstroms or less, the thermal oxide film 110 can be effectively warped by receiving stress from the deposited oxide film 120.

  When warpage occurs in thermal oxide film 110, the adhesion between first main surface 10a of silicon carbide substrate 10 and thermal oxide film 110 is weakened. Thereby, as shown in FIG. 13, gap GP is formed between the edge surrounding opening OP of thermal oxide film 110 and first main surface 10 a of silicon carbide substrate 10.

  When the first main surface 10a of the silicon carbide substrate 10 is newly exposed due to the formation of the gap GP, the exposed first main surface 10a is etched. That is, the region where side surface SW1 and bottom portion BT of trench TR are to be formed is etched through opening OP, and first main surface 10a located near the upper corner of trench TR is etched through gap GP. The At this time, since the (000-1) plane (carbon plane) has the fastest etching rate among the crystal planes of silicon carbide, side etching in the gap GP is substantially promoted. Note that the thermal etching processing time is controlled so that side etching in the gap GP stops in the source region 83, in other words, side etching in the gap GP does not reach the body region 82.

  As a result, trench TR is formed in first main surface 10a of silicon carbide substrate 10 as shown in FIG. Trench TR has side wall surface SW passing through source region 83 and body region 82 to drift region 81, and bottom portion BT connected to side wall surface SW and located in drift region 81. Side wall surface SW is composed of drift region 81 and body region 82, and is composed of side surface SW1 inclined at an angle of 50 degrees or more and 65 degrees or less with respect to (000-1) plane (carbon plane), and source region 83. , And (000-1) plane (carbon plane) and side surface SW2 inclined at an angle smaller than 50 degrees. Side SW1 includes a plane having a plane orientation {0-33-8}.

  When each of source region 83, body region 82, and drift region 81 is thermally etched to form sidewall surface SW of trench TR, etching mask layer 100 is not substantially etched. The main surface 10a is left so as to protrude onto the side wall surface SW of the trench TR. Next, the etching mask layer 100 is removed by an arbitrary method such as etching.

(4) Gate Insulating Film Forming Step Next, a gate insulating film forming step (S40: FIG. 4) is performed. Specifically, silicon carbide substrate 10 in which trench TR is formed in first main surface 10a of silicon carbide substrate 10 is placed in a heating furnace. While maintaining the state where nitrogen (N ₂ ) gas is introduced into the heating furnace, the temperature of silicon carbide substrate 10 is heated from room temperature to 1300 ° C. After silicon carbide substrate 10 reaches 1300 ° C., oxygen (O ₂ ) gas is introduced. By holding silicon carbide substrate 10 at a temperature of about 1300 ° C. for about 1 hour in an oxygen atmosphere, gate insulating film 91 is formed on first main surface 10a of silicon carbide substrate 10. Preferably, silicon carbide substrate 10 is held in an oxygen atmosphere at a temperature of 1100 ° C. or higher and 1400 ° C. or lower, for example, for about 1 hour. The temperature of this thermal oxidation is a temperature that generates a phenomenon in which the thermal oxidation rate differs depending on the plane orientation.

  As described above, as shown in FIG. 14, gate insulating film 91 made of silicon dioxide covers side wall surface SW and bottom portion BT of trench TR and first main surface 10a of silicon carbide substrate 10, It is formed by thermal oxidation.

  Here, regarding the thickness of the gate insulating film 91, as described with reference to FIG. 3, the thickness of the side surface portion covering the side surface SW1 is d1, and the thickness of the side surface portion covering the side surface SW2 is d2. If the thickness of the flat portion covering the surface 10a is d3, d3> d2> d1 is satisfied. Such a magnitude relationship in the thickness of the gate insulating film 91 can be formed using the plane orientation dependence of the thermal oxidation rate in silicon carbide.

  Specifically, in the present embodiment, first main surface 10a of silicon carbide substrate 10 is turned off by 8 degrees or less from (000-1) plane (carbon plane) or (000-1) plane (carbon plane). Surface. In the side wall surface SW of the trench TR, the side surface SW1 is a surface inclined by an angle of 50 degrees or more (preferably an angle of 50 degrees or more and 65 degrees or less) with respect to the (000-1) plane (carbon plane). The surface is inclined at an angle smaller than 50 degrees with respect to the (000-1) plane (carbon plane). Silicon carbide having a hexagonal crystal structure of polytype 4H has a surface orientation dependency of the thermal oxidation rate such that the thermal oxidation rate differs depending on the plane orientation. According to this, the (000-1) plane (carbon plane) has the fastest thermal oxidation rate, and the (0001) plane (silicon plane) has the slowest thermal oxidation rate. Due to the dependence of the thermal oxidation rate on the plane orientation, when the gate insulating film 91 is formed, the first main surface 10a of the silicon carbide substrate 10 has the highest thermal oxidation rate, and the side SW1 has a thermal oxidation rate. It becomes the slowest, and the thermal oxidation rate of the side surface SW2 is in the middle. As a result, the above-described magnitude relationship is formed in the thickness of the gate insulating film 91.

  Note that after the formation of the gate insulating film 91, NO annealing using nitrogen monoxide (NO) gas as an atmospheric gas may be performed. Specifically, for example, silicon carbide substrate 10 on which gate insulating film 91 is formed is held at a temperature of 1100 ° C. or higher and 1300 ° C. or lower for about 1 hour in a nitrogen monoxide atmosphere. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 91 and the body region 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas.

  Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The annealing heating temperature is preferably higher than the NO annealing heating temperature and lower than the melting point of the gate insulating film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of the interface state in the interface region between the gate insulating film 91 and the body region 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

(5) Surface electrode formation process Next, the surface electrode formation process (S50: FIG. 4) is implemented. In the surface electrode formation step, the gate electrode 92 and the source electrode 94 are formed. Referring to FIG. 15, gate electrode 92 is formed on gate insulating film 91. Specifically, the gate electrode 92 made of polysilicon containing impurities is formed on the gate insulating film 91 by, for example, LPCVD (Low Pressure Chemical Vapor Deposition). Gate electrode 92 is formed to face drift region 81, body region 82, and source region 83 with gate insulating film 91 interposed therebetween.

Next, referring to FIG. 16, an interlayer insulating film 93 made of, for example, silicon dioxide is formed so as to cover gate insulating film 91 and gate electrode 92. Thereafter, interlayer insulating film 93 and gate insulating film 91 are patterned so as to have an opening in a region where source electrode 94 is to be formed. Preferably, interlayer insulating film 93 and gate insulating film 91 are etched such that source region 83 and contact region 84 are exposed from interlayer insulating film 93 and gate insulating film 91, respectively. CF ₄ can be used as an etching gas.

  Next, referring to FIG. 16, source electrode 94 is formed in the opening so as to be in contact with both source region 83 and contact region 84 on first main surface 10 a of silicon carbide substrate 10. Preferably, the source electrode 94 includes at least one of titanium (Ti), aluminum (Al), and nickel (Ni). Preferably, the source electrode 94 is made of a material containing TiAlSi. The source electrode 94 is formed by, for example, a sputtering method. Next, with respect to silicon carbide substrate 10 on which source electrode 94 provided in contact with each of source region 83 and contact region 84 is formed on first main surface 10a of silicon carbide substrate 10, for example, 900 ° C. or higher. A heat treatment at 1100 ° C. or lower is performed for about 5 minutes. Thereby, at least a part of source electrode 94 reacts with silicon included in silicon carbide substrate 10 to be silicided to form an alloy layer. Thereby, a source electrode 94 including an alloy layer that is in ohmic contact with the source region 83 is formed. Preferably, source electrode 94 includes an alloy layer that is in ohmic contact with contact region 84.

  Next, a source wiring layer 95 (FIG. 1) is formed so as to be in contact with the source electrode 94 and cover the interlayer insulating film 93. Source wiring layer 95 is made of, for example, a material containing aluminum (Al), and is, for example, AlSiCu. After the formation of the source wiring layer 95, a lamp annealing process may be performed. In the lamp annealing step, silicon carbide substrate 10 on which source wiring layer 95 is formed is heated at a temperature of 700 ° C. or higher and 800 ° C. or lower, for example, for about 30 seconds.

(6) Back electrode formation process Next, a back electrode formation process (S60: Drawing 4) is carried out. Specifically, drain electrode 98 made of, for example, NiSi is formed in contact with second main surface 10b of silicon carbide substrate 10. The drain electrode 98 may be TiAlSi, for example. The formation of the drain electrode 98 is preferably performed by a sputtering method, but may be performed by vapor deposition. After the drain electrode 98 is formed, the drain electrode 98 is heated by, for example, laser annealing. Thereby, at least a part of drain electrode 98 is silicided, and drain electrode 98 that is in ohmic contact with silicon carbide substrate 10 is formed. Thus, the trench MOSFET shown in FIG. 1 is manufactured.

  Next, the effect of the trench MOSFET as the silicon carbide semiconductor device according to the first embodiment and the manufacturing method thereof will be described.

  According to the trench MOSFET according to the first embodiment, the gate insulating film 91 formed by thermally oxidizing the silicon carbide substrate 10 in which the trench TR is formed has the trench TR composed of the drift region 81 and the body region 82. While the thickness is reduced at the side surface SW1, the thickness is increased at the side surface SW2 of the trench TR formed of the source region 83. That is, it is possible to increase the thickness of the gate insulating film 91 in the vicinity of the upper corner portion of the trench TR while reducing the thickness of the gate insulating film 91 in contact with the channel region of the trench MOSFET.

  By forming the thin gate insulating film 91 on the channel region as described above, the electron density of the inversion layer in the channel region is increased. Thereby, since carrier mobility improves, the channel resistance of trench MOSFET can be reduced. In addition, since the thick gate insulating film 91 is formed in the vicinity of the upper corner portion of the trench TR, the upper corner portion where a high electric field tends to concentrate can be kept away from the gate electrode 92. Thereby, since the electric field concentration at the upper corner of trench TR is greatly relieved, the occurrence of leakage current in the vicinity of the upper corner can be suppressed. Therefore, the insulation reliability of the gate insulating film can be ensured while realizing a low channel resistance.

  Furthermore, according to the trench MOSFET according to the first embodiment, side surface SW1 of trench TR is inclined at an angle of 50 degrees or more and 65 degrees or less with respect to the (000-1) plane (carbon plane). Thereby, since the channel resistance in the side surface SW1 can be further reduced, the on-resistance can be further reduced.

  The trench MOSFET manufacturing method according to the first embodiment includes the drift region 81 and the body region 82, and is inclined at an angle of 50 degrees to 65 degrees with respect to the (000-1) plane (carbon plane). Side surface SW1 and source region 83, side surface SW2 inclined at an angle smaller than 50 degrees with respect to (000-1) plane (carbon plane), side wall surface SW, and drift region A trench TR having a bottom BT located at 81 can be formed. Thereby, gate insulating film 91 formed by thermally oxidizing silicon carbide substrate 10 in which trench TR is formed is thinned on side surface SW1 of trench TR according to the surface orientation dependency of the thermal oxidation rate, The thickness is increased at the side surface SW2 of the trench TR. That is, the thickness of the gate insulating film 91 formed near the upper corner of the trench TR can be increased while reducing the thickness of the gate insulating film 91 in contact with the channel region of the trench MOSFET. Thereby, the insulation reliability of the gate insulating film can be ensured while realizing a low channel resistance.

  Furthermore, according to the method for manufacturing a trench MOSFET according to the first embodiment, the etching mask layer 100 is formed more than the thermal oxide film 110 (first film) and the thermal oxide film 110 provided on the thermal oxide film 110. By having a two-layer structure with the low-density deposited oxide film 120 (second film), the thermal oxide film 110 is intentionally warped using stress due to shrinkage of the deposited oxide film 120 during thermal etching. Can do. Thermal etching is performed through the gap GP formed between thermal oxide film 110 and first main surface 10a of silicon carbide substrate 10 due to warpage of thermal oxide film 110, so that side surface SW1, side surface SW2 and Trench TR having bottom BT can be easily formed.

(Embodiment 2)
Next, a method for manufacturing a trench MOSFET according to the second embodiment of the present invention will be described.

  The trench MOSFET manufacturing method according to the second embodiment is such that, in the trench formation step (S30: FIG. 4), before performing thermal etching, a recess is formed in a region where trench TR is to be formed by dry etching. This is different from the manufacturing method according to the first embodiment. Other steps are the same as those in the method for manufacturing the trench MOSFET according to the first embodiment. Therefore, the description of common steps will not be repeated.

  After the etching mask layer forming step (S20: FIG. 4) described in the first embodiment is performed to form the etching mask layer 100, the trench forming step (S30: FIG. 4) is performed.

Referring to FIG. 17, in the opening OP of the etching mask layer 100, the source region 83, the body region 82, and a part of the drift region 81 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive etching (ICP-RIE) can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ can be used as a reaction gas. By such etching, in the region where the trench TR is to be formed, the side wall surface SW substantially perpendicular to the first main surface 10a, the side wall surface SW is connected, and the first main surface 10a is substantially parallel. A concave portion TQ having a bottom portion BT is formed.

  Next, thermal etching is performed on the recess TQ. The thermal etching is performed by heating in an atmosphere containing a reactive gas having at least one kind of halogen atom, as described in the first embodiment. Specifically, as shown in FIG. 18, the inner surface of the recess TQ is etched. Further, during etching, the deposited oxide film 120 contracts due to the heat treatment, so that a compressive stress is applied to the thermal oxide film 110 under the deposited oxide film 120. Due to this compressive stress, thermal oxide film 110 warps in a convex shape toward silicon carbide substrate 10, whereby an edge that surrounds the opening of thermal oxide film 110, first main surface 10 a of silicon carbide substrate 10, and A gap is formed between the two. As a result, the region where side surface SW1 and bottom portion BT of trench TR should be formed is etched through opening OP, and first main surface 10a located near the upper corner of trench TR is etched through the gap. Is done. At this time, since the (000-1) plane (carbon plane) has the fastest etching rate among the crystal planes of silicon carbide, side etching in the gap is substantially promoted.

  As a result, trench TR is formed in first main surface 10a of silicon carbide substrate 10 as shown in FIG. Trench TR has side wall surface SW passing through source region 83 and body region 82 to drift region 81, and bottom portion BT connected to side wall surface SW and located in drift region 81. Side wall surface SW includes drift region 81 and body region 82, and includes side surface SW1 substantially perpendicular to (000-1) plane (carbon plane) and source region 83, and includes (000-1) plane (carbon plane). ) And a side surface SW2 inclined at an angle smaller than 50 degrees.

  Next, by performing the gate insulating film forming step (S40: FIG. 4) described in the first embodiment, as shown in FIG. 19, side wall surface SW and bottom portion BT of trench TR, silicon carbide substrate 10 A gate insulating film 91 made of silicon dioxide is formed by thermal oxidation so as to cover the first main surface 10a. Regarding the thickness of the gate insulating film 91, the thickness of the side surface portion covering the side surface SW1 is d1, the thickness of the side surface portion covering the side surface SW2 is d2, and the thickness of the flat portion covering the first main surface 10a is d3. Then, d3> d2> d1 is satisfied.

  Next, the front surface electrode forming step (S50: FIG. 4) and the back surface electrode forming step (S60: FIG. 4) described in the first embodiment are performed. As described above, the trench MOSFET shown in FIG. 20 is manufactured.

  In the method for manufacturing a trench MOSFET according to the second embodiment, the thermal etching performed after dry etching is mainly aimed at the formation of a gap and the side etching in the gap, and therefore, compared with the thermal etching in the first embodiment. Reduce processing time. In the second embodiment, for example, the thickness of the deposited oxide film 120 is increased or the deposition temperature of the deposited oxide film 120 is increased as compared with the first embodiment so that the gap is effectively formed within a short heat treatment time. By lowering, the volume shrinkage of the deposited oxide film 120 can be increased and the compressive stress can be increased. Alternatively, the thermal oxide film 110 can be easily warped by stress by reducing the thickness of the thermal oxide film 110 as compared with the first embodiment.

  Next, the effect of trench type MOSFET 1 as a silicon carbide semiconductor device according to the second embodiment and the method for manufacturing the same will be described.

  According to the trench MOSFET according to the second embodiment, the gate insulating film 91 formed by thermally oxidizing the silicon carbide substrate 10 in which the trench TR is formed has the trench TR composed of the drift region 81 and the body region 82. While the thickness is reduced at the side surface SW1, the thickness is increased at the side surface SW2 of the trench TR formed of the source region 83. That is, it is possible to increase the thickness of the gate insulating film 91 in the vicinity of the upper corner portion of the trench TR while reducing the thickness of the gate insulating film 91 in contact with the channel region of the trench MOSFET. As a result, the carrier mobility can be improved and the channel resistance of the trench MOSFET can be reduced, and the concentration of the electric field at the upper corner of the trench TR can be reduced to suppress the occurrence of a leak current near the upper corner. can do. That is, the insulation reliability of the gate insulating film can be ensured while realizing a low channel resistance.

  The trench MOSFET manufacturing method according to the second embodiment includes the drift region 81 and the body region 82, and is inclined at an angle of 50 degrees or more (substantially perpendicular) to the (000-1) plane (carbon plane). The side surface SW1 is formed of the source region 83, is inclined with respect to the (000-1) plane (carbon plane) at an angle smaller than 50 degrees, is connected to the side wall surface SW, and drifts. Trench TR having bottom portion BT located in region 81 can be formed. Gate insulating film 91 formed by thermally oxidizing silicon carbide substrate 10 in which trench TR is formed is thinned on side surface SW1 of trench TR according to the surface orientation dependency of the thermal oxidation rate, while It is thickened at the side surface SW2. That is, the thickness of the gate insulating film 91 in the vicinity of the opening of the trench TR can be increased while reducing the thickness of the gate insulating film 91 in contact with the channel region of the trench MOSFET. Thereby, the insulation reliability of the gate insulating film can be ensured while realizing a low channel resistance.

  Furthermore, according to the method for manufacturing a trench MOSFET according to the second embodiment, the etching mask layer 100 is formed by using the thermal oxide film 110 and a deposited oxide film having a lower density than the thermal oxide film 110 provided on the thermal oxide film 110. By using the two-layer structure with 120, the thermal oxide film 110 can be intentionally warped using the compressive stress due to the shrinkage of the deposited oxide film 120 by performing the thermal etching after the dry etching. By performing thermal etching through a gap formed between thermal oxide film 110 and first main surface 10a of silicon carbide substrate 10 due to warpage of thermal oxide film 110, side surface SW1, side surface SW2, and bottom portion described above are performed. The trench TR having the BT can be easily formed.

  In the first and second embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, these conductivity types may be interchanged. However, in order to increase channel mobility, the first conductivity type is preferably n-type.

  The first and second films are not limited to the thermal oxide film and the deposited oxide film, as long as the second film has a lower density than the first film.

  The silicon carbide semiconductor device may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET. Further, the silicon carbide semiconductor device is not limited to the MISFET, and may be any device having a trench gate structure, for example, a trench IGBT (Insulated Gate Bipolar Transistor).

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.

10 Silicon carbide substrate 81 Drift region 82 Body region 83 Source region 84 Contact region 91 Gate insulating film 92 Gate electrode 93 Interlayer insulating film 94 Source electrode 95 Source wiring layer 98 Drain electrode 100 Etching mask layer 110 Thermal oxide film 120 Deposited oxide film TR Trench SW Side wall surface SW1, SW2 Side surface BT Bottom

Claims (9)

A method for manufacturing a silicon carbide semiconductor device, comprising:
Providing a silicon carbide substrate having a carbon surface or a first main surface that is off from the carbon surface by 8 degrees or less, and a second main surface opposite to the first main surface;
The silicon carbide substrate includes a first impurity region that forms the second main surface and has a first conductivity type, and is provided on the first impurity region and has a second conductivity type. A second impurity region and a third impurity region provided on the second impurity region so as to be separated from the first impurity region, forming the first main surface, and having the first conductivity type An impurity region,
Forming a mask layer having an opening on the first main surface of the silicon carbide substrate;
The third impurity region, the second impurity region, and a part of the first impurity region are removed by etching through the opening of the mask layer, whereby the first impurity region of the silicon carbide substrate is removed. Forming a trench in the main surface of 1;
Forming a gate insulating film covering the trench and the first main surface of the silicon carbide substrate by thermal oxidation after removing the mask layer;
Forming a gate electrode on the gate insulating film,
The step of forming the mask layer includes:
Forming a first film covering the first main surface;
Forming a second film having a lower density than the first film on the first film;
Patterning the first and second films so as to have the opening corresponding to the position where the trench is formed,
The step of forming the trench includes the step of performing chemical etching on the first main surface of the silicon carbide substrate exposed at the opening while heating the silicon carbide substrate,
In the step of performing the chemical etching, an edge surrounding the opening of the first film and the first of the silicon carbide substrate due to stress applied to the first film due to thermal contraction of the second film. A method of manufacturing a silicon carbide semiconductor device, wherein a gap is formed between the first main surface and the first main surface of the silicon carbide substrate exposed in the opening and the gap is removed by etching. The side wall surface of the trench is
A first side surface comprising the first and second impurity regions and inclined at an angle of 50 degrees or more with respect to the carbon surface;
2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising: a second side surface made of the third impurity region and inclined at an angle smaller than 50 degrees with respect to the carbon surface.   3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein said first side surface is inclined by 50 degrees or more and 65 degrees or less with respect to said carbon surface.   The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein said first side surface includes a surface having a plane orientation {0-33-8}.   5. The silicon carbide according to claim 1, wherein in the chemical etching step, the silicon carbide substrate is heated in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. A method for manufacturing a semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein an oxide film is formed by thermal oxidation in the step of forming the first film.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein, in the step of forming the second film, an oxide film is formed by deposition.   The step of patterning the first and second films includes removing the portions of the first and second films by etching to form the opening and the silicon carbide substrate exposed at the opening. The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-7 including the process of removing a part of said 1st main surface of this by an etching.   The step of forming the trench further includes a step of performing dry etching on the first main surface of the silicon carbide substrate exposed at the opening before the step of performing chemical etching. The method for manufacturing a silicon carbide semiconductor device according to claim 8.

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