JP6233436B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device having a gate electrode and a method for manufacturing a silicon carbide semiconductor device.

  In power semiconductor devices, it is known that there is generally a trade-off relationship between on-resistance and breakdown voltage. Therefore, in recent years, semiconductor devices having a charge compensation structure such as a super junction structure have been proposed for the purpose of improving the breakdown voltage while suppressing the on-resistance. For example, Japanese Patent Laid-Open No. 2004-342660 (Patent Document 1) discloses a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a charge compensation structure.

JP 2004-342660 A

In the technique described in the above publication, a p ⁺ type base layer that functions as a channel is formed on a p type pillar layer (charge compensation structure). For this reason, the impurities in the charge compensation structure affect the channel characteristics.

  The present invention has been made to solve the above-described problems, and its purpose is to provide a carbonization capable of improving the breakdown voltage while avoiding the influence on the channel characteristics and suppressing the on-resistance. It is providing the manufacturing method of a silicon semiconductor device and a silicon carbide semiconductor device.

  The silicon carbide semiconductor device of the present invention includes a silicon carbide layer, a gate insulating film, a gate electrode, a first electrode, and a second electrode. The silicon carbide layer has a first surface and a second surface that face each other in the thickness direction. The silicon carbide layer has a first region, a second region, a third region, and a fourth region. The first region forms a first surface and has a first conductivity type. The second region is provided on the first region so as to be separated from the first surface by the first region, and has a second conductivity type different from the first conductivity type. The third region is provided on the second region, is separated from the first region by the second region, and has the first conductivity type. The fourth region is provided in the first region apart from each of the first surface and the second region, and has the second conductivity type. The gate insulating film is provided on the second region so as to connect between the first region and the third region. The gate electrode is provided on the gate insulating film. The first electrode is provided on the first region. The second electrode is provided on the third region.

  According to this device, at least part of the electric field in the thickness direction caused by the fixed charge having one of the positive and negative polarities caused by the depletion of the first region causes the fourth region to be depleted. Is compensated by a fixed charge of the other polarity produced by In other words, a charge compensation structure is provided. Thereby, the maximum value of the electric field strength in the thickness direction is suppressed. Therefore, the breakdown voltage of the silicon carbide semiconductor device can be improved. Further, according to the present apparatus, the fourth area is separated from the second area. Thus, it is possible to avoid the impurities in the fourth region from affecting the second region functioning as a channel.

  Preferably, the fourth region has a thickness greater than 5 μm in the thickness direction. As a result, the charge compensation structure is provided over a wider range in the thickness direction. Therefore, the breakdown voltage of the silicon carbide semiconductor device can be further improved.

  Preferably, the second surface is provided with a gate trench having a side wall, penetrating through the third region and the second region to the first region, and away from the fourth region. The gate insulating film is provided on the side wall. Thereby, the charge compensation structure can be applied to a trench type semiconductor device.

  Preferably, the sidewall of the gate trench is inclined with respect to the second surface of the silicon carbide layer by an angle greater than 0 ° and less than 90 °. Thereby, a channel surface having a plane orientation inclined with respect to the second surface can be provided.

  Preferably, the angle of the side surface of the fourth region with respect to the thickness direction is smaller than the angle of the gate trench with respect to the thickness direction. Thereby, charge compensation by the fourth region can be performed more sufficiently.

  Preferably, the silicon carbide layer has a hexagonal crystal structure. Further, the side wall of the gate trench of the silicon carbide layer includes a portion consisting of at least one of {0-33-8} plane and {0-11-4} plane. Thereby, the carrier mobility on a side wall can be raised. Therefore, the on-resistance of the silicon carbide semiconductor device can be suppressed.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes the following steps. A silicon carbide layer having a first surface and a second surface facing each other in the thickness direction is prepared. The silicon carbide layer has a first region, a second region, a third region, and a fourth region. The first region forms a first surface and has a first conductivity type. The second region is provided on the first region so as to be separated from the first surface by the first region, and has a second conductivity type different from the first conductivity type. The third region is provided on the second region, is separated from the first region by the second region, and has the first conductivity type. The fourth region is provided in the first region apart from each of the first surface and the second region, and has the second conductivity type. A gate trench having a side wall on the second surface, penetrating through the third region and the second region to the first region and away from the fourth region is formed. A gate insulating film is formed on the sidewall of the gate trench. A gate electrode is formed on the gate insulating film. A first electrode is formed on the first region of the silicon carbide layer. A second electrode is formed on the third region of the silicon carbide layer.

  According to the silicon carbide semiconductor device obtained by the present manufacturing method, at least a part of the electric field in the thickness direction caused by the fixed charge having one of the positive polarity and the negative polarity caused by depletion of the first region is The four regions are compensated by a fixed charge of the other polarity generated by depletion. In other words, a charge compensation structure is provided. Thereby, the maximum value of the electric field strength in the thickness direction is suppressed. Therefore, the breakdown voltage of the silicon carbide semiconductor device can be improved. Further, according to the present manufacturing method, the fourth region is separated from the second region. Thus, it is possible to avoid the impurities in the fourth region from affecting the second region functioning as a channel.

  Preferably, the gate trench is formed using thermal etching. Thereby, the plane orientation of the side wall of the gate trench can be made crystallographically specific.

  Preferably, the step of preparing the silicon carbide layer includes the following steps. A base portion is provided which forms a first surface and partially forms a first region. A fourth region is formed by epitaxial growth on the base portion. A through portion that exposes a portion of the base portion is formed in the fourth region. A buried portion that partially forms the first region and fills the penetration portion of the fourth region and a covering portion that partially forms the first region and covers the buried portion and the base portion are formed. A second region and a third region are formed on the covering portion. Thereby, the part which penetrates the 4th field can be provided in the 1st field.

  Preferably, the penetrating portion is formed using etching having a physical etching action. Thereby, the etching for forming the penetration portion can be performed more vertically. Thereby, the side surface of the 4th field which consists of the inner surface of a penetration part can be made to follow a thickness direction. Therefore, charge compensation by the fourth region can be performed more sufficiently.

  In the above description, “on the first region of the silicon carbide layer” means “directly on the first region” and “indirectly on” the first region. Can mean both.

  As described above, according to the present invention, the breakdown voltage can be improved while suppressing the on-resistance in the silicon carbide semiconductor device.

1 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention. FIG. 6 is a partial cross sectional view taken along line II-II in each of FIGS. 3 to 5, schematically showing a configuration of a silicon carbide layer included in the silicon carbide semiconductor device of FIG. 1. FIG. 3 is a partial perspective view schematically showing a configuration of a silicon carbide layer in FIG. 2. FIG. 3 is a partial plan view schematically showing a configuration of a silicon carbide layer in FIG. 2. FIG. 5 is a partial plan view showing the configuration of the silicon carbide layer in FIG. 4 in more detail. FIG. 7 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 7 is a partial plan view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 8 is a schematic partial sectional view taken along line VIII-VIII in FIG. 7. FIG. 11 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 8 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 8 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 11 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 11 is a partial plan view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 14 is a schematic partial cross-sectional view taken along line XIV-XIV in FIG. 13. FIG. 12 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 12 is a partial plan view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 17 is a schematic partial sectional view taken along line XVII-XVII in FIG. 16. FIG. 11 is a partial cross sectional view schematically showing a tenth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a fragmentary sectional view which shows schematically the 11th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. FIG. 11 is a partial cross sectional view schematically showing a twelfth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 22 is a partial cross sectional view schematically showing a thirteenth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. FIG. 24 is a partial cross sectional view schematically showing a fourteenth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention. FIG. 24 is a partial cross sectional view schematically showing a configuration of a silicon carbide layer included in the silicon carbide semiconductor device of FIG. 23. FIG. 12 is a partial cross sectional view schematically showing a first step of a method for manufacturing a silicon carbide semiconductor device in Embodiment 2 of the present invention. FIG. 11 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 2 of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, individual planes are indicated by (), and aggregate planes are indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
First, the structure of MOSFET 100 (silicon carbide semiconductor device) of the present embodiment will be described with reference to FIGS.

  As shown in FIG. 1, the MOSFET 100 includes a single crystal substrate 1, an SiC layer 10 (silicon carbide layer), a drain electrode 31 (first electrode), a source electrode 32 (second electrode), and a gate oxide film 21. (Gate insulating film), interlayer insulating film 22, gate electrode 30, and source wiring layer 33.

  Single crystal substrate 1 is made of silicon carbide having n-type (first conductivity type). For example, single crystal substrate 1 is made of silicon carbide having a single crystal structure of either hexagonal system or cubic system. Preferably, the single crystal substrate 1 is provided with a main surface (upper surface in the figure) having an off angle within 5 degrees from the reference plane. In the case of a hexagonal system, the reference plane is a {000-1} plane, and more preferably a (000-1) plane. The reference plane is a {111} plane in the case of a cubic system. Preferably, the off angle is 0.5 degrees or more.

2 to 5, SiC layer 10 has a lower surface F1 (first surface) and an upper surface F2 (second surface) that face each other in thickness direction DD (FIG. 2). The lower surface F1 and the upper surface F2 are substantially parallel to each other. The SiC layer 10 includes an n ⁻ drift region 11 (first region), a p region 12 (second region), an n region 13 (third region), a charge compensation region 14 (fourth region), and a p ⁺ contact region. 15

N ⁻ drift region 11 forms lower surface F1 and has n type (first conductivity type). The n ⁻ drift region 11 has a base portion 11a, a buried portion 11b, and a covering portion 11c. Base portion 11a forms lower surface F1 of SiC layer 10. A charge compensation region 14 is provided on the base portion 11a. The charge compensation region 14 is provided with a through portion PP that connects the base portion 11a and the covering portion 11c. The pitch PT of the through portions PP is preferably the same as the pitch of the gate trench GT described later. The buried portion 11 b fills the through portion PP of the charge compensation region 14. The covering portion 11c covers the embedded portion 11b and the base portion 11a. A p region 12 is provided on the covering portion 11c. Each of the base portion 11a, the embedded portion 11b, and the covering portion 11c may be made of the same material including the impurity concentration.

The p region 12 is provided on the covering portion 11c of the n ⁻ drift region 11 and has p type (second conductivity type different from the first conductivity type). N region 13 is provided on p region 12 and is separated from n ⁻ drift region 11 by p region 12 and has n type (first conductivity type).

The upper surface F2 is provided with a gate trench GT that penetrates the n region 13 and the p region 12 to reach the n ⁻ drift region 11 and has a bottom portion BT and a side wall SS. The gate trench GT is separated from the charge compensation region 14. Sidewall SS has a portion composed of n ⁻ drift region 11, p region 12, and n region 13. The impurity concentration in the n ⁻ drift region 11 is preferably 5 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, more preferably 5 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ^−3. It is as follows.

The charge compensation region 14 has p-type (second conductivity type). The charge compensation region 14 is provided in the n ⁻ drift region 11 apart from each of the lower surface F1 and the p region 12. Specifically, the charge compensation region 14, n ^- are separated from the p region 12 by the covering portion 11c of the drift region 11 ^- base portion is separated from the lower surface F1 by 11a, and n drift region 11. The charge compensation region 14 has a thickness TH (FIG. 2) greater than 5 μm in the thickness direction DD. The impurity concentration of the charge compensation region 14 is preferably 5 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, more preferably 5 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less. is there.

The p ⁺ contact region 15 is directly provided on a part of the p region 12 and forms a part of the upper surface F2 of the SiC layer 10.

Gate oxide film 21 is provided on p region 12 so as to connect between n ⁻ drift region 11 and n region 13. Specifically, gate oxide film 21 covers p region 12 of SiC layer 10 on sidewall SS. The gate electrode 30 is provided on the gate oxide film 21. Thereby, gate electrode 30 is located on p region 12 of SiC layer 10 via gate oxide film 21.

Drain electrode 31 is an ohmic electrode provided on base portion 11 a of n ⁻ drift region 11 of SiC layer 10 through single crystal substrate 1. Source electrode 32 is an ohmic electrode provided directly on n region 13 and p ⁺ contact region 15 of SiC layer 10.

  Preferably, sidewall SS of gate trench GT is inclined by angle AF (FIG. 2) greater than 0 ° and smaller than 90 ° with respect to upper surface F2 of SiC layer 10. More preferably, the angle of the side surface SD (FIG. 2) of the charge compensation region 14 with respect to the thickness direction DD is smaller than the angle AD (FIG. 2) of the gate trench GT with respect to the thickness direction DD.

  SiC layer 10 may have a hexagonal crystal structure, and in this case, sidewall SS of gate trench GT of SiC layer 10 is at least of the {0-33-8} plane and the {0-11-4} plane. It is preferable to include any part. SiC layer 10 may have a cubic crystal structure. In this case, side wall SS of gate trench GT of SiC layer 10 preferably includes a portion formed of a {100} plane.

Next, a method for manufacturing MOSFET 100 will be described below.
As shown in FIG. 6, base portion 11 a that becomes a part of n ⁻ drift region 11 (not shown in FIG. 6) is formed by epitaxial growth of silicon carbide on single crystal substrate 1. Next, the charge compensation region 14 is formed by epitaxial growth on the base portion 11a. Epitaxial growth of silicon carbide is performed by chemical vapor deposition (CVD) using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. It can be implemented by law. For example, nitrogen (N) or phosphorus (P) is used as an impurity for imparting n-type to silicon carbide. For example, aluminum (Al) is used as an impurity for imparting p-type.

As shown in FIGS. 7 and 8, a mask layer 70 is formed on the charge compensation region 14. The mask layer 70 has an opening corresponding to the position of the penetration part PP (FIG. 2) of the charge compensation region 14. Mask layer 70 is made of, for example, silicon oxide (SiO ₂ ).

As shown in FIG. 9, a through portion PP that exposes a part of the base portion 11 a is formed in the charge compensation region 14 by etching using the mask layer 70. Preferably, this etching is performed using etching having a physical etching action. Such etching includes, for example, reactive ion etching (RIE) or ion beam etching (IBE). In particular, inductively coupled plasma (ICP) RIE can be used as RIE. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. Next, the mask layer 70 is removed (FIG. 10).

As shown in FIG. 11, a buried portion 11b and a covering portion 11c, which become a part of n ⁻ drift region 11 (not shown in FIG. 11), are formed. Specifically, first, a buried portion 11b that fills the through portion PP of the charge compensation region 14 is formed. A covering portion 11c is formed to cover the embedded portion 11b and the base portion 11a. As a forming method, a method similar to that of the base portion 11a can be used.

As shown in FIG. 12, p region 12 and n region 13 are formed on covering portion 11c. Specifically, ion implantation is performed on the upper surface layer of the covering portion 11c of the n ⁻ drift region 11 to form the p region 12 and the n region 13, and the portion where the ion implantation has not been performed remains as the covering portion 11c. It is. The region where the p region 12 is formed can be adjusted by adjusting the acceleration energy of the implanted ions. In impurity ion implantation for imparting p-type, for example, aluminum (Al) is used as an impurity. In impurity ion implantation for imparting n-type, phosphorus (P), for example, is used as an impurity. Note that at least one of the p region 12 and the n region 13 may be formed by epitaxial growth instead of ion implantation.

  Thus, SiC layer 10 is formed on single crystal substrate 1. SiC layer 10 has a lower surface F1 and an upper surface F2 that face each other in the thickness direction (vertical direction in the drawing). The lower surface F1 faces the single crystal substrate 1.

As shown in FIGS. 13 and 14, mask layer 71 is formed on upper surface F <b> 2 of SiC layer 10. The mask layer 71 has an opening corresponding to the position where the gate trench GT (FIG. 1) is to be formed. Mask layer 71 is made of, for example, silicon oxide (SiO ₂ ).

  As shown in FIG. 15, a recess is formed on upper surface F <b> 2 of SiC layer 10 in the opening of mask layer 71 by etching using mask layer 71. Preferably, this etching is performed using etching having a physical etching action.

  As shown in FIGS. 16 and 17, gate trench GT is formed in upper surface F <b> 2 by thermal etching of SiC layer 10 using mask layer 71. Details of the thermal etching will be described later. Next, the mask layer 71 is removed (FIG. 18).

As shown in FIG. 19, ap ⁺ contact region 15 is formed by impurity ion implantation. Next, activation annealing is performed to activate the impurities implanted by ion implantation. For example, heating is performed at a temperature of 1700 ° C. for 30 minutes.

  As shown in FIG. 20, the exposed surface of SiC layer 10 is thermally oxidized, whereby gate oxide film 21 is formed. At this time, since the inner surface of the gate trench GT is also thermally oxidized, the gate oxide film 21 covers the p region 12 of the SiC layer 10 on the sidewall SS.

  As shown in FIG. 21, a gate electrode 30 is formed on the gate oxide film 21 in the gate trench GT. Gate electrode 30 is formed to have a portion located on p region 12 of SiC layer 10 with gate oxide film 21 interposed therebetween.

Further, referring to FIG. 22, first, interlayer insulating film 22 is formed on exposed gate oxide film 21 and gate electrode 30 (FIG. 21). Next, the gate oxide film 21 and the interlayer insulating film 22 are patterned, so that an opening exposing the p ⁺ contact region 15 and a part of the n region 13 is formed. Next, the source electrode 32 is formed in the opening. Thereby, the configuration shown in FIG. 22 is obtained.

Referring again to FIG. 1, source wiring layer 33 is formed on interlayer insulating film 22 and source electrode 32. A drain electrode 31 is formed on n ⁻ drift region 11, that is, on lower surface F 1 of SiC layer 10 with single crystal substrate 1 interposed therebetween. Thus, MOSFET 100 is obtained.

  Next, thermal etching used in the above manufacturing method will be described. Thermal etching is etching performed using a chemical reaction generated by supplying a process gas containing a reactive gas to an etching target heated to a predetermined heat treatment temperature.

  As the reactive gas in the process gas, a gas having a chlorine atom is used, preferably a chlorine-based gas, more preferably a chlorine gas. The thermal etching is preferably performed in an atmosphere in which the partial pressure of the chlorine-based gas is 50% or less. The process gas preferably contains a gas having oxygen atoms, for example, oxygen gas. When both chlorine gas and oxygen gas are used, the ratio of the flow rate of oxygen gas to the flow rate of chlorine gas is preferably 0.1 or more and 2.0 or less in the supply of process gas, and more preferably the lower limit of this ratio Is 0.25. The process gas may also contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas, helium gas, or the like can be used. The thermal etching is preferably performed in a reduced pressure atmosphere, and more preferably, the reduced pressure atmosphere has a pressure of 1/10 or less of atmospheric pressure.

  The heat treatment temperature is preferably 700 ° C. or higher, more preferably 800 ° C. or higher, and further preferably 900 ° C. or higher. This can increase the etching rate. The heat treatment temperature is preferably 1200 ° C. or lower, more preferably 1100 ° C. or lower, and further preferably 1000 ° C. or lower. Thereby, the apparatus used for thermal etching can be simplified, and for example, a quartz member can be used.

  The thermal etching mask layer 71 (FIG. 17) is preferably made of silicon oxide. Thereby, the consumption of the mask during etching can be suppressed.

  By thermal etching as described above, a crystallographically specific crystal plane having high chemical stability can be self-formed as the sidewall SS (FIG. 2) of the gate trench GT. When the crystal structure of the SiC layer 10 is a hexagonal system, the crystal plane to be formed may include at least one of a {0-33-8} plane and a {01-1-4} plane. When the crystal structure is cubic, the crystal plane can include a {100} plane.

  Next, a method of using MOSFET 100 (FIG. 1) and the operation and effect of the present embodiment will be described below.

The MOSFET 100 is used as a switching element that performs switching of a current path between the drain electrode 31 and the source wiring layer 33. A positive voltage is applied to the drain electrode 31 with respect to the source wiring layer 33. When a positive voltage equal to or higher than the threshold value is applied to the gate electrode 30, an inversion layer exists in the p region 12 on the side wall SS of the gate trench GT, that is, the channel region. Therefore, n ⁻ drift region 11 and n region 13 are in an electrically connected state, and MOSFET 100 is in an on state.

When the application of a voltage equal to or higher than the threshold value to the gate electrode 30 is stopped, the inversion layer disappears, so that the supply of carriers from the source wiring layer 33 into the n ⁻ drift region 11 is stopped. As a result, depletion proceeds from the pn junction surface by the n ⁻ drift region 11 and the p region 12 toward the drain electrode 31. As a result, n ⁻ drift region 11 and charge compensation region 14 are depleted.

The positive fixed charge of the depleted n ⁻ drift region 11 becomes a factor for increasing the electric field strength in the thickness direction on the pn junction surface. On the other hand, since the depleted charge compensation region 14 has a negative fixed charge, the negative fixed charge cancels at least a part of the electric field intensity. That is, the charge compensation region 14 functions as a charge compensation structure. Thereby, the maximum value of the electric field strength in the thickness direction is suppressed. Therefore, the breakdown voltage of the MOSFET 100 can be improved.

  The charge compensation region 14 (FIG. 2) has a thickness TH that is preferably greater than 5 μm in the thickness direction DD. Thereby, the charge compensation structure is provided over a wider range in the thickness direction DD. Therefore, the breakdown voltage of MOSFET 100 can be further improved.

  In forming the penetration part PP (FIG. 9) of the charge compensation region 14, etching having a physical etching action is preferably used. Thereby, the etching for forming the penetration part PP can be performed more vertically. Thereby, the side surface SD (FIG. 2) of the charge compensation region 14 formed of the inner surface of the penetrating part PP can be along the thickness direction DD. Therefore, charge compensation by the charge compensation region 14 can be performed more sufficiently.

  The charge compensation region 14 (FIG. 1) is separated from the p region 12. Thereby, it is possible to avoid the impurities in the charge compensation region 14 from affecting the p region 12 functioning as a channel.

  In the present embodiment, thermal etching is used when the gate trench GT is formed. Thereby, the plane orientation of the side wall SS of the gate trench GT can be self-formed in a crystallographically specific one. Preferably, side wall SS of gate trench GT is inclined with respect to upper surface F2 of SiC layer 10 by an angle AF (FIG. 2) that is greater than 0 ° and smaller than 90 °. Thereby, a channel surface having a plane orientation inclined with respect to the upper surface F2 can be provided on the side wall SS of the gate trench GT. More preferably, the angle of the side surface SD (FIG. 2) of the charge compensation region 14 with respect to the thickness direction DD is smaller than the angle AD of the gate trench GT with respect to the thickness direction DD. Thereby, charge compensation by the charge compensation region 14 can be performed more sufficiently.

  The SiC layer 10 may have a hexagonal crystal structure. In this case, the sidewall SS of the gate trench GT of the SiC layer 10 is at least of the {0-33-8} plane and the {0-11-4} plane. It is preferable to include any part. Thereby, the carrier mobility on the side wall SS can be increased. Therefore, the on-resistance of MOSFET 100 can be suppressed.

  SiC layer 10 may have a cubic crystal structure. In this case, side wall SS of gate trench GT of SiC layer 10 preferably includes a portion formed of a {100} plane. Thereby, the carrier mobility on the side wall SS can be increased. Therefore, the on-resistance of MOSFET 100 can be suppressed.

  In the present embodiment, the cross section of the gate trench GT (FIG. 2) has a trapezoidal shape, but the shape of the gate trench is not limited to the trapezoid, and may be, for example, a V shape. In other words, the bottom of the gate trench is not necessarily a flat surface.

  The gate trench GT may be formed by dry etching other than thermal etching, and may be formed by, for example, RIE or IBE. The gate trench GT may be formed by etching other than dry etching, for example, wet etching. Further, the side walls facing each other of the gate trench are not necessarily required to have a non-parallel positional relationship as shown in FIG. 1, but may have a parallel relationship.

  Moreover, in the said embodiment, as shown in FIG. 4, the part enclosed by the side wall SS of the gate trench GT of the upper surface F2 has a hexagonal shape. The shape of this portion is not limited to a hexagonal shape, and may be, for example, a rectangle (including a square). This shape is preferably a hexagon having an angle of about 60 ° when the crystal structure of the SiC layer 10 is hexagonal, and is preferably a rectangle when the crystal structure is cubic.

(Embodiment 2)
As shown in FIG. 23, MOSFET 100D includes single crystal substrate 1, SiC layer 10D, drain electrode 31, source electrode 32, gate oxide film 21D, interlayer insulating film 22D, gate electrode 30D, and source wiring. Layer 33.

Further, referring to FIG. 24, SiC layer 10D has a lower surface F1 (first surface) and an upper surface F2 (second surface) that face each other in the thickness direction (vertical direction in the drawing). SiC layer 10D includes n ⁻ drift region 11 (first region), p region 12D (second region), n region 13D (third region), charge compensation region 14 (fourth region), and p ⁺ contact region. 15D. The p region 12D is provided on the covering portion 11c of the n ⁻ drift region 11 and has p type (second conductivity type different from the first conductivity type). N region 13D is provided on p region 12D, is separated from n ⁻ drift region 11 by p region 12D, and has n type (first conductivity type). The p ⁺ contact region 15D is provided directly on a part of the p region 12D and forms a part of the upper surface F2 of the SiC layer 10D.

The p region 12D is separated from the charge compensation region 14. Specifically, the p region 12 </ b> D is separated from the charge compensation region 14 by the covering portion 11 c of the n ⁻ drift region 11.

Gate oxide film 21D is provided on p region 12D so as to connect between n ⁻ drift region 11 and n region 13D on upper surface F2 of SiC layer 10D. Specifically, gate oxide film 21D covers p region 12D on upper surface F2 of SiC layer 10D. The gate electrode 30D is provided on the gate oxide film 21D. Thereby, gate electrode 30D is located on p region 12D of SiC layer 10D via gate oxide film 21D.

A source electrode 32 is provided directly on n region 13D and p ⁺ contact region 15D of SiC layer 10D.

  SiC layer 10D may have a hexagonal crystal structure, and in this case, upper surface F2 of SiC layer 10D is composed of at least one of a {0-33-8} plane and a {0-11-4} plane. It is preferable to include a portion. SiC layer 10D may have a cubic crystal structure, and in this case, upper surface F2 of SiC layer 10D preferably includes a portion formed of a {100} plane.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  Next, a method for manufacturing MOSFET 100D will be described. First, steps similar to those shown in FIGS. 6 to 11 of the first embodiment are performed.

As shown in FIG. 25, p region 12D, n region 13D, and p ⁺ contact region 15D are formed on covered portion 11c of n ⁻ drift region 11 by impurity ion implantation. Next, activation annealing is performed to activate the impurities implanted by ion implantation. For example, heating is performed at a temperature of 1700 ° C. for 30 minutes. Thereby, SiC layer 10 </ b> D is formed on single crystal substrate 1.

Referring to FIG. 26, upper surface F2 of SiC layer 10D is thermally oxidized to form gate oxide film 21D. Thereby, the p region 12D is covered with the gate oxide film 21D. Gate electrode 30 is formed on gate oxide film 21D. Gate electrode 30D is formed to have a portion located on p region 12D of SiC layer 10D through gate oxide film 21D. Interlayer insulating film 22 is formed on exposed gate oxide film 21D and gate electrode 30D. By patterning gate oxide film 21D and interlayer insulating film 22D, an opening that exposes p ⁺ contact region 15D and part of n region 13D is formed. Next, the source electrode 32 is formed in the opening. Thereby, the configuration shown in FIG. 26 is obtained.

Referring to FIG. 23 again, source wiring layer 33 is formed on interlayer insulating film 22D and source electrode 32. A drain electrode 31 is formed on n ⁻ drift region 11, that is, on lower surface F 1 of the SiC layer with single crystal substrate 1 interposed. Thus, MOSFET 100D is obtained.

In the method for manufacturing MOSFET 100 (FIG. 1) or MOSFET 100D (FIG. 23) in each of the above embodiments, a step of removing single crystal substrate 1 may be performed before forming drain electrode 31. In this case, MOSFET 100 (FIG. 1) does not have single crystal substrate 1, and drain electrode 31 is provided directly on n ⁻ drift region 11, that is, on lower surface F1.

  The first conductivity type is not limited to n-type, and may be p-type. The MOSFET is n-channel type when the first conductivity type is n-type, and p-channel type when the first conductivity type is p-type.

  The silicon carbide semiconductor device is not limited to a MOSFET, and may be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than a MOSFET.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the claims of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 single crystal substrate, 10,10D SiC layer (silicon carbide layer), 11 n ^- drift region (first region), 11a base portion, 11b buried portion, 11c covering part, 12, 12d p region (second region) 13, 13D n region (third region), 14 charge compensation region, 15, 15D p ⁺ contact region, 21, 21D gate oxide film (gate insulating film), 22, 22D interlayer insulating film, 30, 30D gate electrode, 31 drain electrode (first electrode), 32 source electrode (second electrode), 33 source wiring layer, 70, 71 mask layer, 100, 100D MOSFET (silicon carbide semiconductor device), BT bottom, F1 bottom surface (first surface) , F2 upper surface (second surface), GT gate trench, SD side surface, SS side wall.

Claims (3)

Forming a first conductivity type first layer on the main surface of the silicon carbide substrate by epitaxial growth;
Forming a second conductivity type second layer on the first layer by epitaxial growth;
Selectively etching the second layer to form first and second penetrating portions reaching the first layer and a charge compensation region between the first and second penetrating portions;
Forming, by epitaxial growth, a first conductive type third layer having first and second embedded portions embedded in the first and second penetrating portions and a covering portion covering the second layer;
Forming a second conductivity type first impurity region on the surface of the third layer, and a first conductivity type second impurity region on the first impurity region;
By selectively etching the second impurity region, the first impurity region, and the covering portion, the first impurity region and the second impurity region are formed above the first and second buried portions. Forming first and second trenches, each having a bottom surface in the covering portion,
Forming first and second gate electrodes on the first and second trenches via a gate insulating film;
Forming a first electrode on the back surface of the silicon carbide substrate;
Forming a second electrode on the second impurity region ,
Forming the first and second trenches includes:
Forming a mask layer on the second impurity region, covering the charge compensation region and having an opening above the first and second buried portions;
Using the mask layer, selectively etching the second impurity region, the first impurity region, and the covering portion, and forming the first and second trenches to have a bottom surface in the covering portion. A method for manufacturing a silicon carbide semiconductor device , comprising:   2. The silicon carbide semiconductor according to claim 1, wherein the first and second trenches are formed such that a pitch between the first and second through portions is equal to a pitch between the first and second trenches. Device manufacturing method. In the step of forming the first and second trenches, thermal etching is performed using the mask layer, so that the angle of the sidewalls of the first and second trenches with respect to the thickness direction of the third layer is The silicon carbide according to claim 1 , further comprising a step of inclining side walls of the first and second trenches so as to be larger than an angle of a side surface of the charge compensation region with respect to a thickness direction of two layers. A method for manufacturing a semiconductor device.

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