JP6234213B2 - Data transfer control device, data transfer control method, and data processing device - Google Patents

Description

  The present invention relates to a data transfer control device, a data transfer control method, and a data processing device.

  In a data processing apparatus such as a system LSI that is mounted on an imaging apparatus such as a digital camera and performs image processing, a single DRAM (Dynamic Random Access Memory) that is provided in the imaging apparatus and connected to the data processing apparatus is subjected to data processing. A plurality of processing blocks (hereinafter referred to as “initiator”) built in the apparatus are shared. In many data processing apparatuses, a plurality of built-in initiators are connected to a data bus (hereinafter referred to as an “interconnect bus”) inside the data processing apparatus, and each initiator connected to the interconnect bus has a DMA ( The DRAM is accessed by Direct Memory Access).

  In recent years, digital cameras have become more sophisticated and multifunctional, and the processing performance of data processing devices has been dramatically improved. For this reason, in a data processing apparatus having a large number of operation modes, it has become difficult to ensure the bus bandwidth of the DRAM to be accessed when executing processing according to the operation modes. In particular, in the case of image processing that needs to continue processing a large amount of image data at high speed, such as shooting still images and moving images simultaneously, multiple initiators perform different operations depending on the operation mode. It is necessary to transfer image data input from the image sensor to the DRAM in real time while arbitrating access requests to the DRAM from a plurality of different initiators to secure the DRAM bus bandwidth.

  In general, in a data processing apparatus, a built-in bus arbitration unit (for example, a bus arbiter) performs appropriate arbitration of access requests to DRAMs issued from respective initiators and optimization of access to DRAMs. DRAM bus bandwidth is secured. However, the DRAM has an operational restriction that, after a certain memory address is accessed once, the same memory bank including this memory address cannot be accessed for a certain period of time. That is, when accessing the same memory bank continuously, there is a period during which access cannot be accepted. Therefore, in a situation where the total load of access to the DRAM is high, when a certain initiator tries to access the DRAM, a waiting time during which the DRAM cannot be accessed due to operational restrictions of the DRAM (hereinafter referred to as “bank collision”). May occur.

  Therefore, conventionally, a technique for effectively using the generated waiting time has been disclosed. For example, in the technique disclosed in Patent Document 1, a refresh operation for a DRAM is executed during this waiting time, thereby effectively using the waiting time that occurs when the same memory bank is continuously accessed. doing.

  However, in the technique disclosed in Patent Document 1, it is not possible to effectively use access to the DRAM by performing other operations during the waiting time that occurs when the same memory bank is continuously accessed. Although it is possible, a bus band for exchanging data with the DRAM cannot be secured. Therefore, even when this technology is applied to a data processing device, an initiator that executes real-time processing such as transferring image data in real time under a situation where the total load of access to the DRAM is high may secure the DRAM bus bandwidth. The problem of being difficult remains.

  For this reason, in a system in which the total load of access to the DRAM is assumed to be high, an access request to the DRAM issued from each initiator and transfer data transferred to the DRAM are temporarily stored in a built-in memory such as a buffer. There is also a technology for data transfer control devices. When this technology is applied to a data processing device, when transferring the stored transfer data to the DRAM, the order of the access request to the DRAM and the transfer data is rearranged so as to avoid continuous access to the same memory bank. Can do. By rearranging the order of the access request to the DRAM and the transfer data, it is possible to eliminate the continuous access to the same memory bank and avoid the waiting time caused by the bank collision.

JP 2004-295976 A

  However, in order to temporarily store access requests to the DRAM issued from a plurality of initiators provided in the data processing device and transfer data transferred to the DRAM, it is necessary to provide a large-capacity built-in memory in the data transfer control device. is there. For example, in a system in which the number of built-in initiators is large (for example, several tens), and the situation in which each initiator accesses the DRAM varies greatly depending on the operation mode, each initiator has to wait for a bank collision. This is because it is necessary to provide a built-in memory having a capacity necessary for absorbing time.

  For this reason, if each of the initiators includes a large number of built-in memories, there is a problem that the circuit scale of the data processing device increases and the cost also increases. In some cases, the memory capacity that can be mounted on the hardware is limited, and in this case, the data transfer control device may not be provided with a built-in memory that is necessary for the data transfer control apparatus.

  The present invention has been made on the basis of the above-mentioned problem recognition, and is capable of ensuring the DRAM bus bandwidth and smoothly transferring transfer data by DMA while suppressing an increase in circuit scale. It is an object to provide a control device, a data transfer control method, and a data processing device.

In order to solve the above-described problem, the data transfer control device of the present invention provides a data transfer that outputs transfer data transferred via the common bus to each of a plurality of data transfer units that transfer data via the common bus. A plurality of transfer controls corresponding to each of the data transfer units and outputting the transfer data input from a data input unit corresponding to each of the data transfer units to the corresponding data transfer unit Each of the data transfer unit and the data transfer unit monitor the status of transferring the transfer data, and based on the transfer status of the transfer data of the monitored data transfer unit, A data transfer state monitoring unit that outputs transfer control information for controlling output of the transfer data to the corresponding data transfer unit, and a plurality of the transfers The at least one transfer control unit among the control units transfers the transfer data transferred by the data transfer unit based on the transfer control information of the corresponding data transfer unit by the data transfer unit. At least one other transfer control unit to which the data is distributed and output to the transfer data transferred by another data transfer unit corresponding to the other transfer control unit, and the transfer data is distributed, is distributed The transferred data is output to the corresponding data transfer unit based on the transfer control information of the corresponding data transfer unit, and each of the plurality of transfer control units includes a corresponding data transfer unit. Based on the transfer control information, a transfer buffer unit that temporarily stores the transfer data input from the corresponding data input unit, A buffer control unit that reads and outputs the transfer data stored in the transmission buffer unit, and is a transfer buffer unit included in the first transfer control unit that is the transfer control unit that distributes the transfer data. The first transfer buffer unit temporarily stores the first transfer data that is the transfer data transferred by the first data transfer unit that is the data transfer unit to which the first transfer control unit corresponds, and The first buffer control unit, which is a buffer control unit provided in the first transfer control unit, is configured based on the first transfer control information that is the transfer control information of the first data transfer unit. The first transfer data read from the transfer buffer unit is transferred by the first data transfer unit transferred by the first data transfer unit and another data transfer unit corresponding to another transfer control unit. The transfer buffer unit included in the second transfer control unit, which is the other transfer control unit to which the first transfer data is distributed, is distributed and output to the first transfer data to be transferred. The second transfer buffer unit temporarily stores the second transfer data that is the transfer data transferred by the second data transfer unit that is the data transfer unit to which the second transfer control unit corresponds, and The second buffer control unit, which is a buffer control unit included in the second transfer control unit, is configured to receive the second data when the first transfer data is not input from the first buffer control unit. Based on the second transfer control information that is the transfer control information of the transfer unit, the second transfer data read from the second transfer buffer unit is output to the second data transfer unit, and the first data transfer unit Buffer control part of Wherein when the first transfer data is input, based on said second transfer control information, and outputs the transfer data of the first to the second data transfer unit,
The data transfer state monitoring unit waits for the transfer of the first transfer data in the first data transfer unit based on a control signal when the first data transfer unit transfers the first transfer data. Data for monitoring time and outputting a time-out signal indicating that the transfer waiting time exceeds a predetermined time when the transfer waiting time of the monitored first transfer data exceeds a predetermined time Based on a signal when the transfer waiting time monitoring unit and the first data transfer unit transfer the first transfer data, a transfer history of the first transfer data in the first data transfer unit, Based on a signal when the second data transfer unit transfers the first transfer data or the second transfer data, the first transfer data or the second transfer data in the second data transfer unit Transfer An access history collection unit that collects the transfer history of the data, and the access history collection unit collects the first transfer data collected when the data transfer wait time monitoring unit outputs the timeout signal. Based on the transfer history and the transfer history of the second transfer data, transfer information for transferring the transfer data by the first transfer data and the second transfer data is transferred to the first buffer control unit. The first buffer control unit outputs the first transfer data to the first data transfer unit and the second buffer based on the transfer information output from the access history collection unit. The output is distributed to the control unit .

  Further, the data transfer state monitoring unit according to the present invention is configured so that the first data transfer unit includes the first data transfer unit based on a control signal when the first data transfer unit transfers the first transfer data. The transfer load of the transfer data is monitored, and it is determined whether or not to distribute the load by comparing the monitored transfer load of the first transfer data with a predetermined load size. A transfer load state monitoring unit that outputs a load distribution instruction for distributing a transfer load in the first data transfer unit based on a result, and the first buffer control unit includes: Based on the output load distribution instruction, the first transfer data is distributed and output to the first data transfer unit and the second buffer control unit.

  Further, the data transfer state monitoring unit of the present invention is configured to store the remaining storage capacity of the first transfer buffer unit based on a control signal when the first data transfer unit transfers the first transfer data. A transfer buffer remaining amount monitoring unit that monitors the amount and outputs a load distribution instruction for distributing the transfer load in the first data transfer unit according to the monitored remaining capacity of the storage capacity, The first buffer control unit sends the first transfer data to the first data transfer unit and the second buffer control unit based on the load distribution instruction output from the transfer buffer remaining amount monitoring unit. It is characterized in that it is sorted and output.

  Further, the data transfer state monitoring unit of the present invention determines a path of the first transfer data when transferring the first transfer data according to a set operation mode, and determines the result of the determination. Based on the route selection instruction output from the mode setting unit. The mode setting unit outputs a route selection instruction representing a route for transferring the first transfer data based on the mode setting unit. The first transfer data is distributed and output to the first data transfer unit and the second buffer control unit.

The data transfer control method of the present invention includes a plurality of transfer control units each having a transfer buffer unit and a buffer control unit, and a data transfer state monitoring unit having a data transfer waiting time monitoring unit and an access history collection unit. each of the plurality of data transfer unit for transferring data via a common bus, the common bus a data transfer control method in the data transfer control device for outputting the transfer data to be transferred via a plurality of transfer control unit Corresponding to each of the data transfer units, a plurality of transfer control procedures for outputting the transfer data input from the data input unit corresponding to each of the data transfer units to the corresponding data transfer unit, and data The transfer status monitoring unit monitors the status of each of the data transfer units transferring the transfer data, and the monitored data transfer unit A data transfer status monitoring procedure for outputting transfer control information for controlling the output of the transfer data to the corresponding data transfer unit in each of the transfer control procedures based on the transfer status of each of the transfer data. And at least one of the plurality of transfer control procedures includes transferring the transfer data transferred by the data transfer unit based on the transfer control information of the corresponding data transfer unit to the data transfer unit. At least one other transfer to which the transfer data is distributed and output to the transfer data to be transferred by the other data transfer unit corresponding to the other transfer control procedure. The control procedure is based on the transfer control information of the data transfer unit corresponding to the transferred data. Output to the data transfer unit to which the corresponding, each of the plurality of the transfer control procedure, the transfer control unit, the transfer buffer unit corresponding, input from the data input portion to which the data transfer unit corresponding the corresponding A transfer buffer procedure for temporarily storing the transfer data, and a buffer control for the corresponding buffer control unit to read out and output the transfer data stored in the corresponding transfer buffer unit based on the transfer control information The first transfer control procedure corresponds to the first transfer buffer procedure that is the transfer buffer procedure included in the first transfer control procedure that is the transfer control procedure that distributes the transfer data. The transfer buffer corresponding to the first transfer data which is the transfer data transferred by the first data transfer unit which is the data transfer unit A first buffer control procedure that is temporarily stored in the first transfer control procedure and that is a buffer control procedure included in the first transfer control procedure is a first transfer control that is the transfer control information of the first data transfer unit. Based on the information, the first transfer data read from the transfer buffer unit corresponding to the first transfer buffer procedure is transferred by the first data transfer unit and the other transfer data. The second transfer, which is another transfer control procedure to which the first transfer data is distributed, and is output after being distributed to the first transfer data transferred by another data transfer unit corresponding to the transfer control procedure. The second transfer buffer procedure which is the transfer buffer procedure included in the control procedure is transferred by the second data transfer unit which is the data transfer unit corresponding to the second transfer control procedure. The second transfer data which is the transfer data is temporarily stored in the corresponding transfer buffer unit, and the second buffer control procedure which is a buffer control procedure included in the second transfer control procedure is the first buffer control procedure. When the first transfer data is not input by the buffer control procedure, the second transfer buffer is based on the second transfer control information which is the transfer control information of the second data transfer unit. When the second transfer data read from the transfer buffer unit corresponding to the procedure is output to the second data transfer unit, and the first transfer data is input by the first buffer control procedure , Based on the second transfer control information, outputting the first transfer data to the second data transfer unit, the data transfer state monitoring procedure, the data transfer waiting time monitoring unit, The first data transfer unit monitors the transfer waiting time of the first transfer data in the first data transfer unit based on a control signal when the first transfer data is transferred, and the monitoring is performed. A data transfer waiting time monitoring procedure for outputting a time-out signal indicating that the transfer waiting time exceeds a predetermined time when the transfer waiting time of the first transfer data exceeds a predetermined time; A history collection unit configured to transfer a transfer history of the first transfer data in the first data transfer unit based on a signal when the first data transfer unit transfers the first transfer data; Based on a signal when the second data transfer unit transfers the first transfer data or the second transfer data, the first transfer data or the second transfer data in the second data transfer unit of An access history collecting procedure for collecting a transfer history, wherein the access history collecting procedure is configured to transfer a transfer history of the first transfer data collected when the timeout signal is output by the data transfer waiting time monitoring procedure. And transfer information for transferring the transfer data by the first transfer data and the second transfer data on the basis of the transfer history of the second transfer data and the second transfer data corresponding to the first buffer control procedure and outputs to the transfer control unit, the first buffer control procedure, based on the transfer information outputted by said access history collection procedure, the first transfer data, said first data transfer unit for It distributes and outputs to the said buffer control part corresponding to a said 2nd buffer control procedure, It is characterized by the above-mentioned.

The data processing apparatus of the present invention includes a plurality of data transfer units that transfer data via a common bus, and a plurality of data that correspond to each of the data transfer units and that output transfer data transferred via the common bus. A plurality of transfer controls corresponding to the data transfer units and outputting the transfer data input from the data input units corresponding to the data transfer units to the corresponding data transfer units. Each of the data transfer unit and the data transfer unit monitor the status of transferring the transfer data, and based on the transfer status of the transfer data of the monitored data transfer unit, A data transfer state monitoring unit that outputs transfer control information for controlling the output of the transfer data to the corresponding data transfer unit. And at least one of the plurality of transfer control units included in the data transfer control device is based on the transfer control information of the corresponding data transfer unit. The transfer data transferred by the data transfer unit is divided into the transfer data transferred by the data transfer unit and the transfer data transferred by another data transfer unit corresponding to the other transfer control unit, and the data transfer Among the plurality of transfer control units provided in the control device, at least one other transfer control unit to which the transfer data is distributed is configured to transfer the transferred data to the corresponding transfer unit. based on the control information, the corresponding output to the data transfer unit, wherein each of the plurality of the transfer control unit provided in the data transfer control device, pairs A transfer buffer unit that temporarily stores the transfer data input from the data input unit to which the data transfer unit corresponds, and the transfer data stored in the transfer buffer unit based on the transfer control information. A first transfer buffer unit that is the transfer buffer unit included in the first transfer control unit that is the transfer control unit that distributes the transfer data. Buffer control provided in the first transfer control unit temporarily stores the first transfer data that is the transfer data transferred by the first data transfer unit that is the data transfer unit to which the transfer control unit corresponds. The first buffer control unit that is a read unit reads from the first transfer buffer unit based on the first transfer control information that is the transfer control information of the first data transfer unit. The first transfer data transferred by the first data transfer unit corresponding to the first transfer data transferred by the first data transfer unit and the other data transfer unit corresponding to the other transfer control unit. The second transfer buffer unit that is the transfer buffer unit included in the second transfer control unit that is the other transfer control unit to which the first transfer data is distributed is The second transfer control unit temporarily stores the second transfer data which is the transfer data transferred by the second data transfer unit which is the corresponding data transfer unit, and is provided in the second transfer control unit. The second buffer control unit, which is a buffer control unit, uses the transfer control information of the second data transfer unit when the first transfer data is not input from the first buffer control unit. A second Based on the transfer control information, the second transfer data read from the second transfer buffer unit is output to the second data transfer unit, and the first transfer data is output from the first buffer control unit. When input, based on the second transfer control information, the first transfer data is output to the second data transfer unit, and the data transfer state monitoring unit provided in the data transfer control device Monitoring a transfer waiting time of the first transfer data in the first data transfer unit based on a control signal when the first data transfer unit transfers the first transfer data, A data transfer waiting time monitoring unit for outputting a time-out signal indicating that the transfer waiting time exceeds a predetermined time when the transfer waiting time of the monitored first transfer data exceeds a predetermined time; ,Previous Based on a signal when the first data transfer unit transfers the first transfer data, the transfer history of the first transfer data in the first data transfer unit, and the second data transfer unit Collecting the transfer history of the first transfer data or the second transfer data in the second data transfer unit based on a signal when transferring the first transfer data or the second transfer data An access history collection unit that performs the transfer history of the first transfer data collected when the data transfer waiting time monitoring unit outputs the timeout signal, and the second transfer history collection unit. Based on the transfer history of the transfer data, the transfer information for transferring the transfer data by the first transfer data and the second transfer data is output to the first buffer control unit, The first buffer control unit distributes the first transfer data to the first data transfer unit and the second buffer control unit based on the transfer information output from the access history collection unit. Output .

  Further, the data processing device of the present invention is configured to connect the data transfer control devices in a daisy chain according to the number of the data transfer units and the data input units, and monitor the data transfer state provided in each data transfer control device. Each of the corresponding data transfer units monitors the transfer state of the transfer data, and outputs the transfer control information to each of the transfer control units provided in the data transfer control device. At least one of the transfer control units provided in the control device, based on the transfer control information, the transfer data input from the corresponding data input unit, and at least one of the data corresponding to the data transfer control device It is characterized by allocating to the transfer unit.

  According to the present invention, it is possible to obtain an effect of ensuring a DRAM bus band and smoothly transferring transfer data by DMA while suppressing an increase in circuit scale.

It is the block diagram which showed an example of schematic structure of the data processor provided with the data transfer control apparatus in embodiment of this invention. It is the block diagram which showed an example of the structure of the data processor provided with the data transfer control apparatus in the 1st Embodiment of this invention. It is the flowchart which showed the process sequence of the data transfer operation | movement by the data transfer control apparatus of the 1st embodiment. It is the block diagram which showed an example of the structure of the data processor provided with the data transfer control apparatus in the 2nd Embodiment of this invention. It is the flowchart which showed the process sequence of the data transfer operation | movement by the data transfer control apparatus of the 2nd embodiment. It is the block diagram which showed an example of the structure of the data processor provided with the data transfer control apparatus in the 3rd Embodiment of this invention. It is the flowchart which showed the process sequence of the data transfer operation | movement by the data transfer control apparatus of the 3rd embodiment. It is the block diagram which showed an example of the structure of the data processor provided with the data transfer control apparatus in the 4th Embodiment of this invention. It is the flowchart which showed the process sequence of the data transfer operation | movement by the data transfer control apparatus of the 4th embodiment. It is the block diagram which showed an example of the structure of the data processor provided with the data transfer control apparatus of the modification of the 3rd Embodiment of this invention. 10 is a flowchart illustrating a processing procedure of a data transfer operation by a data transfer control device according to a modification of the third embodiment. It is the block diagram which showed an example of schematic structure of the data processor provided with the data transfer control apparatus in embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, the data processing device of the present invention is a data processing device such as a system LSI that is mounted on an imaging device such as a digital camera and performs image processing, and the data transfer device of the present invention is transferred to this data processing device. An example when the control device is applied will be described. FIG. 1 is a block diagram illustrating an example of a schematic configuration of a data processing device including a data transfer control device according to the present embodiment. The data processing device 1 shown in FIG. 1 includes a first image data input unit 100, a first data transfer unit 101, a second image data input unit 200, a second data transfer unit 201, and a data A transfer control device 10. Further, the data transfer control device 10 in the data processing device 1 includes a first transfer control unit 110, a second transfer control unit 210, and a data transfer state monitoring unit 130.

  As shown in FIG. 1, each of the first data transfer unit 101 and the second data transfer unit 201 included in the data processing device 1 is connected to an interconnect bus 700 inside the data processing device 1. . In the data processing device 1, the first data transfer unit 101 and the second data transfer unit 201 respectively include the first image data input unit 100 and the second image data input included in the data processing device 1. The image data input from the unit 200 is transferred to a memory (not shown) such as a DRAM via the interconnect bus 700.

  At this time, the data transfer control device 10 controls the image data that the data processing device 1 transfers to the memory by the first data transfer unit 101 and the second data transfer unit 201. In the following description, it is assumed that the memory connected to the data processing device 1 is a DRAM.

  Each of the first image data input unit 100 and the second image data input unit 200 is a supply source of image data to be transferred to the DRAM via the interconnect bus 700. In the following description, the first image data input unit 100 is, for example, a supply source of image data that transfers image data input from an image sensor (not shown) to the DRAM in real time. The description will be made assuming that the image data input unit 200 processes image data processed according to image data input from an image sensor (not shown) as a supply source of image data to be transferred to the DRAM. Here, as processing according to image data input from an image sensor (not shown) performed by the second image data input unit 200, for example, pre-processing for performing black level correction, or image generation for generating a reduced image For example, processing for generating an evaluation value for controlling processing, automatic exposure (Auto Exposure: AE), auto white balance (Auto White Balance: AWB), automatic focusing (Auto Focus: AF), and the like can be considered.

  In the following description, the image data supplied by the first image data input unit 100, that is, the image data transferred to the DRAM is referred to as “first transfer data”, and is supplied by the second image data input unit 200. The image data to be processed is referred to as “second transfer data”. Note that when the first transfer data and the second transfer data are expressed without distinction, they are simply referred to as “transfer data”.

  In the data processing apparatus 1 shown in FIG. 1, the first image data input unit 100 corresponds to the first data transfer unit 101, and the second image data input unit 200 corresponds to the second data transfer unit 201. It corresponds to. That is, FIG. 1 shows a configuration of a data processing apparatus in which one transfer data supply source exists for one data transfer unit. However, the data processing apparatus may have a configuration in which a plurality of transfer data supply sources correspond to one data transfer unit.

  Each of the first data transfer unit 101 and the second data transfer unit 201 outputs the transfer data input from the corresponding first image data input unit 100 or second image data input unit 200 to the interconnect bus 700. By doing so, it is an initiator that transfers each transfer data to the DRAM by DMA.

  However, in the data processing device 1, the data transfer control device 10 controls transfer data transferred to the DRAM by the first data transfer unit 101 and the second data transfer unit 201. Therefore, in the data processing device 1, transfer data that each of the first data transfer unit 101 and the second data transfer unit 201 transfers to the DRAM by DMA is input via the data transfer control device 10. In the following description, it is assumed that the first data transfer unit 101 is an initiator having a higher priority than the second data transfer unit 201.

  When each initiator transfers the transfer data to the DRAM by DMA, the initiator first outputs a request signal for requesting access to the DRAM by DMA to the interconnect bus 700, and then transfers the transfer data to be transferred to the DRAM. The data is output to the interconnect bus 700.

  More specifically, when an initiator requesting access to the DRAM outputs a request signal to the interconnect bus 700, the interconnect bus 700 is connected to a bus arbitration unit (not shown) such as a bus arbiter connected to the interconnect bus 700. A request signal is input via. As a result, a bus arbitration unit (not shown) arbitrates access requests to the DRAM according to the input request signal. The bus arbitration unit (not shown) outputs an acknowledge signal permitting the access request to the interconnect bus 700 when the access request to the DRAM is accepted, and sends an acknowledge signal to the initiator that has output the request signal. Returns (outputs) a signal. As a result, the initiator that has output the request signal outputs the transfer data to be transferred to the DRAM to the bus arbitration unit (not shown) via the interconnect bus 700 in accordance with the input acknowledge signal. A bus arbitration unit (not shown) accesses the DRAM at an appropriate timing, and transfers the input transfer data to the DRAM. In the following description, the above-described operation in which each initiator transfers transfer data to the DRAM by DMA is referred to as “DMA transfer”.

  The data transfer control device 10 monitors the state of DMA transfer in each of the first data transfer unit 101 and the second data transfer unit 201, and according to the monitored result, the first data transfer unit 101 or the second data transfer unit 101 The data transfer unit 201 determines whether to transfer the transfer data by DMA. Then, the data transfer control device 10 outputs the transfer data to the determined data transfer unit of the first data transfer unit 101 or the second data transfer unit 201 to perform the DMA transfer.

  The data transfer status monitoring unit 130 monitors the status of DMA transfer performed in each of the first data transfer unit 101 and the second data transfer unit 201. When the data transfer state monitoring unit 130 monitors the DMA transfer state, for example, the DMA transfer waiting time due to a DRAM bank collision, the access history to the DRAM, or the transfer of transfer data to the DRAM. Additional information such as numbers is also collected.

  Then, the data transfer state monitoring unit 130 outputs first transfer control information corresponding to the monitored DMA transfer state of the first data transfer unit 101 to the first transfer control unit 110. Further, the data transfer state monitoring unit 130 outputs second transfer control information corresponding to the DMA transfer state of the monitored second data transfer unit 201 to the second transfer control unit 210. The first transfer control information and the second transfer control information include the order in which transfer data is output to the corresponding first data transfer unit 101 and second data transfer unit 201, and the first data transfer unit. Also included is control information for arbitrating the timing between the first data transfer unit 101 and the second data transfer unit 201.

  A detailed description of the DMA transfer status monitoring in the data transfer status monitoring unit 130 and the control method of the first data transfer unit 101 and the second data transfer unit 201 will be described later.

  The first transfer control unit 110 receives the first transfer data to be DMA-transferred input from the first image data input unit 100 based on the first transfer control information input from the data transfer state monitoring unit 130. And the first data transfer unit 101 and the second data transfer unit 201. Note that the first transfer control unit 110 basically outputs the first transfer data input from the first image data input unit 100 to the first data transfer unit 101. However, the first transfer control unit 110 indicates that the first transfer control information input from the data transfer state monitoring unit 130 has a long waiting time when the first data transfer unit 101 performs DMA transfer, for example. When the first data transfer unit 101 indicates that the DMA transfer of the first transfer data is not smoothly performed, the first transfer data output to the first data transfer unit 101 is The data is output to the second transfer control unit 210 and transferred by the second data transfer unit 201.

  A detailed description of a method for distributing the first transfer data to the first data transfer unit 101 and the second data transfer unit 201 by the first transfer control unit 110 will be described later.

  The second transfer control unit 210 outputs, to the second data transfer unit 201, the second transfer data to be DMA-transferred input from the second image data input unit 200. However, the second transfer control unit 210 performs data transfer when the first transfer data distributed by the first transfer control unit 110 and transferred by the first image data input unit 100 is DMA-transferred. Based on the second transfer control information input from the state monitoring unit 130, the first transfer data input from the first transfer control unit 110 is selected and output to the second data transfer unit 201.

  Accordingly, the first transfer data output from the first image data input unit 100 is DMA-transferred by the second data transfer unit 201 in addition to the first data transfer unit 101, and the first image data It is possible to secure a bus bandwidth when the first transfer data output from the input unit 100 is DMA-transferred. As a result, the real-time property of the DMA transfer of the first transfer data output from the first image data input unit 100 can be ensured.

  Note that the second transfer control unit 210 selects a second transfer data input from the second image data input unit 200 or a first transfer data input from the first transfer control unit 110. Detailed description will be described later.

<First Embodiment>
Next, the configuration and operation of the data transfer control device 10 of this embodiment will be described in more detail. FIG. 2 is a block diagram illustrating an example of the configuration of the data processing device 1 including the data transfer control device 10 according to the first embodiment. In FIG. 2, the first transfer data input from the first image data input unit 100 is transferred to the first data transfer unit 101 and the second data based on the DMA transfer waiting time and the access history to the DRAM. 2 shows a configuration of the data transfer control device 10 that performs control to be distributed to the data transfer unit 201. The block diagram of the data processing device 1 shown in FIG. 2 only shows the components of the data transfer control device 10 in the data processing device 1 shown in FIG. 1 in more detail. Detailed descriptions regarding components other than 10 will be omitted.

  The first transfer control unit 110 in the data transfer control device 10 includes a first transfer buffer unit 111 and a first buffer control unit 112. The second transfer control unit 210 in the data transfer control device 10 includes a second transfer buffer unit 211 and a second buffer control unit 212. The data transfer state monitoring unit 130 in the data transfer control device 10 includes a data transfer waiting time monitoring unit 131 and a memory access history collection unit 132.

  The first transfer buffer unit 111 temporarily stores the first transfer data output from the first image data input unit 100. For example, the first transfer buffer unit 111 includes a first random access memory (SRAM) memory. This is a temporary storage buffer for transfer data. The first transfer buffer unit 111 outputs the stored first transfer data to the first buffer control unit 112 in accordance with the control from the first buffer control unit 112.

  The first buffer control unit 112 determines the output destination of the first transfer data to be transferred next based on the empty bank information included in the first transfer control information input from the data transfer state monitoring unit 130. The first data transfer unit 101 or the second buffer control unit 212 in the second transfer control unit 210 is determined. Then, the first buffer control unit 112 reads the first transfer data stored in the first transfer buffer unit 111, and outputs the read first transfer data to the determined output destination. That is, the first buffer control unit 112 converts the first transfer data read from the first transfer buffer unit 111 into the first transfer data based on the first transfer control information input from the data transfer state monitoring unit 130. The data transfer unit 101 or the second buffer control unit 212.

  The second transfer buffer unit 211 temporarily stores the second transfer data output from the second image data input unit 200. The second transfer buffer unit 211 temporarily stores the second transfer data, for example, composed of a memory such as an SRAM. It is a buffer. The second transfer buffer unit 211 outputs the stored second transfer data to the second buffer control unit 212 in accordance with the control from the second buffer control unit 212.

  The second buffer control unit 212 outputs the transfer data to be transferred next to the second data transfer unit 201 based on the second transfer control information input from the data transfer state monitoring unit 130. Note that the second buffer control unit 212, when the first transfer data is input from the first buffer control unit 112, the first transfer data input from the first buffer control unit 112, The data is output to the second data transfer unit 201. The second buffer control unit 212 also stores the second transfer data stored in the second transfer buffer unit 211 when the first transfer data is not input from the first buffer control unit 112. , And the read second transfer data is output to the second data transfer unit 201.

  The second buffer control unit 212 outputs the first transfer data input from the first buffer control unit 112 to the second data transfer unit 201 and the second data of the second transfer data. When the output to the transfer unit 201 competes, priority is given to the output of the first transfer data to the second data transfer unit 201. Therefore, the second buffer control unit 212 waits for the output of the conflicting second transfer data to the second data transfer unit 201. That is, the second buffer control unit 212 outputs the second transfer data to the second data transfer unit 201 when the first transfer data is not input from the first buffer control unit 112. .

  The data transfer waiting time monitoring unit 131 performs DMA transfer by the first data transfer unit 101 based on a control signal (for example, a request signal or an acknowledge signal) when the first data transfer unit 101 performs DMA transfer. Monitor latency. Then, the data transfer waiting time monitoring unit 131, when the DMA transfer waiting time by the first data transfer unit 101 exceeds a predetermined time, that is, the first transfer data by the first data transfer unit 101. When the DMA transfer is delayed without being smoothly performed, a time-out signal indicating this is notified (output) to the memory access history collection unit 132.

  The memory access history collection unit 132 is based on a control signal (for example, a request signal, an acknowledge signal, etc.) when the first data transfer unit 101 performs DMA transfer, and bank information obtained from the memory address of the DRAM. 1 collects access history to the DRAM by the data transfer unit 101. Further, the memory access history collection unit 132 is based on a control signal (for example, a request signal or an acknowledge signal) when the second data transfer unit 201 performs the DMA transfer, or bank information obtained from the memory address of the DRAM. The access history to the DRAM by the second data transfer unit 201 is collected.

  When the time-out signal is input from the data transfer wait time monitoring unit 131, the memory access history collection unit 132 sends the collected data to the DRAM by the first data transfer unit 101 and the second data transfer unit 201, respectively. Based on the access history, a memory bank of the DRAM that can be accessed by each of the first data transfer unit 101 and the second data transfer unit 201 is determined. Then, the memory access history collection unit 132 uses the first buffer control unit to store empty bank information representing a memory bank that can be transferred next by the second data transfer unit 201 based on the determined information of the memory bank. To 112.

  Based on this empty bank information, the first buffer control unit 112 determines the output destination of the first transfer data to be transferred next to the second data transfer unit 201 and reads out from the first transfer buffer unit 111. By outputting the first transfer data to the second buffer control unit 212, the first transfer data is DMA-transferred to the second data transfer unit 201. As described above, in the data transfer control device 10, the first transfer data is transferred in parallel by the first data transfer unit 101 and the second data transfer unit 201 by performing the DMA transfer of the first transfer data. Real-time performance of DMA transfer is ensured.

  It should be noted that the output destination of the first transfer data by the first buffer control unit 112 is preferably determined to a data transfer unit that does not cause a bank collision of the DRAM. Accordingly, the first buffer control unit 112 transfers the first transfer data to the first transfer data when the second data transfer unit 201 causes the DMA transfer by the DMA transfer of the first transfer data to be transferred next. The order of reading from the first transfer buffer unit 111 is changed, and even if DMA transfer is performed by the second data transfer unit 201, a bank collision does not occur. For example, the first transfer data to be transferred second is read first, You may output to the 2nd buffer control part 212.

  Next, the operation of the data transfer control device 10 will be described. FIG. 3 is a flowchart showing the processing procedure of the data transfer operation by the data transfer control device 10 of the first embodiment. When the first transfer data is input from the first image data input unit 100, the data transfer control device 10 starts the DMA transfer from step S100 to the first data transfer unit 101 and the second data transfer unit 201. Collection of access information to the DRAM (hereinafter referred to as “memory access information”) such as a control signal and a memory address at the time of execution is started. Note that the collection of memory access information is always performed continuously even when the subsequent processing procedure is executed.

  Then, the data transfer wait time monitoring unit 131 monitors the DMA transfer wait time by the first data transfer unit 101 based on the collected memory access information. More specifically, the DMA transfer waiting time is monitored by measuring the time from when the first data transfer unit 101 outputs a request signal to the interconnect bus 700 until the acknowledge signal is returned.

  Further, the memory access history collection unit 132 collects access histories to the DRAM by the first data transfer unit 101 and the second data transfer unit 201 based on the collected memory access information. More specifically, for example, the memory address of the DRAM specified when the first data transfer unit 101 outputs the request signal to the interconnect bus 700, or the memory address of the DRAM specified when the acknowledge signal is returned. Based on the above, the first data transfer unit 101 determines the memory bank of the DRAM to which the first transfer data is DMA transferred. Then, the information of the determined DRAM memory bank is collected as the access history to the DRAM by the first data transfer unit 101.

  Thereafter, the data transfer waiting time monitoring unit 131 determines that the DMA transfer waiting time by the first data transfer unit 101 being monitored exceeds a predetermined time (“YES” in step S110), that is, the first When a timeout of DMA transfer of the data transfer unit 101 is detected, a timeout signal is output to the memory access history collection unit 132. When a time-out signal is input from the data transfer wait time monitoring unit 131, the memory access history collection unit 132 outputs the empty bank information determined based on the collected access history to the DRAM to the first buffer control unit 112. To do.

  The data transfer wait time monitoring unit 131 determines that the DMA transfer wait time being monitored does not exceed a predetermined time ("NO" in step S110), that is, if no timeout has been detected. Return to step S100 and continue monitoring the DMA transfer waiting time.

  When empty bank information is input from the memory access history collection unit 132, in step S120, the first buffer control unit 112 distributes the output destination of the first transfer data, and the first data transfer unit 101 and the first data transfer unit 101 The parallel transfer of the first transfer data by the second data transfer unit 201 is started. Then, the first buffer control unit 112 outputs the next first transfer data to be DMA-transferred by the second data transfer unit 201 to the second buffer control unit 212.

  Subsequently, in step S130, the second buffer control unit 212 changes the output order of the transfer data output to the second data transfer unit 201, and then outputs the second data output to the second data transfer unit 201. Instead of the transfer data, the first transfer data input from the first buffer control unit 112 is output to the second data transfer unit 201.

  Subsequently, in step S140, the first buffer control unit 112 changes the output order of the first transfer data output to the first data transfer unit 101, that is, causes the second data transfer unit 201 to perform DMA transfer. Assuming that the next first transfer data has been output, the first transfer data to be output to the first data transfer unit 101 is output to the first data transfer unit 101.

  As a result, the first transfer data output to the second data transfer unit 201 in step S130 and the first transfer data output to the first data transfer unit 101 in step S140 are DMA-transferred in parallel. Transferred.

  Thereafter, in step S150, when the memory access history collection unit 132 recognizes that the DMA transfer of the first transfer data by the second data transfer unit 201 is completed based on the collected memory access information, in step S160. The first buffer control unit 112 ends the first parallel transfer of the first transfer data by the first data transfer unit 101 and the second data transfer unit 201. Note that during steps S140 to S160, the memory access history collection unit 132 recognizes the completion of the DMA transfer of the first transfer data by the first data transfer unit 101 based on the collected memory access information. It is thought that there is also.

  Thereafter, the data transfer control device 10 repeats the processing procedure of the flowchart of the data transfer operation shown in FIG. 3 to perform DMA transfer of all the first transfer data input from the first image data input unit 100. .

  According to the first embodiment, each of the plurality of data transfer units (the first data transfer unit 101 and the second data transfer unit 201) that transfers data via the common bus (interconnect bus 700) A data transfer control device (data transfer control device 10) for outputting transfer data transferred via the interconnect bus 700, corresponding to each of the first data transfer unit 101 and the second data transfer unit 201, Transfer data input from data input units (first image data input unit 100 and second image data input unit 200) corresponding to the first data transfer unit 101 and the second data transfer unit 201, respectively, A plurality of transfer control units (the first transfer control unit 110 and the first transfer control unit 110) output to the corresponding first data transfer unit 101 or second data transfer unit 201. And the second transfer control unit 210), the first data transfer unit 101, and the second data transfer unit 201 are monitoring the state of transferring the transfer data, and the first data transfer monitored here First data transfer corresponding to the transfer data in each of the first transfer control unit 110 and the second transfer control unit 210 based on the transfer state of the transfer data of each of the unit 101 and the second data transfer unit 201 Data transfer status monitoring unit (data transfer status monitoring unit 130) that outputs transfer control information (first transfer control information and second transfer control information) for controlling output to the unit 101 or the second data transfer unit 201 And at least one transfer control unit (first transfer control unit 110) among the plurality of first transfer control units 110 and second transfer control units 210 has a corresponding first Transfer data (first transfer data) transferred by the first data transfer unit 101 is transferred by the first data transfer unit 101 based on the first transfer control information of the first data transfer unit 101. 1 transfer data and the other transfer control unit (second transfer control unit 210) distribute and output the first transfer data transferred by the other second data transfer unit 201 corresponding to the transfer data, and the transfer data is distributed The at least one other transfer control unit (second transfer control unit 210) is configured to assign the distributed first transfer data based on the second transfer control information of the corresponding second data transfer unit 201. Thus, the data transfer control device 10 that outputs to the corresponding second data transfer unit 201 is configured.

  Further, according to the first embodiment, each of the plurality of data transfer units (the first data transfer unit 101 and the second data transfer unit 201) that transfers data via the common bus (interconnect bus 700). In addition, a data transfer control method in a data transfer control device (data transfer control device 10) that outputs transfer data transferred via an interconnect bus 700, which includes a first data transfer unit 101 and a second data transfer unit 201. From the data input units (the first image data input unit 100 and the second image data input unit 200) corresponding to the first data transfer unit 101 and the second data transfer unit 201, respectively. A plurality of transfers for outputting the input transfer data to the corresponding first data transfer unit 101 or second data transfer unit 201 The procedure (the processing procedure in the first transfer control unit 110 and the second transfer control unit 210) and the state in which each of the first data transfer unit 101 and the second data transfer unit 201 is transferring the transfer data And the first transfer control unit 110 and the second transfer control based on the transfer state of the respective transfer data of the first data transfer unit 101 and the second data transfer unit 201 monitored here. The transfer control information (first transfer control information and second transfer control information) for controlling the output of the transfer data in the unit 210 to the corresponding first data transfer unit 101 or second data transfer unit 201 is output. A data transfer state monitoring procedure (a processing procedure in the data transfer state monitoring unit 130), and a plurality of first transfer control units 110 and second transfer control units 210 Among the processing procedures, at least one transfer control procedure (a processing procedure in the first transfer control unit 110) is based on the first transfer control information of the corresponding first data transfer unit 101. Transfer data (first transfer data) transferred by the data transfer unit 101 is transferred to the first transfer data transferred by the first data transfer unit 101 and other transfer control procedures (processing in the second transfer control unit 210). At least one other transfer control procedure (second transfer control) in which the transfer data is distributed and output to the first transfer data transferred by the other second data transfer unit 201 to which the corresponding procedure is transferred. The processing procedure in the unit 210) distributes the distributed first transfer data based on the second transfer control information of the corresponding second data transfer unit 201. A data transfer control method for outputting to the data transfer unit 201 is configured.

  Further, according to the first embodiment, a plurality of data transfer units (the first data transfer unit 101 and the second data transfer unit 201) that transfer data via the common bus (interconnect bus 700), Corresponding to each of the first data transfer unit 101 and the second data transfer unit 201, a plurality of data input units (the first image data input unit 100 and the first image data input unit 100 and the second data transfer unit 201) that output transfer data transferred via the interconnect bus 700 2 image data input unit 200), and first data transfer unit 101 and second data transfer unit 201, respectively, and each of first data transfer unit 101 and second data transfer unit 201 The transfer data input from the corresponding first image data input unit 100 or the second image data input unit 200 is converted into the corresponding first data transfer unit. 01 or a plurality of transfer control units (first transfer control unit 110 and second transfer control unit 210) that output to the second data transfer unit 201, the first data transfer unit 101, and the second data transfer unit Each of 201 monitors the state of transferring the transfer data, and based on the transfer state of each transfer data of the first data transfer unit 101 and the second data transfer unit 201 monitored here, Transfer control information (first transfer control) for controlling the output of the transfer data in the first transfer control unit 110 and the second transfer control unit 210 to the corresponding first data transfer unit 101 or second data transfer unit 201 Data transfer state monitoring unit (data transfer state monitoring unit 130) that outputs information and second transfer control information) (data transfer control device) 0), and at least one transfer control unit (first transfer control unit 110) among the plurality of first transfer control units 110 and second transfer control units 210 included in the data transfer control device 10 , Based on the first transfer control information of the corresponding first data transfer unit 101, transfer data (first transfer data) transferred by the first data transfer unit 101 is transferred to the first data transfer. The first transfer data transferred by the unit 101 and the first transfer data transferred by another second data transfer unit 201 corresponding to another transfer control unit (second transfer control unit 210) are output. Then, at least one other transfer control unit (second transfer unit) to which transfer data is distributed among the plurality of first transfer control units 110 and second transfer control units 210 provided in the data transfer control device 10. control The unit 210) outputs the distributed first transfer data to the corresponding second data transfer unit 201 based on the second transfer control information of the corresponding second data transfer unit 201. A processing device (data processing device 1) is configured.

  Further, according to the first embodiment, each of the plurality of first transfer control units 110 and second transfer control units 210 corresponds to the corresponding first data transfer unit 101 or second data transfer unit 201. Is a transfer buffer unit (first transfer buffer unit 111 or second transfer buffer unit) that temporarily stores the transfer data input from the first image data input unit 100 or the second image data input unit 200 corresponding to 211) and the buffer control unit (the first buffer control unit 112 or the second buffer unit) that reads out and outputs the transfer data stored in the first transfer buffer unit 111 or the second transfer buffer unit 211 based on the transfer control information. 2, a buffer control unit 212), and a transfer buffer unit included in the first transfer control unit 110, which is a transfer control unit that distributes the first transfer data. The transfer buffer unit 111 temporarily stores first transfer data which is transfer data transferred by the first data transfer unit 101 which is a data transfer unit to which the first transfer control unit 110 corresponds. The first buffer control unit 112, which is a buffer control unit provided in the first transfer control unit 110, is based on the first transfer control information that is the transfer control information of the first data transfer unit 101. The first transfer data read from the transfer buffer unit 111 is transferred by the first data transfer unit 101 and other data corresponding to the other transfer control unit (second transfer control unit 210). The second transfer control unit 2 which is another transfer control unit to which the first transfer data is distributed and output by being distributed to the first transfer data to be transferred by the transfer unit (second data transfer unit 201). A second transfer buffer unit 211 that is a transfer buffer unit provided for 0 is a second transfer data that is transferred by the second data transfer unit 201 that is a data transfer unit to which the second transfer control unit 210 corresponds. The second buffer control unit 212, which is a buffer control unit provided in the second transfer control unit 210, temporarily receives the first transfer data from the first buffer control unit 112. If not, the second transfer data read from the second transfer buffer unit 211 is converted to the second data based on the second transfer control information that is the transfer control information of the second data transfer unit 201. When the first transfer data is output to the transfer unit 201 and is input from the first buffer control unit 112, the first transfer data is transferred to the second data transfer based on the second transfer control information. Part The data transfer control device 10 that outputs to 201 is configured.

  In addition, according to the first embodiment, the data transfer state monitoring unit 130 controls the control signal (for example, a request signal or an acknowledge signal) when the first data transfer unit 101 transfers the first transfer data. The first data transfer unit 101 monitors the first transfer data transfer waiting time based on the first transfer data, and the first transfer data transfer waiting time monitored here exceeds a predetermined time. A data transfer waiting time monitoring unit (data transfer waiting time monitoring unit 131) that outputs a time-out signal indicating that the transfer waiting time has exceeded a predetermined time, and the first data transfer unit 101 uses the first transfer data The first data transfer unit 101 uses the first data transfer unit 101 based on a signal (for example, a request signal, an acknowledge signal, or a DRAM memory address). Based on a transfer history of transfer data and a signal (for example, a request signal, an acknowledge signal, or a memory address of a DRAM) when the second data transfer unit 201 transfers the first transfer data or the second transfer data. An access history collection unit (memory access history collection unit 132) for collecting the first transfer data or the transfer history of the second transfer data in the second data transfer unit 201, and collecting the memory access history When the data transfer waiting time monitoring unit 131 outputs a time-out signal, the unit 132 determines the first transfer data based on the transfer history of the first transfer data and the transfer history of the second transfer data collected. Transfer information (empty bank information) for transferring the transfer data with the second transfer data is output to the first buffer control unit 112, and The buffer control unit 112 distributes the first transfer data to the first data transfer unit 101 and the second buffer control unit 212 based on the empty bank information output from the memory access history collection unit 132. A data transfer control device 10 for outputting is configured.

  In this manner, the data transfer control device 10 uses the first transfer data input from the first image data input unit 100 as the first transfer data based on the DMA transfer waiting time and the access history to the DRAM. The data is transferred to the data transfer unit 101 and the second data transfer unit 201, and DMA transfer is performed in parallel. As a result, the data transfer control device 10 secures a bus bandwidth for DMA transfer of the first transfer data output from the first image data input unit 100, and the DMA transfer is smoothly performed. Real-time property of DMA transfer of transfer data can be ensured.

  Note that the DMA transfer of the transfer data by the first data transfer unit 101 and the second data transfer unit 201 is preferably determined as a data transfer unit that does not cause a DRAM bank collision. For this reason, each of the first buffer control unit 112 and the second buffer control unit 212 also outputs the transfer data to the corresponding data transfer unit even in normal DMA transfer. It is conceivable that the output order of transfer data is rearranged so that DMA transfer is performed to different memory banks of the DRAM. Accordingly, the first transfer data output from the first buffer control unit 112 to the second buffer control unit 212 in step S120 is the next first transfer data, that is, the current DMA transfer as described above. The first transfer data is not limited to the first transfer data continuous to the first transfer data.

  In the first embodiment, the configuration in which the data transfer wait time monitoring unit 131 detects the timeout of the DMA transfer wait time has been described. For example, the DMA transfer wait time in the first data transfer unit 101 is described. And a DMA transfer waiting time in the second data transfer unit 201 may be monitored. Further, for example, the data transfer waiting time monitoring unit 131 sets the average time of the DMA transfer waiting time in the first data transfer unit 101 and the average time of the DMA transfer waiting time in the second data transfer unit 201, respectively. May be configured to monitor. In this case, the memory access history collection unit 132 determines the DMA transfer waiting time and the average waiting time of the first data transfer unit 101 and the second data transfer unit 201 monitored by the data transfer waiting time monitoring unit 131. Based on the ratio, for example, the first buffer control unit 112 may be configured to output information indicating the ratio of distributing the output destination of the first transfer data to the first buffer control unit 112. Even in such a configuration, the data transfer control device 10 uses the first data transfer unit 101 and the second data transfer unit 201 as the first transfer data input from the first image data input unit 100. And DMA transfer can be performed in parallel.

<Second Embodiment>
Next, another configuration and operation of the data transfer control device 10 of this embodiment will be described. In the following description, in order to distinguish the data transfer control device 10 of the present embodiment from the data transfer control device 10 of the first embodiment, the data transfer control device of the second embodiment is referred to as “data It is referred to as “transfer control device 20”. The data processing device provided with the data transfer control device 20 is referred to as “data processing device 2”. FIG. 4 is a block diagram illustrating an example of the configuration of the data processing device 2 including the data transfer control device 20 according to the second embodiment. In FIG. 4, the first transfer data input from the first image data input unit 100 is transferred to the first data transfer unit 101 and the second data transfer unit 201 based on the load state of the DMA transfer. 2 shows a configuration of a data transfer control device 20 that performs distribution control.

  The data processing device 2 shown in FIG. 4 has a configuration in which the data transfer control device 10 in the data processing device 1 shown in FIG. 2 replaces the data transfer control device 20, and the constituent elements of the data transfer control device 20 are the same. Shows in more detail. The components in the data processing device 2 and the data transfer control device 20 shown in FIG. 4 include the components in the data processing device 1 and the data transfer control device 10 shown in FIGS. Constituent elements similar to the constituent elements are included. Therefore, in the components of the data processing device 2 and the data transfer control device 20 shown in FIG. 4, the same components as those of the data processing device 1 and the data transfer control device 10 shown in FIGS. The same reference numerals are given, and detailed descriptions of the respective components are omitted.

  Similar to the data transfer control device 10 of the first embodiment, the data transfer control device 20 transfers transfer data that the data processing device 2 performs DMA transfer to the DRAM by the first data transfer unit 101 and the second data transfer unit 201. To control. Therefore, also in the data processing device 2, similarly to the data transfer control device 10 of the first embodiment, the transfer data that each of the first data transfer unit 101 and the second data transfer unit 201 performs DMA transfer is the data transfer. It is input via the control device 20. In the following description, as in the data processing apparatus 1 of the first embodiment, the first data transfer unit 101 is an initiator having a higher priority than the second data transfer unit 201. Will be described.

  The data transfer control device 20 monitors the state of the DMA transfer in each of the first data transfer unit 101 and the second data transfer unit 201, and according to the monitored result, the first data transfer unit 101 or the second data transfer unit 20 The data transfer unit 201 of the first data transfer unit 201 determines whether the transfer data is DMA-transferred, and the transferred data is transferred to the data transfer unit of the determined first data transfer unit 101 or the second data transfer unit 201. Is output to cause DMA transfer. The data transfer control device 20 includes a first transfer control unit 140, a second transfer control unit 210, and a data transfer state monitoring unit 150.

  Similar to the first transfer control unit 110 of the first embodiment, the first transfer control unit 140 transfers the first transfer data input from the first image data input unit 100 for DMA transfer to the data transfer unit. Based on the first transfer control information input from the state monitoring unit 150, the data is distributed to the first data transfer unit 101 and the second data transfer unit 201. The first transfer control unit 140 includes a first transfer buffer unit 111 and a first buffer control unit 142.

  The first transfer buffer unit 111 stores the first transfer data output from the first image data input unit 100, and stores the first transfer stored in accordance with the control from the first buffer control unit 142. The data is output to the first buffer control unit 142.

  The first buffer control unit 142 sets the output destination of the first transfer data to be transferred next in response to the load distribution instruction included in the first transfer control information input from the data transfer state monitoring unit 150. The first data transfer unit 101 or the second buffer control unit 212 in the second transfer control unit 210 is determined. Then, the first buffer control unit 142 reads the first transfer data stored in the first transfer buffer unit 111, and outputs the read first transfer data to the determined output destination. In other words, the first buffer control unit 142 responds to the load distribution instruction input from the data transfer state monitoring unit 150 in the same manner as the first buffer control unit 112 in the first embodiment, as in the first transfer buffer. The first transfer data read from the unit 111 is distributed to either the first data transfer unit 101 or the second buffer control unit 212.

  Then, when the first transfer data is input from the first buffer control unit 142, the second buffer control unit 212 receives the first transfer data input from the first buffer control unit 142, The data is output to the second buffer control unit 212. Thereby, the first transfer data output from the first image data input unit 100 is added to the first data transfer unit 101 and the second transfer data in the same manner as the data transfer control device 10 of the first embodiment. The data transfer unit 201 also performs DMA transfer.

  The data transfer state monitoring unit 150 is a DMA transfer state performed in each of the first data transfer unit 101 and the second data transfer unit 201, similarly to the data transfer state monitoring unit 130 of the first embodiment. To monitor. At this time, the data transfer state monitoring unit 150 collects transfer load information such as a DMA transfer waiting time due to DRAM bank collision and the number of transfer data transferred to the DRAM. Then, the data transfer state monitoring unit 150 uses the load distribution instruction according to the monitored DMA transfer load state of the first data transfer unit 101 as the first transfer control information in the first transfer control unit 140. 1 to the buffer control unit 142.

  Note that the second transfer control information output to the second transfer control unit 210 according to the DMA transfer state of the second data transfer unit 201 monitored by the data transfer state monitoring unit 150 is the same as that of the first embodiment. This is the same as the data transfer state monitoring unit 130. Further, the first transfer control information and the second transfer control information include the same as the first transfer control information and the second transfer control information output by the data transfer state monitoring unit 130 of the first embodiment. Control for arbitrating the order of outputting the transfer data to the corresponding first data transfer unit 101 and second data transfer unit 201 and the timing of the first data transfer unit 101 and the second data transfer unit 201 Information is also included. The data transfer state monitoring unit 150 includes a transfer load state monitoring unit 151.

  The transfer load state monitoring unit 151 loads the DMA transfer by the first data transfer unit 101 based on a control signal (for example, a request signal or an acknowledge signal) when the first data transfer unit 101 performs DMA transfer. To monitor. Then, the transfer load state monitoring unit 151 determines whether or not to distribute the load depending on whether or not the DMA transfer load in the monitored first data transfer unit 101 is larger than a predetermined load. Then, the transfer load state monitoring unit 151 outputs, to the first buffer control unit 142, a load distribution instruction for distributing the load when the first data transfer unit 101 performs the DMA transfer based on the determined result. To do.

  In response to this load distribution instruction, the first buffer control unit 142 determines the output destination of the first transfer data to be transferred next to the second data transfer unit 201 and reads it from the first transfer buffer unit 111. By outputting the first transfer data to the second buffer control unit 212, the first transfer data is DMA-transferred to the second data transfer unit 201. Thus, in the data transfer control device 20, the first data transfer is performed by causing the first data transfer unit 101 and the second data transfer unit 201 to perform the DMA transfer of the first transfer data in parallel. The load when the unit 101 performs DMA transfer is distributed, and the real-time property of DMA transfer of the first transfer data is ensured.

  Further, the transfer load state monitoring unit 151 is based on a control signal (for example, a request signal or an acknowledge signal) when the second data transfer unit 201 performs DMA transfer, or bank information obtained from a memory address of the DRAM. The state of DMA transfer by the second data transfer unit 201 is monitored.

  Even when the first buffer control unit 142 distributes the load when the first data transfer unit 101 performs DMA transfer, it is desirable that no bank collision of DRAM occurs. Therefore, the first buffer control unit 142, like the first buffer control unit 112 of the first embodiment, changes the order of reading the first transfer data from the first transfer buffer unit 111, etc. The first transfer data to be output to the second buffer control unit 212 may be selected.

  Next, the operation of the data transfer control device 20 will be described. FIG. 5 is a flowchart showing the processing procedure of the data transfer operation by the data transfer control device 20 of the second embodiment. When the first transfer data is input from the first image data input unit 100, the data transfer control device 20 starts DMA transfer in the first data transfer unit 101 and the second data transfer unit 201 from step S200. Collection of transfer load information (hereinafter referred to as “transfer load information”) is started. Note that the collection of transfer load information is always performed continuously even when the subsequent processing procedure is executed.

  Then, the transfer load state monitoring unit 151 monitors the load state of the DMA transfer in the first data transfer unit 101 based on the collected transfer load information. More specifically, the DMA transfer waiting time until the acknowledge signal is returned after the first data transfer unit 101 outputs the request signal to the interconnect bus 700, or the first data transfer unit 101 requests the request. The DMA transfer load state is monitored by measuring the number of times the signal is output.

  Further, the transfer load state monitoring unit 151 monitors the state of the DMA transfer by the second data transfer unit 201 based on the collected transfer load information. More specifically, based on the memory address of the DRAM specified when the second data transfer unit 201 outputs the request signal to the interconnect bus 700, or the memory address of the DRAM specified when the acknowledge signal is returned. Thus, the second data transfer unit 201 monitors the memory bank of the DRAM that is DMA-transferred.

  Thereafter, when the load state of the DMA transfer by the monitored first data transfer unit 101 is larger than a predetermined load (“YES” in step S210), the transfer load state monitoring unit 151 performs the first data transfer. The load of the unit 101 is determined to be distributed, and a load distribution instruction is output to the first buffer control unit 142.

  The transfer load state monitoring unit 151 determines that the load state of the DMA transfer by the first data transfer unit 101 being monitored is not larger than a predetermined load (“NO” in step S210), step S200. Returning to FIG. 2, the monitoring of the DMA transfer load state in the first data transfer unit 101 is continued.

  When a load distribution instruction is input from the transfer load state monitoring unit 151, in step S220, the first buffer control unit 142 distributes the output destination of the first transfer data, that is, the first data transfer unit 101 and The parallel transfer of the first transfer data by the second data transfer unit 201 is started. Then, the first buffer control unit 142 outputs the next first transfer data to be DMA-transferred by the second data transfer unit 201 to the second buffer control unit 212.

  Subsequently, in step S230, the second buffer control unit 212 changes the output order of the transfer data output to the second data transfer unit 201, and then outputs the second data output to the second data transfer unit 201. Instead of the transfer data, the first transfer data input from the first buffer control unit 142 is output to the second data transfer unit 201.

  Subsequently, in step S240, the first buffer control unit 142 changes the output order of the first transfer data output to the first data transfer unit 101, that is, the second data transfer unit 201 performs the DMA transfer. Assuming that the next first transfer data has been output, the first transfer data to be output to the first data transfer unit 101 is output to the first data transfer unit 101.

  As a result, the first transfer data output to the second data transfer unit 201 in step S230 and the first transfer data output to the first data transfer unit 101 in step S240 are each in parallel. Transferred.

  Thereafter, in step S250, when the transfer load state monitoring unit 151 recognizes that the DMA transfer of the first transfer data by the second data transfer unit 201 is completed based on the collected transfer load information, in step S260. The first buffer control unit 142 ends the first parallel transfer of the first transfer data by the first data transfer unit 101 and the second data transfer unit 201. In addition, between step S240 and step S260, the transfer load state monitoring unit 151 recognizes the completion of the DMA transfer of the first transfer data by the first data transfer unit 101 based on the collected transfer load information. It is thought that there is also.

  Thereafter, the data transfer control device 20 repeats the processing procedure in the flowchart of the data transfer operation shown in FIG. 5 to perform DMA transfer of all the first transfer data input from the first image data input unit 100. .

  According to the second embodiment, the data transfer state monitoring unit (data transfer state monitoring unit 150) controls the control signal (eg, request signal) when the first data transfer unit 101 transfers the first transfer data. And the load of the first transfer data in the first data transfer unit 101, and the transfer load of the first transfer data monitored here and the predetermined load are large. Transfer load state for determining whether or not to distribute the load by comparing the two, and outputting a load distribution instruction for distributing the transfer load in the first data transfer unit 101 based on the determination result A monitoring unit (transfer load state monitoring unit 151), and the first buffer control unit (first buffer control unit 142) receives the load distribution instruction output from the transfer load state monitoring unit 151. Zui, the first transfer data, the first data transfer unit 101 distributes the second buffer control unit 212 outputs a data transfer control device (data transfer control device 20) is constructed.

  In this way, the data transfer control device 20 uses the first transfer data input from the first image data input unit 100 as the first transfer data based on the DMA transfer load state in the first data transfer unit 101. The data transfer unit 101 and the second data transfer unit 201 are divided into DMA transfer in parallel. As a result, in the data transfer control device 20 as well, as in the data transfer control device 10 of the first embodiment, the bus bandwidth for DMA transfer of the first transfer data output from the first image data input unit 100 is reduced. As a result, the DMA transfer is performed smoothly, and the real-time property of the DMA transfer of the first transfer data can be ensured.

  In the data transfer control device 20, as in the data transfer control device 10 of the first embodiment, a DRAM bank is used for DMA transfer of transfer data by the first data transfer unit 101 and the second data transfer unit 201. It is desirable that the first buffer control unit 142 determines the first transfer data to be distributed to the second buffer control unit 212 so that no collision occurs. Accordingly, the first transfer data output from the first buffer control unit 142 to the second buffer control unit 212 in step S220 is not limited to the next first transfer data as described above.

<Third Embodiment>
Next, still another configuration and operation of the data transfer control device 10 of the present embodiment will be described. In the following description, in order to distinguish the data transfer control device 10 of the present embodiment from the data transfer control device 10 of the first embodiment, the data transfer control device of the third embodiment is referred to as “data This is referred to as “transfer control device 30”. The data processing device including the data transfer control device 30 is referred to as “data processing device 3”. FIG. 6 is a block diagram illustrating an example of the configuration of the data processing device 3 including the data transfer control device 30 according to the third embodiment. FIG. 6 shows the first image data input unit 100 based on the remaining storage capacity of the first transfer buffer unit for storing the first transfer data to be DMA transferred (hereinafter referred to as “buffer remaining amount”). 2 shows a configuration of the data transfer control device 30 that performs control to distribute the first transfer data input from 1 to the first data transfer unit 101 and the second data transfer unit 201.

  The data processing device 3 shown in FIG. 6 has a configuration in which the data transfer control device 10 in the data processing device 1 shown in FIG. 2 replaces the data transfer control device 30, and the constituent elements of the data transfer control device 30 are the same. Shows in more detail. Note that the components in the data processing device 3 and the components in the data transfer control device 30 shown in FIG. 6 include the components in the data processing device 1 and the data transfer control device 10 shown in FIGS. Constituent elements similar to the constituent elements are included. Therefore, in the components of the data processing device 3 and the data transfer control device 30 shown in FIG. 6, the same components as those of the data processing device 1 and the data transfer control device 10 shown in FIGS. The same reference numerals are given, and detailed descriptions of the respective components are omitted.

  Similarly to the data transfer control device 10 of the first embodiment, the data transfer control device 30 transfers data transferred by the data processing device 3 to the DRAM by the first data transfer unit 101 and the second data transfer unit 201. To control. Therefore, also in the data processing device 3, similarly to the data transfer control device 10 of the first embodiment, the transfer data that each of the first data transfer unit 101 and the second data transfer unit 201 performs DMA transfer is data transfer. It is input via the control device 30. In the following description, as in the data processing apparatus 1 of the first embodiment, the first data transfer unit 101 is an initiator having a higher priority than the second data transfer unit 201. Will be described.

  The data transfer control device 30 stores the first transfer data to be DMA-transferred in the data transfer control device 30 itself based on the memory access information when the first data transfer unit 101 performs the DMA transfer. Whether the transfer data is DMA-transferred by the first data transfer unit 101 or the second data transfer unit 201 according to the monitored buffer remaining amount. To decide. Then, the data transfer control device 30 transfers to the determined data transfer unit of the first data transfer unit 101 or the second data transfer unit 201 in the same manner as the data transfer control device 10 of the first embodiment. Data is output and DMA transfer is performed. The data transfer control device 30 includes a first transfer control unit 160, a second transfer control unit 210, and a data transfer state monitoring unit 170.

  Similar to the first transfer control unit 110 of the first embodiment, the first transfer control unit 160 performs data transfer on the first transfer data to be DMA-transferred input from the first image data input unit 100. Based on the first transfer control information input from the state monitoring unit 170, the data is distributed to the first data transfer unit 101 and the second data transfer unit 201. The first transfer control unit 160 includes a first transfer buffer unit 111 and a first buffer control unit 162.

  The first transfer buffer unit 111 stores the first transfer data output from the first image data input unit 100, and stores the first transfer data in accordance with control from the first buffer control unit 162. The data is output to the first buffer control unit 162.

  The first buffer control unit 162 sets the output destination of the first transfer data to be transferred next in response to the load distribution instruction included in the first transfer control information input from the data transfer state monitoring unit 170. 1st data transfer unit 101 or the second buffer control unit 212 in the second transfer control unit 210 is determined, and the first transfer data stored in the first transfer buffer unit 111 is read. To the determined output destination. That is, the first buffer control unit 162 responds to the load distribution instruction input from the data transfer state monitoring unit 170 in the same manner as the first buffer control unit 112 of the first embodiment, The first transfer data read from the unit 111 is distributed to either the first data transfer unit 101 or the second buffer control unit 212.

  The second buffer control unit 212 receives the first transfer data input from the first buffer control unit 162 when the first transfer data is input from the first buffer control unit 162. The data is output to the second buffer control unit 212. Thereby, the first transfer data output from the first image data input unit 100 is added to the first data transfer unit 101 and the second transfer data in the same manner as the data transfer control device 10 of the first embodiment. The data transfer unit 201 also performs DMA transfer.

  Similarly to the data transfer status monitoring unit 130 of the first embodiment, the data transfer status monitoring unit 170 is a status of DMA transfer performed in each of the first data transfer unit 101 and the second data transfer unit 201. To monitor. At this time, the data transfer state monitoring unit 170 monitors the remaining buffer capacity of the first transfer buffer unit 111 based on a control signal when the first data transfer unit 101 performs DMA transfer. Then, the data transfer state monitoring unit 170 uses, as the first transfer control information, the first transfer control unit 160 in the first transfer control unit 160 as a load distribution instruction according to the monitored buffer remaining capacity of the first transfer buffer unit 111. The data is output to the buffer control unit 162.

  Note that the second transfer control information output to the second transfer control unit 210 according to the DMA transfer state of the second data transfer unit 201 monitored by the data transfer state monitoring unit 170 is the same as that of the first embodiment. This is the same as the data transfer state monitoring unit 130. Further, the first transfer control information and the second transfer control information include the same as the first transfer control information and the second transfer control information output by the data transfer state monitoring unit 130 of the first embodiment. Control for arbitrating the order of outputting the transfer data to the corresponding first data transfer unit 101 and second data transfer unit 201 and the timing of the first data transfer unit 101 and the second data transfer unit 201 Information is also included. The data transfer state monitoring unit 170 includes a transfer buffer remaining amount monitoring unit 171.

  The transfer buffer remaining amount monitoring unit 171 receives the buffer remaining amount of the first transfer buffer unit 111 based on a control signal (for example, a request signal or an acknowledge signal) when the first data transfer unit 101 performs DMA transfer. To monitor. The transfer buffer remaining amount monitoring unit 171 determines whether or not to distribute the load depending on whether or not the monitored buffer remaining amount of the first transfer buffer unit 111 is less than a predetermined storage capacity. . The transfer buffer remaining amount monitoring unit 171 then gives a load distribution instruction for distributing the load when the first data transfer unit 101 performs DMA transfer to the first buffer control unit 162 based on the determined result. Output.

  In response to this load distribution instruction, the first buffer control unit 162 determines the output destination of the first transfer data to be transferred next as the second data transfer unit 201 and reads out from the first transfer buffer unit 111. By outputting the first transfer data to the second buffer control unit 212, the first transfer data is DMA-transferred to the second data transfer unit 201. As described above, also in the data transfer control device 30, the first data transfer is performed by causing the first data transfer unit 101 and the second data transfer unit 201 to perform the DMA transfer of the first transfer data in parallel. The load when the unit 101 performs DMA transfer is distributed, and the real-time property of DMA transfer of the first transfer data is ensured.

  Even when the first buffer control unit 162 distributes the load when the first data transfer unit 101 performs the DMA transfer, it is desirable that no bank collision of the DRAM occurs. Accordingly, the first buffer control unit 162 changes the order in which the first transfer data is read from the first transfer buffer unit 111, as in the first buffer control unit 112 of the first embodiment. The first transfer data to be output to the second buffer control unit 212 may be selected.

  Also, the transfer buffer remaining amount monitoring unit 171 monitors the buffer remaining amount of the first transfer buffer unit 111 based on information other than the control signal when the first data transfer unit 101 performs DMA transfer. You can also For example, a write signal when the first image data input unit 100 stores (writes) the first transfer data in the first transfer buffer unit 111, and the first buffer control unit 162 sets the first transfer buffer unit 111. The remaining amount of the buffer in the first transfer buffer unit 111 can be monitored based on the read signal when reading the first transfer data from.

  Next, the operation of the data transfer control device 30 will be described. FIG. 7 is a flowchart illustrating a processing procedure of a data transfer operation by the data transfer control device 30 according to the third embodiment. When the first transfer data is input from the first image data input unit 100, the transfer buffer remaining amount monitoring unit 171 in the data transfer state monitoring unit 170 included in the data transfer control device 30 performs the first data transfer. The remaining buffer capacity of the first transfer buffer unit 111 is monitored based on information of a control signal when the unit 101 performs DMA transfer. More specifically, the first data transfer unit 101 stores the request signal to the interconnect bus 700 and the difference between the number of times the acknowledge signal is returned and is stored in the first transfer buffer unit 111, and the DMA. The data amount of the first transfer data that has not been transferred is calculated. It is assumed that the amount of data that the first data transfer unit 101 transfers to the DRAM by one DMA transfer is constant. Then, the remaining amount of the buffer in the first transfer buffer unit 111 is monitored by subtracting the calculated amount of the first transfer data from the storage capacity of the first transfer buffer unit 111. Note that the monitoring of the remaining buffer capacity of the first transfer buffer unit 111 is continuously performed even when the subsequent processing procedure is being executed.

  Thereafter, the transfer buffer remaining amount monitoring unit 171 determines that the buffer remaining amount of the first transfer buffer unit 111 being monitored is smaller than a predetermined storage capacity (“YES” in step S300), that is, the first When an insufficient storage capacity of the transfer buffer unit 111 is detected, it is determined that the load of the first data transfer unit 101 is to be distributed, and a load distribution instruction is output to the first buffer control unit 162.

  The transfer buffer remaining amount monitoring unit 171 determines that the buffer remaining amount of the first transfer buffer unit 111 being monitored is not less than a predetermined storage capacity (“NO” in step S300), that is, the first If the storage capacity of the transfer buffer unit 111 is sufficient, monitoring of the remaining buffer capacity of the first transfer buffer unit 111 in step S300 is continued.

  When a load distribution instruction is input from the transfer buffer remaining amount monitoring unit 171, in step S <b> 310, the first buffer control unit 162 distributes the output destination of the first transfer data, that is, the first data transfer unit 101. And the second data transfer unit 201 start parallel transfer of the first transfer data.

  Note that the parallel transfer processing procedure of the first transfer data in the first buffer control unit 162 is the same as the first transfer data parallel transfer processing procedure of the first buffer control unit 112 of the first embodiment. It is the same. More specifically, it is the same as step S120 to step S150 in the processing procedure of the data transfer operation by the data transfer control device 10 shown in FIG. Therefore, a detailed description of the processing procedure of the parallel transfer of the first transfer data in the first buffer control unit 162 is omitted.

  Thereafter, the first buffer control unit 162, when the shortage of the storage capacity of the first transfer buffer unit 111 is resolved (“YES” in step S320), that is, from the transfer buffer remaining amount monitoring unit 171 When the load distribution instruction is canceled, in step S330, one parallel transfer of the first transfer data by the first data transfer unit 101 and the second data transfer unit 201 is terminated.

  Note that the first buffer control unit 162 determines that the shortage of the storage capacity of the first transfer buffer unit 111 has not been resolved (“NO” in step S320), that is, from the transfer buffer remaining amount monitoring unit 171. When the load distribution instruction is input, the process returns to step S310, and the parallel transfer by the second data transfer unit 201 of the next first transfer data is stored in the first transfer buffer unit 111. Repeat until the capacity shortage is resolved.

  Thereafter, the data transfer control device 30 repeats the processing procedure of the flowchart of the data transfer operation shown in FIG. 7 to perform DMA transfer of all the first transfer data input from the first image data input unit 100. .

  According to the third embodiment, the data transfer state monitoring unit (data transfer state monitoring unit 170) controls the control signal (for example, a request signal) when the first data transfer unit 101 transfers the first transfer data. Based on the remaining storage capacity of the first transfer buffer unit 111, and the transfer load in the first data transfer unit 101 is determined according to the monitored remaining storage capacity. A transfer buffer remaining amount monitoring unit (transfer buffer remaining amount monitoring unit 171) that outputs a load distribution instruction for distribution, and the first buffer control unit (first buffer control unit 162) includes a transfer buffer remaining amount Data transfer control for distributing and outputting the first transfer data to the first data transfer unit 101 and the second buffer control unit 212 based on the load distribution instruction output from the monitoring unit 171 Location (the data transfer control device 30) is constructed.

  In this way, the data transfer control device 30 inputs from the first image data input unit 100 based on the remaining buffer capacity of the first transfer buffer unit 111 used when the first transfer data is DMA-transferred. The transferred first transfer data is distributed to the first data transfer unit 101 and the second data transfer unit 201, and DMA-transferred in parallel. As a result, in the data transfer control device 30 as well, as in the data transfer control device 10 of the first embodiment, the bus bandwidth for DMA transfer of the first transfer data output from the first image data input unit 100 is reduced. As a result, the DMA transfer is performed smoothly, and the real-time property of the DMA transfer of the first transfer data can be ensured.

  In the data transfer control device 30 as well, as in the data transfer control device 10 of the first embodiment, in the DMA transfer of the transfer data by the first data transfer unit 101 and the second data transfer unit 201, the DRAM bank It is desirable that the first buffer control unit 162 determines the first transfer data to be distributed to the second buffer control unit 212 so that no collision occurs. Accordingly, the first transfer data output from the first buffer control unit 162 to the second buffer control unit 212 in step S310 when the shortage of the storage capacity of the first transfer buffer unit 111 has not been resolved. As described above, is not limited to the next first transfer data.

<Fourth Embodiment>
Next, still another configuration and operation of the data transfer control device 10 of the present embodiment will be described. In the following description, in order to distinguish the data transfer control device 10 of the present embodiment from the data transfer control device 10 of the first embodiment, the data transfer control device of the fourth embodiment is referred to as “data This is referred to as “transfer control device 40”. The data processing device including the data transfer control device 40 is referred to as “data processing device 4”. FIG. 8 is a block diagram illustrating an example of the configuration of the data processing device 4 including the data transfer control device 40 according to the fourth embodiment. FIG. 8 shows the first transfer data input from the first image data input unit 100 as the first data transfer unit 101 and the second data transfer unit 201 according to the operation mode of the data processing device 4. 2 shows a configuration of a data transfer control device 40 that performs control to distribute the data.

  The operation mode of the data processing device 4 is set by a control unit (not shown) such as a CPU (Central Processing Unit) that controls the entire data processing device 4. The operation mode of the data processing device 4 includes, for example, an operation mode for capturing a still image and a moving image at the same time, an operation mode for capturing still images continuously, and an operation mode for capturing only a moving image.

  The data processing device 4 shown in FIG. 8 has a configuration in which the data transfer control device 10 in the data processing device 1 shown in FIG. 2 is replaced with the data transfer control device 40. Shows in more detail. The components in the data processing device 4 and the data transfer control device 40 shown in FIG. 8 include the components in the data processing device 1 and the data transfer control device 10 shown in FIGS. Constituent elements similar to the constituent elements are included. Therefore, in the components of the data processing device 4 and the data transfer control device 40 shown in FIG. 8, the same components as those of the data processing device 1 and the data transfer control device 10 shown in FIGS. The same reference numerals are given, and detailed descriptions of the respective components are omitted.

  Similar to the data transfer control device 10 of the first embodiment, the data transfer control device 40 is transfer data that the data processing device 4 performs DMA transfer to the DRAM by the first data transfer unit 101 and the second data transfer unit 201. To control. Therefore, also in the data processing device 4, similarly to the data transfer control device 10 of the first embodiment, the transfer data that each of the first data transfer unit 101 and the second data transfer unit 201 performs DMA transfer is the data transfer. It is input via the control device 40. In the following description, as in the data processing apparatus 1 of the first embodiment, the first data transfer unit 101 is an initiator having a higher priority than the second data transfer unit 201. Will be described.

  The data transfer control device 40 determines which one of the first data transfer unit 101 and the second data transfer unit 201 performs DMA transfer of the transfer data according to the set operation mode. Then, the data transfer control device 40 transfers to the determined data transfer unit of the first data transfer unit 101 or the second data transfer unit 201 in the same manner as the data transfer control device 10 of the first embodiment. Data is output and DMA transfer is performed. The data transfer control device 40 includes a first transfer control unit 180, a second transfer control unit 210, and a data transfer state monitoring unit 190.

  Similar to the first transfer control unit 110 of the first embodiment, the first transfer control unit 180 transfers the first transfer data input from the first image data input unit 100 for DMA transfer to the data transfer unit. Based on the first transfer control information input from the state monitoring unit 190, the data is distributed to the first data transfer unit 101 and the second data transfer unit 201. The first transfer control unit 180 includes a first transfer buffer unit 111 and a first buffer control unit 182.

  The first transfer buffer unit 111 stores the first transfer data output from the first image data input unit 100, and stores the first transfer stored in accordance with the control from the first buffer control unit 182. The data is output to the first buffer control unit 182.

  The first buffer control unit 182 determines the output destination of the first transfer data to be transferred in accordance with the path selection instruction included in the first transfer control information input from the data transfer state monitoring unit 190. Decide on either the data transfer unit 101 or the second buffer control unit 212 in the second transfer control unit 210, read the first transfer data stored in the first transfer buffer unit 111, Output to the determined output destination. That is, the first buffer control unit 182 responds to the path selection instruction input from the data transfer state monitoring unit 190 in the same manner as the first buffer control unit 112 of the first embodiment, The first transfer data read from the unit 111 is distributed to either the first data transfer unit 101 or the second buffer control unit 212.

  Then, when the first transfer data is input from the first buffer control unit 182, the second buffer control unit 212 receives the first transfer data input from the first buffer control unit 182, The data is output to the second buffer control unit 212. Thereby, the first transfer data output from the first image data input unit 100 is added to the first data transfer unit 101 and the second transfer data in the same manner as the data transfer control device 10 of the first embodiment. The data transfer unit 201 also performs DMA transfer.

  The data transfer status monitoring unit 190 is the status of DMA transfer performed in each of the first data transfer unit 101 and the second data transfer unit 201 as in the data transfer status monitoring unit 130 of the first embodiment. To monitor. Further, the data transfer state monitoring unit 190 uses the path selection instruction for instructing the path for transferring the first transfer data to the DRAM as the first transfer control information according to the set operation mode. The data is output to the first buffer control unit 182 in the unit 180.

  Note that the second transfer control information output to the second transfer control unit 210 according to the DMA transfer state of the second data transfer unit 201 monitored by the data transfer state monitoring unit 190 is the same as that of the first embodiment. This is the same as the data transfer state monitoring unit 130. Further, the first transfer control information and the second transfer control information include the same as the first transfer control information and the second transfer control information output by the data transfer state monitoring unit 130 of the first embodiment. Control for arbitrating the order of outputting the transfer data to the corresponding first data transfer unit 101 and second data transfer unit 201 and the timing of the first data transfer unit 101 and the second data transfer unit 201 Information is also included. The data transfer state monitoring unit 190 includes a mode setting unit 191.

  The mode setting unit 191 determines the path of the first transfer data when the first transfer data is DMA-transferred to the DRAM, for example, according to an operation mode set by a CPU (not shown). Then, the mode setting unit 191 outputs a route selection instruction representing a route for DMA transfer of the first transfer data to the first buffer control unit 182 based on the determined result. For example, when the operation mode for continuously capturing still images is set, the first data transfer unit 101 DMA-transfers the first transfer data of the odd-numbered still image, and the even-numbered still image is transferred. A parallel transfer path selection instruction that instructs the second data transfer unit 201 to perform DMA transfer of the first transfer data of the image is output to the first buffer control unit 182. For example, when two DRAMs for DMA transfer of the first transfer data are provided, the first data transfer unit 101 DMA-transfers the first transfer data of the odd-numbered row of the still image to one DRAM. Then, a parallel transfer path selection instruction for instructing the second data transfer unit 201 to perform DMA transfer of the first transfer data in the even-numbered row of the still image to the other DRAM is output to the first buffer control unit 182. To do.

  In response to the parallel transfer path selection instruction, the first buffer control unit 182 sets the output destination of the first transfer data to the first data transfer unit 101 or the second data for each first transfer data to be transferred. The first transfer data is determined as one of the data transfer units 201, and the first transfer data read from the first transfer buffer unit 111 is output to the determined output destination. 101 and the second data transfer unit 201 perform DMA transfer in parallel. As described above, also in the data transfer control device 40, the first data transfer is performed by causing the first data transfer unit 101 and the second data transfer unit 201 to perform the DMA transfer of the first transfer data in parallel. The load when the unit 101 performs DMA transfer is distributed, and the real-time property of DMA transfer of the first transfer data is ensured.

  Even when the first buffer control unit 182 distributes the load when the first data transfer unit 101 performs DMA transfer, it is desirable that no bank collision of DRAM occurs. Accordingly, the first buffer control unit 182 changes the order in which the first transfer data is read from the first transfer buffer unit 111 in the same manner as the first buffer control unit 112 of the first embodiment. The first transfer data to be output to the second buffer control unit 212 may be selected.

  Next, the operation of the data transfer control device 40 will be described. FIG. 9 is a flowchart illustrating a processing procedure of a data transfer operation performed by the data transfer control device 40 according to the fourth embodiment. When the operation mode is set in the mode setting unit 191, in step S400, the mode setting unit 191 determines whether or not the set operation mode is an operation mode in which the first transfer data is transferred in parallel. . The determination of the operation mode in the mode setting unit 191 is always performed continuously even when the subsequent processing procedure is executed.

  In the determination in step S400, when the set operation mode is not an operation mode in which the first transfer data is transferred in parallel (“NO” in step S400), the mode setting unit 191 converts the first transfer data into the normal transfer data. A route, that is, a route selection instruction for DMA transfer of the first transfer data by only the first data transfer unit 101 is output to the first buffer control unit 182, and the process is terminated. After that, when the first transfer data is input from the first image data input unit 100, the first buffer control unit 182 reads the first transfer data from the first transfer buffer unit 111, and reads the read first transfer data. 1 transfer data is DMA-transferred by the first data transfer unit 101.

  On the other hand, in the determination in step S400, when the set operation mode is an operation mode in which the first transfer data is transferred in parallel (“YES” in step S400), the mode setting unit 191 sets the first transfer data. Is transmitted to the first buffer control unit 182 by the first data transfer unit 101 and the second data transfer unit 201 for DMA transfer.

  When the parallel transfer path selection instruction is input from the mode setting unit 191 and the first transfer data is input from the first image data input unit 100, in step S410, the first buffer control unit 182 Distribution of the output destination of the transfer data, that is, parallel transfer of the first transfer data by the first data transfer unit 101 and the second data transfer unit 201 is started.

  The processing procedure of the parallel transfer of the first transfer data in the first buffer control unit 182 is the data transfer by the first buffer control unit 112 in the data transfer control device 10 of the first embodiment shown in FIG. This is the same as step S120 to step S150 in the operation procedure. Therefore, a detailed description of the processing procedure of the parallel transfer of the first transfer data in the first buffer control unit 182 is omitted.

  Thereafter, the first buffer control unit 182 selects the parallel transfer path from the mode setting unit 191 when the operation mode for performing the parallel transfer of the first transfer data is canceled (“YES” in step S420). When the instruction is canceled, in step S430, the parallel transfer of the first transfer data by the first data transfer unit 101 and the second data transfer unit 201 is terminated.

  Note that the first buffer control unit 182 determines the parallel transfer path from the mode setting unit 191 when the operation mode for performing the parallel transfer of the first transfer data has not been released (“NO” in step S420). When the selection instruction is input, the process returns to step S410, and the operation mode for performing the parallel transfer of the first transfer data by the second data transfer unit 201 and the parallel transfer of the first transfer data is set. Repeat until released.

  Thereafter, the data transfer control device 40 repeats the processing procedure of the flowchart of the data transfer operation shown in FIG. 9 to perform DMA transfer of all the first transfer data input from the first image data input unit 100. .

  According to the fourth embodiment, the data transfer state monitoring unit (data transfer state monitoring unit 190) determines the first transfer data when transferring the first transfer data according to the set operation mode. A mode setting unit (mode setting unit 191) for determining a route and outputting a route selection instruction representing a route for transferring the first transfer data based on the result determined here, and the first buffer control unit ( The first buffer control unit 182) distributes the first transfer data to the first data transfer unit 101 and the second buffer control unit 212 based on the path selection instruction output from the mode setting unit 191. The data transfer control device (data transfer control device 40) is configured to output.

  In this way, in the data transfer control device 40, the first transfer data input from the first image data input unit 100 is transferred to the first data transfer according to the operation mode set in the mode setting unit 191. It distributes to the unit 101 and the second data transfer unit 201, and performs DMA transfer in parallel. As a result, in the data transfer control device 40 as well, as with the data transfer control device 10 of the first embodiment, the bus bandwidth for DMA transfer of the first transfer data output from the first image data input unit 100 is reduced. As a result, the DMA transfer is performed smoothly, and the real-time property of the DMA transfer of the first transfer data can be ensured.

  In the data transfer control device 40 as well, as in the data transfer control device 10 of the first embodiment, in the DMA transfer of the transfer data by the first data transfer unit 101 and the second data transfer unit 201, the DRAM bank It is desirable that the first buffer control unit 182 determines the first transfer data to be distributed to the second buffer control unit 212 so that no collision occurs.

  As described above, in the data transfer control device of the present invention, various conditions (more specifically, DMA transfer waiting time, DRAM access history, DMA transfer load status) when transfer data is DMA transferred. DMA transfer of the first transfer data in accordance with the remaining buffer capacity of the first transfer buffer unit 111, the operation mode of the data processing device, etc.), the first data transfer unit 101 and the second data transfer unit 201 Can be performed in parallel. As a result, it is possible to secure a bus bandwidth for DMA transfer of the first transfer data output from the first image data input unit 100, and to secure the real-time property of the DMA transfer of the first transfer data.

  In the present embodiment, the configurations and operations corresponding to the different conditions when the transfer data is DMA-transferred in the first to fourth embodiments have been described. However, it is also possible to adopt a configuration and operation corresponding to a combination of a plurality of conditions when transferring transfer data by DMA. This can be realized by configuring the data transfer control device to have the configurations, operations, or functions shown in the first to fourth embodiments corresponding to a combination of a plurality of conditions at the same time. . For example, by configuring the data transfer control device having all the configurations shown in the first to fourth embodiments, the DMA transfer waiting time, access history to the DRAM, DMA transfer load state, It is possible to realize a data transfer control device that performs an operation according to all conditions such as the remaining buffer capacity of one transfer buffer unit 111 and the operation mode of the data processing device.

  In the first to fourth embodiments, after the transfer data input from the image data input unit is temporarily stored in the transfer buffer unit, the buffer control unit reads it and outputs it to each data transfer unit. The configuration, that is, the transfer control unit in which the transfer data transferred to the DRAM is transferred in the order of the transfer buffer unit and the buffer control unit has been described. For example, in the first transfer control unit 110 according to the first embodiment, the arrangement in which the first transfer data is transferred in the order of the first transfer buffer unit 111 and the first buffer control unit 112 has been described. However, the arrangement of the transfer buffer unit and the buffer control unit in the transfer control unit is not limited to the arrangement order shown in the first to fourth embodiments.

<Modification of Third Embodiment>
Here, as an example of the case where the arrangement of the transfer buffer unit and the buffer control unit in the transfer control unit is different, the first buffer based on the remaining buffer capacity of the first transfer buffer unit 111 shown in the third embodiment is used. The configuration and operation of a modification of the data transfer control device 30 that transfers transfer data in parallel will be described. In the following description, in order to distinguish the data transfer control device of the present modification from the data transfer control device 30 of the third embodiment, the data transfer control device of the present modification is referred to as “data transfer control device 50. " The data processing device provided with the data transfer control device 50 is referred to as “data processing device 5”. FIG. 10 is a block diagram illustrating an example of the configuration of the data processing device 5 including the data transfer control device 50 according to a modification of the third embodiment. Similarly to the data transfer control device 30 of the third embodiment, the data transfer control device 50 shown in FIG. 10 also has the remaining buffer capacity of the first transfer buffer unit 111 that stores the first transfer data to be DMA transferred. Based on this, control is performed to distribute the first transfer data input from the first image data input unit 100 to the first data transfer unit 101 and the second data transfer unit 201.

  The data processing device 5 shown in FIG. 10 has a configuration in which the data transfer control device 30 in the data processing device 3 shown in FIG. 6 is replaced with the data transfer control device 50. Shows in more detail. Note that the components in the data processing device 5 and the components in the data transfer control device 50 shown in FIG. 10 are the same as the components in the data processing device 3 and the configuration in the data transfer control device 30 shown in FIG. Constituent elements similar to the elements are also included. Therefore, in the components of the data processing device 5 and the data transfer control device 50 shown in FIG. 10, the same components as those of the data processing device 3 and the data transfer control device 30 shown in FIG. Reference numerals are given, and detailed description of each component is omitted.

  Similarly to the data transfer control device 30 of the third embodiment, the data transfer control device 50 also transfers data transferred by the data processing device 5 to the DRAM by the first data transfer unit 101 and the second data transfer unit 201. To control. Therefore, also in the data processing device 5, similarly to the data transfer control device 30 of the third embodiment, the transfer data that each of the first data transfer unit 101 and the second data transfer unit 201 performs DMA transfer is the data transfer. It is input via the control device 50. In the following description, as in the data processing device 3 of the third embodiment, the first data transfer unit 101 is an initiator having a higher priority than the second data transfer unit 201. Will be described.

  Similar to the data transfer control device 30 of the third embodiment, the data transfer control device 50 is provided in the data transfer control device 50 itself based on the memory access information when the first data transfer unit 101 performs DMA transfer. Further, the remaining capacity of the first transfer buffer section for storing the first transfer data to be DMA transferred is monitored, and the first data transfer section 101 or the second data transfer section is selected according to the monitored buffer remaining capacity. The data transfer unit 201 determines whether the transfer data is DMA-transferred. Then, the data transfer control device 50 transfers to the determined data transfer unit of the first data transfer unit 101 or the second data transfer unit 201 in the same manner as the data transfer control device 30 of the third embodiment. Data is output and DMA transfer is performed. The data transfer control device 50 includes a first transfer control unit 260, a second transfer control unit 220, and a data transfer state monitoring unit 170.

  Similar to the first transfer control unit 160 in the third embodiment, the first transfer control unit 260 performs data transfer on the first transfer data input from the first image data input unit 100 for DMA transfer. Based on the first transfer control information input from the state monitoring unit 170, the data is distributed to the first data transfer unit 101 and the second data transfer unit 201. The first transfer control unit 260 includes a first transfer buffer unit 261 and a first buffer control unit 262.

  Similarly to the second transfer control unit 210 of the third embodiment, the second transfer control unit 220 performs the second transfer data to be DMA-transferred input from the second image data input unit 200 or the first transfer data. The second transfer control input from the data transfer state monitoring unit 170 to any one of the first transfer data distributed by the transfer control unit 260 and transferred by the first image data input unit 100 by DMA. Based on the information, the data is output to the second data transfer unit 201. The second transfer control unit 220 includes a second transfer buffer unit 221 and a second buffer control unit 222.

  Note that each of the first transfer buffer unit 261 and the first buffer control unit 262 included in the first transfer control unit 260 is the first transfer control unit 160 included in the first embodiment. The transfer buffer unit 111 and the first buffer control unit 162 have the same functions. In addition, each of the second transfer buffer unit 221 and the second buffer control unit 222 included in the second transfer control unit 220 is a second included in the second transfer control unit 210 of the third embodiment. The transfer buffer unit 211 and the second buffer control unit 212 have the same functions.

  However, as can be seen by comparing the first transfer control unit 160 shown in FIG. 6 with the first transfer control unit 260 shown in FIG. 10, the first transfer buffer unit in the first transfer control unit 260. The arrangement of the H.261 and the first buffer control unit 262 is opposite to that of the first transfer control unit 160. Further, as can be seen by comparing the second transfer control unit 210 shown in FIG. 6 with the second transfer control unit 220 shown in FIG. 10, the second transfer buffer unit in the second transfer control unit 220. The arrangement of 221 and the second buffer control unit 222 is also opposite to that of the second transfer control unit 210.

  In response to the load distribution instruction included in the first transfer control information input from the data transfer state monitoring unit 170, the first buffer control unit 262 determines the output destination of the first transfer data as the first transfer buffer. The first transfer data input from the first image data input unit 100 is determined as one of the second buffer control unit 212 in the unit 261 or the second transfer control unit 220, and the determined output destination Output to. That is, the first buffer control unit 262 receives the first transfer data output from the first image data input unit 100 in response to the load distribution instruction input from the data transfer state monitoring unit 170. A branch is made when it is input to the control unit 262 itself, and it is distributed to either the first data transfer unit 101 or the second buffer control unit 212.

  The first transfer buffer unit 261 temporarily stores the first transfer data input from the first buffer control unit 262, and then outputs the stored first transfer data to the first data transfer unit 101. . As a result, the first transfer data distributed to the first transfer buffer unit 261 by the first buffer control unit 262 is DMA-transferred by the first data transfer unit 101.

  The second buffer control unit 222 converts the second transfer data input from the second image data input unit 200 into the second transfer data based on the second transfer control information input from the data transfer state monitoring unit 170. Output to the transfer buffer unit 221. The second buffer controller 222 receives the first transfer data input from the first buffer controller 262 when the first transfer data is input from the first buffer controller 262. The data is output to the second transfer buffer unit 221.

  The second transfer buffer unit 221 temporarily stores the transfer data input from the second buffer control unit 222, and then outputs the stored transfer data to the second data transfer unit 201. Accordingly, the second transfer data output from the second image data input unit 200 or the first transfer data distributed to the second buffer control unit 222 by the first buffer control unit 262 is the second transfer data. The data transfer unit 201 performs DMA transfer.

  With this configuration, the data transfer control device 50 performs the DMA transfer of the first transfer data output from the first image data input unit 100 with the first data transfer unit 101, the second data transfer unit 201, and the like. In parallel. As a result, in the data transfer control device 50 as well as the data transfer control device 30 of the third embodiment, the load when the first data transfer unit 101 performs DMA transfer is distributed, and the DMA of the first transfer data is reduced. Ensure real-time transfer.

  Even when the first buffer control unit 262 distributes the load when the first data transfer unit 101 performs DMA transfer, it is desirable that no bank collision of DRAM occurs. Accordingly, the first buffer control unit 262 may change the output destination of the first transfer data input from the first image data input unit 100.

  Next, the operation of the data transfer control device 50 will be described. FIG. 11 is a flowchart illustrating a processing procedure of a data transfer operation performed by the data transfer control device 50 according to the modification of the third embodiment. When the data transfer control device 50 starts operation, the transfer buffer remaining amount monitoring unit 171 in the data transfer state monitoring unit 170 provided in the data transfer control device 50 is used when the first data transfer unit 101 performs DMA transfer. Based on the information of the control signal, the remaining buffer capacity of the first transfer buffer unit 261 is monitored. Note that the monitoring of the remaining buffer capacity of the first transfer buffer unit 261 is always performed continuously even when the subsequent processing procedure is executed.

  Thereafter, the transfer buffer remaining amount monitoring unit 171 determines that the first transfer buffer unit 261 being monitored has a remaining buffer amount smaller than a predetermined storage capacity (“YES” in step S500), that is, the first When it is detected that the storage capacity of the transfer buffer unit 261 is insufficient, the load of the first data transfer unit 101 is determined to be distributed, and a load distribution instruction is output to the first buffer control unit 262.

  The transfer buffer remaining amount monitoring unit 171 determines that the buffer remaining amount of the first transfer buffer unit 261 being monitored is not less than a predetermined storage capacity (“NO” in step S500), that is, the first When the storage capacity of the transfer buffer unit 261 is sufficient, the monitoring of the remaining buffer capacity of the first transfer buffer unit 261 in step S500 is continued.

  When a load distribution instruction is input from the transfer buffer remaining amount monitoring unit 171, the first buffer control unit 262 receives the first transfer data from the first image data input unit 100 in step S <b> 510. The data is branched and output to either the first data transfer unit 101 or the second buffer control unit 212. That is, the first data transfer unit 101 and the second data transfer unit 201 start parallel transfer of the first transfer data. As a result, the first transfer data input from the first image data input unit 100 is temporarily stored in either the first transfer buffer unit 261 or the second transfer buffer unit 221, and then the first transfer data is stored. The data transfer unit 101 or the second data transfer unit 201 performs DMA transfer.

  Thereafter, the first buffer control unit 262 determines that when the shortage of the storage capacity of the first transfer buffer unit 261 is resolved (“YES” in step S520), that is, from the transfer buffer remaining amount monitoring unit 171. When the load distribution instruction is canceled, one parallel transfer of the first transfer data by the first data transfer unit 101 and the second data transfer unit 201 is terminated in step S530.

  Note that the first buffer control unit 262 determines that the shortage of the storage capacity of the first transfer buffer unit 261 has not been resolved (“NO” in step S520), that is, from the transfer buffer remaining amount monitoring unit 171. When the load distribution instruction is input, the process returns to step S510 to perform parallel transfer of the first transfer data input from the first image data input unit 100 by the second data transfer unit 201. The process is repeated until the shortage of the storage capacity of the first transfer buffer unit 261 is resolved.

  Thereafter, the data transfer control device 50 repeats the processing procedure of the flowchart of the data transfer operation shown in FIG. 11 until the first transfer data input from the first image data input unit 100 is completed. DMA transfer of the transferred data is performed.

  In the data transfer control device 50 as well, it is desirable to perform DMA transfer so that DRAM bank collision does not occur in DMA transfer of transfer data by the first data transfer unit 101 and the second data transfer unit 201. In this case, when each of the first transfer buffer unit 261 and the second transfer buffer unit 221 outputs the transfer data to the corresponding data transfer unit, each data transfer unit transfers the DMA to a different memory bank of the DRAM. It is conceivable that the output order of the transfer data is rearranged so as to transfer. For this reason, when the first buffer control unit 262 branches the input first transfer data to the second buffer control unit 222 in step S510, the first buffer control unit 262 prevents the DRAM bank collision from occurring. The timing for branching the transfer data to the second buffer control unit 222 may be changed.

  As described above, the data transfer control device 50 also receives an input from the first image data input unit 100 based on the remaining buffer capacity of the first transfer buffer unit 261 used when the first transfer data is DMA-transferred. The first transfer data can be distributed to the first data transfer unit 101 and the second data transfer unit 201 and can be DMA-transferred in parallel. As a result, in the data transfer control device 50 as well, as with the data transfer control device 30 of the third embodiment, the bus bandwidth for DMA transfer of the first transfer data output from the first image data input unit 100 is reduced. As a result, the DMA transfer is performed smoothly, and the real-time property of the DMA transfer of the first transfer data can be ensured.

  In the present embodiment, two image data input units (first image data input unit 100 and second image data input) are used in the data processing apparatuses of the first to fourth embodiments and the modified example. Unit 200), and two data transfer units (first data transfer unit 101 and second data transfer unit 201) corresponding to the respective image data input units respectively output the transfer data to the interconnect bus 700. The configuration for DMA transfer is described above. However, the number of image data input units and data transfer units provided in the data processing apparatus is not limited to the numbers shown in the first to fourth embodiments and the modifications, and more image data. A configuration including an input unit and a data transfer unit is also conceivable.

  Here, an example of a configuration in which the data processing apparatus includes more image data input units and data transfer units will be described. FIG. 12 is a block diagram illustrating an example of a schematic configuration of a data processing device including the data transfer control device according to the present embodiment. The data processing device 6 shown in FIG. 12 includes a first image data input unit 100, a first data transfer unit 101, a second image data input unit 200, a second data transfer unit 201, and a data Transfer control device 10, third image data input unit 300, third data transfer unit 301, data transfer control device 11, fourth image data input unit 400, and fourth data transfer unit 401 The data transfer control device 12 is provided. Each of the data transfer control devices 10 to 12 includes two transfer control units and one data transfer state monitoring unit. However, as can be seen from FIG. 12, the data transfer control device 10 includes a first transfer control unit 110, a second transfer control unit 210, and a data transfer state monitoring unit 130. The data transfer control device 11 includes a second transfer control unit 210, a third transfer control unit 310, and a data transfer state monitoring unit 230. The data transfer control device 12 includes a third transfer control unit 310, a fourth transfer control unit 410, and a data transfer state monitoring unit 330.

  The data processing device 6 shown in FIG. 12 has a configuration in which there are four image data input units and four data transfer units provided in the data processing device 1 shown in FIG. In addition, the number of image data input units and the number of data transfer units is four, so that the number of data transfer control devices is three. Note that the components in the data processing device 6 and the components in the data transfer control device are the same as the components in the data processing device 1 and the data transfer control device 10 shown in FIG. is there. More specifically, each of the first image data input unit 100 to the fourth image data input unit 400 includes the first image data input unit 100 and the second image data input unit 200 shown in FIG. Similarly, it is a supply source of image data to be transferred to the DRAM via the interconnect bus 700. Further, each of the first data transfer unit 101 to the fourth data transfer unit 401 corresponds to the corresponding image data input similar to the first data transfer unit 101 and the second data transfer unit 201 shown in FIG. This is an initiator for transferring each piece of transfer data by DMA by outputting the transfer data input from the communication unit to the interconnect bus 700.

  In the data processing device 6, each of the data transfer control device 10 to the data transfer control device 12 distributes transfer data to be DMA-transferred by each data transfer unit, similarly to the data transfer control device 10 shown in FIG. 1. . At this time, each of the data transfer state monitoring unit 130 to the data transfer state monitoring unit 330 included in each of the data transfer control device 10 to the data transfer control device 12 is similar to the data transfer state monitoring unit 130 illustrated in FIG. The status of the DMA transfer being performed in each of the two corresponding data transfer units is monitored. As can be seen from FIG. 12, in the data processing device 6, in the data transfer control device 10 to the data transfer control device 12, one transfer control unit is redundantly included in the two data transfer control devices. Yes. For this reason, one transfer control unit included redundantly in the two data transfer control devices distributes the transfer data input from the corresponding image data input unit and DMA transfers the distributed transfer data Both functions will be provided.

  More specifically, the second transfer control unit 210 is redundantly included in the data transfer control device 10 and the data transfer control device 11. Therefore, the second transfer control unit 210 performs the first transfer distributed by the first transfer control unit 110 in the same manner as the second transfer control unit 210 provided in the data processing apparatus 1 illustrated in FIG. In addition to the function of transferring data by DMA, the second transfer data input from the second image data input unit 200 is the same as the first transfer control unit 110 provided in the data processing apparatus 1 shown in FIG. Is distributed to the second data transfer unit 201 and the third data transfer unit 301 (third transfer control unit 310). The third transfer control unit 310 is redundantly included in the data transfer control device 11 and the data transfer control device 12. For this reason, the third transfer control unit 310 performs the second transfer distributed by the second transfer control unit 210 in the same manner as the second transfer control unit 210 provided in the data processing apparatus 1 illustrated in FIG. In addition to the function of DMA transfer of data, the third transfer data input from the third image data input unit 300 is the same as the first transfer control unit 110 provided in the data processing apparatus 1 shown in FIG. Is distributed to the third data transfer unit 301 and the fourth data transfer unit 401 (fourth transfer control unit 410).

  According to the present embodiment, the data transfer control device (data transfer control devices 10 to 12) is changed to a data transfer unit (first data transfer unit 101, second data transfer unit 201, third data transfer unit 301, And a fourth data transfer unit 401), a data input unit (first image data input unit 100, second image data input unit 200, third image data input unit 300, and fourth image data input unit) 400), the data transfer state monitoring units (data transfer state monitoring unit 130, data transfer state monitoring unit 230, and the like included in each of the data transfer control devices 10-12, And the data transfer state monitoring unit 330) correspond to the corresponding first data transfer unit 101, second data transfer unit 201, third data transfer unit 301, and fourth data transfer unit 401. The transfer state of each transfer data is monitored, and each transfer control unit (first transfer control unit 110, second transfer control unit 210, third transfer control) provided in the data transfer control devices 10-12 is provided. Unit 310 or the fourth transfer control unit 410), transfer control information is output, and at least one transfer control unit (the first transfer control unit 110, the second transfer control unit 10) included in each of the data transfer control devices 10 to 12 is provided. Based on the transfer control information, the transfer control unit 210 and the third transfer control unit 310) correspond to the corresponding data input unit (the first image data input unit 100, the second image data input unit 200, or the third Transfer data input from the image data input unit 300) is transferred to at least one data transfer unit (second data transfer unit 201, third data transfer) corresponding to the data transfer control devices 10-12. Transfer section 301, and distributes the four data transfer unit 401 of) the data processing apparatus (data processing apparatus 6) is constructed.

  As described above, by providing the data transfer control devices corresponding to the number of image data input units and data transfer units provided in the data processing device in the form of a daisy chain, each input from one image data input unit. The DMA transfer of the transfer data can be performed in parallel by the two data transfer units. As a result, in each data transfer control device, a bus band for DMA transfer of the transfer data output from the corresponding image data input unit is secured, DMA transfer is performed smoothly, and DMA transfer of each transfer data is performed. Real-time performance can be ensured.

  As described above, according to the embodiment for carrying out the present invention, the DMA transfer of the transfer data is smoothly performed by monitoring the state of the DMA transfer by the data transfer unit corresponding to the image data input unit. It is determined whether or not. If the DMA transfer of the transfer data by the data transfer unit is not performed smoothly, the transfer of the transfer data is also performed by a data transfer unit different from the data transfer unit currently transferring the transfer data. The transfer data is distributed to each data transfer unit. Thereby, in the embodiment for carrying out the present invention, the transfer data can be DMA-transferred in parallel in each data transfer unit, and the transfer data input from the image data input unit can be DMA-transferred. Bus bandwidth can be secured. As a result, in the embodiment for carrying out the present invention, it is possible to suppress a decrease in throughput when the transfer data output from the image data input unit is DMA-transferred, and it is possible to ensure the real-time property of the transfer data.

  According to the embodiment for carrying out the present invention, when each transfer control unit in the data transfer control device outputs the transfer data to the corresponding data transfer unit, the transfer data output order is rearranged. be able to. As a result, in the embodiment for carrying out the present invention, it is possible to reduce the probability of occurrence of DRAM bank collision when DMA transfer of transfer data, and to reduce waiting time due to DRAM bank collision. At this time, in the mode for carrying out the present invention, the order of output of the transfer data can be rearranged using the respective transfer buffer units used in the normal DMA transfer. Bank conflicts can be avoided.

  As a result, in the mode for carrying out the present invention, the performance of the system including the data processing device can be improved.

  In the present embodiment, the transfer data output from each image data input unit is transferred to the DRAM, that is, the write transfer in which the data processing apparatus outputs the transfer data to the DRAM has been described. However, the transfer direction of the transfer data is not limited to the direction from the data processing apparatus shown in the embodiment for carrying out the present invention to the DRAM. For example, in the read transfer in which the data processing device reads the transfer data stored in the DRAM, the concept of the present invention is similarly applied by reversing the flow of the transfer data described in this embodiment. Can do. Further, for example, the concept of the present invention can be similarly applied to a configuration in which write transfer and read transfer are combined.

  Further, in the present embodiment, in the data processing apparatus having a configuration including many image data input units and transfer units shown in FIG. 12, each data transfer control device includes two transfer control units and one data. The case where the transfer state monitoring unit is configured has been described. However, the number of transfer control units included in one data transfer control device is not limited to the number shown in the embodiment for carrying out the present invention. For example, one data transfer control device includes three transfer control units. It may be configured by a control unit and one data transfer state monitoring unit. More specifically, referring to the example shown in FIG. 12, the data transfer control device 10 includes a first transfer control unit 110, a second transfer control unit 210, a third transfer control unit 310, And a data transfer state monitoring unit 130. In the case of this configuration, the data transfer status monitoring unit 130 monitors the status of the DMA transfer performed in each of the first transfer control unit 110, the second transfer control unit 210, and the third transfer control unit 310. To do. Then, the first transfer control unit 110 adds the first transfer data input from the first image data input unit 100 to the third transfer control unit 310 in addition to the second transfer control unit 210. Distribute. Accordingly, the first transfer data can be DMA-transferred in parallel by the third data transfer unit 301 in addition to the first data transfer unit 101 and the second data transfer unit 201.

  In this embodiment, a system LSI mounted on an imaging apparatus such as a digital camera and performing image processing is used as the data processing apparatus of the present invention, and the data transfer control apparatus of the present invention is applied to this system LSI. did. The case where the transfer data transferred by the data transfer control device is image data has been described. However, the system of the data processing apparatus to which the data transfer control apparatus of the present embodiment can be applied is not limited to the data processing apparatus system shown in the embodiment for carrying out the present invention. The system of the data transfer control device of the present invention can be similarly applied to any system as long as it is a data processing device system that transfers transfer data by DMA. Therefore, transfer data transferred by the data transfer control device is not necessarily limited to image data.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

1, 2, 3, 4, 5, 6... Data processing device 100... First image data input unit (data input unit)
101... First data transfer unit (data transfer unit, first data transfer unit)
200: Second image data input unit (data input unit)
201: second data transfer unit (data transfer unit, second data transfer unit)
10, 20, 30, 40, 50, 11, 12... Data transfer control device 110, 140, 160, 180, 260... First transfer control unit (transfer control unit, first transfer control unit)
111, 261 ... first transfer buffer unit (transfer control unit, transfer buffer unit, first transfer buffer unit)
112, 142, 162, 182, 262... First buffer control unit (transfer control unit, buffer control unit, first buffer control unit)
210, 220 ... second transfer control unit (transfer control unit, second transfer control unit)
211, 221 ... second transfer buffer unit (transfer control unit, transfer buffer unit, second transfer buffer unit)
212, 222 ... second buffer control unit (transfer control unit, buffer control unit, second buffer control unit)
130, 150, 170, 190, 230, 330... Data transfer state monitoring unit 131... Data transfer waiting time monitoring unit (data transfer state monitoring unit, data transfer waiting time monitoring unit)
132: Memory access history collection unit (data transfer status monitoring unit, access history collection unit)
151: Transfer load status monitoring unit (data transfer status monitoring unit, transfer load status monitoring unit)
171... Transfer buffer remaining amount monitoring unit (data transfer state monitoring unit, transfer buffer remaining amount monitoring unit)
191: Mode setting unit (data transfer state monitoring unit, mode setting unit)
300: Third image data input unit (data input unit)
301: Third data transfer unit (data transfer unit)
400: Fourth image data input unit (data input unit)
401: Fourth data transfer unit (data transfer unit)
310: Third transfer control unit (transfer control unit)
410: Fourth transfer control unit (transfer control unit)

Claims (7)

A data transfer control device that outputs transfer data to be transferred via the common bus to each of a plurality of data transfer units that transfer data via a common bus,
A plurality of transfer control units that correspond to the respective data transfer units and that output the transfer data input from the data input units corresponding to the respective data transfer units to the corresponding data transfer units;
Each of the data transfer units monitors a state of transferring the transfer data, and the transfer data in each of the transfer control units is based on the transfer state of each of the transfer data of the monitored data transfer unit A data transfer state monitoring unit that outputs transfer control information for controlling output to the corresponding data transfer unit;
With
Among the plurality of transfer control units, at least one transfer control unit includes:
Based on the transfer control information of the corresponding data transfer unit, the transfer data transferred by the data transfer unit is transferred to the other transfer control unit corresponding to the transfer data transferred by the data transfer unit. Output by sorting to the transfer data transferred by the data transfer unit,
At least one other transfer control unit to which the transfer data is distributed,
The sorted transfer data is output to the corresponding data transfer unit based on the transfer control information of the corresponding data transfer unit,
Each of the plurality of transfer control units includes:
A transfer buffer unit for temporarily storing the transfer data input from the data input unit corresponding to the corresponding data transfer unit;
A buffer control unit that reads out and outputs the transfer data stored in the transfer buffer unit based on the transfer control information;
With
The first transfer buffer unit that is the transfer buffer unit provided in the first transfer control unit that is the transfer control unit that distributes the transfer data,
Temporarily storing the first transfer data that is the transfer data transferred by the first data transfer unit that is the data transfer unit to which the first transfer control unit corresponds;
The first buffer control unit, which is a buffer control unit provided in the first transfer control unit,
Based on the first transfer control information that is the transfer control information of the first data transfer unit, the first transfer data read from the first transfer buffer unit is transferred by the first data transfer unit. The first transfer data to be transferred and the first transfer data to be transferred by the other data transfer unit corresponding to the other transfer control unit are distributed and output,
The second transfer buffer unit which is the transfer buffer unit provided in the second transfer control unit which is the other transfer control unit to which the first transfer data is distributed,
Temporarily storing the second transfer data that is the transfer data transferred by the second data transfer unit that is the data transfer unit to which the second transfer control unit corresponds;
The second buffer control unit, which is a buffer control unit provided in the second transfer control unit,
When the first transfer data is not input from the first buffer control unit, the second transfer control information based on the second transfer control information that is the transfer control information of the second data transfer unit is used. Output the second transfer data read from the transfer buffer unit to the second data transfer unit,
When the first transfer data is input from the first buffer control unit, the first transfer data is output to the second data transfer unit based on the second transfer control information. ,
The data transfer state monitoring unit
Based on a control signal when the first data transfer unit transfers the first transfer data, the transfer waiting time of the first transfer data in the first data transfer unit is monitored and monitored. A data transfer waiting time monitoring unit that outputs a timeout signal indicating that the transfer waiting time exceeds a predetermined time when the transfer waiting time of the first transfer data exceeds a predetermined time;
Based on a signal when the first data transfer unit transfers the first transfer data, the transfer history of the first transfer data in the first data transfer unit and the second data transfer unit , Based on a signal when transferring the first transfer data or the second transfer data, the transfer history of the first transfer data or the second transfer data in the second data transfer unit An access history collection unit to collect;
With
The access history collection unit is based on the collected transfer history of the first transfer data and the transfer history of the second transfer data when the data transfer waiting time monitoring unit outputs the timeout signal. Outputting transfer information for transferring the transfer data by the first transfer data and the second transfer data to the first buffer control unit;
The first buffer control unit includes:
Based on the transfer information output from the access history collection unit, the first transfer data is distributed and output to the first data transfer unit and the second buffer control unit,
A data transfer control device. The data transfer state monitoring unit
Based on a control signal when the first data transfer unit transfers the first transfer data, the load of the transfer of the first transfer data in the first data transfer unit is monitored and monitored It is determined whether or not to distribute the load by comparing the transfer load of the first transfer data with a predetermined load size, and the transfer in the first data transfer unit based on the determined result A transfer load state monitoring unit for outputting a load distribution instruction for distributing the load,
With
The first buffer control unit includes:
Based on the load distribution instruction output from the transfer load state monitoring unit, the first transfer data is distributed and output to the first data transfer unit and the second buffer control unit,
The data transfer control device according to claim 1. The data transfer state monitoring unit
Based on a control signal when the first data transfer unit transfers the first transfer data, the remaining storage capacity of the first transfer buffer unit is monitored, and the monitored remaining storage capacity And a transfer buffer remaining amount monitoring unit that outputs a load distribution instruction for distributing the transfer load in the first data transfer unit,
With
The first buffer control unit includes:
Based on the load distribution instruction output from the transfer buffer remaining amount monitoring unit, the first transfer data is distributed and output to the first data transfer unit and the second buffer control unit.
The data transfer control device according to claim 1 or 2, characterized by the above. The data transfer state monitoring unit
In accordance with a set operation mode, a path of the first transfer data when transferring the first transfer data is determined, and a path for transferring the first transfer data is determined based on the determined result. A mode setting unit for outputting a route selection instruction to represent,
With
The first buffer control unit includes:
Based on the path selection instruction output from the mode setting unit, the first transfer data is distributed and output to the first data transfer unit and the second buffer control unit,
The data transfer control device according to any one of claims 1 to 3, wherein: A plurality of transfer controllers each having a transfer buffer unit and a buffer control unit, and a data transfer state monitoring unit having a data transfer waiting time monitoring unit and an access history collection unit, and transferring a plurality of data via a common bus A data transfer control method in a data transfer control device for outputting transfer data transferred via the common bus to each of the data transfer units,
A plurality of transfer control units correspond to each of the data transfer units, and a plurality of transfers that output the transfer data input from the data input unit corresponding to each of the data transfer units to the corresponding data transfer unit Control procedures;
A data transfer state monitoring unit monitors a state in which each of the data transfer units is transferring the transfer data, and based on the transfer state of the transfer data of each of the monitored data transfer units, A data transfer state monitoring procedure for outputting transfer control information for controlling the output of the transfer data to the corresponding data transfer unit in the transfer control procedure;
Including
Among the plurality of transfer control procedures, at least one of the transfer control procedures is:
Based on the transfer control information of the corresponding data transfer unit, the transfer data transferred by the data transfer unit is transferred to the other transfer control procedure corresponding to the transfer data transferred by the data transfer unit. Output by sorting to the transfer data transferred by the data transfer unit,
At least one other transfer control procedure to which the transfer data is distributed is:
The sorted transfer data is output to the corresponding data transfer unit based on the transfer control information of the corresponding data transfer unit,
Each of the plurality of transfer control procedures includes:
A transfer buffer procedure in which the transfer control unit temporarily stores the transfer data input from the data input unit corresponding to the corresponding data transfer unit in the corresponding transfer buffer unit;
A corresponding buffer control unit reads out and outputs the transfer data stored in the corresponding transfer buffer unit based on the transfer control information; and
Including
The first transfer buffer procedure that is the transfer buffer procedure included in the first transfer control procedure that is the transfer control procedure that distributes the transfer data is:
Temporarily storing the first transfer data, which is the transfer data transferred by the first data transfer unit, which is the data transfer unit corresponding to the first transfer control procedure, in the corresponding transfer buffer unit;
The first buffer control procedure that is a buffer control procedure included in the first transfer control procedure is:
Based on the first transfer control information that is the transfer control information of the first data transfer unit, the first transfer data read from the transfer buffer unit corresponding to the first transfer buffer procedure, The first transfer data transferred by the first data transfer unit and the first transfer data transferred by the other data transfer unit corresponding to another transfer control procedure are distributed and output,
The second transfer buffer procedure which is the transfer buffer procedure included in the second transfer control procedure which is the other transfer control procedure to which the first transfer data is distributed,
Temporarily storing the second transfer data, which is the transfer data transferred by the second data transfer unit, which is the data transfer unit corresponding to the second transfer control procedure, in the corresponding transfer buffer unit;
The second buffer control procedure that is a buffer control procedure included in the second transfer control procedure is:
When the first transfer data is not input by the first buffer control procedure, the second transfer control information based on the second transfer control information that is the transfer control information of the second data transfer unit is used. Output the second transfer data read from the transfer buffer unit corresponding to the transfer buffer procedure to the second data transfer unit;
When the first transfer data is input by the first buffer control procedure, the first transfer data is output to the second data transfer unit based on the second transfer control information. ,
The data transfer state monitoring procedure includes:
A data transfer waiting time monitoring unit waits for transfer of the first transfer data in the first data transfer unit based on a control signal when the first data transfer unit transfers the first transfer data. Data for monitoring time and outputting a time-out signal indicating that the transfer waiting time exceeds a predetermined time when the transfer waiting time of the monitored first transfer data exceeds a predetermined time Transfer waiting time monitoring procedure,
An access history collection unit, based on a signal when the first data transfer unit transfers the first transfer data, a transfer history of the first transfer data in the first data transfer unit; and Based on a signal when the second data transfer unit transfers the first transfer data or the second transfer data, the first transfer data or the second transfer in the second data transfer unit Access history collection procedure for collecting data transfer history,
Including
The access history collection procedure includes:
Based on the transfer history of the first transfer data and the transfer history of the second transfer data collected when the time-out signal is output by the data transfer waiting time monitoring procedure, Outputting transfer information for transferring the transfer data by the second transfer data to the transfer control unit corresponding to the first buffer control procedure;
The first buffer control procedure includes:
Based on the transfer information output by the access history collection procedure, the first transfer data is distributed to the first data transfer unit and the buffer control unit corresponding to the second buffer control procedure. Output,
A data transfer control method. A plurality of data transfer units for transferring data via a common bus;
A plurality of data input units corresponding to each of the data transfer units and outputting transfer data to be transferred via the common bus;
A plurality of transfer control units that correspond to the respective data transfer units and that output the transfer data input from the data input units corresponding to the respective data transfer units to the corresponding data transfer units; and the data transfer Each of the units monitors the state of transferring the transfer data, and the transfer data corresponding to the transfer data in each of the transfer control units is based on the transfer state of the transfer data of each of the monitored data transfer units A data transfer state monitoring unit that outputs transfer control information for controlling output to the data transfer unit, and a data transfer control device comprising:
With
Among the plurality of transfer control units provided in the data transfer control device, at least one of the transfer control units is:
Based on the transfer control information of the corresponding data transfer unit, the transfer data transferred by the data transfer unit is transferred to the other transfer control unit corresponding to the transfer data transferred by the data transfer unit. Output by sorting to the transfer data transferred by the data transfer unit,
Among the plurality of transfer control units provided in the data transfer control device, at least one other transfer control unit to which the transfer data is distributed,
The sorted transfer data is output to the corresponding data transfer unit based on the transfer control information of the corresponding data transfer unit,
Each of the plurality of transfer control units provided in the data transfer control device,
A transfer buffer unit for temporarily storing the transfer data input from the data input unit corresponding to the corresponding data transfer unit;
A buffer control unit that reads out and outputs the transfer data stored in the transfer buffer unit based on the transfer control information;
With
The first transfer buffer unit that is the transfer buffer unit provided in the first transfer control unit that is the transfer control unit that distributes the transfer data,
Temporarily storing the first transfer data that is the transfer data transferred by the first data transfer unit that is the data transfer unit to which the first transfer control unit corresponds;
The first buffer control unit, which is a buffer control unit provided in the first transfer control unit,
Based on the first transfer control information that is the transfer control information of the first data transfer unit, the first transfer data read from the first transfer buffer unit is transferred by the first data transfer unit. The first transfer data to be transferred and the first transfer data to be transferred by the other data transfer unit corresponding to the other transfer control unit are distributed and output,
The second transfer buffer unit which is the transfer buffer unit provided in the second transfer control unit which is the other transfer control unit to which the first transfer data is distributed,
Temporarily storing the second transfer data that is the transfer data transferred by the second data transfer unit that is the data transfer unit to which the second transfer control unit corresponds;
The second buffer control unit, which is a buffer control unit provided in the second transfer control unit,
When the first transfer data is not input from the first buffer control unit, the second transfer control information based on the second transfer control information that is the transfer control information of the second data transfer unit is used. Output the second transfer data read from the transfer buffer unit to the second data transfer unit,
When the first transfer data is input from the first buffer control unit, the first transfer data is output to the second data transfer unit based on the second transfer control information. ,
The data transfer state monitoring unit provided in the data transfer control device,
Based on a control signal when the first data transfer unit transfers the first transfer data, the transfer waiting time of the first transfer data in the first data transfer unit is monitored and monitored. A data transfer waiting time monitoring unit that outputs a timeout signal indicating that the transfer waiting time exceeds a predetermined time when the transfer waiting time of the first transfer data exceeds a predetermined time;
Based on a signal when the first data transfer unit transfers the first transfer data, the transfer history of the first transfer data in the first data transfer unit and the second data transfer unit , Based on a signal when transferring the first transfer data or the second transfer data, the transfer history of the first transfer data or the second transfer data in the second data transfer unit An access history collection unit to collect;
With
The access history collection unit is based on the collected transfer history of the first transfer data and the transfer history of the second transfer data when the data transfer waiting time monitoring unit outputs the timeout signal. Outputting transfer information for transferring the transfer data by the first transfer data and the second transfer data to the first buffer control unit;
The first buffer control unit includes:
Based on the transfer information output from the access history collection unit, the first transfer data is distributed and output to the first data transfer unit and the second buffer control unit,
A data processing apparatus. The data transfer control device is connected in a daisy chain according to the number of the data transfer unit and the data input unit,
The data transfer state monitoring unit provided in each data transfer control device is
Monitoring the transfer state of each transfer data of the corresponding data transfer unit, and outputting the transfer control information to each transfer control unit provided in the data transfer control device,
At least one of the transfer control units included in each data transfer control device,
Based on the transfer control information, the transfer data input from the corresponding data input unit is distributed to at least one data transfer unit corresponding to the data transfer control device,
The data processing apparatus according to claim 6.

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