JP6235510B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  Nitride-based compound semiconductors such as gallium nitride (GaN) have a wide band gap and high breakdown field strength, and are therefore used as power device materials that require high output or high voltage operation. . For example, in a semiconductor device such as a high electron mobility transistor (HEMT) having a structure in which an aluminum gallium nitride (AlGaN) layer is stacked on a gallium nitride layer, the gallium nitride layer and the aluminum gallium nitride layer Since a high-concentration two-dimensional electron gas is generated at the interface, the on-resistance is small, and a high output can be obtained with low loss.

  On the other hand, in such a semiconductor device, a phenomenon called current collapse in which the on-resistance increases and the drain current decreases when a high voltage is applied may occur. Since current collapse affects the characteristics of a semiconductor device, it is desired to suppress current collapse.

JP 2008-210934 A

  Embodiments of the present invention provide a semiconductor device in which current collapse is suppressed and a method for manufacturing the same.

According to the embodiment of the present invention, a semiconductor device including a semiconductor layer, a source electrode and a drain electrode, a gate electrode, and a protective layer is provided. The semiconductor layer includes a nitride semiconductor. The source electrode and the drain electrode are provided on the semiconductor layer and are electrically connected to the semiconductor layer. The gate electrode is provided on the semiconductor layer and between the source electrode and the drain electrode. The protective layer is provided on the gate electrode and between the source electrode and the drain electrode. The protective layer includes an insulating material. The polarity of the charge density of the protective layer is positive. The protective layer has a first region and a second region. The first region is located closer to the drain electrode than the gate electrode. The second region has a charge density lower than that of the first region.

1 is a schematic diagram showing a semiconductor device according to a first embodiment. FIG. 2A to FIG. 2C are schematic views illustrating a part of another semiconductor device according to the first embodiment. FIG. 6 is a reference diagram illustrating characteristics of a semiconductor device. It is a figure which shows the characteristic of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the characteristic of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the voltage applied to the semiconductor device which concerns on 1st Embodiment. It is a figure showing the characteristic of the semiconductor device concerning a 1st embodiment. It is a figure which shows the characteristic of the semiconductor device which concerns on 1st Embodiment. FIG. 9A to FIG. 9D are schematic views illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is a schematic diagram which shows the semiconductor device which concerns on 2nd Embodiment. FIG. 11A to FIG. 11C are schematic views showing a method for manufacturing a semiconductor device according to the second embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

In the present specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1). ) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In this specification, “provided on” includes not only the case of being provided in direct contact but also the case of being provided with another layer or film interposed therebetween. In addition to the case of being “provided facing”, the case of being provided in direct contact with the top or bottom includes the case of being provided with another layer or film interposed therebetween.

(First embodiment)
FIG. 1 is a schematic diagram illustrating the semiconductor device according to the first embodiment.
FIG. 2A to FIG. 2C are schematic views illustrating a part of another semiconductor device according to the first embodiment.
FIG. 3 is a reference diagram illustrating characteristics of the semiconductor device.
FIG. 4 is a diagram illustrating characteristics of the semiconductor device according to the first embodiment.
FIG. 1 shows a cross-sectional view of the semiconductor device 100. 2A to 2C are enlarged cross-sectional views in the vicinity of the gate electrode 30. FIG. 3 and 4 show enlarged cross sections in the vicinity of the drain electrode 50. FIG. 3 shows the characteristics of the semiconductor device of the comparative example.

  As shown in FIG. 1, the semiconductor device 100 includes a semiconductor layer 10, a first insulating layer 20, a gate electrode 30, a source electrode 40, a drain electrode 50, a second insulating layer 60, and a protective layer 70. And a third insulating layer 80 are provided. The semiconductor device 100 is, for example, a high electron mobility transistor having a structure in which an aluminum gallium nitride (AlGaN) layer is stacked on a gallium nitride (GaN) layer. A direction from the semiconductor layer 10 toward the first insulating layer 20 is a stacking direction (first direction).

  The semiconductor layer 10 is, for example, a nitride semiconductor layer. The semiconductor layer 10 includes an electron transit layer 10a and an electron supply layer 10b. The semiconductor layer 10 may be provided with a buffer layer formed on a substrate such as silicon (Si) by an epitaxial growth method such as a MOCVD (Metal Organic Chemical Vapor Deposition) method. The buffer layer can alleviate lattice mismatch between the substrate and the semiconductor layer 10. For example, the buffer layer is formed with a multilayer structure containing aluminum gallium nitride.

  The electron transit layer 10a is a channel layer. The electron transit layer 10a is a layer containing, for example, gallium nitride. The film thickness of the electron transit layer 10a is, for example, not less than 0.1 micrometers and not more than 10 micrometers.

The electron supply layer 10b is a barrier layer. The electron supply layer 10b is provided on the electron transit layer 10a. The electron supply layer 10b is a layer containing, for example, aluminum gallium nitride. The electron supply layer 10b is, for example, gallium nitride, aluminum gallium nitride _{(Al x Ga 1-x N} (0 <x <1)), there are indium nitride (InN), indium aluminum nitride _{(In y Al 1-y N} (0 <y <1)), indium gallium nitride _{(in z Ga 1-z N} (0 <z <1)) may be a layer containing at least one such. The film thickness of the electron supply layer 10b is, for example, not less than 10 nanometers and not more than 50 nanometers.

  The electron transit layer 10a is formed of a compound different from the compound contained in the electron supply layer 10b. A heterojunction is formed between the electron transit layer 10a and the electron supply layer 10b, and piezo polarization, or piezo polarization and spontaneous polarization are generated in the electron supply layer 10b by the hetero junction. By the electric field based on such polarization, a two-dimensional electron gas (2DEG) is generated in the vicinity of the heterojunction of the electron transit layer 10a. For example, in the semiconductor device 100, the switching operation can be performed by controlling the two-dimensional electron gas generated at the interface between the electron transit layer 10a and the electron supply layer 10b with a gate. The semiconductor layer 10 is not limited to the two-layer structure of the electron transit layer 10a and the electron supply layer 10b, and may have a layer structure of three or more layers.

The first insulating layer 20 is provided between the semiconductor layer 10 (electron supply layer 10 b) and the gate electrode 30. The first insulating layer 20 is a gate insulating layer. The first insulating layer 20 is a layer containing a nitride such as silicon nitride (SiN), for example. The first insulating layer 20 may be a film containing an oxide such as silicon oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ).

  The first insulating layer 20 includes, for example, a first layer 20a and a second layer 20b provided on the first layer 20a. The first insulating layer 20 may have a single layer structure or a layer structure of three or more layers. When the 1st insulating layer 20 has a several layer structure, each layer can be formed with a different compound.

  The gate electrode 30 includes, for example, a metal. For example, a metal film containing tungsten (W), molybdenum (Mo), copper (Cu), Ta (tantalum), or Al (aluminum) is used for the gate electrode 30. As the gate electrode 30, titanium nitride (TiN) or tantalum nitride (TaN) may be used. An aluminum alloy may be used for the gate electrode 30. The aluminum alloy has aluminum as a main component and hillock countermeasures are taken.

  For example, the gate electrode 30 includes a first portion 30 a provided in the first layer 20 a of the first insulating layer 20 and a second portion 30 b provided in the second layer 20 b of the first insulating layer 20. The second portion 30b is provided so as to protrude onto the first insulating layer 20 toward the drain electrode 50 side. That is, the gate electrode 30 of this embodiment has a GFP (Gate Field Plate) structure.

  Further, the side surface of the gate electrode 30 may be inclined with respect to the stacking direction. That is, the side surface of the gate electrode 30 may be tapered. By covering the side surface of the gate electrode 30 with a tapered shape, the coverage with the second insulating layer 60 formed on the gate electrode 30 is enhanced. Leakage current can be suppressed by increasing the coverage.

  The source electrode 40 and the drain electrode 50 are provided on the electron supply layer 10 b of the semiconductor layer 10. The source electrode 40 and the drain electrode 50 are electrically connected to the semiconductor layer 10. A metal film containing molybdenum, titanium (Ti), tantalum, tungsten, or aluminum is used for the source electrode 40 and the drain electrode 50. For the source electrode 40 and the drain electrode 50, molybdenum nitride (MoN), titanium nitride, or tantalum nitride may be used. A stacked film of two or more films of these conductive materials may be used for the source electrode 40 and the drain electrode 50. A film containing ITO (Indium Tin Oxide) may be used for the source electrode 40 and the drain electrode 50.

  The second insulating layer 60 is provided on the first insulating layer 20 and the gate electrode 30. For example, the second insulating layer 60 is provided so as to cover the gate electrode 30. The second insulating layer 60 is a layer that electrically insulates the gate electrode 30 from the source electrode 40 and the drain electrode 50. The second insulating layer 60 is a layer containing an oxide such as silicon oxide or aluminum oxide, for example. The second insulating layer 60 may be a film containing a nitride such as silicon nitride.

  The third insulating layer 80 is provided on the source electrode 40, the drain electrode 50, and the protective layer 70. For example, the third insulating layer 80 is a layer containing an oxide such as silicon oxide. The third insulating layer 80 is, for example, an overcoat layer. The third insulating layer 80 may be a layer containing the same material as the second insulating layer 60.

  The protective layer 70 is provided on the second insulating layer 60. For example, the protective layer 70 is a layer containing a nitride such as silicon nitride or aluminum nitride (AlN). The protective layer 70 may be a layer containing silicon oxide, Teos (Tetra Ethyl Ortho Silicate: TEOS), or aluminum oxide. The protective layer 70 may be a layer containing polycrystalline silicon such as high-resistance polysilicon. Further, two or more layers of silicon nitride, silicon oxide, theos, aluminum oxide, and polycrystalline silicon may be stacked on the protective layer 70.

  When the protective layer 70 is provided between the second insulating layer 60 and the third insulating layer 80, the protective layer 70 is made of a material having a band gap value smaller than that of the material of the second insulating layer 60. Can be formed. Further, the protective layer 70 can be formed of a material having a band gap value smaller than that of the material of the third insulating layer 80.

  When the second insulating layer 60 and the third insulating layer 80 are layers containing silicon oxide, the protective layer 70 is a layer containing silicon nitride. The band gap value of silicon oxide is 9.0 eV, and the band gap value of silicon nitride is 5.0 eV.

  When the second insulating layer 60 and the third insulating layer 80 are layers containing silicon oxide, the protective layer 70 is a layer containing aluminum nitride. The band gap value of silicon oxide is 9.0 eV, and the band gap value of aluminum nitride is 6.0 eV.

  When the second insulating layer 60 and the third insulating layer 80 are layers containing aluminum oxide, the protective layer 70 is a layer containing silicon nitride. The band gap value of aluminum oxide is 7.0 eV, and the band gap value of silicon nitride is 5.0 eV.

  When the second insulating layer 60 and the third insulating layer 80 are layers containing silicon oxide, the protective layer 70 is a layer containing high-resistance polysilicon. The band gap value of silicon oxide is 9.0 eV, and the band gap value of high resistance polysilicon is 1.1 eV.

  When the second insulating layer 60 and the third insulating layer 80 are layers including silicon nitride, the protective layer 70 is a layer including high-resistance polysilicon. The band gap value of silicon nitride is 5.0 eV, and the band gap value of high resistance polysilicon is 1.1 eV.

  When the protective layer 70 is formed of a material having a band gap value smaller than that of the material of the second insulating layer 60 and the third insulating layer 80, the protection layer 70 is not limited to the above-described example, and the protective layer 70 is protected by a combination of various materials. The layer 70, the second insulating layer 60, and the third insulating layer 80 can be formed. In the example described above, the material of the second insulating layer 60 and the material of the third insulating layer 80 are the same, but they may be different.

  As described above, in the semiconductor device 100 having the GFP structure, when the protective layer 70 is provided between the second insulating layer 60 and the third insulating layer 80, the band gap value of the protective layer 70 and the second insulating layer 60 and the band gap value of the third insulating layer 80 are shown. However, the magnitude relationship between the band gap values is not limited to such a structure of the semiconductor device 100.

  As illustrated in FIG. 2A, the gate electrode 30 is provided between the first insulating layer 20 and the second insulating layer 60, and the protective layer 70 is provided between the second insulating layer 60 and the third insulating layer 80. The protective layer 70 may be formed of a material having a band gap value smaller than the band gap values of the materials of the second insulating layer 60 and the third insulating layer 80.

  As shown in FIG. 2B, the gate electrode 30 is provided between the first insulating layer 20 and the protective layer 70, and the protective layer 70 is provided between the first insulating layer 20 and the third insulating layer 80. In this case, the protective layer 70 may be formed of a material having a band gap value smaller than that of the material of the first insulating layer 20 and the third insulating layer 80.

  For example, as shown in FIG. 2C, the gate electrode 30 is provided between the first insulating layer 20 and the second insulating layer 60, and the interlayer insulating layer 65 is formed between the second insulating layer 60 and the protective layer 70. A protective layer 70 is provided between the interlayer insulating layer 65 and the third insulating layer 80. In such a case, the protective layer 70 may be formed of a material having a band gap value smaller than that of the material of the interlayer insulating layer 65 and the third insulating layer 80.

  The protective layer 70 has a first region 70a and a second region 70b. For example, the second region 70b is a region provided around the first region 70a. The first region 70a is, for example, a region where positive charges are accumulated. For example, the first region 70a is formed by providing a positive fixed charge layer such as a silicon compound. Further, the first region is formed by supplying positive charges to the protective layer 70 by plasma processing such as corona discharge, for example.

For example, the first region 70 a in which positive charges are accumulated is provided between the source electrode 40 and the drain electrode 50. The electron trap exists in the interface between the semiconductor layer 10 and the first insulating layer 20 or in the first insulating layer 20, and the electric field generated by the positive charge in the first region 70a is an electron (trap charge) captured by the electron trap. The electric field generated by can be canceled out. Thereby, the decrease in the concentration of the two-dimensional electron gas due to current collapse is suppressed.
For example, the first region 70a is a region that does not overlap with the gate electrode 30 in the stacking direction. As a result, the electric field generated by the positive charges in the first region 70 a is suppressed from affecting the control of the gate electrode 30.

The first region 70a is provided so that the charge density of the first region 70a is higher than the charge density of the second region 70b. The charge density of the first region 70a can be set so as to compensate for the decrease in the concentration of the two-dimensional electron gas due to current collapse. For example, assuming that the decrease in the concentration of the two-dimensional electron gas due to current collapse is ΔNs (cm ⁻² ) and the thickness of the first region 70 is W1 (cm), the charge density N _fix (cm ⁻³ ) of the first region 70 a. Is represented by the following formula (1).

N _fix = ΔNs / W1 (1)

For example, the charge density value of the first region 70a can be set to be 1.0 × 10 ¹⁶ cm ⁻³ or more.

  Here, in a semiconductor device using a nitride semiconductor, it is known that a phenomenon called current collapse in which the drain current decreases when a stress such as a high voltage is applied between the source electrode and the drain electrode occurs. Electrons during high-voltage operation are captured by an electron trap that exists at a high density in the interface between the semiconductor layer 10 and the first insulating layer 20 or in the first insulating layer 20, and are generated by the trapped electrons (trap charges). The electric field reduces and depletes the two-dimensional electron gas generated at the interface between the electron transit layer 10a and the electron supply layer 10b. Depletion of the two-dimensional electron gas increases the on-resistance. This reduces the drain current.

  As shown in FIG. 3, in the semiconductor device, when the first region 70 a is not provided in the protective layer 70, the interface b <b> 1 between the electron supply layer 10 b of the semiconductor layer 10 and the first layer 20 a of the first insulating layer 20 is formed. The first electric field E1 is generated by the electrons e1 captured by the existing electron trap. The first electric field E1 reduces and depletes the two-dimensional electron gas generated at the interface b2 between the electron transit layer 10a and the electron supply layer 10b. Depletion of the two-dimensional electron gas increases the on-resistance and decreases the drain current.

  In the semiconductor device 100 of the present embodiment, the first region 70 a having a charge density higher than that of the second region 70 b is provided in the protective layer 70. When such a first region 70a is provided, the electric field generated by the positive charges in the first region 70a can cancel the electric field generated by the electrons captured by the electron trap. Thereby, the decrease in the concentration of the two-dimensional electron gas due to current collapse is suppressed.

  For example, as illustrated in FIG. 4, in the semiconductor device 100, the first is generated by the electrons e <b> 1 captured by the electron traps present at the interface b <b> 1 between the electron supply layer 10 b of the semiconductor layer 10 and the first layer 20 a of the first insulating layer 20. An electric field E1 is generated. On the other hand, the second electric field E2 is generated by the positive charge of the first region 70a. Since the first electric field E1 is canceled by the second electric field E2 in the direction opposite to the first electric field E1, the first electric field E1 is suppressed from affecting the interface b2 between the electron transit layer 10a and the electron supply layer 10b. Thereby, it is possible to suppress the decrease of the two-dimensional electron gas generated at the interface b2, and to suppress the decrease of the drain current due to the increase of the on-resistance.

  In the following, the results of the study on which the above effects are found will be described.

FIG. 5 is a diagram illustrating characteristics of the semiconductor device according to the first embodiment.
FIG. 6 is a diagram illustrating a voltage applied to the semiconductor device according to the first embodiment.
FIG. 7 is a diagram illustrating characteristics of the semiconductor device according to the first embodiment.
FIG. 8 is a diagram illustrating characteristics of the semiconductor device according to the first embodiment.

5, 7, and 8, the characteristics of the semiconductor device 100 are shown. In the semiconductor device 100, the protective layer 70 is a silicon oxide (SiO ₂ ) layer. The first region 70a is provided in the protective layer 70, and the charge density of the first region 70a is 2.0 × 10 ¹⁷ cm ⁻³ . FIG. 6 shows a waveform of stress applied to the semiconductor device 100. 7 and 8, the characteristics of the semiconductor device 100 when stress is applied as shown in FIG. 6 are shown. Such characteristics are evaluated by simulation.

  FIG. 5 is a graph showing the relationship between the drain voltage Vd and the drain current Id. The vertical axis in FIG. 5 represents the drain current Id (A). The horizontal axis in FIG. 5 represents the drain voltage Vd (V). A curve CL1 is a curve showing the relationship between the drain voltage Vd applied to the semiconductor device 100 and the drain current Id flowing through the semiconductor device 100. A curve CL2 is a curve of the reference example, and is a curve showing a relationship between the drain voltage Vd and the drain current Id in a semiconductor device in which the first region 70a is not provided in the protective layer 70.

  As shown in FIG. 5, when the curve CL1 and the curve CL2 are compared, it is found that the drain current Id increases when the first region 70a is provided in the protective layer 70.

  FIG. 6 shows waveforms of the gate voltage Vg and the drain voltage Vd when a stress is applied to the semiconductor device 100 with a pulse time of 1 s, a gate voltage of −15 V, and a drain voltage of 500 V. The vertical axis | shaft of FIG. 6 has each shown voltage V (V). The horizontal axis in FIG. 6 indicates time t (s).

  FIG. 7 is a graph showing the relationship between the drain voltage Vd and the drain current Id. The vertical axis in FIG. 7 indicates the drain current Id (A). The horizontal axis in FIG. 7 indicates the drain voltage Vd (V). A curve CL3 is a curve showing the relationship between the drain voltage Vd applied to the semiconductor device 100 after the stress is applied and the drain current Id flowing through the semiconductor device 100. A curve CL4 is a curve of the reference example, and is a curve showing a relationship between the drain voltage Vd and the drain current Id in a semiconductor device in which the first region 70a is not provided in the protective layer 70 after stress is applied. The curves CL1 and CL2 are the curves CL1 and CL2 in FIG. 5 and show the relationship between the drain voltage Vd and the drain current Id before stress application.

  As shown in FIG. 7, when the curve CL1 is compared with the curve CL4, it is found that when the first region 70a is provided in the protective layer 70, the decrease in the drain current Id is suppressed. It has been found that the electric field generated by the electrons captured by the electron trap can suppress the reduction of the two-dimensional electron gas by affecting the interface between the electron transit layer 10a and the electron supply layer 10b.

FIG. 8 shows a change in the state of electrons in the vicinity of the semiconductor layer 10. The vertical axis in FIG. 8 indicates the charge density D (cm ⁻² ) at the interface between the electron transit layer 10 a and the electron supply layer 10 b, that is, the channel cross section. The horizontal axis in FIG. 8 indicates the stacking direction and the vertical direction (X direction). That is, FIG. 8 shows a change in the charge density of the cross section of the channel in the X direction near the semiconductor layer 10.

  A curve CL5 indicates the charge density in the X direction before the stress is applied. A curve CL6 indicates the charge density in the X direction immediately before the stress is applied. A curve CL7 indicates the charge density in the X direction after the stress is applied.

  As shown in FIG. 8, when the curves CL5 to CL7 were compared, it was found that there was no significant difference in the waveform of the curve before and after stress application. This means that the electric field due to the positive charge in the first region 70a affects the vicinity of the semiconductor layer 10 before the stress is applied. Further, it was found that there is a convex portion P in which the charge density increases before and after stress application. It has been found that there is a region where electrons are easily injected by the convex portion P.

  As shown in FIGS. 5 to 8, when the first region 70a having a charge density higher than that of the second region 70b is provided in the protective layer 70, it is generated at the interface between the electron transit layer 10a and the electron supply layer 10b. It was found that the decrease in the two-dimensional electron gas can be suppressed and the decrease in the drain current due to the increase in the on-resistance can be suppressed.

  According to the present embodiment, a semiconductor device in which current collapse is suppressed is provided.

FIG. 9A to FIG. 9D are schematic views illustrating the method for manufacturing the semiconductor device according to the first embodiment.
As illustrated in FIG. 9A, a stacked body 90 including the semiconductor layer 10, the first insulating layer 20, the gate electrode 30, the source electrode 40, the drain electrode 50, and the second insulating layer 60 is formed. .

  The semiconductor layer 10 includes an electron transit layer 10a and an electron supply layer 10b. For example, the electron transit layer 10a and the electron supply layer 10b are formed on a substrate such as silicon. The semiconductor layer 10 is formed using, for example, an epitaxial growth method such as an MOCVD method. Thereafter, the first insulating layer 20 is formed on the semiconductor layer 10. The first insulating layer 20 is a layer containing silicon nitride or the like, and includes, for example, a first layer 20a and a second layer 20b formed on the first layer 20a.

  A gate electrode 30 is formed on the first insulating layer 20, and a source electrode 40 and a drain electrode 50 are formed on the semiconductor layer 10. For example, after forming a metal film by vapor deposition or sputtering, the metal film is etched to form each electrode. Each electrode may be formed using a mask vapor deposition method or a lift-off method after the metal film is formed. The gate electrode 30 includes, for example, a first portion 30a formed on the first layer 20a of the first insulating layer 20, and a second portion 30b formed on the second layer 20b of the first insulating layer 20. Have.

  A second insulating layer 60 is formed on the first insulating layer 20 and the gate electrode 30 so as to cover the gate electrode 30. The second insulating layer 60 is a layer containing silicon oxide or the like. The second insulating layer 60 is formed using, for example, a plasma CVD (Chemical Vapor Deposition) method.

  As shown in FIG. 9B, after forming the protective layer 70 on the second insulating layer 60, a resist mask 91 is formed on the protective layer 70. The protective layer 70 is a layer containing silicon nitride or the like. The protective layer 70 is formed using, for example, a plasma CVD method.

  As shown in FIG. 9C, corona discharge treatment is performed on the resist mask 91 to supply positive charges to the protective layer 70, thereby forming the first region 70 a in the protective layer 70. For example, positive corona irradiation is performed by discharge between electrodes using a high-frequency power source, and positive charges are supplied to the protective layer 70. As a result, a first region 70 a having a charge density higher than that of the second region 70 b is formed in the protective layer 70. After the normal corona irradiation, the resist mask 91 is peeled off. Note that the first region 70a may be formed in the protective layer 70 by a positive fixed charge layer such as a silicon compound.

For example, the first region 70a is formed between the source electrode 40 and the drain electrode 50 so as not to overlap the gate electrode 30 in the stacking direction. The charge density of the first region 70a can be set so as to compensate for the decrease in the concentration of the two-dimensional electron gas due to current collapse. For example, the charge density of the first region 70a can be set to be 1.0 × 10 ¹⁶ cm ⁻³ or more.

  As illustrated in FIG. 9D, the third insulating layer 80 is formed on the source electrode 40, the drain electrode 50, and the protective layer 70. The third insulating layer 80 is a layer containing silicon oxide or the like. The third insulating layer 80 is formed using, for example, a plasma CVD method.

  According to the present embodiment, a method for manufacturing a semiconductor device in which current collapse is suppressed is provided.

(Second Embodiment)
FIG. 10 is a schematic view showing a semiconductor device according to the second embodiment.
FIG. 10 shows a cross-sectional view of the semiconductor device 110.

  As shown in FIG. 10, the semiconductor device 110 includes a semiconductor layer 10, a first insulating layer 20, a gate electrode 30, a source electrode 40, a drain electrode 50, a second insulating layer 60, and a protective layer 71. And are provided. The direction from the semiconductor layer 10 toward the first insulating layer 20 is the stacking direction.

  The first insulating layer 20 is provided between the semiconductor layer 10 (electron supply layer 10 b) and the gate electrode 30. The first insulating layer 20 is a gate insulating layer.

  The gate electrode 30 includes, for example, a first portion 30a provided on the first layer 20a of the first insulating layer 20, and a second portion 30b provided on the second layer 20b of the first insulating layer 20. Have.

  The source electrode 40 and the drain electrode 50 are provided on the electron supply layer 10 b of the semiconductor layer 10. The source electrode 40 and the drain electrode 50 are electrically connected to the semiconductor layer 10. The source electrode 40 is provided so as to cover a part of the second insulating layer 60. Thereby, the source electrode 40 overlaps with the gate electrode 30 in the stacking direction.

  The second insulating layer 60 is provided on the first insulating layer 20 and the gate electrode 30. For example, the second insulating layer 60 is provided so as to cover the gate electrode 30.

  The protective layer 71 is provided on the source electrode 40, the drain electrode 50, and the second insulating layer 60. The protective layer 71 is provided so as to cover the source electrode 40, the drain electrode 50, and the second insulating layer 60. A third insulating layer 80 containing an oxide such as silicon oxide may be provided so as to cover the protective layer 71.

  The protective layer 71 includes a first region 71a overlapping with the second insulating layer 60 in the stacking direction, a second region 71b overlapping with the source electrode 40 in the stacking direction, and a third region 71c overlapping with the drain electrode 50 in the stacking direction. And having. The first region 71a is provided between the second region 71b and the third region 71c in the direction perpendicular to the stacking direction.

  For example, the protective layer 71 is a layer containing a nitride such as silicon nitride or aluminum nitride (AlN). The protective layer 71 may be a layer containing silicon oxide, Teos (Tetra Ethyl Ortho Silicate: TEOS), or aluminum oxide. The protective layer 71 may be a layer containing polycrystalline silicon such as high-resistance polysilicon. Further, two or more layers of silicon nitride, silicon oxide, theos, aluminum oxide, and polycrystalline silicon may be stacked on the protective layer 71.

Further, the charge density in the protective layer 71 (the first region 71a to the third region 71c) can be set so as to compensate for the decrease in the concentration of the two-dimensional electron gas due to current collapse. When the amount of decrease in the concentration of the two-dimensional electron gas due to current collapse is ΔNs (cm ⁻² ) and the thickness of the protective layer 71 is W2 (cm), the charge density N _fix (cm ⁻³ ) in the protective layer 71 is as follows: (2)

N _fix = ΔNs / W2 (2)

For example, the value of the charge density in the protective layer 71 can be set to be 1.0 × 10 ¹⁶ cm ⁻³ or more. That is, the protective layer 71 corresponds to a layer in which positive charges are accumulated.

For example, the first region 71 a of the protective layer 71 is provided between the source electrode 40 and the drain electrode 50. The electron trap exists in the interface between the semiconductor layer 10 and the first insulating layer 20 or in the first insulating layer 20, and the electric field generated by the positive charge in the first region 71a is an electron (trap charge) captured by the electron trap. The electric field generated by can be canceled out. Thereby, the decrease in the concentration of the two-dimensional electron gas due to current collapse is suppressed.
For example, the source electrode 40 is provided between the gate electrode 30 and the protective layer 71 in the stacking direction. As a result, the electric field generated by the positive charges in the second region 71 b of the protective layer 71 is shielded by the source electrode 40, so that the control of the gate electrode 30 is suppressed.

  The semiconductor device 110 of the present embodiment is provided with a protective layer 71 in which positive charges are accumulated. When such a protective layer 71 is provided, the electric field generated by the positive charges in the first region 71a of the protective layer 71 can cancel the electric field generated by the electrons captured by the electron trap. Thereby, the decrease in the concentration of the two-dimensional electron gas due to current collapse is suppressed.

  According to the present embodiment, a semiconductor device in which current collapse is suppressed is provided.

FIG. 11A to FIG. 11C are schematic views showing a method for manufacturing a semiconductor device according to the second embodiment.
As illustrated in FIG. 11A, after a stacked body 92 including the semiconductor layer 10, the first insulating layer 20, the gate electrode 30, and the second insulating layer 60 is formed, a conductive film is formed on the stacked body 92. 93 is formed.

The laminated body 92 is formed as follows.
The semiconductor layer 10 includes an electron transit layer 10a and an electron supply layer 10b. For example, the electron transit layer 10a and the electron supply layer 10b are formed on a substrate such as silicon. The semiconductor layer 10 is formed using, for example, an epitaxial growth method such as an MOCVD method. Thereafter, the first insulating layer 20 is formed on the semiconductor layer 10. The first insulating layer 20 is a layer containing silicon nitride or the like, and includes, for example, a first layer 20a and a second layer 20b formed on the first layer 20a.

  A gate electrode 30 is formed on the first insulating layer 20. The gate electrode 30 is formed by, for example, forming a metal film by vapor deposition or sputtering and then etching the metal film. The gate electrode 30 may be formed using a mask vapor deposition method or a lift-off method after the metal film is formed. For example, the gate electrode 30 includes a first portion 30 a formed in the first layer 20 a of the first insulating layer 20 and a second portion 30 b formed in the second layer 20 b of the first insulating layer 20.

  A second insulating layer 60 is formed on the first insulating layer 20 and the gate electrode 30 so as to cover the gate electrode 30. The second insulating layer 60 is a layer containing silicon oxide or the like. The second insulating layer 60 is formed using, for example, a plasma CVD (Chemical Vapor Deposition) method.

  After the stacked body 92 is formed, a conductive film 93 is formed on the stacked body 92. The conductive film 93 is formed to be electrically connected to the semiconductor layer 10 (electron supply layer 10b) and cover the first insulating layer 20 and the second insulating layer 60. The conductive film 93 is a metal film, for example, and is formed by a vapor deposition method or a sputtering method.

  As shown in FIG. 11B, a part of the conductive film 93 is etched to form the source electrode 40 and the drain electrode 50. When the conductive film 93 is a metal film, the source electrode 40 and the drain electrode 50 may be formed using a mask vapor deposition method or a lift-off method after the metal film is formed.

  As shown in FIG. 11C, a protective layer 71 is formed on the source electrode 40, the drain electrode 50, and the second insulating layer 60. The protective layer 71 is formed so as to cover the source electrode 40, the drain electrode 50, and the second insulating layer 60. The protective layer 71 is a layer containing silicon nitride or the like. The protective layer 71 is formed using, for example, a plasma CVD method.

In the case where the protective layer 71 such as silicon nitride is formed using the plasma CVD method, the protective layer 71 can be formed using a film formation temperature of 400 ° C. and a source gas as a mixed gas of Si ₄ —NH ₃ . The charge density in the protective layer 71 is controlled by the flow rate of NH ₃ and the output of the film forming apparatus. Thereby, the charge density in the protective layer 71 is set so as to compensate for the decrease in the concentration of the two-dimensional electron gas due to current collapse. For example, the charge density in the protective layer 71 can be set to be 1.0 × 10 ¹⁶ cm ⁻³ or more.

  After forming the protective layer 71, a third insulating layer 80 containing an oxide such as silicon oxide may be formed so as to cover the protective layer 71. The third insulating layer 80 is formed using, for example, a plasma CVD method.

  According to the present embodiment, a method for manufacturing a semiconductor device in which current collapse is suppressed is provided.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 10a ... Electron travel layer, 10b ... Electron supply layer, 20 ... 1st insulating layer, 20a ... 1st layer, 20b ... 2nd layer, 30 ... Gate electrode, 30a ... 1st part, 30b ... 1st 2 parts, 40 ... source electrode, 50 ... drain electrode, 60 ... second insulating layer, 65 ... interlayer insulating layer, 70, 71 ... protective layer, 70a, 71a ... first region, 70b, 71b ... second region, 71c ... 3rd area | region, 80 ... 3rd insulating layer, 90, 92 ... Laminated body, 91 ... Resist mask, 93 ... Conductive film, 100, 110 ... Semiconductor device, b1, b2 ... Interface, CL1-CL7 ... Curve, e1 ... Electrons, E1 ... first electric field, E2 ... second electric field, P ... convex part, Vd ... drain voltage, Vg ... gate voltage, W1, W2 ... thickness

Claims (9)

A semiconductor layer comprising a nitride semiconductor;
A source electrode and a drain electrode provided on the semiconductor layer and electrically connected to the semiconductor layer;
A gate electrode provided on the semiconductor layer and between the source electrode and the drain electrode;
A is on the gate electrode, is provided between the drain electrode and the source electrode, the insulating material seen including a protective layer polarity charge density is positive,
With
The protective device includes a first region located closer to the drain electrode than the gate electrode, and a second region having a charge density lower than that of the first region. 2. The semiconductor device according to claim 1, wherein a value of a charge density in the first region is 1.0 × 10 ¹⁶ cm ⁻³ or more.   3. The semiconductor device according to claim 1, wherein the first region does not overlap the gate electrode in a first direction from the semiconductor layer toward the gate electrode. A first insulating layer provided between the semiconductor layer and the gate electrode;
A second insulating layer provided between the gate electrode and the protective layer;
A third insulating layer provided on the protective layer;
Further comprising
The band gap value of the material included in the protective layer is smaller than the band gap value of the material included in the second insulating layer and the band gap value of the material included in the third insulating layer. The semiconductor device according to any one of the above. A semiconductor layer comprising a nitride semiconductor;
A source electrode and a drain electrode provided on the semiconductor layer and electrically connected to the semiconductor layer;
A gate electrode provided on the semiconductor layer and between the source electrode and the drain electrode;
An insulating layer provided on the gate electrode;
A protection provided on the source electrode, the drain electrode, and the insulating layer, including an insulating material, having a positive charge density polarity and a charge density value of 1.0 × 10 ¹⁶ cm ⁻³ or more. Layers,
A semiconductor device comprising:   The semiconductor device according to claim 5, wherein the source electrode overlaps with the gate electrode in a first direction from the semiconductor layer toward the gate electrode. A semiconductor layer including a nitride semiconductor; a source electrode and a drain electrode provided on the semiconductor layer and electrically connected to the semiconductor layer; and the source electrode and the drain electrode on the semiconductor layer. Forming a protective layer including an insulating material on the gate electrode and between the source electrode and the drain electrode, in a stacked body including a gate electrode provided between the source electrode and the drain electrode;
Supplying a positive charge to the protective layer, forming a first region located nearer to the drain electrode than the gate electrode and having a higher charge density than other regions in the protective layer;
A method for manufacturing a semiconductor device comprising:   The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the first region, positive charges are supplied to the protective layer by corona discharge treatment. In a stacked body including a semiconductor layer including a nitride semiconductor, a gate electrode provided on the semiconductor layer, and an insulating layer provided on the gate electrode, a conductive film is formed on the stacked body. Forming, and
Removing a part of the conductive film to form a source electrode and a drain electrode electrically connected to the semiconductor layer;
Forming a protective layer including an insulating material on the source electrode, the drain electrode, and the insulating layer;
With
The polarity of the charge density of the protective layer is positive,
The manufacturing method of the semiconductor device whose charge density value of the said protective layer is 1.0 * 10 < ¹⁶ > cm < ^-3 > or more.

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