JP6236940B2 - Printed circuit board and printed circuit board patterning method - Google Patents

Description

  The present invention relates to a printed circuit board and a method for patterning the printed circuit board.

  When reflow mounting surface mount type electronic components (also called chip components) such as chip capacitors, chip resistors, and IC chips (semiconductor components) on the printed circuit board lands, paste solder (solder paste) is applied to the lands. After printing, a chip component terminal is placed and passed through a reflow furnace, whereby the solder paste is melted and the land and the chip component terminal are joined (also referred to as a reflow process).

  At this time, the so-called bridging phenomenon where the molten solder is connected to the solder of the adjacent land, the component misalignment where the chip component is pulled in the direction in which the solder melts and flows, and in severe cases the terminal of the chip component is Mounting defects such as erroneous connection of terminals connected to the terminal may occur.

  Such a mounting failure takes into account the shape of adjacent lands, and a solder resist that suppresses the spread of the melted solder in places where the bridges between the lands are easily bridged or wiring portions extending from the lands where the solder is likely to melt and flow out. (For example, refer patent document 1).

  FIG. 7A is a perspective view illustrating a method of using the solder resist 9 on a conventional printed circuit board. As shown in FIG. 7A, the wiring 3 extending from the land 2 is covered with the solder resist 9 among the conductor portions including the land 2 and the wiring 3, so that the solder 3 melted in the reflow process extends from the land. It is possible to prevent the chip part from being displaced by being pulled in the direction in which the molten solder flows and the terminal 5 of the chip part to be spread.

  FIG. 7B shows a printed circuit board in which the solder resist 9 is removed from the printed circuit board having the structure shown in FIG. 7A, and the solder 6 is attached to the lead portion of the wiring extending from the land by heating in the reflow process. It is a perspective view which shows the state which melted and spread. When the solder 6 wets and spreads on the lead-out portion of the wiring, the terminal 5 of the chip component has a tensile force F [N] (F = T) proportional to the surface tension T [N / m] of the solder and the wiring width W [mm]. × W) is added, causing the position of the component to shift.

JP 2000-299548 A

  Incidentally, in recent years, in order to improve the mounting density of components, electronic components are mounted inside a multilayer board. In such a component-embedded substrate, due to problems such as a decrease in delamination strength between layers due to insufficient adhesion between the solder resist and the substrate material and an increase in the number of man-hours, the land provided in the component mounting area inside the substrate and the solder on the wiring portion In general, no resist is applied.

  Since the printed circuit board with such a structure cannot be covered with a solder resist at the wiring portion extending from the land or the place where the land is easily bridged, it is not suitable for mounting defects such as a bridge phenomenon, component misalignment, and terminal misconnection. Measures must be taken. Further, chip components are not limited to two terminals, and there are many multi-terminal components such as IC chips, and it is necessary to deal with such multi-terminal components. Furthermore, it goes without saying that even in normal surface mounting, it is better to take measures against mounting defects without using a solder resist.

  The present invention has been made to solve such problems, such as bridge phenomenon, component misalignment, and terminal misconnection without using a solder resist when reflow mounting a surface mount type electronic component on a printed circuit board. It is an object of the present invention to provide a printed circuit board and a method for patterning the printed circuit board that can take measures against mounting defects.

In order to solve the above problems, a printed circuit board according to one embodiment of the present invention includes a substrate, a plurality of lands disposed on a surface of the substrate and connected to each other using an electronic component and a solder member, and the plurality of lands. And a lead wire having a lead wire width and a lead direction drawn from each of them and connected to the land, and the solder melted when melting the solder member to connect the electronic component and the plurality of lands. The width of each lead- out wiring is changed according to the force in the flowing direction, and the plurality of forces applied to the component are canceled within one electronic component by melting the solder member and flowing in the lead-out direction of the wiring. It is characterized by the provision.
Furthermore, the wiring of each of a plurality of lands connected to one electronic component has a different extraction wiring width. That is, the lead wiring width of the wiring corresponding to one electronic component is two or more types.

  According to another aspect of the printed circuit board of the present invention, the plurality of lands connected to the one electronic component from the origin is set at a point in a region corresponding to one electronic component arranged on the surface of the substrate. The sum of the moments in each land derived from the distance to the center of each land and the pulling direction force of the wiring drawn from each land is the moment of the component, and the average value of the lead wiring width of each land When the lead wire width is uniform, the sum of the moments in each land is set as a reference moment, and the lead direction of the wire and the lead wire are set so that the absolute value of the moment of the component is smaller than the absolute value of the reference moment. The width is specified.

In the printed circuit board patterning method of one embodiment of the present invention, a plurality of lands connected using electronic components and solder members are arranged on a surface of the substrate, and a wiring drawing direction for drawing wiring from each of the plurality of lands is provided. In determining the lead- out wiring width, each lead-out wiring width is changed according to the force in the direction in which the molten solder flows when the solder member is melted to connect the electronic component and the plurality of lands, and The lead- out direction of the wiring and the lead- out wiring width are defined so that a plurality of forces applied to the component are canceled in one electronic component by melting the solder member and flowing in the lead- out direction of the wiring. .
The printed circuit board patterning method according to one aspect of the present invention is the method for determining the direction of drawing out the wiring and the width of the drawing wiring, and after the direction of drawing out the wiring is defined, the wiring width of the drawing is reduced in the component. It is characterized by having been prescribed | regulated.

  In the present invention, when the electronic component and the land are connected by melting a solder member such as a solder paste, the solder member melts and flows in the wiring drawing direction so as to cancel out a plurality of forces applied to the component. By defining the wiring lead-out direction and lead-out wiring width, it is possible to suppress the phenomenon that electronic components rotate or shift due to imbalance in the surface tension of the solder, so bridge phenomena, component shifts and terminals without using solder resist It is possible to take measures to suppress the occurrence of mounting defects such as incorrect connection.

  According to the present invention, a printed circuit board and a printed circuit board capable of taking measures to suppress the occurrence of mounting defects such as a bridge phenomenon, component misalignment, and erroneous connection without using a solder resist when an electronic component is reflow-mounted on the board. The patterning method can be provided.

It is a figure which shows the structure of the printed circuit board of 1st Embodiment. It is a figure which shows the relationship between the direction which the solder flows when a solder paste melts, and the force concerning components. It is a figure which shows an example of the printed circuit board in which the wiring pattern was formed for 8 terminal IC chips. It is a figure which shows the measurement result at the time of changing the wiring width of a wiring extraction position with respect to the land of the printed circuit board shown in FIG. 3 by a list. It is a figure which shows an example of the printed circuit board in which the wiring pattern for 24 terminal IC components which is 2nd Embodiment was formed. It is a figure which shows an example of the electronic component built-in board | substrate which is 3rd Embodiment. It is a figure explaining the effect of the soldering resist in the conventional printed circuit board.

  Hereinafter, a printed circuit board according to an embodiment of the printed circuit board and the printed circuit board patterning method of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of a printed circuit board and a mounting state of an IC chip according to the first embodiment, and FIG. 2 is a diagram illustrating a relationship between a direction in which solder flows when a solder paste is melted and a force acting on an electronic component.

FIG. 1B is a diagram illustrating the i-th land, the land, and the wiring portion drawn out from the land in detail.
FIG. 1C is a cross-sectional view of the land 2a and land 2b along the line AA in FIG. 1A. The solder paste 6 is applied to the lands 2a and 2b, and the terminals 5a and 5b of the IC chip 4 are applied. Is shown in cross-section in a state in which is placed in alignment with the lands 2a and 2b.
In FIG. 1A, the subscripts a, b, to h of the land 2 and the wiring 3 correspond to the subscripts 1, 2, and 8 of the wiring width W, and these subscripts (integers) are i. And the wiring width may be expressed as Wi. The force Fi acting on the terminal, the moment component Fim of the force acting on the terminal, and the subscript i of the radial direction component Fir are also expressed in the same manner. Further, the subscript i of the angles θi and δi in the wiring drawing direction in FIG.

(First embodiment)
As shown in FIG. 1A, it is assumed that the printed circuit board according to the first embodiment is an IC chip 4 such as an 8-pin electronic component to be mounted.
The printed circuit board shows an example provided with a substrate 1, for example, a plurality of lands 2a to 2h, and wirings 3a to 3h.

  The substrate 1 is an insulating plate material using, for example, an epoxy resin. The lands 2a to 2h are formed on one surface of the substrate. The lands 2a to 2h are metal foil patterns for connecting terminals of an electronic component such as the IC chip 4, for example, and are designed in a shape corresponding to each terminal of the electronic component.

  When electronic components are mounted on the substrate 1, a solder member such as a solder paste 6 is placed on the lands 2a to 2h by printing using a metal mask. In the lands 2a to 2h, the terminals 5a to 5h of the IC chip 4 are correspondingly placed on the solder paste 6 at the time of component mounting. In this state, the substrate 1 is carried into a reflow furnace, and the solder paste 6 is applied. By heating and melting, the terminals 5a to 5h and the lands 2a to 2h are joined (connected).

  The wires 3a to 3h are drawn from the lands 2a to 2h in the respective drawing directions (angles θ1 to θ8) as shown in FIG. 1B, and the drawing wire widths W1 to W8 at the drawing positions are defined. Yes. Here, the wiring drawing direction θi is an angle measured counterclockwise from the horizontal axis (referred to as x-axis in the figure) to the wiring drawing direction.

  For example, the wiring 3a is led out from the land 2a in the left direction (θ1 = 180 °) toward the drawing, and the width of the leading wiring is W1. The wiring 3b is drawn downward from the land 2b toward the drawing (θ2 = −90 °), and the width of the drawing wiring is W2. The same applies to the other wirings 3c to 3h.

  In FIG. 1A, the lead-out wiring width W1 of the wiring 3a is set narrower than the lead-out wiring width W2 of the wiring 3b. The lead-out wiring width W1 and the lead-out wiring width W2 are set so as to adjust the force in the direction in which the solder flows.

  In this example, the land 2a and the land 2b have similar directions from the center of the component, but the lead-out directions of the wiring 3a and the wiring 3b are different, and the directions of the moments F1m and F2m (arrows) are reversed. F1m and moment F2m have directions that cancel each other.

  The wirings 3a to 3h define the center (center of gravity) of the IC chip 4 or the average position of the centers of the lands 2a to 2h as the origin O, and the distance from the origin O to the center points P1 to P8 of the lands 2a to 2h. Lead wiring widths W1 to W8 of the wirings 3a to 3h at the connection positions with the lands 2a to 2h so as to cancel a plurality of forces F1m to F8m (moment of moment) that rotate the IC chip 4 generated according to r1 to r8. And a drawing direction (angles θ1 to θ8) are defined.

  That is, the wirings 3a to 3h are solder pastes when the wiring directions of the wirings 3a to 3h (angles θ1 to θ8) and the wiring widths W1 to W8 are connected to the terminals 5a to 5h of the IC chip 4 and the lands 2a to 2h. It is specified that a plurality of forces applied to the electronic component are canceled by mutual melting of 6 and flowing in the wiring drawing direction.

Here, a method for patterning a printed circuit board according to the first embodiment will be described.
When the surface tension when the solder paste printed and placed on the lands 2a to 2h of the respective wirings 3a to 3h is melted is expressed as T [N / m], and the respective wiring widths are W1 to W8, The force Fi in the direction in which the solder flows to each wiring 3i is expressed as Fi = T × Wi [N].

  For example, the position of the average value of the centers P1 to P8 of the lands 2a to 2h corresponding to the IC chip 4 is defined as the origin O, and the distance from the origin O to the centers P1 to P8 of the lands 2a to 2h is denoted as r1 to r8. Assume that the angles formed by the line connecting the origin O and the center Pi of each land and the wiring drawing direction of each land (that is, the direction of Fi) are δ1 to δ8. Here, δi can be obtained by subtracting the angle formed by the straight line connecting the origin O and the center Pi of the land with the horizontal direction (x-axis direction) from the angle θi in the wiring drawing direction.

  The moment Fim acting on the terminal 5i of the IC chip 4 at the position of each land 2a to 2h is expressed as Fim = Fi × ri × sin δi (i is an arbitrary number). The individual lead-out wiring widths W1 to W8 are adjusted and set so that the total sum M of moments acting on each terminal 5 of one IC chip 4 is reduced.

  That is, the position of the average value of the centers P1 to P8 of the lands 2a to 2h corresponding to the IC chip 4 on the main surface of the substrate 1 is the origin O, and the distances r1 to r1 from the origin O to the centers Pi of the lands 2a to 2h. The sum M of moments F1m to F8m in each land 2a to 2h derived from r8 and the forces F1 to F8 in the drawing direction (angles θ1 to θ8) of the wirings 3a to 3h drawn from each land 2a to 2h is set to zero or zero. The lead-out direction of the wirings 3a to 3h and the lead-out wiring widths W1 to W8 are defined so as to approach each other.

  In general, as shown in FIG. 2, when the surface tension of the solder 6 is T [N / m] and the wiring width is Wi [m], the solder 6 flows in the direction in which the wiring 3 is pulled out. The force Fi acting on the terminal 5i is Fi = T × Wi [N]. Therefore, it can be said that the force Fi acting on the terminal 5i of the electronic component 4 increases or decreases in proportion to the wiring width Wi.

  If the relation of Fi = T × Wi is substituted into the sum M of moments acting on each terminal 5i of the IC chip 4 and expressed as a function of Wi, M = T × r1 × sin δ1 × W1 + T × r2 × sin δ2 × W2 +. + T × r8 × sin δ8 × W8 (= T × Σ (ri × sin δi × Wi)... From this equation 1, it can be seen that the sign of the moment acting on each terminal is determined by sin δi (that is, the wiring drawing direction), and the magnitude can be increased or decreased by the drawing wiring width Wi.

There are various methods for obtaining the lead wiring width Wi for sufficiently reducing the moment sum M. As a simple method, the lead line width of the land where sin δi is positive in each term of Equation 1 of the moment sum M. Substituting (W + ΔW) for Wi, substituting (W−ΔW) for the lead line width Wi of a land where sin δi is negative, giving W as a constant, and obtaining ΔW that minimizes or minimizes the absolute value of moment M Good. If ΔW is determined, two types of lead wiring widths are obtained as (W + ΔW) and (W−ΔW).
As another method for obtaining the lead wiring width Wi that makes the sum of moments M sufficiently small, the square of the sum of moments M is used as an evaluation function, the least square method is used with Wi as a parameter, and the wiring width constraints are satisfied. By obtaining the combination of Wis that gives the minimum value of the evaluation function, the combination of the lead line widths Wi that minimizes the magnitude of the sum M of moments can be obtained.

  In the present invention, the force applied to each chip component due to the surface tension of the solder melted in the reflow process cancels out the force applied to the component by adjusting the lead-out direction of the wiring drawn from each land and the width of the lead-out wiring. It is an object of the present invention to provide a means for preventing chip components from moving in the reflow process and preventing terminals from being misconnected or causing bridges. At this time, it has been found that sufficiently reducing the sum of moments applied to each terminal for each chip component is effective in preventing erroneous connection of terminals and occurrence of bridges. The reason for this is considered to be that reducing the sum of moments effectively prevents erroneous connection that occurs when the chip component rotates and the terminal contacts an adjacent land.

  Furthermore, it is important to make fine adjustments to the lead-out wiring width while considering how to reduce the sum of the moments by adjusting the lead-out wiring width by setting the wiring lead-out direction so that the moment is divided into positive and negative. I found out. In other words, in the design of the printed circuit board, the wiring drawing direction is limited by the design rules (for example, vertical, horizontal, 45 degrees), and there are restrictions that come from wiring routing. However, it is difficult to sufficiently reduce the sum of moments, but the lead-out wiring width can be fine-tuned between the maximum line width and the minimum line width in the design, and the moment is offset to make it sufficiently small. It was found that it is possible to prevent erroneous connection of terminals and occurrence of bridges.

(Example)
As shown in FIG. 3, for example, an 8-terminal IC chip (2 × 4 pin IC) wiring pattern is formed on the substrate, and the lands A1 to A8 are not changed without changing the positions and shapes of the lands A1 to A8. As a result of soldering by reflow after mounting electronic components on a printed circuit board that has been changed to four different wiring widths W1 to W8 (Example 1, Example 2, Example 3, Example 4) I tried to measure the occurrence rate of parts misalignment and bridge.

Specifically, the lands A1 to A8 of each wiring are set, the center of the IC chip to be mounted is set as the origin O, and the sum M of moments at the center points of the plurality of lands A1 to A8 is obtained.
The IC chip package used for the actual measurement has a model number called WLCSP8, and 8 terminals are arranged in 2 rows and 4 columns on a 0.4 mm grid. The lands A1 to A8 are also arranged on a 0.4 mm grid correspondingly. The solder paste used is a solder paste having a composition called Sn-3Ag-0.5Cu, and the surface tension T at the time of melting is 0.45 to 0.55 [N / m]. In the following moment calculation, the surface tension is not expressed as a numerical value but as a symbol T [N / m].

  In Example 1, the lead-out wiring widths W1 to W8 were determined so that the sum of moments of the plurality of lands A1 to A8 was 0.006 T [μN · m] (moment ratio was 6%). In Example 2, the lead-out wiring width W was determined so that the sum of moments was −0.017 T [μN · m] (moment ratio was 16%). In Example 3, the lead-out wiring width W was determined so that the sum of moments was −0.030 T [μN · m] (moment ratio was 28%). In Example 4, the lead-out wiring width W was determined so that the sum of moments was −0.052 T [μN · m] (moment ratio was 52%).

  Here, the moment ratio is the sum of moments M0 when the average value of the lead wiring widths W1 to W8 set in relation to the component of interest is W0 and all the lead wiring widths corresponding to the component are W0 ( The absolute value of the ratio M / M0 to the reference moment M0 of the sum of moments M (sometimes referred to as component moments) when the wiring width is W1 to W8 is calculated as a percentage. It is the indicated value. The moment ratio defined in this way represents the degree of reduction of the component moment M due to the adjustment of the wiring widths W1 to W8 as a ratio (percentage) to the reference moment M0. According to the moment ratio, the surface tension T of the solder is canceled by the ratio and disappears. Therefore, the decrease in the moment due to the adjustment of the lead wiring width Wi can be evaluated by the relative value of the moment determined only by the wiring pattern.

  Table 1 in FIG. 4 shows the results of actual measurement of the component deviation occurrence rate and the bridge occurrence rate by creating a printed circuit board having the lead-out wiring width obtained in Examples 1 to 4 and mounting the components by the solder reflow process. Shown in According to Table 1, in Example 4, the component deviation occurrence rate of the printed circuit board having a moment ratio of 52% is 8.3%, and the bridge occurrence rate is 6.3%. In Example 3, the moment ratio was reduced to 28%, but the component deviation occurrence rate was 6.4%, and the bridge occurrence rate was 4.5%. When the moment ratio was reduced to 16% in Example 2, the component deviation occurrence rate was 1.2% and the bridge occurrence rate was 2.4%. Compared to Example 4, the component deviation occurrence rate was 1/6, and the bridge occurrence rate. It improved greatly to 1 / 2.6. Further, as shown in Example 1, when the moment ratio was reduced to 6%, a remarkable effect of reducing mounting defects was obtained with a component deviation occurrence rate of 0% and a bridge occurrence rate of 0.75%.

  From the results of Table 1 above, the printed circuit board of the wiring pattern in which the lead wiring width Wi is determined so that the moment ratio is within 0 to 16% as shown in Example 2 is the component deviation occurrence rate in the reflow process. And the bridge occurrence rate is greatly improved, which is preferable. More preferably, the pattern having the wiring width W determined so that the moment ratio is within 0 to 6% as shown in Example 1 has a significantly improved component deviation rate and bridge rate, and the most desirable result. I was able to show that

  As described above, according to the first embodiment, the drawing directions θ1 to θ8 of the wirings 3a to 3h drawn from the lands 2a to 2h and the wiring widths W1 to W8 are determined based on the surface of the solder when the solder paste is melted in the reflow process. By prescribing to suppress the effect of surface tension so that the IC chip 4 does not shift or rotate due to tension, it is possible to take measures against mounting defects such as bridge occurrence rate and component deviation occurrence rate, and maintain a high yield. Can do.

  That is, measures for mounting defects such as bridging phenomenon, component misalignment, and erroneous connection should be taken without applying a solder resist during reflow mounting by designing the land 2a-2h and wirings 3a-3h on the substrate 1. Can do.

(Second Embodiment)
As shown in FIG. 5, the second embodiment is an example in which wiring patterns are formed symmetrically.

  In this example, as an example of wiring design for component mounting on a printed circuit board, an electronic component (a flat package 51 or the like) having a large number of terminals such as n pins (for example, 24 pins) is assumed. Design the wiring pattern (n is an arbitrary number). The flat package 51 is, for example, a BGA (Ball Grid Array).

  In this case, the wiring pattern is point-symmetrically patterned with respect to the center point O of the flat package 51. Note that the center point O coincides with the center of gravity.

  In this example, the wiring pattern is also line-symmetrically patterned with respect to the longitudinal center axis Qx passing through the center point O and the axis Qy passing through the center point O orthogonal to the center axis Qx.

  Further, in this example, the wiring width of the wiring drawn from the land near the outer edge of the flat package 51 is formed thick, and the wiring drawn from the land located at a place far from the outer edge of the flat package 51 (place near the center) is formed. The lead wiring width is narrow. The permissible range of the lead-out wiring width of the wiring is within ± 10%.

  That is, in this embodiment, a wiring pattern composed of a plurality of lands and lead-out wirings is formed point-symmetrically and / or line-symmetrically with respect to the center point O of the flat package 51 arranged on the main surface of the substrate 1. .

  In this example, since the wiring patterns are formed in line symmetry, for example, forces f1 and f2 acting in the direction of the wiring drawn from the land due to the surface tension of the solder between the wiring patterns facing each other via the central axis Qx. , F3, f4, f9, f10 and forces f5, f6, f7, f8, f11, f12 are canceled (cancelled). Further, the force f1, f2, f5, f6, f11 and the force f3, f4, f7, f8, f10 acting in the direction of the wiring drawn from the land due to the surface tension of the solder between the wiring patterns opposed via the central axis Qy. , F12 are canceled (cancelled).

  Therefore, when the flat package 51 is mounted on this printed circuit board and the solder paste is heated and melted in the reflow process, the surface tension of the solder is applied almost evenly to the flat package 51, and displacement and rotation are suppressed. The

  As described above, according to the second embodiment, since the wiring patterns are arranged symmetrically, not only the moment of force of the first embodiment but also the force attracting at the left and right and up and down of the central axis of the electronic component is canceled. The surface tension of the solder at the time of melting the solder paste in the reflow process is applied almost evenly to the flat package 51, the positional displacement and rotation of the flat package 51 are suppressed, and the bridge phenomenon, component displacement and It is possible to take measures against mounting defects such as incorrect connection.

(Third embodiment)
As shown in FIG. 6, the printed circuit board according to the third embodiment is provided with openings 68 in four substrates 63 to 66 that are inner layers of a laminated substrate in which a plurality of substrates 61 to 67 are stacked. This is an electronic component built-in substrate in which a semiconductor component 81 as an electronic component is mounted in a space formed by the opening 68.

  A solder resist layer 69 is formed on one surface of the lowermost substrate 61. A wiring pattern 70 is formed on the uppermost substrate 67. Also, a solder resist layer 71 is formed on the uppermost substrate 67 so as to overlap a part of the wiring pattern 70.

  A wiring pattern 72 is formed in a portion exposed to the space of the substrate 62. The wiring pattern 72 defines the lead-out direction θi and the lead-out wiring width Wi of the wirings 3a to 3h from the lands 2a to 2h shown in the first embodiment. A terminal 83 of a semiconductor component 81 mounted by reflow is joined (connected) to the wiring pattern 72 by solder 85.

  That is, in the printed circuit board of the third embodiment, one or more semiconductor components 81 (active components) or passive components are mounted in a component mounting space (space) in the inner layer of the substrate, and one or more semiconductor components 81 or passive components are mounted. The components are electrically connected via the wiring pattern 72.

  In the third embodiment, a wiring pattern that defines the direction and width of the wiring from the land is formed in the component mounting space formed on the outer surface or inside of the multilayer substrate in which a plurality of substrates 61 to 67 are stacked. By mounting the electronic component, the semiconductor component 81 can be mounted without forming a solder resist layer in the component mounting space provided in the inner layer of the multilayer substrate.

  The invention of the present application is not limited to the above-described embodiment. In the implementation stage, the constituent elements are modified without departing from the scope of the invention (partial deletion of elements, change of combination of elements between the embodiments, etc.). May be.

  In the above embodiment, the wiring pattern 72 that defines the lead-out direction θi and the lead-out wiring width Wi of the wirings 3a to 3h from the lands 2a to 2h is formed in the space formed in the laminated substrate. A wiring pattern 72 may be formed on the outer surface (outer layer).

  The printed circuit board patterning method described in the above embodiment may be realized by a program installed in a storage such as a memory of a computer. The program may be stored in a computer-readable electronic medium. The computer may realize the patterning method of the printed circuit board by causing the computer to read from the electronic medium.

  Examples of the electronic medium include a recording medium such as a CD-ROM, a flash memory, and a removable media. Further, the configuration may be realized by distributing and storing components in different computers connected via a network, and communicating between computers in which the components are functioning.

DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2a-2h, A1-A8 ... Land 3a-3h ... Wiring 4 ... IC chip 5a-5h ... Terminal 6 ... Solder paste 21 ... Wiring 23 ... Electronic component 51 ... Flat package 61-67 ... Board | substrate 68 ... Opening 69 ... Solder resist layer 70 ... Wiring pattern 71 ... Solder resist layer 72 ... Wiring pattern 81 ... Semiconductor component 83 ... Terminal 85 ... Solder

Claims (7)

A substrate,
A plurality of lands disposed on the surface of the substrate and connected to each other using electronic components and solder members;
A wiring connected to the land having a width and a direction of a lead wiring drawn from each of the plurality of lands,
When the solder member is melted to connect the electronic component and the plurality of lands, the width of each lead-out wiring is changed according to the force in the direction in which the molten solder flows, and the solder member is melted and wired. A printed circuit board characterized in that a wiring drawing direction and a drawing wiring width are defined so that a plurality of forces applied to the electronic component by flowing in the drawing direction are canceled within one electronic component .   A point in a region corresponding to one electronic component arranged on the surface of the substrate as an origin, a distance from the origin to the center of each of the lands connected to the one electronic component; The sum of the moments in each land derived from the pull-out direction force of the wiring drawn from each land is used as the moment of the component, and the lead-out wiring width is equalized with the average value of the lead-out wiring width of each land. The lead-out direction and the lead-out wiring width of the wiring are defined so that a sum of moments in each land is a reference moment, and an absolute value of the moment of the component is smaller than an absolute value of the reference moment. The printed circuit board according to 1.   The printed circuit board according to claim 2, wherein a wiring drawing direction and a drawing wiring width are defined so that an absolute value of the moment of the component is within 0 to 16% of an absolute value of the reference moment.   2. The print according to claim 1, wherein a wiring pattern including the plurality of lands and the wiring is formed point-symmetrically and / or line-symmetrically with respect to a center of an electronic component disposed on the surface of the substrate. substrate.   The electronic component is mounted by forming a wiring pattern defining a wiring drawing direction and a wiring width from the land in a space formed on the outer surface or inside of a multilayer substrate in which a plurality of substrates are stacked. Item 4. The printed circuit board according to item 1. A plurality of lands on which a solder member for connection to an electronic component is placed are arranged on the surface of the substrate, and the solder member is melted in determining the direction and width of the lead wiring from each of the plurality of lands. Each lead wiring width is changed according to the force in the direction in which the molten solder flows when connecting the electronic component and the plurality of lands, and the solder member melts and flows in the wiring drawing direction. A method for patterning a printed circuit board, wherein the wiring drawing direction and the drawing wiring width are defined so as to cancel a plurality of forces applied to the electronic component in one electronic component.   7. The method for determining a direction of drawing out the wiring and a width of the drawing wiring, wherein the direction of drawing out the wiring is defined, and then the width of the drawing wiring is defined so as to reduce a moment of the component. Patterning method for printed circuit boards.

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