JP6237202B2 - Semiconductor memory device and control method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a technique for suppressing malfunction of a semiconductor memory device using a flash memory.

  As electronic devices such as information terminal devices become smaller and higher in performance, semiconductor memory devices using nonvolatile semiconductor memory elements are widely used for storing data in electronic devices. A magnetic disk or the like has been the mainstream for storing large-capacity data. However, with the development of element formation technology, it is possible to increase the capacity of a semiconductor memory device. A large-capacity semiconductor memory device using a nonvolatile semiconductor memory element is also called an SSD (Solid State Drive). Since the semiconductor memory element does not have a mechanical drive unit, the semiconductor memory device can read and write data at a higher speed than a magnetic disk or the like, and can suppress power consumption.

  A NAND flash memory is often used as a memory element of a large-capacity semiconductor memory device. The flash memory can repeatedly write and read data, but due to the operation principle, the insulating film forming the memory element is deteriorated by the repeated operation. If the number of storage elements whose deterioration of the insulating film has progressed increases, it cannot be compensated by an error correction function or the like, and an operation failure may occur. Therefore, a semiconductor memory device using a flash memory may have a spare storage area for dealing with the occurrence of defects due to continuous use. In the NAND flash memory, the written data is erased in units of areas formed by a certain number of elements called blocks. Therefore, in the NAND flash memory, a spare storage area corresponding to a defective block in which a defect has occurred is also provided in block units as an alternative block. However, since the storage capacity of the entire storage area is limited, the storage capacity that can normally be used is reduced if a large number of alternative blocks that are spare storage areas are provided. Therefore, it is desirable that the size of the spare storage area for the substitute block is suppressed as much as possible. On the other hand, if all the substitute blocks are in use, the semiconductor memory device may be unusable. In order to avoid an unusable state, in a semiconductor memory device using a flash memory, a technique for suppressing the shortage of alternative blocks has been actively studied. As a technique for suppressing the shortage of substitute blocks, for example, a technique as disclosed in Patent Document 1 is disclosed.

  Patent Document 1 relates to a technique for suppressing the number of replacement blocks used in a flash memory and preventing the shortage of replacement blocks. In Patent Document 1, a block in which the number of error occurrences when reading data exceeds a predetermined number is determined as a defective block. The number of error occurrences for determining whether the block is a bad block is changed according to the remaining number of replacement blocks. In Patent Document 1, when the number of remaining substitute blocks is smaller than a set value, the number of use of substitute blocks is suppressed by setting a large number of error occurrences used for determining whether the block is a defective block. As a result, it is possible to prevent a situation in which the flash memory becomes unusable suddenly by suppressing a rapid decrease of the substitute blocks.

  Patent Document 2 relates to a technique for securing the number of substitute blocks by changing a normal block to a substitute block in a flash memory. In Patent Document 2, a block determined to be defective is tested again to determine whether the defect is temporary or permanent. When it is determined that the defect is permanent, the normal block is changed to a substitute block when the remaining number of substitute blocks is equal to or less than a predetermined number. In Patent Document 2, it is possible to avoid a state in which the flash memory cannot be operated by converting a normal block into a substitute block and securing a certain number of substitute blocks.

JP 2010-61507 A JP 2005-284700 A

  However, the technique of Patent Document 1 is not sufficient in the following points. In Patent Document 1, the threshold value of the number of errors for determining a block as defective is changed according to the remaining number of alternative blocks. In Patent Document 1, by relaxing the condition for determining as defective, a block with a large number of error occurrences is also treated as a normal block, and a decrease in the number of alternative blocks as a spare storage area is suppressed. Therefore, even in a block treated as a normal block, many errors may occur during writing and reading. In addition, when a number of blocks in which the number of error occurrences exceeds the threshold that eases the condition occurs, a replacement block is used, and thus a decrease in the replacement block cannot be suppressed. For this reason, it is necessary to provide a sufficient number of alternative blocks in order to cope with the occurrence of errors that exceed the thresholds with relaxed conditions. Therefore, in Patent Document 1, it is necessary to sufficiently reserve a spare storage area for a substitute block, and the technique of Patent Document 1 is a technique for avoiding an unusable state while suppressing the spare storage area. Not enough.

  Further, in the technique of Patent Document 2, when the remaining number of substitute blocks that are spare storage areas is equal to or less than a predetermined number, the blocks in the normal storage area are changed to substitute blocks. For this reason, when the remaining number of alternative blocks is equal to or less than a predetermined number, the storage capacity of the normal storage area may decrease in order to secure a spare storage area. Therefore, with the technique of Patent Document 2, it is not possible to suppress a decrease in alternative blocks while maintaining the normal storage capacity of the semiconductor memory device. It is desirable that the semiconductor memory device can be used as it is at the initially set storage capacity. Therefore, Patent Document 2 is not sufficient as a technique for use in a semiconductor memory device using a flash memory.

  An object of the present invention is to obtain a semiconductor memory device capable of continuing the operation even when many defective blocks occur while suppressing the size of the spare storage area.

  In order to solve the above problems, the semiconductor memory device of the present invention includes a storage unit, an address management unit, a substitute block forming unit, and a control unit. The storage means stores data in a storage area divided into a plurality of blocks for each predetermined storage capacity. The address management means manages the address of a normal area by dividing a defective block in which an abnormality has occurred among the blocks into a plurality of areas. The substitute block forming means forms a second substitute block that is treated as one block by combining normal areas of defective blocks so as to satisfy the predetermined storage capacity. When the predetermined condition is satisfied, the control means writes data in a continuous area from the normal area of the block forming the second alternative block.

  According to the method for controlling a semiconductor memory device of the present invention, a defective block in which an abnormality has occurred among a plurality of blocks divided into a plurality of blocks for each predetermined storage capacity is divided into a plurality of areas, and addresses of normal areas Manage. The method for controlling a semiconductor memory device of the present invention forms a second alternative block that is treated as one block by combining normal areas of defective blocks so as to satisfy a predetermined storage capacity. In the semiconductor memory device control method of the present invention, data is written to a normal area of the block forming the second alternative block when a predetermined condition is satisfied.

  According to the present invention, it is possible to continue the operation even when many bad blocks occur while suppressing the size of the spare storage area.

It is a figure which shows the outline | summary of a structure of the 1st Embodiment of this invention. It is a figure which shows the outline | summary of a structure of the 2nd Embodiment of this invention. It is the figure which showed the example of the allocation of the address for description of the 2nd Embodiment of this invention. It is the figure which showed the example of the abnormality occurrence location in the 2nd Embodiment of this invention. It is the figure which showed the example of the data table in the 2nd Embodiment of this invention. It is the figure which showed the example of the data table in the 2nd Embodiment of this invention. It is the figure which showed the outline | summary of the operation | movement flow in the 2nd Embodiment of this invention. It is the figure which showed the outline | summary of the operation | movement flow in the 2nd Embodiment of this invention. It is the figure which showed the outline | summary of the operation | movement flow in the 2nd Embodiment of this invention. It is the figure which showed the outline | summary of the operation | movement flow in the 3rd Embodiment of this invention.

  A first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an outline of the configuration of the semiconductor memory device of this embodiment. The semiconductor memory device of this embodiment includes a storage unit 1, an address management unit 2, an alternative block forming unit 3, and a control unit 4.

  The storage unit 1 stores data in a storage area divided into a plurality of blocks for each predetermined storage capacity. The address management unit 2 manages the addresses of normal areas by dividing a defective block in which an abnormality has occurred among the blocks into a plurality of areas. The substitute block forming means 3 forms a second substitute block that is treated as one block by combining normal areas of defective blocks so as to satisfy a predetermined storage capacity. Further, the control means 4 writes data in a normal area of the block forming the second alternative block when a predetermined condition is satisfied.

  The semiconductor memory device according to the present embodiment divides a defective block in which an abnormality has occurred into a plurality of areas, and combines the normal areas so as to have a predetermined storage capacity, thereby obtaining a second alternative block that is a virtual block. Forming. By using the second substitute block instead of the defective block, the operation can be continued without assigning a normal block composed of a continuous area to the block used as a substitute. As a result, in the semiconductor memory device of this embodiment, the operation can be continued even when many defective blocks occur while suppressing the size of the spare storage area.

  A second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows an outline of the configuration of the semiconductor memory device of this embodiment. The memory element of the semiconductor memory device of this embodiment is formed as a NAND flash memory. A storage area of a semiconductor memory device using a NAND flash memory is divided into a plurality of areas for each predetermined storage capacity, and one divided area is called a block. In the semiconductor memory device of this embodiment, when an abnormality occurs in a part of a block, a defective block which is a block in which an abnormality has occurred is divided, and an area in which no abnormality has occurred is determined as a storage area. Use. In the semiconductor memory device of this embodiment, when a defective block is divided and used as a storage area, normal areas of a plurality of defective blocks are used in combination. The semiconductor memory device of this embodiment uses a defective block as a storage area by virtually creating a block having the same storage capacity as one normal block by combining a plurality of defective normal areas.

  As shown in FIG. 2, the semiconductor memory device of this embodiment includes a memory unit 10, a control unit 21, a buffer memory unit 22, a defective block management unit 23, and a secondary replacement area management unit 24. . A control bus for inputting / outputting control signals is connected to the semiconductor memory device of this embodiment. In addition, a data bus for inputting / outputting data to / from the outside is connected to the semiconductor memory device of this embodiment. The control bus is connected to the control unit 21. Data input / output via the data bus is temporarily stored in the buffer memory unit 22.

  The memory unit 10 is divided into a plurality of blocks. Each block of the memory unit 10 is divided into a normal block in the normal storage area 11 and an alternative block in the spare storage area 12. A normal block is a block used for writing and reading data. A substitute block is a block that is used in place of a normal block when a normal block that cannot be used occurs due to an abnormality. In the present embodiment, a block that cannot be used due to an abnormality in the elements constituting the block is referred to as a defective block. Of all the blocks in the memory unit 10, a predetermined number or proportion of blocks are set as substitute blocks for the spare storage area 12.

  Each block is composed of a predetermined number of pages. Each page is composed of a combination of a predetermined number of memory cells sharing control wiring. A memory cell is a unit for storing 1-bit information. In the NAND flash memory, data stored in the memory cell is erased in units of blocks. Data writing and reading are performed in units of pages.

  The control unit 21 has a function of performing overall control relating to writing, reading, and erasing of data in the memory unit 10. The control unit 21 writes data to a block at an address designated as a write destination of the memory unit 10 in accordance with a write request sent from the outside. Data to be written is input to the buffer memory unit 22 via the data bus and temporarily stored. Further, the control unit 21 reads data from the block of the memory unit 10 designated as the read source in accordance with the read request. The control unit 21 temporarily stores the read data in the buffer memory unit 22 and outputs it via the data bus.

  The control unit 21 may be configured to have an address conversion function. In the case of a configuration including an address conversion function, the control unit 21 converts an address designated as a write destination into an address of a free normal block based on a predetermined algorithm. The predetermined algorithm is set so that the number of times of use for each block is leveled in order to prevent the number of times of use for each block from being biased. The control unit 21 associates the address before conversion and the address after conversion and stores them in the address conversion table. When the address is converted, the control unit 21 performs each process by regarding the converted address as the designated address. When reading from the address before conversion is designated, the control unit 21 reads data from the address after conversion based on the address conversion table and outputs the read data. The technique for leveling the number of times of use for each block described above is also called wear leveling.

  The buffer memory unit 22 has a function of temporarily storing input data. Data that is input to the buffer memory unit 22 from the outside via the data bus and stored is sent to the memory unit 10 based on an instruction from the control unit 21. The buffer memory unit 22 is also used for temporarily storing data when data called from the memory unit 10 is sent to the outside. The buffer memory unit 22 outputs the temporarily stored data based on an instruction from the control unit 21 to the outside through the data bus.

  The defective block management unit 23 has a function of managing an address of a defective block and an address of an alternative block used instead of the defective block. Further, the defective block management unit 23 has a function of storing the presence / absence of use of a secondary replacement block as a replacement block. The secondary replacement block is formed by combining normal areas of defective blocks. The bad block management unit 23 includes a data table that stores an address of a bad block in association with an address of an alternative block used instead of the bad block. In the present embodiment, a data table in which a bad block and a substitute block are associated and stored is referred to as a bad block management table.

  The secondary replacement area management unit 24 has a function of managing addresses of usable areas among the divided block areas when a defective block is divided. The secondary replacement area management unit 24 manages areas that can be used by a plurality of defective blocks in combination. For example, when the defective block is divided into two, the secondary replacement area management unit 24 manages the usable areas of the two defective blocks in combination. The secondary replacement area management unit 24 includes a data table that stores the head addresses of the areas to be used in the combined defective blocks in association with each other. In the present embodiment, the data table that stores the head address of the area to be used in association is called a secondary alternative area management table. In the present embodiment, a virtual block formed by combining areas where a plurality of blocks can be used is called a secondary substitute block. In the present embodiment, the area used for the secondary replacement block is referred to as a secondary replacement area.

  A defective block management table and a secondary replacement area management table in this embodiment will be described. Assume that each block of the memory unit 10 of this embodiment is assigned an address as shown in FIG. FIG. 3 schematically shows an address assigned to each block for the purpose of explaining the present embodiment. The notation of the address in FIG. 3 is simply shown by substituting alphabets and numbers for the sake of simplicity. For example, in the spare storage area 12 shown in FIG. 3, the block composed of the addresses “S1” and “S2” has the head address “S1”, and the head of the rear area when the block is divided into two. This indicates that the address of “S2” is “S2”. FIG. 4 shows an example in which an abnormality occurs in some blocks when addresses are assigned as shown in FIG. FIG. 4 shows an example in which a page where writing or the like cannot be performed occurs in the area on the front side of the block starting with the address “M3” and the area on the back side of the block starting with the address “A9”. In the example of FIG. 4, blocks starting with addresses “M3” and “A9” are defective blocks. In the example of FIG. 4, the block starts with the address “M3”. It is assumed that an area starting with the rear address “M4” can be used. In the example of FIG. 4, it is assumed that the area starting with the address “A9” on the front side is usable and the area starting with the address “A10” on the back side is unusable among the blocks starting with the address “A9”.

  A defective block management table of the semiconductor memory device of this embodiment will be described. FIG. 5 shows an example of the bad block management table of this embodiment. In the item of “bad block address” in the bad block management table of FIG. 5, the head address of a block that has been treated as a bad block due to an abnormality is registered. In the example of FIG. 5, in addition to the blocks starting with the addresses “M3” and “A9” shown in FIG. 4, the block starting with the address “N5” is treated as a bad block. “Alternative block address” in FIG. 5 indicates the head address of an alternative block used as a data storage destination instead of a defective block. FIG. 5 shows an example in which the blocks with the addresses “S1” and “S3” in the spare storage area 12 are assigned as alternatives to the blocks with the addresses “M3” and “A9”. The item “Presence / absence of use of secondary substitute block” in FIG. 5 is registered as to whether a secondary substitute block is used as a substitute block. In FIG. 5, “1” is registered when the secondary substitute block is used as the substitute block, and “0” is registered when it is not used. When the secondary replacement block is used, the address registered in the “substitution block address” of the bad block management table is used as the head address of the secondary replacement block.

  Next, the secondary alternative area management table will be described. FIG. 6 shows an example of the secondary alternative area management table of the present embodiment. “Secondary alternative block start address” in FIG. 6 indicates the start address of the storage area used as the front area among the blocks used as the secondary alternative block. The “secondary alternative block head address” is also registered as the “substitute block address” in the defective block management table. “Secondary alternative block subaddress” indicates the head address of the storage area used as the rear area among the blocks used as the secondary alternative block. In the example of FIG. 6, the storage areas starting with addresses “M3” and “M8” are treated as virtually forming one block. The address “H2” in FIG. 6 indicates a state in which the rear storage area used in combination is unregistered. In the example of FIG. 6, the storage area starting with the address “H2” is in a state where it cannot be used as a secondary replacement block because the storage area used in combination is not registered.

  An operation when data is written in the semiconductor memory device of this embodiment will be described. FIG. 7 shows an outline of a flow when data is written in the semiconductor memory device of this embodiment. First, a write request, a write destination address, and data to be written are sent from the outside to the semiconductor memory device (step 101). Data sent to the semiconductor memory device via the data bus is input to the buffer memory unit 22. When data is input to the buffer memory unit 22, the buffer memory unit 22 stores the input data (step 102).

  The control unit 21 checks the bad block management table of the bad block management unit 23 to check whether the address designated as the data write destination is not included in the bad block management table (step 103). When the data write destination address is included in the bad block management table, the control unit 21 checks whether or not the secondary replacement block is used. When the secondary alternative area is used, the control unit 21 confirms the secondary alternative area management table. In the secondary replacement area management table, the control unit 21 determines the data write destination together with the address area registered in combination with the address registered in the bad block management table. If the write destination address is registered in the bad block management table, but the secondary replacement area is not used, the control unit 21 determines the replacement block address as the write destination. If the data write destination address is not included in the bad block management table, the control unit 21 determines a block in the normal storage area 11 whose address matches the write destination address as the write destination (step 104). ).

  When determining the data write destination, the control unit 21 checks whether the write destination block is a normal block or a bad block. Whether or not the block to be written to is normal is confirmed, for example, by applying a voltage to the source line shared for each page and applying the voltage normally. When previous data remains in the write destination block, the control unit 21 erases the data stored in the write destination block at a time before performing the write operation. When the write destination is a secondary alternative block, erasure is performed in units of blocks, so that an erasure process is also applied to an area that is determined to be an abnormal area and is not used.

  When the write destination block is a normal block (No in step 105), the control unit 21 saves the data saved in the buffer memory unit 22 in the block determined as the write destination (step 113). When an abnormality occurs in the write destination block and the block is a defective block (Yes in step 105), the control unit 21 adds the address of the defective block that is the block in which the abnormality has occurred to the defective block management table and saves it. (Step 106).

  When the address of the defective block is added to the defective block management table, the control unit 21 determines whether or not the number of alternative blocks being used is equal to or less than a predetermined number. If the number of used alternative blocks is less than or equal to the predetermined number (Yes in step 107), the control unit 21 stores the data that was to be written in the defective block stored in the buffer memory unit 22 in the spare storage area. It is determined that data is written in 12 alternative blocks. If it is determined that the data is to be written to the alternative block, the control unit 21 determines the address of the alternative block to be written from the available alternative blocks (step 111). When the address of the alternative block to be written is determined, the control unit 21 stores the determined alternative block address in the defective block management table in association with the address of the defective defective block (step 112). When information on the replacement block to be used is stored in the defective block management table, the control unit 21 writes the data stored in the buffer memory unit 22 to the selected replacement block (step 113).

  If the number of replacement blocks being used is greater than the predetermined number (No in step 107), the control unit 21 determines whether the secondary replacement block can be used as a data write destination. The control unit 21 checks the secondary replacement area management table and determines whether the secondary replacement block can be used depending on whether there is a secondary replacement block that can be used (step 108). If there is no secondary substitute block that can be used (No in Step 109), the control unit 21 determines the address of the alternative block to be written from the available substitute blocks (Step 111). When the address of the alternative block to be written is determined, the control unit 21 stores the determined alternative block address in the defective block management table in association with the address of the defective defective block (step 112). When information on the replacement block to be used is stored in the defective block management table, the control unit 21 writes the data stored in the buffer memory unit 22 to the selected replacement block (step 113).

  If there is a usable secondary replacement block (Yes in step 109), the control unit 21 determines a secondary replacement block to be used for writing data from the secondary replacement area management table (step 110). The control unit 21 selects one unused pair as a secondary replacement block from a combination of two addresses registered in the secondary replacement area management table, and determines it as a secondary replacement block to be used. When determining the secondary replacement block to be used, the control unit 21 refers to the bad block management table and determines whether or not the secondary replacement block is used. When the secondary replacement block to be used is determined, the control unit 21 stores the head address of the secondary replacement block in association with the address of the defective block in the defective block management table. Further, the control unit 21 stores information indicating that the secondary replacement block is used in the bad block management table. When the secondary alternative block to be used for data writing is determined, the control unit 21 writes the data stored in the buffer memory unit 22 to the selected secondary alternative block (step 113). The control unit 21 performs control so that the remaining data stored in the buffer memory unit 22 is written to the other block after data is written to one of the two combined blocks. Thus, the data write operation to the memory unit 10 in the semiconductor memory device of this embodiment is completed.

  Next, in the semiconductor memory device of this embodiment, an operation when reading stored data will be described. FIG. 8 shows an outline of an operation flow when data stored in the semiconductor memory device of this embodiment is read.

  It is assumed that a read request for stored data is sent from the outside together with the read source address and is input to the control unit 21 (step 121). Upon receiving the data read request, the control unit 21 checks the bad block management table in order to check whether the read source address is an alternative address (step 122).

  If the read source address is not an alternative block (No in step 123), the control unit 21 reads the data of the block designated as the read source (step 124). The control unit 21 sequentially reads data from the block of the memory unit 10 corresponding to the address to the buffer memory unit 22. Data read from the memory unit 10 is stored in the buffer memory unit 22.

  The controller 21 measures the number of memory cells in which a data read error has occurred when reading data (step 125). In the present embodiment, the control unit 21 divides one block into two, and measures the number of error occurrences for each divided area. When the reading of one block of data is completed, the control unit 21 determines whether the number of memory cells in which an error has occurred is less than a predetermined number for each divided area. If the number of memory cells in which an error has occurred is less than the predetermined number in both areas (Yes in step 126), the control unit 21 determines that the block from which data has been read is normal. When the control unit 21 determines that the block from which the data has been read is a normal block, the control unit 21 outputs the data stored in the buffer memory unit 22 via the data bus. When the data in the buffer memory unit 22 is output, the data read operation is completed. Further, when there is a request for data to be read, the operation from step 121 is repeated.

  When the number of errors in reading data is equal to or greater than a predetermined number in one or both areas (No in step 126), the control unit 21 determines that the block from which data is read is a bad block. . When the control unit 21 determines that the block from which the data has been read is a defective block, the control unit 21 stores the address of the block as a defective block (step 128). When the control unit 21 stores the information on the defective block, the control unit 21 also stores the head address of the normal area in the defective block. When determining that the block from which the data has been read is a defective block, the control unit 21 moves the data determined to be a defective block to another block (step 129). The control unit 21 performs data transfer of defective blocks when there is no data read or write request. When data transfer is performed, the control unit 21 controls the operation from step 107 in FIG. 7 to write data to another block.

  When the read source address is an alternative block (Yes in step 123), the control unit 21 checks whether the read source address is that of the secondary alternative block. The control unit 21 checks the bad block management table and determines whether the address that is the read source is that of the secondary alternative block. When the read source address is not the secondary alternative block (No in step 130), the control unit 21 confirms the address of the alternative block corresponding to the read source address. When the control unit 21 confirms the address of the alternative block, the control unit 21 sequentially reads data from the memory cell of the memory unit 10 corresponding to the address to the buffer memory unit 22 and performs the operation from step 124.

  If the read source address is not that of the secondary replacement block (Yes in step 130), the control unit 21 refers to the secondary replacement area management table and confirms the address of the secondary replacement block that is the read source. When the control unit 21 confirms the address of the secondary substitute block, it reads data from the secondary substitute block (step 133). The control unit 21 sequentially reads out data from the address on the head block side among the blocks used in combination as the secondary alternative block and stores them in the buffer memory unit 22. Next, the control unit 21 reads the data of the other block and stores it in the buffer memory unit 22 so as to be continuous data. When the data is read from the secondary alternative block and stored in the buffer memory unit 22, the control unit 21 measures the number of error occurrences and performs the operation from step 125.

  Next, an operation when a virtual block is formed and registered as a secondary alternative block by combining normal areas among defective blocks in which an abnormality has occurred will be described. FIG. 9 shows an outline of a flow when a normal part of a block in which an abnormality has occurred is registered as a secondary alternative block in the semiconductor memory device of this embodiment.

  It is assumed that when the writing or reading operation is not performed, the control unit 21 detects that a defective block is generated and there is a normal area when divided (step 201). The control unit 21 extracts information on the head address of the area on which there is no abnormality, that is, the normal side, when the block in which the abnormality has occurred is divided into two. Next, the control unit 21 checks the secondary alternative area management table in order to determine whether an address that is not combined with other addresses among registered addresses is registered (step 202).

  If there is no address that is not combined with another (No in Step 203), the control unit 21 registers a new address in the secondary replacement block management table without combining with another address. If not combined with another address, the control unit 21 registers the newly registered address as the head address of the secondary alternative block (step 204). An address registered without being combined with another address is combined with an address on the usable side of a newly generated defective block when a new defective block is generated. If an address that is not combined with others is registered (Yes in Step 203), the control unit 21 registers a new address and an already registered address in combination (Step 205). The control unit 21 registers a new address in association with the address already registered as the head address of the secondary alternative block.

  In the semiconductor memory device of this embodiment, a defective block is divided into two and normal areas are combined and managed as a secondary replacement block in the secondary replacement area management table. If a defective block occurs when the number of replacement blocks reaches a predetermined number or less, the control unit determines whether or not the secondary replacement block can be used and, if it can be used, controls to use the secondary replacement block. It is carried out. When using the secondary substitute block, the control unit regards an area extending over a plurality of blocks as one continuous area, and writes and reads data. As described above, by using the secondary substitute block in which the normal areas are combined among the defective blocks, it is possible to reduce the number of normal substitute blocks made up of continuous areas. Therefore, it is possible to suppress the size of the spare storage area for forming the substitute block. Further, even if the number of alternative blocks decreases, it may be possible to continue the operation by using secondary alternative blocks. As described above, in the semiconductor memory device of this embodiment, it is possible to continue the operation even when many defective blocks occur while suppressing the size of the spare storage area.

  The third embodiment of the present invention will be described in detail. In the second embodiment, the semiconductor memory device performs the operation related to the formation of the secondary substitute block when data is not written or read. In the present embodiment, a secondary replacement block is formed and used as a recording area even during a data write operation.

  The configuration of the semiconductor memory device of this embodiment is the same as that of the second embodiment. Hereinafter, a data write operation in the semiconductor memory device of this embodiment will be described. Further, since the configuration is the same as that of the semiconductor memory device of the present embodiment, a description will be given with reference to FIG. 2 regarding the configuration of the semiconductor memory device of the second embodiment.

  FIG. 10 shows an outline of a flow when data is written in the semiconductor memory device of this embodiment. First, a write request, a write destination address, and write data are sent from the outside to the semiconductor memory device (step 141). The data sent to the semiconductor memory device is input to the buffer memory unit 22. When data is input to the buffer memory unit 22, the buffer memory unit 22 stores the input data (step 142).

  The control unit 21 refers to the bad block management table of the bad block management unit 23 and confirms whether the address designated as the data write destination is not included in the bad block management table (step 143). When the data write destination address is included in the bad block management table, the control unit 21 checks whether or not the secondary replacement block is used. When information using the secondary replacement block is registered, the control unit 21 checks the secondary replacement area management table and determines the address of the corresponding secondary replacement block as a data write destination. If the write destination address is registered in the bad block management table, but the information using the secondary substitute block is not registered, the control unit 21 determines the substitute block address as the write destination. . If the data write destination address is not included in the bad block management table, the control unit 21 determines the block in the normal storage area 11 whose address matches the write destination address as the write destination (step 144). ).

  When determining the data write destination, the control unit 21 checks whether the write destination block is a normal block or a bad block. Confirmation of the write destination block can be performed in the same manner as the data write in the second embodiment. When the write destination block is a normal block (No in step 145), the control unit 21 saves the data saved in the buffer memory unit 22 in the block determined as the write destination (step 146). Whether or not the block to be written to is normal is confirmed, for example, by applying a voltage to the source line shared for each page and applying the voltage normally. When previous data remains in the write destination block, the control unit 21 erases the data stored in the write destination block at a time before performing the write operation.

  If an abnormality has occurred in the write destination block (Yes in step 145), the control unit 21 adds the address of the defective block, which is the block in which the abnormality has occurred, to the defective block management table and stores it (step S1). 147). When storing the address of the defective block, the control unit 21 divides the defective block into two, and registers the address of the normal area in the secondary replacement area management table (step 148). When there is no normal area, the operation of registering in the secondary alternative area management table is not performed. If the secondary replacement block has already been used, only the normal side is registered again and the side on which an abnormality has occurred is deleted.

  When the normal area is registered in the secondary replacement area management table, the control unit 21 determines whether the number of used replacement blocks is equal to or less than a predetermined number. When the number of used alternative blocks is equal to or less than the predetermined number (Yes in step 149), the control unit 21 writes the data stored in the buffer memory unit 22 to the alternative block in the spare storage area 12. to decide. If it is determined that the data is to be written to the alternative block, the control unit 21 determines the address of the alternative block to be written from the available alternative blocks (step 150). When the address of the alternative block to be written is determined, the control unit 21 stores the determined alternative block address in the defective block management table in association with the address of the defective defective block (step 151). When the information on the replacement block to be used is stored in the bad block management table, the control unit 21 writes the data stored in the buffer memory unit 22 to the replacement block determined as the write destination (step 146).

  If the number of used replacement blocks is greater than the predetermined number (No in step 149), the control unit 21 determines whether the secondary replacement block can be used as the data write destination. The management table is confirmed (step 152). The control unit 21 checks the secondary replacement area management table to determine whether the secondary replacement block can be used. If there is no secondary substitute block that can be used (No in step 153), the control unit 21 determines the address of the write-in substitute block from the available substitute blocks (step 150). When the address of the alternative block to be written is determined, the control unit 21 stores the determined alternative block address in the defective block management table in association with the address of the defective defective block (step 151). When the information on the replacement block to be used is stored in the bad block management table, the control unit 21 writes the data stored in the buffer memory unit 22 to the replacement block determined as the write destination (step 146).

  If there is a usable secondary replacement block (Yes in step 153), the control unit 21 determines a secondary replacement block to be used for writing data from the secondary replacement area management table. When the secondary replacement block is determined, the control unit 21 stores the address of the head block of the secondary replacement block in the defective block management table in combination with the address specified in the data write request (step 154). . Further, the control unit 21 stores information indicating that the secondary replacement block is used in the bad block management table. When the secondary substitute block used for data writing is determined and stored, the control unit 21 writes the data in the buffer memory unit 22 to the selected secondary substitute block (step 146). The control unit 21 performs control so that after the data is written to one of the combined two blocks, the remaining data stored in the buffer memory unit 22 is written to the other block. . Thus, the data write operation to the memory unit 10 in the semiconductor memory device of this embodiment is completed.

  In the semiconductor memory device of this embodiment, the operation flow when reading data is the same as that of the second embodiment. In the semiconductor memory device of this embodiment, the operation flow when forming the secondary alternative block when data is not written or read is the same as that of the second embodiment.

  In the semiconductor memory device of the present embodiment, when a block abnormality is detected during data writing, the control unit forms a secondary replacement block in the write flow, and the secondary replacement block is satisfied when a predetermined condition is satisfied. It is controlled to write data to. In the present embodiment, the normal area of a block that was scheduled to be used for writing can also be used as a secondary substitute block, and therefore there is a high possibility that a usable secondary substitute block exists. For this reason, when a defective block occurs, the opportunity to reduce the number of normal replacement blocks used can be increased as compared to the second embodiment. Therefore, in the semiconductor memory device according to the present embodiment, the number of alternative blocks used can be more effectively suppressed, so that it is possible to further avoid the operation stop due to the shortage of alternative blocks.

  In the second embodiment and the third embodiment, the secondary replacement block is used when the remaining number of unused replacement blocks is equal to or less than a predetermined number. However, regardless of the remaining number of unused replacement blocks. A configuration using a secondary replacement block may also be used. When the secondary replacement block is used regardless of the remaining number of unused replacement blocks, when an abnormality occurs in the write destination block, the control unit checks whether there is a usable secondary replacement block. If there is a secondary replacement block that can be used, the control unit writes data to the secondary replacement block. By using the secondary replacement block regardless of the remaining number of unused replacement blocks, a decrease in the number of replacement blocks can be suppressed. As a result, it is possible to avoid the stoppage of the operation due to the shortage of alternative blocks.

  In the second embodiment and the third embodiment, the defective block is divided into two regions. However, the defective block may be divided into three or more regions. When dividing into three or more areas, the number of addresses corresponding to the number of divided blocks is managed in the secondary alternative area management table. When dividing into three or more areas, a plurality of normal areas from one defective block may be registered in the secondary replacement area management table. In the NAND flash memory, data is erased in units of blocks, so that when using a plurality of normal areas of one defective block, each area in one defective block is included in the same secondary replacement block. There is a need to.

  In the second and third embodiments, when one defective block is divided into a plurality of areas, the defective blocks are divided so that the storage capacity of each divided area is the same. It has been broken. Further, when forming the secondary substitute block, normal areas of defective blocks are combined so as to have the same storage capacity as that of one block. Instead of such a configuration, it is possible to configure a secondary replacement block by combining defective blocks without dividing the defective block. When combining the defective blocks without dividing them, the defective blocks are combined so that the total storage capacity of the normal areas of the defective blocks satisfies the storage capacity of one block to form a secondary replacement block. By adopting such a configuration, it is possible to form a secondary replacement block by a combination of a defective block having a large abnormality area and a small defective block. It is also possible to secure a storage capacity for one block by combining a plurality of defective blocks having a large abnormality area and a small normal area. If the defective block is not divided, the control of the formation of the secondary replacement block and the data writing may be complicated, but the secondary replacement block is formed by effectively utilizing the defective block having a large abnormality area. be able to. As a result, it is possible to suppress the decrease in the replacement block.

  In the third embodiment, when an abnormality is detected at the time of data writing, a secondary alternative block that has been combined in the writing operation is also used as a data writing destination candidate. Instead of such a configuration, when the amount of data stored in the buffer memory unit is detected and the capacity of the defective block is less than the normal area capacity, the normal area of the defective block is temporarily stored. It can also be configured to be used as a data write destination. With such a configuration, when a normal area of a defective block is used as a temporary write destination, a secondary replacement block is formed and a defective block is transferred to the defective block when a write operation is not performed. Allocation is done. After the substitute block is set, the temporarily stored data is transferred to the set substitute block. As described above, by temporarily suspending the process of setting a substitute block by using a normal area of a defective block according to the amount of data, it is possible to suppress a decrease in the processing speed at the time of writing.

  The present invention can be used as a technique for managing a storage area of a semiconductor memory device, and in particular, can be used for a semiconductor memory device using a NAND flash memory.

DESCRIPTION OF SYMBOLS 1 Memory | storage means 2 Address management means 3 Alternative block formation means 4 Control means 10 Memory part 11 Normal storage area 12 Spare storage area 21 Control part 22 Buffer memory part 23 Bad block management part 24 Secondary alternative area management part 101-113 Write step 121-133 Data read step 141-154 Data write step 201-204 Secondary alternative block formation step

Claims (8)

Storage means for storing data in a storage area divided into a plurality of blocks for each predetermined storage capacity;
Among the blocks, an address management means for managing a normal area address by dividing a defective block in which an abnormality has occurred into a plurality of areas;
An alternative block forming means for combining the addresses of normal areas of the defective blocks so as to satisfy the predetermined storage capacity and forming a second alternative block that is treated as one block;
Control means for writing data to a normal area of a block forming the second substitute block when a predetermined condition is satisfied ,
The storage means includes a predetermined number or percentage of the plurality of blocks as a first substitute block that is a spare block,
The control means writes data in at least one of the first alternative block and the second alternative block when a block other than the first alternative block cannot be used as a write destination. apparatus. Further comprising an abnormality detection means for detecting an abnormality of the block,
The control means writes data in at least one of the first alternative block or the second alternative block when the abnormality detection means detects an abnormality in a write destination block. The semiconductor memory device described in 1. The substitute block forming unit forms the second substitute block before the control unit writes data to the storage area when the abnormality detecting unit detects an abnormality. Item 3. The semiconductor memory device according to Item 2. 4. The semiconductor memory device according to claim 1, wherein the predetermined condition is that the number of unused blocks in the first alternative block is equal to or less than a predetermined number. Of the blocks of the storage area divided into a plurality of blocks for each predetermined storage capacity, manage the addresses of normal areas by dividing a defective block in which an abnormality has occurred into a plurality of areas,
A predetermined number or percentage of the plurality of blocks is a first substitute block that is a spare block,
Combining addresses of normal areas of the defective blocks so as to satisfy the predetermined storage capacity to form a second alternative block that is treated as one block,
When a block other than the first substitute block cannot be used as a write destination, data is written to at least one of the first substitute block or the second substitute block;
A method for controlling a semiconductor memory device, wherein data is written to a normal area of a block forming the second substitute block when a predetermined condition is satisfied. Detecting an abnormality of the block,
6. The method of controlling a semiconductor memory device according to claim 5, wherein when an abnormality in a write destination block is detected, data is written to at least one of the first substitute block or the second substitute block. 7. The method of controlling a semiconductor memory device according to claim 6, wherein when the abnormality is detected, the second alternative block is formed before data is written to the storage area. 8. The method of controlling a semiconductor memory device according to claim 5, wherein the predetermined condition is that the number of unused blocks in the first alternative block is equal to or less than a predetermined number.

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