JP6252015B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  With the recent progress of broadband, the demand for high-capacity high-speed wireless communication is increasing. In order to increase the capacity, the third generation of mobile phone base station amplifiers will spread, and it will be further developed to the fourth generation in the future. Also, a new communication system such as LTE (Long Term Evolution) has been put into practical use, and it is expected that the capacity will further increase in the future. Therefore, further higher output, higher efficiency, smaller size, and lower cost are required. On the other hand, radar transmission / reception modules are required to have higher output and wider bandwidth for higher performance such as increased detection distance and improved resolution, and further to reduce operational costs and downsize coolers. High efficiency is required. As a semiconductor device used for such a purpose, there is a transistor having a comb gate structure.

Japanese Patent Laid-Open No. 56-6476 JP-A 61-172376 JP-A-8-172104 JP 2003-318319 A

  By the way, the comb-shaped gate structure has a structure in which gate fingers to be a plurality of gate electrodes are provided in portions corresponding to teeth of the comb-shaped gate structure, and each gate finger is connected to the gate wiring portion. is there. Further, it is connected to the gate terminal portion at the central portion of the gate wiring portion, and a gate voltage is applied from the gate terminal portion. In such a comb-shaped gate structure, the phase difference is large because the wiring length between the gate finger connected at the central portion of the gate wiring portion and the gate finger connected at the end of the gate wiring portion is different, The characteristics at high frequencies are degraded.

  Therefore, there is a demand for a transistor having good characteristics at high frequencies among transistors having a comb gate structure.

According to one aspect of the present embodiment, a plurality of gate fingers elongated from one end to the other end, a gate wiring portion connected to the one end of the gate finger, and the gate A gate terminal connected to the central portion of the wiring portion to which a gate voltage is supplied, a plurality of source fingers formed elongated from one end toward the other end, and the one end of the source finger A source wiring portion to be connected; a plurality of drain fingers formed elongated from one end toward the other end; and a drain wiring portion connected to the one end of the drain finger, The gate finger is formed between the source finger and the drain finger, and the gate finger extends from the one end of the source finger. A direction toward one end of the drain finger and a direction from the one end toward the other end of the drain finger are opposite directions, and the gate wiring portion includes a wiring width inclined region in the vicinity of the gate terminal portion and A narrow wiring region having a constant wiring width, and the wiring width inclined region has a width in a direction connecting the one end of the gate finger to the other end of the gate terminal portion. It is widest in the vicinity and gradually becomes narrower as it moves away from the gate terminal portion. In the gate wiring portion, the wiring width of the narrow wiring region is the narrowest, and the narrow wiring region and the source the source connection wiring portion is connected to the wiring portion is overlapped in a top view, the source wiring portion is provided between the drain wiring portion and the gate wiring part, the source The source terminal portion connected to the source voltage to the scan connecting wiring part is supplied are provided, the source terminal portion, characterized in that provided in the gate terminal portion side of the source wiring portion .

  According to the disclosed semiconductor device, high-frequency characteristics can be improved in a comb-gate transistor.

Structure diagram of semiconductor device with comb-shaped gate structure Structure diagram of the semiconductor device in the first embodiment Sectional drawing of the semiconductor device in 1st Embodiment Correlation diagram between frequency and maximum gain in semiconductor devices Electrical characteristics diagram of semiconductor device having structure shown in FIG. Electrical characteristics diagram of semiconductor device in first embodiment Structural diagram of the semiconductor device according to the first embodiment provided with a plurality of transistors Structure diagram of semiconductor device according to second embodiment Sectional drawing of the semiconductor device in 2nd Embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
First, a transistor having a comb gate structure will be described. As shown in FIG. 1, a transistor having a comb gate structure is provided with a plurality of gate fingers 911 and the like that are a plurality of gate electrodes that are elongated from one end to the other end. One end of each gate finger 911 is connected to the gate wiring portion 912, and the gate wiring portion 912 is connected to the gate terminal portion 913 at the central portion of the gate wiring portion 912, and the gate terminal portion 913 receives the gate. A voltage is applied.

  In such a comb gate transistor, the source electrode and the drain electrode are usually formed in a comb shape. Specifically, the plurality of source electrodes 921 serving as source fingers are formed to be elongated from one end to the other end, and one end of the plurality of source electrodes 921 is connected to the source terminal portion 922. ing. The source terminal portion 922 is grounded via the via hole 923. Similarly, the plurality of drain electrodes 931 serving as drain fingers are formed to be elongated from one end to the other end, and one end of the plurality of drain electrodes 931 is connected to the drain wiring portion 932. . The drain wiring portion 932 is connected to the drain terminal portion 933 at the central portion of the drain wiring portion 932, and a drain voltage is applied through the drain terminal portion 933.

  In the transistor having a comb-shaped gate structure, the gate finger 911, the source electrode 921, and the drain electrode 931 are formed so that their extending directions are parallel, that is, the longitudinal direction is parallel. In addition, one gate finger 911 is formed between the source electrode 921 and the drain electrode 931.

  Here, in the case of a semiconductor device corresponding to a high voltage, if a wiring reaching the source electrode 921 is formed on a wiring reaching the drain electrode 931, an interlayer insulating film formed between the wirings is formed. If the thickness is not sufficient, it is influenced by each other and loss occurs, which is not preferable. For this reason, in the semiconductor device corresponding to the high voltage, as shown in FIG. 1, the positions of the source terminal portion 922 and the drain wiring portion 932 are opposite to each other around the source electrode 921 and the drain electrode 931. The formed structure is preferred.

  That is, a structure in which the direction from one end to the other end of the source electrode 921 and the direction from one end to the other end of the drain electrode 931 are opposite to each other is preferable.

  In this manner, by forming the source terminal portion 922 and the drain wiring portion 932 so as to be opposite to each other, the wiring reaching the source electrode 921 is formed on the wiring reaching the drain electrode 931. Therefore, loss can be prevented from occurring. The above-described problem can be solved by increasing the thickness of the interlayer insulating film, but in this case, it takes time to form the interlayer insulating film, leading to an increase in cost. Further, when the interlayer insulating film is thick, there is a problem that disconnection or the like is likely to occur in the formed wiring, which is not preferable.

  In the transistor having the structure shown in FIG. 1, the gate finger 911α and the gate finger 911β have different wiring lengths from the gate terminal portion 913 because the positions connected to the gate wiring portion 912 are different. For this reason, a phase difference is generated between the gate finger 911α and the gate finger 911β, and the characteristics at high frequencies are deteriorated.

(Semiconductor device)
Next, a transistor which is a semiconductor device in this embodiment will be described with reference to FIGS. The semiconductor device 10 in this embodiment is a comb-gate transistor. 3A is a cross-sectional view taken along the alternate long and short dash line 2A-2B in FIG. 2, and FIG. 3B is a cross-sectional view taken along the alternate long and short dash line 2C-2D in FIG. (C) is sectional drawing cut | disconnected in the dashed-dotted line 2E-2F in FIG.

  Specifically, the transistor in this embodiment includes a gate finger 111 serving as a plurality of gate electrodes, a source electrode 121 serving as a plurality of source fingers, and a drain electrode 131 serving as a plurality of drain fingers on the semiconductor substrate 100. Is formed. Note that an electron transit layer 101, an electron supply layer 102, and the like are formed of a nitride semiconductor on the semiconductor substrate 100, thereby forming a semiconductor circuit. The gate finger 111, the source electrode 121, and the drain electrode 131 are formed on the electron supply layer 102 thus formed. In the present embodiment, a SiC substrate, a GaN substrate, or the like is used as the semiconductor substrate 100, the electron transit layer 101 is formed of GaN or the like, and the electron supply layer 102 is formed of AlGaN or the like. .

  In addition, an insulating film 140 serving as an interlayer insulating film is formed on the semiconductor substrate 100, the gate finger 111, the source electrode 121, and the drain electrode 131 using a resin material such as silicon nitride or polyimide.

  As shown in FIG. 2, each gate finger 111 to be a plurality of gate electrodes is elongated from one end 111a to the other end 111b, and one end 111a of the gate finger 111 is a gate It is connected to the wiring part 112. The gate wiring portion 112 is connected to the gate terminal portion 113 at the central portion of the gate wiring portion 112, and a gate voltage is applied from the gate terminal portion 113.

  The plurality of source electrodes 121 are elongated from one end 121 a to the other end 121 b, and one end 121 a of the source electrode 121 is connected to the source wiring portion 122. The source wiring portion 122 is connected to the source terminal portion 124 via the source connection wiring portion 123 in the vicinity of the end portion of the source wiring portion 122, and the source terminal portion 124 is grounded via the via hole 125. Similarly, the plurality of drain electrodes 131 are elongated from one end 131a to the other end 131b, and one end 131a of the drain electrode 131 is connected to the drain wiring portion 132. The drain wiring portion 132 is connected to the drain terminal portion 133 at the center portion, and a drain voltage is applied through the drain terminal portion 133.

  In the present embodiment, the gate finger 111, the source electrode 121, and the drain electrode 131 are formed so that the extending directions are parallel, that is, the longitudinal direction is parallel. One gate finger 111 is formed between the source electrode 121 and the drain electrode 131.

  In the present embodiment, as shown in FIG. 2, the source wiring part 122 and the drain wiring part 132 are formed so as to be opposite to each other with the source electrode 121 and the drain electrode 131 as the center. That is, the source electrode 121 is formed so that the direction from one end 121a to the other end 121b and the direction from the one end 131a to the other end 131b in the drain electrode 131 are opposite to each other. Further, the gate wiring part 112 and the drain wiring part 132 are formed so as to be opposite to each other with the gate finger 111 and the drain electrode 131 as the center. That is, the direction from the one end 111a to the other end 111b in the gate finger 111 and the direction from the one end 131a to the other end 131b in the drain electrode 131 are opposite to each other. In this embodiment, the gate finger 111 has a width of about 0.25 μm and a length of about 100 μm, the source electrode 121 has a width of about 20 μm and a length of about 70 μm, and the drain electrode 131. Has a width of about 20 μm and a length of about 100 μm.

  In the present embodiment, as shown in FIG. 3B, the source wiring portion 122 is formed on the insulating film 140 so as to cross over the gate finger 111 and the drain electrode 131. As shown in FIG. 3C, a part of the source connection wiring portion 123 that connects the source wiring portion 122 and the source terminal portion 124 crosses over the narrow wiring region 112 b in the gate wiring portion 112. And formed on the insulating film 140.

  In the present embodiment, the gate wiring portion 112 has a wiring width inclined region 112a and a narrow wiring region 112b formed with a constant wiring width. Specifically, in the gate wiring portion 112, a wiring width inclined region 112a is formed in the vicinity of the gate terminal portion 113, and a constant wiring width region 112b is formed in a region away from the gate terminal portion 113. The wiring width inclined region 112a is formed to be the widest in the vicinity of the gate terminal portion 113, and is formed so that the width gradually decreases as the distance from the gate terminal portion 113 increases. The constant wiring width region 112b is connected to the narrowest portion of the wiring width inclined region 112a. As described above, by forming the wiring width inclined region 112a in the gate wiring portion 112, the resistance in the wiring width inclined region 112a can be lowered, so that the characteristics at high frequency can be improved.

(Characteristics of semiconductor devices)
Next, characteristics measured in the semiconductor device in this embodiment and the semiconductor device having the structure shown in FIG. 1 will be described. FIG. 4 shows the frequency dependence of the maximum gain in the semiconductor device. Characteristic 4A shows the frequency characteristic of the maximum gain of the semiconductor device in this embodiment, and characteristic 4B shows the semiconductor device having the structure shown in FIG. The frequency characteristics of maximum gain are shown. As shown by the characteristic 4B, in the semiconductor device having the structure shown in FIG. 1, the frequency at which the maximum gain is 0 dB is 31.4 GHz. On the other hand, as shown in characteristic 4A, in the semiconductor device in the present embodiment, the frequency at which the maximum gain is 0 dB is 41.4 GHz. Thus, in the semiconductor device according to the present embodiment, the frequency at which the maximum gain becomes 0 dB can be improved by about 1.3 times as compared with the semiconductor device having the structure shown in FIG.

  Next, FIG. 5 shows results of measuring output power, gain, PAE (power efficiency), and drain efficiency in the semiconductor device having the structure shown in FIG. 1. In the semiconductor device in this embodiment, output power, gain, The results of measuring PAE and drain efficiency are shown in FIG.

In the semiconductor device having the structure shown in FIG. 1, the output power is 36 dBm and the PAE is 48.5% at 26.5 dBm where the input power is maximum in FIG. On the other hand, in the semiconductor device according to the present embodiment, the output power was 36.5 dBm and the PAE was 50.5% at 25.5 dBm where the input power was maximum in FIG. Therefore, the semiconductor device in this embodiment can improve the output power by 0.5 dBm (about 10%) and improve the PAE by 2% compared to the semiconductor device having the structure shown in FIG. it can.

  As described above, the semiconductor device in this embodiment can have higher frequency, higher output, and higher efficiency than the semiconductor device having the structure illustrated in FIG.

  The present embodiment may have a structure in which a plurality of semiconductor devices 10 having the structure shown in FIG. 2 are connected. For example, as shown in FIG. 7, two or more semiconductor devices 10 having the structure shown in FIG. 2 are formed, the gate wiring portions 112 in each semiconductor device 10 are connected, and the source wiring portions 122 are connected. It may be. As a result, the output can be further increased.

  The semiconductor device in this embodiment can also be used for a high-power monolithic integrated circuit (MMIC). Specifically, a semiconductor device according to the present embodiment and electronic elements (passive elements, etc.) such as capacitors and resistors are formed on a semiconductor substrate, and these are connected by wiring to form a high output monolithic integrated circuit. can do. The high-power monolithic integrated circuit formed as described above has higher output and higher efficiency than the conventional one.

[Second Embodiment]
Next, a second embodiment will be described. In this embodiment, a part of the wiring has an air bridge structure without forming the insulating film 140 to be an interlayer insulating film. Even with the semiconductor device having such a structure, it is possible to obtain the same effect as that of the semiconductor device according to the first embodiment.

  A transistor which is a semiconductor device in this embodiment will be described with reference to FIGS. 9A is a cross-sectional view taken along the alternate long and short dash line 8A-8B in FIG. 8, and FIG. 9B is a cross-sectional view taken along the alternate long and short dash line 8C-8D in FIG. (C) is sectional drawing cut | disconnected by the dashed-dotted line 8E-8F in FIG.

  In the present embodiment, as shown in FIG. 9A, a gate finger 111, a source electrode 121, and a drain electrode 131 that are a plurality of gate electrodes are formed on a semiconductor substrate 100. As shown in FIG. 9B, the source wiring part 122 is formed by an air bridge structure above the gate finger 111 and the drain electrode 131 so as to cross over the gate finger 111 and the drain electrode 131. As shown in FIG. 9C, a part of the source connection wiring portion 123 that connects the source wiring portion 122 and the source terminal portion 124 crosses over the narrow wiring region 112b in the gate wiring portion 112. An air bridge structure is formed above the gate wiring portion 112.

  The contents other than the above are the same as in the first embodiment.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A plurality of gate fingers formed elongated from one end to the other end;
A gate wiring portion connected to one end of the gate finger;
A gate terminal to which a gate voltage connected to a central portion of the gate wiring portion is supplied;
A plurality of source fingers formed elongated from one end toward the other end;
A source wiring portion connected to one end of the source finger;
A plurality of drain fingers formed elongated from one end to the other end;
A drain wiring portion connected to one end of the drain finger;
Have
The gate finger is formed between the source finger and the drain finger;
The direction from one end to the other end of the source finger and the direction from one end to the other end of the drain finger are opposite directions,
The semiconductor device according to claim 1, wherein the gate wiring portion has a wiring width inclined region that is widest in the vicinity of the gate terminal portion and gradually decreases as the distance from the gate terminal portion increases.
(Appendix 2)
The semiconductor device according to appendix 1, wherein a direction from one end to the other end of the gate finger and a direction from one end to the other end of the drain finger are opposite directions.
(Appendix 3)
An insulating film is formed on the gate finger,
3. The semiconductor device according to appendix 1 or 2, wherein the source wiring portion is formed above the gate finger through the insulating film.
(Appendix 4)
The source wiring portion is formed above the gate finger,
The semiconductor device according to appendix 1 or 2, wherein the gate finger and the source wiring portion are spatially separated.
(Appendix 5)
The gate wiring portion has a narrow wiring region,
The narrow wiring region is connected at a portion farthest from the gate terminal portion in the wiring width inclined region,
The insulating film is formed on the narrow wiring region in the gate wiring portion,
The source connection wiring portion for connecting the grounded source terminal portion and the source wiring portion to each other is formed above the narrow wiring region via the insulating film. Semiconductor device.
(Appendix 6)
The gate wiring portion has a narrow wiring region,
The narrow wiring region is connected at a portion farthest from the gate terminal portion in the wiring width inclined region,
Above the narrow wiring region in the gate wiring portion, a source connection wiring portion that connects the grounded source terminal portion and the source wiring portion is formed,
The semiconductor device according to appendix 4, wherein the source connection wiring portion and the narrow wiring region in the gate wiring portion are spatially separated.
(Appendix 7)
The gate finger, the gate wiring part, the gate terminal part, the source finger, the source wiring part, the drain finger and the drain wiring part are formed on a semiconductor layer formed on a substrate. There,
The semiconductor device according to any one of appendices 1 to 6, wherein the semiconductor layer is made of a material including a nitride semiconductor.
(Appendix 8)
8. The semiconductor device according to any one of appendices 1 to 7, wherein an electronic element is formed on the substrate.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 100 Semiconductor substrate 101 Electron travel layer 102 Electron supply layer 111 Gate finger (gate electrode)
112 Gate wiring portion 112a Wiring width inclined region 112b Narrow wiring region 113 Gate terminal portion 121 Source electrode (source finger)
122 Source wiring portion 123 Source connection wiring portion 124 Source terminal portion 125 Via hole 131 Drain electrode (drain finger)
132 Drain wiring portion 133 Drain terminal portion 140 Insulating film

Claims (5)

A plurality of gate fingers formed elongated from one end to the other end;
A gate wiring portion connected to the one end of the gate finger;
A gate terminal to which a gate voltage connected to a central portion of the gate wiring portion is supplied;
A plurality of source fingers formed elongated from one end toward the other end;
A source wiring portion connected to the one end of the source finger;
A plurality of drain fingers formed elongated from one end to the other end;
A drain wiring portion connected to the one end of the drain finger;
Have
The gate finger is formed between the source finger and the drain finger;
The direction from the one end of the source finger toward the other end and the direction from the one end of the drain finger toward the other end are opposite directions,
The gate wiring portion is formed by a wiring width inclined region in the vicinity of the gate terminal portion and a narrow wiring region having a constant wiring width,
The wiring width inclined region is widest in the direction connecting the one end of the gate finger to the other end in the vicinity of the gate terminal portion, and gradually becomes narrower as the gate terminal portion moves away. And
In the gate wiring portion, the wiring width of the narrow wiring area is the narrowest,
The narrow wiring region and the source connection wiring part connected to the source wiring part overlap in a top view,
The source wiring portion is provided between the gate wiring portion and the drain wiring portion ,
A source terminal portion to which a source voltage connected to the source connection wiring portion is supplied is provided,
The semiconductor device, wherein the source terminal portion is provided closer to the gate terminal portion than the source wiring portion . A direction toward the other end from the one end of the gate fingers, a direction toward the other end from the one end of the drain finger, according to claim 1, characterized in that in the opposite direction Semiconductor device. Wherein between the narrow wiring region and the source connection wiring portion, the semiconductor device according to claim 1 or 2, wherein an insulating film is formed. An insulating film is formed on the gate finger,
Wherein the above said gate fingers through the insulating film, a semiconductor device according to any one of claims 1 to 3, characterized in that the source wiring portion is formed. The source wiring portion is formed above the gate finger,
Wherein the gate fingers and the source wiring portion, the semiconductor device according to claim 1 or 2, characterized in that spatially separated.

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