JP6257378B2 - Spread spectrum receiver - Google Patents

Description

  The present invention relates to a spread spectrum receiver and a spread spectrum transmitter.

  Spread spectrum communication is a method of transmitting a transmission signal having a certain bandwidth by spreading it over a wider bandwidth. Spread spectrum communication has been widely studied from the advantages of being able to reduce the amount of interference given to other systems, having strong interference resistance, and being strong against fading of radio propagation paths.

  The direct spreading method, which is a kind of spread spectrum communication, obtains a spread spectrum signal by multiplying a transmission signal by a wide band spreading code. In a direct spread system receiver, a despreading process is performed on the received signal by the complex conjugate of the spreading code multiplied by the transmitter, and the signal spread over a wide band is returned to the original narrowband signal and then predetermined. Is demodulated. In the despreading process, it is necessary to multiply the spreading code held in the receiver in synchronization with the spreading code included in the received signal. Therefore, the receiver needs to perform initial acquisition for detecting the leading timing of the spread code from the received signal. In general, a sequence having good autocorrelation characteristics such as a PN (Pseudorandom Noise) sequence is used as a spreading code. Utilizing this fact, the initial acquisition can be realized by performing a correlation operation between the received signal and the spreading code held in the receiver and detecting the peak.

  For example, when FSK (Frequency Shift Keying) is used as the primary modulation in spread spectrum communication, the primary modulation signal waveform generally varies within one symbol. Therefore, the transmitter transmits a spread signal whose primary modulation signal is known in advance to the receiver, and the receiver performs a correlation operation between the held replica of the known spread signal and the received signal, and performs peak calculation. Initial capture is performed by detecting. The technique of the initial acquisition method using such a known signal is disclosed in Patent Document 1 below, for example.

Japanese Patent No. 2689890

  However, according to the above conventional technique, it is necessary to transmit a known signal, and user information cannot be transmitted in the known signal portion. Therefore, there has been a problem that communication efficiency is significantly impaired.

  In general, a receiver needs to estimate and correct a frequency offset existing between a transmitter and a receiver in addition to an initial acquisition process as a synchronization process. In the above conventional technique, although improvement of initial acquisition performance in an environment where a frequency offset exists is mentioned, no estimation and correction of frequency offset are disclosed. That is, in the receiver, after the initial acquisition is established, it is necessary to pull in the frequency offset using another means, and there is a problem that the apparatus scale and the processing delay increase.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a spread spectrum receiver and a spread spectrum transmitter that can realize high-speed synchronization processing without impairing communication efficiency.

In order to solve the above-described problems and achieve the object, the present invention spreads a modulated signal from a spread spectrum transmitter to a modulated signal having the same period and a different repetitive pattern for each transmission information regardless of transmission information. When receiving a signal multiplied by a code, a spread code multiplying means for multiplying the received signal from the spread spectrum transmitter by the complex conjugate of the spread code, and a signal after multiplying the complex conjugate of the spread code A phase difference calculating means for calculating a phase difference between chips at a symbol interval defined within one symbol, an addition processing means for adding the phase difference between the chips, and a power value from the phase difference between the chips after the addition. Power calculating means for calculating the power value, determination means for determining spreading code synchronization based on the power value input from the power calculating means and information on the chip number corresponding to the power value, Based on the determination result by the constant means and the phase difference between the chip, characterized in that it comprises a frequency calculating means for calculating a frequency offset, a.

  According to the present invention, there is an effect that synchronization processing can be realized at high speed without impairing communication efficiency.

FIG. 1 is a diagram illustrating a configuration example of a spread spectrum transmitter according to the first embodiment. FIG. 2 is a diagram illustrating a signal spectrum image output from the modulation unit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of the spread spectrum receiver according to the first embodiment. FIG. 4 is a diagram illustrating a configuration example of the initial capturing unit according to the first embodiment. FIG. 5 is a diagram illustrating a configuration example of the spreading code multiplication unit according to the first embodiment. FIG. 6 is a diagram illustrating a signal waveform of one symbol time when the FSK subcarrier arrangement according to the first embodiment is used. FIG. 7 is a diagram illustrating a signal spectrum image output from the modulation unit according to the second embodiment. FIG. 8 is a diagram illustrating a configuration example of the initial capturing unit according to the second embodiment. FIG. 9 is a diagram illustrating a signal waveform of one symbol time when the FSK subcarrier arrangement according to the second embodiment is used.

  Embodiments of a spread spectrum receiver and a spread spectrum transmitter according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
First, the configuration and operation of the spread spectrum transmitter will be described. FIG. 1 is a diagram illustrating a configuration example of a spread spectrum transmitter according to the present embodiment. The spread spectrum transmitter includes a modulator 10, a spreader 11, a spread code generator 12, a D / A (Digital to Analog) converter 13, a high frequency processor 14, and a transmission antenna 15. The overall operation of the spread spectrum transmitter will be described along with the description of each configuration. In the present embodiment, the spread spectrum transmitter uses FSK (Frequency Shift Keying) that transmits information by changing the frequency of a signal as primary modulation.

  The modulation unit 10 selects a signal frequency according to the information bits and outputs a corresponding complex sine wave signal to the spreading unit 11. FIG. 2 is a diagram illustrating a signal spectrum image output from the modulation unit 10 according to the present embodiment. In the example of FIG. 2, a state where eight subcarriers are defined on the frequency axis is shown. The subcarriers 20 to 23 indicate four subcarriers (hereinafter referred to as FSK subcarriers 20 to 23) that can be selected by the modulation unit 10, and the subcarriers 24 to 27 are remaining that cannot be selected by the modulation unit 10. 4 subcarriers are shown.

  Here, the four FSK subcarriers 20 to 23 are defined at regular intervals in the eight subcarriers. That is, an FSK subcarrier is defined every other subcarrier. Since one is selected from the four FSK subcarriers 20 to 23, two bits can be transmitted simultaneously. In the modulation unit 10, for example, when transmitting information bits “0, 0”, the FSK subcarrier 20 is transmitted. When transmitting information bits “0, 1”, the FSK subcarrier 21 is transmitted, and information bits “1, 0” are transmitted. FSK subcarrier 22 is transmitted when transmitting information bits, and FSK subcarrier 23 is selected when transmitting information bits “1, 1”, and a complex sine wave corresponding to the selected FSK subcarrier is output to spreading section 11. To do.

  The spreader 11 multiplies the complex sine wave input from the modulator 10 by the spread code input from the spread code generator 12 and outputs the result to the D / A converter 13.

  The D / A conversion unit 13 converts the input signal into an analog signal and then outputs the analog signal to the high frequency processing unit 14.

  The high frequency processing unit 14 up-converts the input signal to a high frequency and then transmits it from the transmission antenna 15.

  Next, the configuration and operation of the spread spectrum receiver will be described. FIG. 3 is a diagram illustrating a configuration example of the spread spectrum receiver according to the present embodiment. The spread spectrum receiver includes a reception antenna 30, a high frequency processing unit 31, an A / D conversion processing unit 32, a reception filter 33, an initial acquisition unit 34, a despreading processing unit 35, a demodulation unit 36, and a control. Unit 37. The overall operation of the spread spectrum receiver will be described together with the description of each configuration.

  When the signal transmitted from the spread spectrum transmitter is received by the receiving antenna 30, the high frequency processing unit 31 down-converts the received signal, and the A / D conversion processing unit 32 converts the down-converted received signal into a received digital signal. Convert.

  The reception filter 33 performs a filtering process on the received digital signal, and passes the received digital signal after the filtering process to the initial capturing unit 34 and the despreading processing unit 35.

  When the spread spectrum receiver is in an asynchronous state, the initial acquisition unit 34 estimates a spread code timing and a frequency offset using synchronization processing described later, and notifies the control unit 37 of the estimation result.

  The control unit 37 instructs the despreading processing unit 35 to multiply the received digital signal after filter processing by the complex conjugate of the spreading code using the spreading code timing received from the initial capturing unit 34. . Further, the control unit 37 corrects the frequency offset of the spread spectrum receiver based on the estimated value of the frequency offset received from the initial acquisition unit 34.

  The despreading processing unit 35 uses the spread code timing notified from the control unit 37 and applies the spread code of the spread spectrum transmitter (see FIG. 1) to the received digital signal after the filter processing received from the reception filter 33. The spreading code generated by the generation unit 12 is multiplied by a code having a complex conjugate relationship.

  The demodulator 36 performs a process for determining a transmission signal on the despread signal received from the despread processor 35 to restore the information data.

  Next, the configuration and operation of the initial capturing unit 34 that performs characteristic operations in the present embodiment will be described in detail. FIG. 4 is a diagram illustrating a configuration example of the initial capturing unit 34 according to the present embodiment. The initial acquisition unit 34 includes a spread code multiplication unit 40, a spread code generation unit 41, a phase difference calculation unit 42, an addition processing unit 43, an averaging processing unit 44, a power calculation unit 45, and a determination unit 46. And a frequency calculation unit 47.

  The spread code multiplying unit 40 receives the received digital signal after the filter process passed from the reception filter 33 in the preceding stage of the initial capturing unit 34 and the spread code passed from the spread code generating unit 41. The spread code multiplication unit 40 multiplies the received digital signal after the filter processing by the complex conjugate of the spread code, and passes the multiplication result to the phase difference calculation unit 42. The spread code multiplication unit 40 can be configured using, for example, a shift register and a multiplier shown in FIG. FIG. 5 is a diagram illustrating a configuration example of the spread code multiplication unit 40 of the present embodiment. FIG. 5 illustrates a case where one symbol is spread using a spreading code having a spreading code length of 8. In FIG. 5, delay elements 50 to 57 are one-chip-length delay elements, and spreading codes c0 to c7 indicate spreading codes input from the spreading code generation unit 41.

In the spread code multiplying unit 40, the received digital signal after filtering input from the receiving filter 33 is input to the delay element 50, and the output of each multiplier is transferred to the phase difference calculating unit 42 in the subsequent stage. For each input from the reception filter 33, the spread code multiplier 40 multiplies the received digital signal after the filter processing by the complex conjugate of the spread codes c0 ^{* to} c7 ^* , and the multiplication results a0 to a7 to the phase difference calculator 42. Deliver.

  The spreading code generation unit 41 generates a code having a complex conjugate relationship with a spreading code in which eight chips generated by the spreading code generation unit 12 are one cycle, and outputs the code to the spreading code multiplication unit 40.

  The phase difference calculator 42 calculates a phase difference between predetermined chips in the symbol for the signal after spreading code multiplication passed from the spreading code multiplier 40, and outputs it to the addition processor 43.

  FIG. 6 is a diagram illustrating a signal waveform of one symbol time when the FSK subcarrier arrangement according to the present embodiment is used. This corresponds to the FSK subcarrier arrangement shown in FIG. In FIG. 6, signal waveforms 60 to 63 are signal waveforms of one symbol time when information bits “0, 0”, “0, 1”, “1, 0”, and “1, 1” are transmitted, respectively. . Note that the signal waveform output from the modulation unit 10 is a complex sine wave and has both an in-phase component and a quadrature component, but FIG. 6 shows only the in-phase component as a representative example. As can be seen from FIG. 6, the complex sine wave generated by the modulation unit 10 indicates that the first half of the symbol and the second half of the symbol have the same waveform, that is, the same waveform at 0.5 symbol intervals regardless of the information bits. ing.

Using this, the phase difference calculation unit 42 calculates a phase difference between chips at an interval of 0.5 symbols with respect to the input signal after multiplication by the spread code, and outputs it to the subsequent addition processing unit 43. To do. Specifically, the phase difference calculation unit 42 calculates “b0 = a4 × a0 ^* ” and “b1 = a5 × a1” with respect to the multiplication results a0 to a7 passed from the spread code multiplication unit 40 as the phase difference calculation. ^* "," B2 = a6 * a2 ^* ", and" b3 = a7 * a3 ^* ". “ ^* ” Represents a complex conjugate.

  The addition processing unit 43 adds all the phase differences b0 to b3 input from the phase difference calculation unit 42 as “d = b0 + b1 + b2 + b3”, and then outputs the addition result d to the averaging processing unit 44.

  The averaging processing unit 44 performs a process of averaging the addition result d input from the addition processing unit 43 among a plurality of symbols. In this process, for example, a memory capable of holding data for 8 chips is prepared in the averaging processing unit 44, and the storage content of the memory is determined between the input addition result d and the signal held in the memory. This can be achieved by updating with the averaged result. The memory address may be incremented each time the input signal is switched, and the memory may be circulated so as to return to the head address after the last 8-chip address.

  The power calculation unit 45 updates the averaging result held in the memory of the averaging processing unit 44 by one symbol period, that is, the data held in the memory for 8 chips included in the averaging processing unit 44 is updated equally. Every time it is read, each power value is calculated and compared in magnitude. The power calculation unit 45 detects the maximum power value and passes the value (maximum power value) and the chip number to the determination unit 46.

  The determination unit 46 compares the maximum power value input from the power calculation unit 45 and the chip number taking the maximum power value with a threshold value for determining completion of initial acquisition with respect to spreading code synchronization. It is determined whether or not As a threshold determination method, for example, a threshold value α for the maximum power value and a threshold value β for the number of continuous detections are prepared, and the maximum power value satisfies the threshold value α and the chip number satisfying α. Can be used when the initial acquisition is determined to be complete when β is the same for β consecutive times. The determination unit 46 outputs a threshold determination result and a chip number that takes the maximum power value.

  Similar to the power calculation unit 45, the frequency calculation unit 47 reads all the averaging results held in the memory of the averaging processing unit 44 in one symbol period. When the frequency calculation unit 47 refers to the threshold determination result input from the determination unit 46 and receives a signal that the threshold is satisfied, the frequency calculation unit 47 inputs the threshold determination result from the determination unit 46. The averaged result stored at the address equal to the chip number is taken out.

  Next, the frequency calculation unit 47 calculates a frequency offset using the obtained averaged result. The averaged result corresponds to the averaged phase difference of 0.5 symbol intervals calculated by the phase difference calculating unit 42. Deriving the frequency from the averaged result (phase difference) using these pieces of information can be easily realized by those skilled in the art. The frequency calculation unit 47 finally outputs the calculated frequency offset. When the threshold determination result input from the determination unit 46 indicates that the threshold is not satisfied, the frequency calculation unit 47 does not perform any particular processing, and outputs, for example, zero as the frequency. The predetermined initial state is retained.

  Upon receiving a notification that the threshold value is satisfied from the initial capturing unit 34, the control unit 37 generates spreading code timing for use in the despreading processing unit 35 from the information of the chip number notified at the same time. Notify the diffusion processing unit 35. Moreover, the control part 37 performs the process which draws in a frequency offset based on the calculation result of a frequency offset.

  As described above, in the present embodiment, in the spread spectrum transmitter, modulation section 10 defines FSK subcarriers so that the first half and the second half of one symbol show the same waveform regardless of the value of information bits. As a result, a modulated signal having periodicity with a period of 0.5 symbol intervals and a different repetition pattern for each information bit is generated and output. Further, the initial acquisition unit 34 of the spread spectrum receiver is configured to calculate the phase difference between the first half and the second half in one symbol using the above-described characteristics of the transmission waveform, and to combine and average the result. Thus, in the spread spectrum receiver, when the timing at which the spreading code multiplication unit 40 multiplies the spreading code coincides with the spreading code timing in the received signal, the signal level of the averaging processing result of the timing in the averaging processing unit 44 Becomes larger than other timings. This can be used to complete the initial acquisition without using a known signal. Further, the spread spectrum receiver can calculate the frequency offset from the averaging process result corresponding to the timing when the initial acquisition is completed. As a result, it is possible to perform spread spectrum communication between the spread spectrum transmitter and the spread spectrum receiver to complete the synchronization processing (initial acquisition / frequency offset estimation) at high speed without impairing communication efficiency.

  In the present embodiment, the phase difference calculation unit 42 calculates the phase difference between chips at intervals of 0.5 symbols. However, the present invention is not limited to this, and the phase difference is calculated at different symbol intervals. You may comprise. For example, when the modulation unit 10 is configured so that four FSK subcarriers are defined at regular intervals for 16 subcarriers, the modulation unit 10 is periodically generated at intervals of 0.25 symbols in one symbol regardless of the information bits to be transmitted. A signal having the same waveform is generated. In this case, the phase difference calculation unit 42 can be configured to calculate the phase difference at intervals of 0.25 symbols. As described above, the phase difference calculation unit 42 can be configured to calculate the phase difference between chips at an interval that matches the periodicity of the signal appearing in one symbol regardless of the information bits. Generally, when the chip interval for calculating the phase difference is narrowed, a wider range of frequency offset can be estimated. As a result, good synchronization performance can be realized.

Embodiment 2. FIG.
In the present embodiment, FSK subcarriers are defined every 4 subcarriers among all subcarriers. In addition, the initial capturing unit 34 is configured to have two systems each of a phase difference calculation unit, an addition processing unit, an averaging processing unit, and a power calculation unit.

  The configuration of the spread spectrum transmitter in the present embodiment is the same as that in the first embodiment (see FIG. 1). However, the signal transmitted from the modulation unit 10 is generated based on four FSK subcarriers defined for 16 subcarriers as illustrated in FIG. FIG. 7 is a diagram illustrating a signal spectrum image output from the modulation unit 10 according to the present embodiment. In the example of FIG. 7, 16 subcarriers are defined on the frequency axis, and the FSK subcarrier defining method in the present embodiment is shown. FSK subcarriers 70 to 73 each indicate an FSK subcarrier. For example, for information bits to be transmitted, the modulation unit 10 selects the FSK subcarrier 70 when the information bits are “0, 0”, and selects the FSK subcarrier 71 when the information bits are “0, 1”. When the bit is “1,0”, the FSK subcarrier 72 is selected, and when the information bit is “1,1”, the FSK subcarrier 73 is selected. Accordingly, the spread code generation unit 12 generates a spread code having a length of 16 chips per symbol, and the spread unit 11 outputs an output from the modulation unit 10 and a spread code having a length of 16 chips per symbol. Multiply with.

  Next, the configuration and operation of the spread spectrum receiver will be described. The configuration of the spread spectrum receiver of the present embodiment is the same as that of the first embodiment (see FIG. 3), but the configuration of the initial acquisition unit 34 is different. FIG. 8 is a diagram illustrating a configuration example of the initial capturing unit 34 according to the present embodiment. The initial capturing unit 34 includes a spreading code multiplication unit 80, a spreading code generation unit 81, phase difference calculation units 42 and 82, addition processing units 43 and 83, averaging processing units 44 and 84, and a power calculation unit 45. , 85, a determination unit 86, and a frequency calculation unit 87. In addition, the part which has the same function as Embodiment 1 (refer FIG. 4) attaches | subjects the same code | symbol, and abbreviate | omits the detailed description.

  The initial acquisition unit 34 of the present embodiment is configured on the premise of 16 chips per symbol so as to correspond to a transmission signal in which FSK subcarriers are defined with respect to the 16 subcarriers illustrated in FIG.

The spread code multiplication unit 80 can be composed of a shift register and a multiplier as in FIG. 5, but it has 16 shift registers and 16 multipliers. In this case, for each input from the reception filter 33, the spread code multiplication unit 80 multiplies the received digital signal after the filter processing by the complex conjugate of the spread codes c0 ′ ^{* to} c15 ′ ^* , and the multiplication results a0 ′ to a15 ′. Is transferred to the phase difference calculation unit 42 and the phase difference calculation unit 82.

  The spreading code generation unit 81 generates a code having a complex conjugate relationship with a spreading code with 16 chips generated by the spreading code generation unit 12 as one cycle, and outputs the code to the spreading code multiplication unit 80.

  The phase difference calculation unit 42 calculates the phase difference between chips at intervals of 0.5 symbols as in the first embodiment. Thereafter, the addition processing unit 43 to the power calculation unit 45 perform the same processing as in the first embodiment. As a result, the maximum power value and the corresponding chip number are delivered from the power calculation unit 45 to the determination unit 86. The multiplication results a0 ′ to a15 ′ delivered from the spreading code multiplication unit 80 are a0 ′ corresponding to a0 and a2 ′ corresponding to a1 with respect to the multiplication results a0 to a7 of the first embodiment. a4 ′ corresponds to a2, a6 ′ corresponds to a3, a8 ′ corresponds to a4, a10 ′ corresponds to a5, a12 ′ corresponds to a6, and a14 ′ corresponds to a7.

  The phase difference calculation unit 82 is the same as the phase difference calculation unit 42 in that the phase difference between chips in one symbol is calculated at a predetermined interval with respect to the input signal, but the phase difference calculation interval is the phase difference. The calculation unit 42 is configured differently. In the present embodiment, the phase difference calculation unit 82 calculates the phase difference between chips at intervals of 0.25 symbols. Note that the symbol interval used in the phase difference calculation unit 42 and the phase difference calculation unit 82 is a timing at which the timing of multiplying the spread code is synchronized with the spread code cycle in the received signal according to the periodicity indicated by the complex sine wave within one symbol. In such a case, the interval is selected so that the phase difference can be calculated between the same waveforms.

  FIG. 9 is a diagram illustrating a signal waveform of one symbol time when the FSK subcarrier arrangement according to the present embodiment is used. The signal waveform of 1 symbol time at the time of using FSK subcarrier arrangement | positioning is illustrated. This corresponds to the FSK subcarrier arrangement shown in FIG. In FIG. 9, signal waveforms 90 to 93 are signal waveforms of one symbol time when information bits “0, 0”, “0, 1”, “1, 0”, and “1, 1” are transmitted, respectively. . The signal waveform output from the modulation unit 10 is a complex sine wave and has both an in-phase component and a quadrature component, but FIG. 9 shows only the in-phase component as a representative example. As can be seen from FIG. 9, the complex sine wave generated by the modulator 10 has the same waveform in the first half of the symbol and the second half of the symbol, that is, the same waveform at 0.5 symbol intervals, regardless of the information bits. The same waveform for every 1/4 of the symbol, that is, the same waveform at 0.25 symbol intervals.

  Utilizing this fact, the phase difference calculation unit 82 calculates the phase difference between chips at an interval of 0.25 symbols with respect to the input signal after multiplication of the spread code, and outputs it to the addition processing unit 83 in the subsequent stage. To do. Thereafter, the addition processing unit 83 to the power calculation unit 85 perform the same processing as that of the addition processing unit 43 to the power calculation unit 45 on the processing result of the phase difference calculation unit 82 in another system.

  In addition, the structure for implementing the process with respect to the output of the phase difference calculation unit 42 and the process with respect to the output of the phase difference calculation unit 82 in different systems may be arbitrary. Separate circuits may be provided independently, and the calculation function is shared in a time-sharing manner, so that only the memory that holds the calculation results is provided independently, resulting in a configuration equivalent to that implemented using a separate system. May be. The power calculator 85 outputs the maximum power value and the corresponding chip number to the determination unit 86.

  The determination unit 86 performs threshold determination using the maximum power value input from each of the power calculation unit 45 and the power calculation unit 85 and the corresponding chip number. The determination unit 86 compares a value obtained by adding the maximum power values input from the two power calculation units 45 and 85 with the threshold value α. Further, whether or not the chip numbers input from the two power calculation units 45 and 85 are the same is checked, and if they are the same, the number of consecutive times that the chip number indicates the maximum power value is compared with the threshold value β. . The determination unit 86 determines that the threshold value is satisfied when the sum of the maximum power values is greater than α and the number of consecutive times that the chip number indicates the maximum power value is β times. In other cases, it is determined that the threshold value is not satisfied. The determination unit 86 outputs a threshold determination result and a chip number that takes the maximum power value.

  Similarly to the frequency calculation unit 47 in the first embodiment, when receiving the notification that the threshold value is satisfied from the determination unit 86, the frequency calculation unit 87 reads the average result of the chip number that takes the maximum power value, Calculate the offset. Here, in the present embodiment, a signal (phase difference calculated at an interval of 0.5 symbols) held in the memory of the averaging processor 44 and a signal held in the memory of the averaging processor 84. (Phase difference calculated at an interval of 0.25 symbols) is read out, and frequency offsets are calculated from these two signals. Thereafter, the two frequency offset calculation results are synthesized and output. Here, the synthesis of the frequency offset calculation result can be easily realized by those skilled in the art by using a known technique disclosed in the following literature, for example.

  Hiroshi KUBO, Keishi MURAKAMI, Makito MIYAKE, Tadashi FUJINO, “A Multiple Open-Loop Frequent Sense Ref. Commun, VOL-E82-B, no. 1, January 1999.

  As described above, in the present embodiment, in the spread spectrum transmitter, modulation section 10 defines FSK subcarriers at intervals of 4 subcarriers for 16 subcarriers as shown in FIG. Thus, a modulated signal having periodicity with different periods of 0.5 symbol interval and 0.25 symbol interval within one symbol and having a different repetitive pattern for each information bit is generated regardless of information bits. In the spread spectrum receiver, the initial acquisition unit 34 includes two systems of phase difference calculation units, an addition processing unit, and an averaging processing unit that calculate the phase difference between chips at intervals that match the periodicity in the symbols described above. And it was set as the structure which has an electric power calculation part. Furthermore, the threshold determination and the frequency offset calculation are performed using the processing results of the two systems. As a result, it is possible to perform initial acquisition and frequency offset estimation based on the phase difference calculated from two different symbol intervals, and there is an effect that synchronization processing can be completed at high speed and with high accuracy.

  In the present embodiment, the FSK subcarrier definition method illustrated in FIG. 7 is used. However, the present invention is not limited to this, and any FSK subcarrier may be used as long as it has periodicity within one symbol regardless of information bits. A carrier definition can be used. At this time, when there are more combinations that show periodicity within one symbol than two patterns of 0.5 symbols and 0.25 symbols, the initial acquisition unit includes a processing system from the phase difference calculation unit to the power calculation unit. The number of periodic patterns can be prepared. An improvement in initial synchronization performance can be expected as the number of periodic patterns used in the initial acquisition unit increases.

  In the present embodiment, the determination unit 86 is configured to determine the threshold value using the sum of the maximum power values input from the power calculation unit 45 and the power calculation unit 85. Only the power value of may be used. Thereby, the amount of processing can be reduced. In addition, the threshold determination condition is that the chip numbers indicating the maximum power values input from the power calculation unit 45 and the power calculation unit 85 are the same. For example, paying attention to only one of them The threshold number may be determined so that the chip number appears β times continuously. Alternatively, the threshold value indicates that the chip number having the maximum power sum appears β times continuously regardless of the chip number indicating the maximum power value input from the power calculator 45 and the power calculator 85. It can also be a condition for determination. The threshold value setting and threshold value determination method in the determination unit 86 can be any method that satisfies the performance required from the communication environment and the requirements for the initial synchronization performance.

  Further, in the frequency calculation unit 87, the frequency offset is calculated for each of the averaged results of the averaging processing unit 44 and the averaging processing unit 84, and then synthesized, but only one of them is used. A frequency offset may be calculated. With this configuration, a reduction in processing amount can be expected. Further, the phase difference read from the averaging processing unit 44 and the averaging processing unit 84 used for calculating the frequency offset may refer to different chip numbers. For example, the phase difference read from the averaging processing unit 44 and the averaging processing unit 84 can be a chip number indicating the maximum power value input from the power calculation unit 45 and the power calculation unit 85, respectively. In this case, the frequency offset can be calculated based on a more probable phase difference when the synchronization determination is made with different chip numbers indicating the maximum power values.

  The details of the present invention have been illustrated above, but the scope of the present invention is not limited to the embodiment described above, and all possible configurations are included in the scope.

  As described above, the spread spectrum receiver and the spread spectrum transmitter according to the present invention are useful for spread spectrum communication, and are particularly suitable for the direct spread system.

  DESCRIPTION OF SYMBOLS 10 Modulation part, 11 Spreading part, 12 Spreading code generation part, 13 D / A conversion part, 14 High frequency processing part, 15 Transmission antenna, 30 Reception antenna, 31 High frequency processing part, 32 A / D conversion processing part, 33 Reception filter , 34 initial acquisition unit, 35 despreading processing unit, 36 demodulation unit, 37 control unit, 40, 80 spreading code multiplication unit, 41, 81 spreading code generation unit, 42, 82 phase difference calculation unit, 43, 83 addition processing unit , 44, 84 Averaging processing unit, 45, 85 Power calculation unit, 46, 86 determination unit, 47, 87 Frequency calculation unit.

Claims (3)

When receiving a signal obtained by multiplying a modulation signal having a repetition pattern that is the same period and different for each transmission information from a spread spectrum transmitter by a spreading code, regardless of transmission information,
Spreading code multiplication means for multiplying the received signal from the spread spectrum transmitter by the complex conjugate of the spreading code;
A phase difference calculating means for calculating a phase difference between chips at a symbol interval defined in one symbol using a signal obtained by multiplying the complex conjugate of the spreading code;
Addition processing means for adding the phase difference between the chips;
Power calculating means for calculating a power value from the phase difference between the chips after the addition,
Determination means for determining spreading code synchronization based on the power value input from the power calculation means and the chip number information corresponding to the power value;
A frequency calculating means for calculating a frequency offset based on a determination result by the determining means and a phase difference between the chips;
A spread spectrum receiver. When receiving a signal obtained by multiplying a modulation signal having a repetition pattern that is the same period and different for each transmission information from a spread spectrum transmitter by a spreading code, regardless of transmission information,
Spreading code multiplication means for multiplying the received signal from the spread spectrum transmitter by the complex conjugate of the spreading code;
A phase difference calculating means for calculating a phase difference between chips in one symbol using a signal after multiplication of the complex conjugate of the spreading code;
Addition processing means for adding the phase difference between the chips;
Power calculating means for calculating a power value from the phase difference between the chips after the addition,
Determination means for determining spreading code synchronization based on the power value input from the power calculation means and the chip number information corresponding to the power value;
A frequency calculating means for calculating a frequency offset based on a determination result by the determining means and a phase difference between the chips;
With
A spread signal is multiplied by a spread code from a spread spectrum transmitter to a modulated signal having the same period regardless of transmission information, a different repetition pattern for each transmission information, and having the repetition pattern corresponding to a plurality of different periods. When receiving
A plurality of the phase difference calculation means, the addition processing means, and the power calculation means, a plurality of systems comprising the phase difference calculation means, the addition processing means, and the power calculation means,
The plurality of phase difference calculating means calculate the phase difference between chips corresponding to the different periods,
The determination means determines spread code synchronization based on the power value input from the plurality of power calculation means of each system and the chip number information corresponding to the power value,
The frequency calculation means calculates a frequency offset based on a determination result by the determination means and a phase difference between chips corresponding to the different periods;
Features and to Luz spectrum spread receiver that. The modulated signal is a signal modulated by FSK (Frequency Shift Keying).
The spread spectrum receiver according to claim 1 or 2.

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