JP6284292B2 - Silicon carbide semiconductor device - Google Patents

Description

The present invention is, for example, silicon carbide having a semiconductor switching element such as a trench gate structure (hereinafter, referred to as SiC) relates to semiconductor equipment.

  Conventionally, in an SiC semiconductor device including a MOSFET as a semiconductor switching element, an ohmic electrode is formed by performing high concentration ion implantation on a source electrode on the substrate surface side. However, a composite defect of a point defect generated during ion implantation and a threading transition existing in the epitaxial film greatly affects the leak (see, for example, Non-Patent Document 1). For this reason, the method shown by patent documents 1-3 is proposed as a method of suppressing a leak.

Specifically, in Patent Document 1, in order to prevent the influence of point defect diffusion of the p ⁺ type body contact region that is brought into contact with the source electrode and to keep the channel length short, the lower part of the p ⁺ type body contact region is used. Only the p-type base region is made thick. Specifically, the distance from the bottom of the p ⁺ -type body contact region to the PN junction interface at the bottom of the p-type base layer embedded in the trench is set to 4 μm or more.

  In Patent Document 2, in order to suppress ion implantation defects, phosphorus or aluminum is ion-implanted so that ohmic contact can be easily made on the surface of the source contact region or the body contact region. Then, nitrogen or boron which can reduce ion implantation damage is ion-implanted thereunder.

In Patent Document 3, a substrate having a transition density of 5 × 10 ³ cm ⁻² or less is used, and the impurity concentration of the p ⁺ -type contact region brought into contact with the source electrode is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ^21. It is set to be cm ^-3 or less.

Special table 2010-258386 JP 2009-231545 A JP 2010-087397 A

Tatsumi, SiC and related wide gap semiconductor research group 4th Individual Discussion Meeting, Proceedings 74, 09/7

However, in the method of Patent Document 1, the diffusion may exceed 4 μm depending on the impurity concentration of the p ⁺ type body contact region and the annealing conditions, and the point defect is also affected in the n ⁺ type source region. Also, in the methods of Patent Documents 2 and 3, point defects may be deeply distributed depending on the impurity concentration and annealing conditions, and a leak path may be formed to cause drain leakage.

  In view of the above points, an object of the present invention is to provide a SiC semiconductor device having a structure capable of reducing drain leakage due to point defects.

To achieve the above object, according to the invention of claim 1, the distribution of point defects in the depth direction from the surface of the semiconductor substrate definitive source region (4) and the contact region (5) (1-3), X <Y, where X is the depth of the peak position of the number of point defects from the surface of the semiconductor substrate, and Y is the depth to the PN junction interface between the base region (3) and the drift layer (2). It is characterized by that.

  As described above, the relationship X <Y is satisfied between the depth X of the peak position of the number of point defects from the surface of the semiconductor substrate and the depth Y to the PN junction interface between the base region and the drift layer (2). It is made to hold. Thereby, drain leak can be suppressed.

Further, in the invention according to claim 3, cathode luminescence in the depth direction from the surface of the semiconductor substrate definitive source region and the contact area (hereinafter, CL hereinafter) for spectrum measurement, of points of the spectrum of the CL measurement X <Y, where X is the depth from the surface of the semiconductor substrate of the spectral intensity in the portion corresponding to the defect, and Y is the depth to the PN junction interface between the base region and the drift layer. .

  In this way, the distribution of point defects can be shown by the spectrum of CL measurement. For this reason, the depth X from the surface of the semiconductor substrate of the spectrum intensity in the portion corresponding to the point defect in the spectrum of CL measurement and the depth Y to the PN junction interface between the base region and the drift layer are also expressed as X < By making Y, the same effect as in claim 1 can be obtained. In particular, as described in claim 4, if the spectral intensity ratio is set to 0.8, drain leakage can be further suppressed.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a SiC semiconductor device including an n-channel type inversion MOSFET according to a first embodiment of the present invention. (A) is a cross-sectional view of an experimental sample, and (b) and (c) are spectral intensity distributions at the L ₁ line when CL measurement is performed in the depth direction of the semiconductor substrate for the sample shown in (a). FIG. It is a figure which shows the result of having investigated the profile of CL spectrum intensity regarding the distribution of the point defect in the depth direction of a semiconductor substrate, changing the dose amount of Al. It is a figure which shows the result of having analyzed the CL spectrum intensity in arbitrary places about the sample in which the dose amount was set like FIG. 3 (a), (b). It is the figure which showed the comparison result of the point defect profile after correction | amendment of CL spectrum intensity. FIG. 3 is a cross-sectional view showing a manufacturing process of the MOSFET having the trench gate structure shown in FIG. It is sectional drawing of the SiC semiconductor device provided with the n channel type inversion type MOSFET concerning 2nd Embodiment of this invention. It is sectional drawing of the SiC semiconductor device provided with the n channel type inversion type MOSFET concerning 3rd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. Here, an SiC semiconductor device in which an inverted MOSFET having a trench gate structure is formed as a semiconductor switching element will be described as an example.

  As shown in FIG. 1, an n-channel type inversion MOSFET is formed in the SiC semiconductor device. A MOSFET having a plurality of cells is configured by arranging MOSFETs having the same structure as the MOSFET shown in FIG.

Specifically, the SiC semiconductor device uses, as a semiconductor substrate, an n ⁻ type drift layer 2 made of SiC and a p type base region 3 which are epitaxially grown in this order on the main surface of an n ⁺ type substrate 1 made of SiC. Is formed.

The n ⁺ -type substrate 1 has an n-type impurity concentration such as nitrogen of 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm.

The n ⁻ type drift layer 2 is formed on the surface of the n ⁺ type substrate 1 and has an n type impurity concentration such as nitrogen of 3.0 × 10 ^{15 to} 2.0 × 10 ¹⁶ / cm ³ and a thickness of 10 to ¹⁵ μm. It is said to be about. The impurity concentration of the n ⁻ type drift layer 2 may be constant in the depth direction, but the concentration distribution is inclined, and the n ⁺ type substrate 1 side of the n ⁻ type drift layer 2 is n ⁺ type. The concentration can be higher than that on the side away from the substrate 1. In this way, since the internal resistance of the n ⁻ type drift layer 2 can be reduced, the on-resistance can be reduced.

The p-type base region 3 is formed on the surface of the n ⁻ -type drift layer 2 and has a p-type impurity concentration such as boron or aluminum of 1.0 × 10 ^{16 to} 2.0 × 10 ¹⁹ / cm ³ and a thickness of 1 .3 μm or more, for example, 2.0 μm.

Further, an n ⁺ type source region 4, a p ⁺ type contact layer 5 and a p type body layer 6 are formed in the upper layer portion of the p type base region 3. The n ⁺ type source region 4 has an n type impurity concentration (surface concentration) such as nitrogen in the surface layer portion of, for example, 1.0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ and a thickness of about 0.3 μm. ing. The p ⁺ -type contact layer 5 has, for example, a p-type impurity concentration (surface concentration) such as boron or aluminum in the surface layer portion of, for example, 1.0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ and a thickness of about 0.15 μm. It consists of The p-type body layer 6 is composed of, for example, 1.0 × 10 ^{18 to} 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 0.45 μm. Although the structure including the p-type body layer 6 is shown here, the p-type body layer 6 is formed as necessary.

The n ⁺ -type source region 4 is disposed on both sides of a trench gate structure described later, and the p ⁺ -type contact layer 5 is provided on the opposite side of the trench gate structure with the n ⁺ -type source region 4 interposed therebetween. The p-type body layer 6 is disposed so as to surround the periphery of the p ⁺ -type contact layer 5, and is disposed so as to enter the lower part of the n ⁺ -type source region 4.

In addition, a structure in which the p-type base region 3 and the n ⁺ -type source region 4 are penetrated to the n ⁻ -type drift layer 2 and the bottom portion has a predetermined width, for example, the width is 0.5 to 2.0 μm and the depth is A trench 7 of 2.0 μm or more (for example, 2.4 μm) is formed. The p-type base region 3 and the n ⁺ -type source region 4 are arranged so as to be in contact with the side surface of the trench 7.

  The trench 7 is formed with the left-right direction in FIG. 1 as the width direction, the vertical direction in the drawing as the longitudinal direction, and the up-down direction as the depth direction. Only one trench 7 is shown in the figure. The trenches 7 are arranged in parallel to each other in the left-right direction to form a stripe shape. The corner portion of the bottom of the trench 7 is rounded by a rounding process.

  Furthermore, the inner wall surface of the trench 7 is covered with a gate insulating film 8 made of an oxide film or the like, and a gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8, The inside of the trench 7 is filled. The gate insulating film 8 is formed by thermally oxidizing the inner wall surface of the trench 7, and the thickness of the gate insulating film 8 is about 100 nm on both the side surface side and the bottom side of the trench 7. In this way, a trench gate structure is configured.

A source electrode 11 and a gate wiring (not shown) are formed on the surface of the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5 and the surface of the gate electrode 9 via an interlayer insulating film 10. The source electrode 11 and the gate wiring are composed of a plurality of metals (for example, Ni / Al, etc.), and at least n-type SiC (specifically, the n ⁺ -type source region 4 and the gate electrode 9 in the case of n doping) The portion in contact with n-type SiC is made of a metal capable of ohmic contact with n-type SiC, and the portion in contact with at least p-type SiC (specifically, p ⁺ -type contact layer 5 or gate electrode 9 in the case of p-doping) is p-type. It is made of a metal capable of ohmic contact with SiC. The source electrode 11 and the gate wiring are electrically insulated on the interlayer insulating film 10, and the source electrode 11 is connected to the n ⁺ type source region 4 and the p ⁺ type through a contact hole formed in the interlayer insulating film 10. The contact layer 5 is in electrical contact, and the gate wiring is in electrical contact with the gate electrode 9.

Then, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel inversion type MOSFET having a trench gate structure is formed.

  Such an inverted MOSFET having a trench gate structure operates as follows. First, the inversion layer is not formed in the p-type base region 3 before the gate voltage is applied to the gate electrode 9. Therefore, even if a positive voltage is applied to the drain electrode 12, electrons cannot reach the p-type base region 3 from the n-type source region 4, and no current flows between the source electrode 11 and the drain electrode 12. Not flowing.

Next, when off (gate voltage = 0 V, drain voltage = 650 V, source voltage = 0 V), a reverse bias is applied even if a voltage is applied to the drain electrode 12, so the p-type base region 3 and the n ⁻ -type drift layer A depletion layer spreads between two. At this time, since the concentration of the p-type base region 3 is higher than that of the n ⁻ -type drift layer 2, the depletion layer extends almost to the n ⁻ -type drift layer 2 side. Since the depletion layer is wider than in the case of the drain 0 V, the region that behaves as an insulator further spreads, so that no current flows between the source electrode 11 and the drain electrode 12.

On the other hand, when ON (gate voltage = 20 V, drain voltage = 1 V, source voltage = 0 V), 20 V is applied as the gate voltage to the gate electrode 9, so that it is in contact with the trench 7 in the p-type base region 3. A channel is formed on the surface. For this reason, electrons injected from the source electrode 11 pass through the channel formed in the p-type base region 3 from the n ⁺ -type source region 4 and then reach the n ⁻ -type drift layer 2. As a result, a current can flow between the source electrode 11 and the drain electrode 12.

In this inversion type MOSFET having a trench gate structure, the present embodiment further has a structure in which the peak position of the number of point defects due to ion implantation is in the p-type base region 3. In addition, at a position deeper than the peak position, the number of point defects monotonously decreases as the depth increases. That is, the depth of the peak position of the distribution of the number of point defects along the depth direction from the surface of the semiconductor substrate is X, and the PN junction position formed by the n ⁻ -type drift layer 2 and the p-type base region 3 from the surface When Y is Y, the relationship X <Y is established.

The drain leak generated due to the point defect is caused by diffusion of the point defect in the ion implanted portion, and a leak path in the depletion layer formed in the vicinity of the PN junction interface between the n ⁻ type drift layer 2 and the p type base region 3. It is assumed that it occurs when it can. In particular, in a place where threading dislocations are present, drain leakage increases due to the collection of point defects around the dislocations.

Therefore, the relationship between the distribution of point defects and the depletion layer in the vicinity of the PN junction interface between the n ⁻ -type drift layer 2 and the p-type base region 3 is considered to be a point for suppressing drain leakage. The present inventors paid attention to this point and conducted various studies on the positional relationship between the distribution of point defects and the PN junction interface between the n ⁻ -type drift layer 2 and the p-type base region 3, as described above. It was found that drain leakage is reduced when X <Y.

Specifically, as shown in FIG. 2A, in the structure in which an n ⁻ type drift layer 2 and a p type base region 3 are epitaxially grown on the surface of an n ⁺ type substrate 1 in this order, Al ions are implanted and impurities are introduced. After performing the thermal diffusion step, the distribution of point defects and the presence or absence of drain leakage were examined. The distribution of point defects was analyzed by CL measurement.

  As a result, as shown in the profiles shown in FIGS. 2B and 2C, there was a drain leak when the distribution of point defects was in a relationship of X> Y. There was no drain leak when the distribution was such that X <Y.

More specifically, in the structure shown in FIG. 2A, the n ^- type drift layer 2 has an n-type impurity concentration of 5 × 10 ¹⁵ / cm ³ , a thickness of 13 μm, and a p-type impurity concentration of the p-type base region 3. The thickness was 1 × 10 ¹⁷ / cm ³ and the thickness was 1.8 μm. In addition, the ion implantation energy of Al ions is set to 350 keV so that the p ⁺ type contact region 5 is formed with a thickness of about 0.3 μm. Samples were prepared for a case where the dose was 1.0 × 10 ²¹ / cm ³ and a case where the dose was 1.0 × 10 ²⁰ / cm ^3, and CL representing the distribution of point defects in the depth direction of the semiconductor substrate. The spectral intensity profile was examined. The activation annealing temperature was 1500 ° C., and the time was 30 minutes. As a result, profiles as shown in FIGS. 3A and 3B were obtained. Note that the profiles in FIGS. 3A and 3B correspond to the CL spectral intensities of the respective portions of the cross section shown on the left side of the drawing.

In the CL measurement, the number of point defects and the like are represented by the intensity in the unique spectrum, and the greater the intensity of the spectrum unique to the point defect, the greater the number of point defects. For example, when the CL spectrum intensity at an arbitrary place is analyzed for a sample with a dose set as shown in FIGS. 3A and 3B, the analysis results as shown in FIGS. 4A and 4B are obtained. Obtained. In this figure, the spectrum of Q ₀ is the normal light emission in the spectrum generated at the band edge, PRs is the normal light emission in the intrinsic spectrum generated by lattice vibration in the phonon replica, and DAP is the normal light emission due to the donor-acceptor pair and impurities. , L ₁ is light emission from point defects. Since the intensity in the spectrum of L ₁ increases as the number of point defects increases and the distribution increases, the distribution of point defects is analyzed based on the spectrum intensity. The L ₁ line is the spectral wavelength of the composite defect of carbon (C) antisite and silicon (Si) antisite, and since the wavelength λ is about 426 nm, a bandpass filter that passes only this wavelength is used. , Only the profile in that band is extracted and the distribution of point defects is analyzed. The result is a profile represented as shown in FIGS.

With respect to these profiles, the intensity ratio was calculated under the assumption that the emission intensity of PRs of λ = 388 nm at the position of the n ⁻ -type drift layer 2 in the sample with and without leaking coincided, and FIG. When the CL spectrum intensity of b) was corrected by the ratio and the scale was matched with FIG. 3A, the comparison result shown in FIG. 5 was obtained. As shown in this figure, the peak positions of the distribution of point defects are different for each sample. For the sample having no drain leak, the peak position is included in the thickness of the p-type base region 3 (1.8 μm in the experimental example). For the sample having the drain leak, the peak position is The position was deeper than the thickness of the p-type base region 3. Further, the sample having no drain leak has a structure in which the number of point defects monotonously decreases as the depth increases at a position deeper than the peak position.

Thus, the intensity distribution of the spectrum of the CL measurement along the depth direction from the surface of the semiconductor substrate, that is, the depth X of the peak position of the distribution of the number of point defects, and the n ⁻ type drift layer 2 and the p-type from the surface. With respect to the PN junction position Y with the base region 3, the relationship X <Y is established. By adopting such a structure and suppressing the point defects from diffusing into the depletion layer near the PN junction interface between the n ⁻ type drift layer 2 and the p-type base region 3, it is possible to suppress the formation of a leak path in the depletion layer. . Therefore, drain leakage can be suppressed.

  Further, the ratio of the CL spectrum intensity (intensity (Y)) at the Y position, that is, the PN junction interface to the CL spectrum intensity (intensity (X)) at the X position, ie, the peak position (= intensity (Y) / intensity (X) (hereinafter referred to as CL spectrum intensity ratio) and the drain leakage suppression effect were also examined. Specifically, when the CL spectral intensity ratios were examined for 0.7, 0.8, and 0.9, respectively, drain leakage could be suppressed in all cases, that is, if the relationship X <Y was satisfied. However, as shown in FIG. 2C in particular, the drain leakage was completely eliminated at 0.8 or less. Therefore, drain leakage can be suppressed by satisfying the relationship of X <Y, and drain leakage can be further suppressed by setting the CL spectrum intensity ratio to 0.8. become.

In the above description, the experimental results when Al ions are implanted in the structure shown in FIG. 2A have been described as an example. However, the relationship between point defects and drain leaks is formed by ion implantation. The same can be said for both the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5. Therefore, after performing ion implantation and thermal diffusion for forming them, the relationship of X <Y should be satisfied for the distribution of point defects.

Here, the case where the spectral wavelength of the L ₁ line where λ = 426, that is, the composite defect of carbon antisite and silicon antisite, is considered has been described. However, with respect to point defects of other factors as well, drain leaks can be suppressed by making the point positions of the point defects within the p-type base region 3 as described above. Specific examples include point defects caused by silicon vacancies and point defects caused by combined defects of carbon vacancies and carbon antisites. The CL spectrum wavelength of a point defect caused by silicon vacancies is 860 nm, and the CL spectrum wavelength of a point defect caused by a composite defect of carbon vacancies and carbon antisite is 1078 nm. For this reason, the above effects can be obtained by using a bandpass filter that passes these wavelengths, extracting only the profile in that band, and controlling the distribution of point defects.

  Next, a method for manufacturing the MOSFET having the trench gate structure shown in FIG. 1 will be described with reference to FIG.

[Step shown in FIG. 6A]
First, a semiconductor substrate in which an n ⁻ type drift layer 2 and a p type base region 3 are epitaxially grown on the surface of an n ⁺ type substrate 1 is prepared. The n ⁺ type substrate 1 has an n type impurity concentration of, for example, 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm. The n ⁻ type drift layer 2 has an n type impurity concentration of, for example, 3.0 × 10 ^{15 to} 2.0 × 10 ¹⁶ / cm ³ and a thickness of about 15 μm, and the p type base region 3 has a p type impurity concentration. The thickness is 1.0 × 10 ^{16 to} 2.0 × 10 ¹⁹ / cm ³ and the thickness is 1.3 μm or more.

[Step shown in FIG. 6B]
Subsequently, after forming a mask (not shown) made of, for example, LTO on the p-type base region 3, a mask is formed on the formation region of the n ⁺ -type source region 4 through a photolithography process. Open. Thereafter, n-type impurities (for example, nitrogen) are ion-implanted. At this time, for example, the ion implantation energy is 310 keV, and the dose is 1.0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ .

Further, after removing the previously used mask, a mask (not shown) is formed again, and the mask is opened on a region where the p ⁺ -type contact layer 5 is to be formed through a photolithography process. Thereafter, p-type impurities (for example, boron and aluminum) are ion-implanted. At this time, for example, the ion implantation energy is set to 160 keV, and the dose is set to 1.0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ .

At this time, ion implantation of a p-type impurity for forming the p-type body layer 6 may be performed as necessary. Then, the implanted ions are activated by performing an activation annealing treatment at 1600 ° C. for 30 minutes, for example. Thereby, the n ⁺ type source region 4, the p ⁺ type contact layer 5 and the p type body layer 6 are formed. Thereafter, the mask is removed.

[Step shown in FIG. 6 (c)]
After forming an etching mask (not shown) on the p-type base region 3, the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, the etching mask is opened in a region where the trench 7 is to be formed. And the trench 7 is formed by performing the trench etching process using an etching mask. Thereafter, the etching mask is removed.

Further, if necessary, hydrogen etching is performed to remove damage from trench etching and to activate heat treatment. Specifically, hydrogen etching is performed for 5 minutes by heat treatment in a hydrogen atmosphere under a reduced pressure of 1600 ° C. or higher, for example, a high temperature hydrogen atmosphere of 1625 ° C. and 2.7 × 10 ⁴ Pa (200 Torr). Thereby, the rounding process of the inner wall surface of the trench 7 is performed, and the opening corner part of the trench 7, the corner part of the bottom part, the convex part of the side face, and the like are rounded.

[Step shown in FIG. 6 (d)]
By performing a gate insulating film forming step by thermal oxidation or the like, the gate insulating film 8 is formed on the entire surface of the substrate including the inside of the trench 7. Specifically, the gate insulating film 8 is formed by gate oxidation (thermal oxidation) by a pyrogenic method using a wet atmosphere. Subsequently, after a polysilicon layer doped with n-type impurities is formed on the surface of the gate insulating film 8 at a temperature of about 440 nm, for example, at a temperature of 600 ° C., an etch back process or the like is performed, whereby the gate insulating film is formed in the trench 7. 8 and the gate electrode 9 are left.

Further, after forming the interlayer insulating film 10, the interlayer insulating film 10 is patterned to form contact holes connected to the n ⁺ type source region 4 and the p ⁺ type contact layer 5, and contact holes connected to the gate electrode 9 are formed. It is formed in another cross section. Subsequently, after depositing an electrode material so as to fill the contact hole, the source electrode 11 and the gate wiring are formed by patterning the electrode material.

Thereafter, although not shown, the drain electrode 12 is formed on the back surface side of the n ⁺ type substrate 1 to complete the MOSFET shown in FIG.

As described above, according to the SiC semiconductor device of the present embodiment, the depth X of the peak position of the distribution of the number of point defects along the depth direction from the surface of the semiconductor substrate, and the n ⁻ type drift layer from the surface For the PN junction position Y constituted by 2 and the p-type base region 3, the relationship X <Y is established. As a result, it is possible to suppress drain leakage caused by point defects. In particular, drain leakage can be further suppressed by setting the CL spectrum ratio to 0.8 or less.

(Second Embodiment)
A second embodiment of the present invention will be described. This embodiment is different from the first embodiment in the structure of the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, and is otherwise the same as the first embodiment. Only portions different from the embodiment will be described.

As shown in FIG. 7, in this embodiment, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 are formed using two types of impurities. Specifically, the n ⁺ type source region 4 is formed using nitrogen and phosphorus, and the p ⁺ type contact layer 5 is formed using boron and aluminum. In the n ⁺ -type source region 4, the lower layer portion having a depth of up to about 0.3 μm is formed by nitrogen ion implantation, and the upper layer portion up to a depth of about 0.15 μm is formed by phosphorus ion implantation which can easily make ohmic contact. Further, the lower layer portion of the p ⁺ -type contact layer 5 having a depth of up to about 0.3 μm is formed by boron ion implantation, and the upper layer portion of a depth of about 0.15 μm is formed by aluminum ion implantation which can easily make ohmic contact. Yes.

For example, when the n ⁺ -type source region 4 is formed, the energy is 310 keV, the dose is 1.0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ , nitrogen, the energy is 160 keV, and the dose is 1. Phosphorus is ion-implanted at 0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ . When the p ⁺ -type contact layer 5 is formed, the energy is 310 keV, the dose is 1.0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ , boron, the energy is 160 keV, and the dose is 1. Aluminum is ion-implanted at 0 × 10 ^{19 to} 1.0 × 10 ²⁰ / cm ³ . Then, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 can be formed by activating the implanted ions by performing an activation annealing process at 1600 ° C. for 30 minutes, for example.

  Thus, even when ion implantation species are combined, it is possible to obtain the same effect as in the first embodiment by making the relationship of X <Y with respect to the distribution of point defects. Become.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, similarly to the second embodiment, the structures of the n ⁺ type source region 4 and the p ⁺ type contact layer 5 are changed, but an impurity and an inert element are combined as an ion implantation species. It is. Since other aspects are the same as those in the first and second embodiments, only different portions from the first and second embodiments will be described.

As shown in FIG. 8, in this embodiment, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 are formed by implanting an inert element together with impurities. Specifically, the n ⁺ type source region 4 is formed by implanting phosphorus and silicon, and the p ⁺ type contact layer 5 is formed by implanting aluminum and silicon. phosphorus and silicon is implanted in forming the n ⁺ -type source region 4 is injected in the entire region of the n ⁺ -type source region 4 together. Similarly, aluminum and silicon is injected in forming the p ⁺ -type contact layer 5 are also implanted in the entire region of the p ⁺ -type contact layer 5 together.

For example, when the n ⁺ -type source region 4 is formed, the energy is 310 keV, the dose is 1.0 × 10 ²¹ / cm ³ , phosphorus, the energy is 310 keV, and the dose is 1.0 × 10 ¹⁹ to 1. Silicon is ion-implanted at 0 × 10 ²⁰ / cm ³ . When the p ⁺ -type contact layer 5 is formed, the energy is 310 keV, the dose is 1.0 × 10 ²¹ / cm ³ , aluminum, the energy is 310 keV, and the dose is 1.0 × 10 ¹⁹ to 1. Silicon is ion-implanted at 0 × 10 ²⁰ / cm ³ . Then, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 can be formed by activating the implanted ions by performing an activation annealing process at 1600 ° C. for 30 minutes, for example.

  As described above, even when the impurity and the inert element are combined as the ion implantation species, the same effect as that of the first embodiment can be obtained by satisfying the relationship of X <Y with respect to the distribution of the point defects. Can be obtained. In addition, by injecting an inert element at the same time as the impurity, an effect of repairing point defects can be obtained, so that point defects can be reduced and drain leakage caused by point defects can be further suppressed. It becomes.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. This embodiment is different from the first embodiment in the heat treatment method for forming the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, and is otherwise the same as the first embodiment. Therefore, only different parts from the first embodiment will be described.

In the present embodiment, when forming the n ⁺ -type source region 4, the energy is 310 keV, the dose is 1.0 × 10 ^{19 to} 1.0 × 10 ²¹ / cm ³ , and an n-type impurity such as nitrogen or phosphorus. Ion implantation. When the p ⁺ -type contact layer 5 is formed, p-type impurities such as boron or aluminum are ion-implanted with an energy of 310 keV and a dose of 1.0 × 10 ^{19 to} 1.0 × 10 ²¹ / cm ^3. To do. Then, for example, activation annealing is performed by RTA (Rapid Thermal Anneal) such as lamp heating at 1600 ° C. for 5 minutes to activate the implanted ions. Thereby, the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5 can be formed.

  Thus, by performing the activation annealing process in a short time such as RTA, it becomes possible to suppress the diffusion of point defects due to the heat treatment. Therefore, the relationship of X <Y can be established more preferably for the distribution of point defects, and the drain leakage can be more reliably suppressed.

(Other embodiments)
In each of the above embodiments, a semiconductor substrate in which the n ⁻ type drift layer 2 and the p type base region 3 are epitaxially grown on the surface of the n ⁺ type substrate 1 is used, and impurity ions are implanted into the surface layer portion of the p type base region 3. Thus, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 were formed. On the other hand, a triple epi substrate having an n ⁺ type source region 4 formed by epitaxial growth on the surface of the p type base region 3 may be used as a semiconductor substrate.

In each of the above embodiments, an inversion type MOSFET having a trench gate structure has been described as an example. However, the present invention can also be applied to a planar inversion type MOSFET. In the case of a planar inverting MOSFET, a gate insulating film 8 is formed on the surface of the p-type base region 3 in a portion sandwiched between the n ⁺ -type source region 4 and the n ⁻ -type drift layer 2, and a gate is formed thereon. The electrode 9 is formed.

  In the above embodiment, the n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the p-channel in which the conductivity type of each component is inverted is described. The present invention can also be applied to a type of MOSFET. In the above description, a MOSFET having a trench gate structure has been described as an example. However, the present invention can also be applied to an IGBT having a similar trench gate structure. The IGBT only changes the conductivity type of the substrate 1 from n-type to p-type with respect to the above-described embodiment, and the other structures and manufacturing methods are the same as those in the above-described embodiment.

In the above-described embodiment, an example in which the present invention is applied has been described. However, design changes can be made as appropriate. For example, in the above-described embodiment, an oxide film by thermal oxidation has been described as an example of the gate insulating film 8, but an oxide film or nitride film not by thermal oxidation may be included. Further, the process of forming the drain electrode 12 may be performed before the source electrode 11 is formed. Further, although ion implantation for forming the p ⁺ -type contact layer 5 is performed after ion implantation for forming the n ⁺ -type source region 4, the order of these may be reversed. In the second and third embodiments, ion implantation species are combined, but any species may be ion-implanted first.

  Nitrogen and phosphorus are exemplified as n-type impurities, but arsenic (As) and antimony (Sb) may be used. Boron and aluminum are exemplified as p-type impurities, but gallium (Ga) and indium ( Any one or a combination of In) may be used. Further, as inert impurities, in addition to silicon, carbon, fluorine (F), chlorine (Cl), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc. Any one or a combination may be used.

1 n ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 4 n ⁺ type source region 5 p ⁺ type contact layer 7 trench 8 gate insulating film 9 gate electrode 11 source electrode 12 drain electrode

Claims (8)

A first or second conductivity type substrate (1) made of silicon carbide, and a drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate. A semiconductor substrate having a base region (3) formed on the drift layer and made of an epitaxial film made of silicon carbide of the second conductivity type and using aluminum as the second conductivity type impurity; ,
A source region (4) formed of silicon carbide of the first conductivity type formed on the base region and having a higher impurity concentration than the drift layer;
A contact region (5) made of silicon carbide of the second conductivity type connected to the base region and having a higher impurity concentration than the base layer;
A gate insulating film (8) formed on the surface of the base region sandwiched between the source region and the drift layer;
A gate electrode (9) formed on the gate insulating film;
A source electrode (11) electrically connected to the base region via the source region and the contact region;
A drain electrode (12) formed on the back side of the substrate,
Wherein the distribution of point defects from the source region and the definitive in contact area of the semiconductor substrate surface in the depth direction, the depth of the number of peak positions of point defects from the surface of the semiconductor substrate X, the base region And a depth to the PN junction interface between the drift layer and the drift layer, where Y is X <Y.   2. The silicon carbide semiconductor device according to claim 1, wherein the point defects monotonously decrease at a position deeper than X. 3. A first or second conductivity type substrate (1) made of silicon carbide, and a drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate. A semiconductor substrate having a base region (3) formed on the drift layer and made of an epitaxial film made of silicon carbide of the second conductivity type and using aluminum as the second conductivity type impurity; ,
A source region (4) formed of silicon carbide of the first conductivity type formed on the base region and having a higher impurity concentration than the drift layer;
A contact region (5) made of silicon carbide of the second conductivity type connected to the base region and having a higher impurity concentration than the base layer;
A gate insulating film (8) formed on the surface of the base region sandwiched between the source region and the drift layer;
A gate electrode (9) formed on the gate insulating film;
A source electrode (11) electrically connected to the base region via the source region and the contact region;
A drain electrode (12) formed on the back side of the substrate,
The spectrum of cathode luminescence measurement of the depth direction from the source region and the definitive in contact area of the semiconductor substrate surface, of the semiconductor substrate of the spectral intensity at a portion corresponding to the out point defects of the spectrum of the cathodoluminescence measurement A silicon carbide semiconductor device, wherein X <Y, where X is a depth from the surface, and Y is a depth to the PN junction interface between the base region and the drift layer.   The silicon carbide semiconductor device according to claim 3, wherein the spectral intensity monotonously decreases at a position deeper than the X.   5. The silicon carbide semiconductor device according to claim 3, wherein a spectral intensity ratio, which is a ratio of the spectral intensity at the Y position to the spectral intensity at the X position, is 0.8 or less.   The silicon carbide semiconductor device according to claim 1, wherein the point defect is a composite defect of carbon antisite and silicon antisite.   6. The silicon carbide semiconductor device according to claim 1, wherein the point defect is a silicon vacancy.   6. The silicon carbide semiconductor device according to claim 1, wherein the point defect is a composite defect of carbon vacancies and carbon antisites.

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