JP6291934B2 - Information processing apparatus, drawing method, and program - Google Patents

Description

  The present invention relates to an information processing apparatus, a drawing method, and a program that can prevent a common bus from being occupied by a drawing process.

  As an image drawing technique in an information processing apparatus such as a computer or a portable terminal, a technique for writing display data to a main memory and then transferring the display data from the main memory to the video memory via a bus (for example, (See Patent Documents 1 and 2).

  In the technique described in Patent Document 1, a memory data transfer controller reads display data from a main memory via a memory bus in synchronization with rewriting of display data, and transfers it to a video memory on a PCI bus (common bus). An image is drawn by performing write transfer. According to the technique described in Patent Document 1, display data read transfer from the main memory to the memory data transfer controller and write transfer from the memory data transfer controller to the video memory on the common bus are performed in parallel. Since it can be executed, the display data transfer speed can be increased.

  In the technique described in Patent Document 2, the data transfer control device DMA-transfers display data recorded in the main memory to the video memory on the common bus at a cycle according to the operation mode of the CPU. Thus, an image is drawn. More specifically, when the CPU operation mode is the normal operation mode, the DMA transfer is executed in synchronization with the frame rewrite cycle, and the operation mode is the standby mode in which display data is not rewritten. DMA transfer is stopped to reduce power consumption.

JP-A-8-180012 JP 2003-122335 A

  In the technique described in Patent Document 1 described above, the memory data transfer controller transfers the display data from the main memory to the video memory in synchronization with the rewriting of the display data. There is a risk that the common bus is occupied by the drawing process at the time of high-frequency drawing in which a large number of write commands for writing are generated in succession. If the common bus is exclusively used for drawing processing, processing using a device such as a USB controller or a LAN controller connected to the common bus cannot be performed.

  In the technique described in Patent Document 2, the data transfer control device DMA-transfers display data from the main memory to the video memory on the common bus in synchronization with the frame rewrite cycle. When write commands for writing display data to the memory are continuously generated, there is a risk that the common bus will be occupied by the drawing process.

[Object of invention]
Therefore, an object of the present invention is to provide an information processing apparatus that solves the problem that there is a risk that a common bus may be occupied by drawing processing during high-frequency drawing.

An information processing apparatus according to the present invention includes:
A first memory connected to a common bus;
A second memory connected to the local bus;
Writing means for writing display data to the second memory in response to a write command for instructing writing of display data to the first memory;
Transfer means for transferring the display data recorded in the second memory to the first memory at a transfer frequency different from the display data write frequency to the second memory.

The drawing method according to the present invention includes:
In response to a write command instructing writing of display data to the first memory connected to the common bus, the writing means writes the display data to the second memory connected to the local bus,
The transfer means transfers the display data recorded in the second memory to the first memory at a transfer frequency different from the display data write frequency to the second memory.

The program according to the present invention is:
A computer comprising a first memory connected to a common bus and a second memory connected to a local bus;
Writing means for writing display data to the second memory in response to a write command for instructing writing of display data to the first memory;
It functions as transfer means for transferring display data recorded in the second memory to the first memory at a transfer frequency different from the display data write frequency to the second memory.

  According to the present invention, it is possible to reduce the risk that the common bus is occupied by the drawing process during high-frequency drawing.

It is a block diagram which shows the structural example of the information processing apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the process example of a writing means. It is a flowchart which shows the example of a process of a transfer means. It is a block diagram which shows the structural example of the information processing apparatus which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the process example of a filter driver. It is a flowchart which shows the process example of a driver.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

[First embodiment of the present invention]
Referring to FIG. 1, an information processing apparatus such as a computer according to a first embodiment of the present invention includes a first memory 1 connected to a common bus 11 and a second memory connected to a local bus 12. 2, a writing unit 3, and a transfer unit 4.

  The first memory 1 connected to the common bus 11 is a video memory, in which display data representing an image to be displayed is recorded. In addition to the first memory 1, devices such as a USB controller and a LAN controller are connected to the common bus 11, but are not shown in FIG. 1.

  The second memory 2 connected to the local bus 12 is a main memory, and display data to be transferred to the first memory 1 is recorded.

  The writing unit 3 has a function of writing display data to the second memory 2 in response to a write command instructing writing of display data to the first memory 1.

  The transfer means 4 displays the display data recorded in the second memory 2 at a transfer frequency (transfer count per unit time) different from the display data write frequency (write count per unit time) to the second memory 2. Is transferred to the first memory 1. More specifically, the transfer unit 4 transfers the display data recorded in the second memory 2 to the first memory 1 with a transfer frequency lower than the display data write frequency to the second memory 2. It has a function.

  Note that the writing unit 3 and the transfer unit 4 can be realized by a CPU. In this case, for example, the following is performed. A disk, a semiconductor memory, and other recording media recording programs for causing the CPU to function as the writing unit 3 and the transfer unit 4 are prepared, and the CPU reads the program. The CPU realizes the writing unit 3 and the transfer unit 4 on its own CPU by controlling its own operation according to the read program.

  Next, the operation of the present embodiment will be described.

  When a write command for instructing writing of display data to the first memory 1 is input (step S21 in FIG. 2 is Yes), the writing means 3 writes the display data into the second memory (step S22). On the other hand, when a command other than the write command is input (No in step S21), the input command is executed as it is (step S23).

  On the other hand, as shown in the flowchart of FIG. 3, the transfer unit 4 displays the display data (for example, display data for one frame) recorded in the second memory 2 every time the transfer timing comes (Yes in step S31). ) Is transferred to the first memory 1 (step S32). Here, whether the transfer timing has come is determined based on, for example, whether a predetermined time has passed. The predetermined time is set such that the display data transfer frequency from the second memory 2 to the first memory 1 is lower than the display data write frequency to the second memory 2.

[Effect of the first embodiment]
According to the present embodiment, it is possible to obtain an effect that it is possible to reduce the risk that the common bus is occupied by the drawing process during high-frequency drawing. This is because the display data recorded in the second memory is transferred to the first memory at a transfer frequency lower than the display data write frequency to the second memory. That is, the transfer process from the second memory to the first memory is intentionally thinned out.

[Second embodiment of the present invention]
Next, an information processing apparatus according to the second embodiment of the present invention will be described.

  Referring to FIG. 4, in the information processing apparatus according to the present embodiment, a CPU 101, a main memory 102, and a south bridge 105 are connected to a north bridge 104 via buses (local buses) B1 to B3. Is provided with a virtual VRAM 103. A bus (common bus) B4 is connected to the south bridge 105, and a SAS controller 201, a LAN controller 202, a video controller 203, and a USB controller 204 are connected to the common bus B4. In addition, each of the controllers 201, 203, and 204 is connected to an HDD 211, a VRAM 212, and a USB device 213. In the information processing apparatus according to this embodiment, the application program 302, the video driver 303, the filter driver 304, and the driver 305 are operating on the operating system 301.

  The VRAM 212 functions as a first memory and records display data representing an image to be displayed. The virtual VRAM 103 provided on the main memory 102 functions as a second memory, and display data to be transferred to the VRAM 212 is written therein.

  The application program 302 has a function of issuing a drawing command for displaying the processing result.

  The video driver 303 has a function of creating a posted light command for displaying an image in accordance with a drawing command issued by the application program 302. The posted write command includes display data and an address on the VRAM 212 as a write address.

  The filter driver 304 functions as a writing unit, and displays a posted write command output from the video driver 303 into a write command for the virtual VRAM 103 on the main memory 102 or a converted write command. It has a function of writing data to the virtual VRAM 103. Since the write address included in the posted write command is an address on the VRAM 212, when the posted write command is converted into a write command for the virtual VRAM 103, the write address is a corresponding address on the virtual VRAM 103. Need to be converted to More specifically, the address is converted into an address on the virtual VRAM 103 by using a correspondence table showing a correspondence relationship between a predetermined address on the VRAM 212 and an address on the virtual VRAM 103 or an arithmetic expression.

  The driver 305 functions as a transfer unit, and has a function of transferring display data recorded in the virtual VRAM 103 to the VRAM 212 at a transfer frequency lower than the display data write frequency to the virtual VRAM 103. For example, when the display data writing frequency to the virtual VRAM 103 is 60 frames per second, the transfer frequency is set to 30 frames per second.

  Next, the operation of the present embodiment will be described in detail.

  When the application program 302 that operates on the operating system 301 outputs a drawing command to display the processing result, the operating system 301 that has detected the drawing command passes the drawing command to the video driver 303. As a result, the video driver 303 creates and outputs a posted write command for writing the display data to the VRAM 212.

  When a posted write command for writing display data to the VRAM 212 is output from the video driver 303 (step S51 in FIG. 5 is Yes), the filter driver 304 disposed below the video driver 303 outputs the posted write command. The command is converted into a write command for the virtual VRAM 103, and the converted write command is executed (step S52). As a result, the display data is written to the corresponding address in the virtual VRAM 212. If the command output from the video driver 303 is a command other than the posted write command for the VRAM 212 (No in step S51), the filter driver 304 executes the command as it is. In this embodiment, it is assumed that display data for one frame is written into the virtual VRAM every 1/60 seconds.

  On the other hand, the driver 305 for transferring the contents of the virtual VRAM 103 to the VRAM 212, as shown in the flowchart of FIG. 6, every time 1/30 seconds elapse (steps S61 to S63), for one frame recorded in the virtual VRAM 103. Are transferred to the VRAM 212.

  In the above-described embodiment, the transfer frequency from the virtual VRAM 103 to the VRAM 121 is set to one frame every 1/30 seconds. However, the transfer frequency is not limited to this as long as it is less than the write frequency to the virtual VRAM 103. Further, the transfer frequency may be a variable value that increases as the writing frequency increases (however, it needs to be lower than the writing frequency). More specifically, the filter driver 304 notifies the driver 305 of the display data writing frequency to the virtual VRAM 103, and the display recorded in the virtual VRAM 103 at a transfer frequency corresponding to the notified writing frequency. Data is transferred to the VRAM 212. Furthermore, as the transfer frequency, a fixed value smaller than the write frequency and smaller than the maximum bandwidth of the common bus B4 or a variable value smaller than the write frequency and smaller than the maximum bandwidth of the common bus B4 is used. You may make it do. Thus, by determining the transfer frequency in consideration of the maximum bandwidth of the common bus B4, it is possible to prevent the common bus B4 from being exclusively used for drawing processing.

[Effect of the second embodiment]
According to the present embodiment, it is possible to reduce the risk that the common bus is occupied by the drawing process during high-frequency drawing. This is because the display data written in the virtual VRAM is transferred to the VRAM on the common bus at a transfer frequency lower than the display data write frequency to the virtual VRAM on the main memory.

<Appendix>
A part or all of the above embodiment can be described as the following supplementary notes, but is not limited thereto.

(Appendix 1)
A first memory connected to a common bus;
A second memory connected to the local bus;
Writing means for writing display data to the second memory in response to a write command for instructing writing of display data to the first memory;
Transfer means for transferring display data recorded in the second memory to the first memory at a transfer frequency different from the display data write frequency to the second memory. Processing equipment.

(Appendix 2)
In the information processing apparatus according to attachment 1,
The information processing apparatus, wherein the transfer frequency is lower than a display data write frequency to the second memory.

(Appendix 3)
In the information processing apparatus according to appendix 1 or 2,
The write command includes an address on the first memory as a write address,
The writing means determines a write address included in the write command based on a predetermined correspondence relationship between the address on the first memory and the address on the second memory. An information processing apparatus that converts an address on a memory and writes display data to the converted address.

(Appendix 4)
In the information processing apparatus according to any one of appendices 1 to 3,
The information processing apparatus, wherein the transfer frequency is a fixed value.

(Appendix 5)
In the information processing apparatus according to any one of appendices 1 to 3,
The information processing apparatus, wherein the transfer frequency is a variable value that changes in accordance with the write frequency.

(Appendix 6)
In the information processing apparatus according to any one of appendices 1 to 5,
The information processing apparatus, wherein the write command is a posted write command.

(Appendix 7)
In response to a write command instructing writing of display data to the first memory connected to the common bus, the writing means writes the display data to the second memory connected to the local bus,
A drawing method, wherein the transfer means transfers the display data recorded in the second memory to the first memory at a transfer frequency different from the display data write frequency to the second memory.

(Appendix 8)
In the drawing method according to attachment 7,
The drawing method, wherein the transfer frequency is lower than a display data write frequency to the second memory.

(Appendix 9)
In the drawing method according to appendix 7 or 8,
The write command includes an address on the first memory as a write address,
The writing means determines a write address included in the write command based on a predetermined correspondence relationship between the address on the first memory and the address on the second memory. A drawing method characterized by converting to an address on a memory and writing display data to the converted address.

(Appendix 10)
In the drawing method according to any one of appendices 7 to 9,
The drawing method, wherein the transfer frequency is a fixed value.

(Appendix 11)
In the drawing method according to any one of appendices 7 to 9,
The drawing method, wherein the transfer frequency is a variable value that changes in accordance with the writing frequency.

(Appendix 12)
In the drawing method according to any one of appendices 7 to 11,
The drawing method, wherein the write command is a posted write command.

(Appendix 13)
A computer comprising a first memory connected to a common bus and a second memory connected to a local bus;
Writing means for writing display data to the second memory in response to a write command for instructing writing of display data to the first memory;
A program for functioning as transfer means for transferring display data recorded in the second memory to the first memory at a transfer frequency different from the writing frequency of display data to the second memory.

(Appendix 14)
In the program described in Appendix 13,
The program according to claim 1, wherein the transfer frequency is lower than a display data write frequency to the second memory.

(Appendix 15)
In the program described in Appendix 13 or 14,
The write command includes an address on the first memory as a write address,
The writing means determines a write address included in the write command based on a predetermined correspondence relationship between the address on the first memory and the address on the second memory. A program for converting to an address on a memory and writing display data to the converted address.

(Appendix 16)
In the program according to any one of appendices 13 to 15,
The transfer frequency is a fixed value.

(Appendix 17)
In the program according to any one of appendices 13 to 15,
The transfer frequency is a variable value that changes in accordance with the write frequency.

(Appendix 18)
In the program according to any one of appendices 13 to 17,
The program, wherein the write command is a posted write command.

  The present invention can be used when displaying an image in an information processing apparatus such as a computer, an FT server, or a portable terminal.

DESCRIPTION OF SYMBOLS 1 ... 1st memory 2 ... 2nd memory 3 ... Writing means 4 ... Transfer means 11 ... Common bus 12 ... Local bus 101 ... CPU
102: Main memory 103: Virtual VRAM
104: North Bridge 105 ... South Bridge 201 ... SAS Controller 202 ... LAN Controller 203 ... Video Controller 204 ... USB Controller 211 ... HDD
212 ... VRAM
213: USB device 301 ... Operating system 302 ... Application program 303 ... Video driver 304 ... Filter driver 305 ... Driver B1-B4 ... Bus

Claims (7)

A first memory connected to a common bus;
A second memory connected to the local bus;
Writing means for writing display data to the second memory in response to a write command for instructing writing of display data to the first memory;
The display recorded in the second memory at a frequency of data transfer in frame units that is a transfer frequency lower than the data write frequency in frame units that is the display data write frequency to the second memory An information processing apparatus comprising transfer means for transferring data to the first memory. The information processing apparatus according to claim 1 Symbol placement,
The write command includes an address on the first memory as a write address,
The writing means determines a write address included in the write command based on a predetermined correspondence relationship between the address on the first memory and the address on the second memory. An information processing apparatus that converts an address on a memory and writes display data to the converted address. The information processing apparatus according to claim 1 or 2 ,
The information processing apparatus, wherein the transfer frequency is a fixed value. The information processing apparatus according to claim 1 or 2 ,
The information processing apparatus, wherein the transfer frequency is a variable value that changes in accordance with the write frequency. The information processing apparatus according to any one of claims 1 to 4 ,
The information processing apparatus, wherein the write command is a posted write command. Writing means is responsive to a write command for instructing writing of display data to the first memory connected to the common bus, writing the display data in the second memory connected to local bus,
The transfer means records data in the second memory at a frequency of data transfer in frame units that is a transfer frequency lower than a data write frequency in frame units that is a display data write frequency in the second memory. A drawing method, wherein the displayed display data is transferred to the first memory. A computer comprising a first memory connected to a common bus and a second memory connected to a local bus;
Writing means for writing display data to the second memory in response to a write command for instructing writing of display data to the first memory;
The display recorded in the second memory at a frequency of data transfer in frame units that is a transfer frequency lower than the data write frequency in frame units that is the display data write frequency to the second memory A program for causing data to function as transfer means for transferring data to the first memory.

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