JP6292871B2 - Power measuring device - Google Patents

Description

  The present invention relates to a power measurement apparatus, and more particularly to improvement of measurement accuracy.

  FIG. 4 is a block diagram showing an example of a conventional power measuring apparatus. In FIG. 4, the entire power measuring apparatus includes an input unit 10, a calculation unit 20, and a CPU unit 30. The output signal of the input unit 10 is input to the calculation unit 20, and the calculation unit 20 is connected to the CPU unit 30 via a bus.

  The input unit 10 includes a voltage input unit 11, an A / D converter 12 that converts an analog signal output from the voltage input unit 11 into a digital signal, a current input unit 13, and an analog output from the current input unit 13. An A / D converter 14 for converting a signal into a digital signal, a voltage divider 15 connected to the outside of the voltage input terminal when measuring a high voltage, and a shunt connected to the outside of the current input terminal when measuring a large current 16.

  The voltage input unit 11 includes a voltage dividing resistor 11a and an operational amplifier 11b. The voltage divided output of the voltage dividing resistor 11a is normalized by the operational amplifier 11b and input to the A / D converter 12. The voltage divider 15 connected to the outside of the voltage input terminal at the time of measuring a high voltage converts a high voltage exceeding the input allowable range into a voltage within the input allowable range.

  The current input unit 13 includes a shunt resistor 13a and an operational amplifier 13b. The shunt output of the shunt resistor 13a is normalized by the operational amplifier 13b and input to the A / D converter 14. The shunt 16 connected to the outside of the current input terminal at the time of measuring a large current converts a large current exceeding the input allowable range into a current within the input allowable range. The outputs of these A / D converters 12 and 14 are input to the arithmetic unit 20.

  The arithmetic unit 20 is configured by an FPGA (Field Programmable Gate Array), and the outputs of the A / D converters 12 and 14 are input from a plurality of input units 10.

  The computing unit 20 includes a voltage computing unit 21 that computes an instantaneous voltage value based on the output of the A / D converter 12 of each input system, and a current that computes an instantaneous current value based on the output of the A / D converter 14. The calculation unit 22, the power calculation unit 23 that calculates the instantaneous value of power based on the outputs of the A / D converters 12 and 14, the instantaneous value calculated by the voltage calculation unit 21, the current calculation unit 22, and the power calculation unit 23 The instantaneous value storage unit 24 to store, the average value calculation unit 25 to calculate the average value of a predetermined section (for example, 50 msec to 20 sec) for the voltage value, current value, and power value stored in the instantaneous value storage unit 24, and the average An average value storage unit 26 that stores the average value calculated by the value calculation unit 25 is provided. The average value stored in the average value storage unit 26 is transferred and stored in the measurement data storage unit 34 of the CPU unit 30 in response to an interrupt from the CPU 31.

  Further, the calculation unit 20 is provided with an offset storage unit 27 in which the voltage offset value and the current offset value of each input system stored in the voltage offset storage unit 36 and the current offset storage unit 37 of the CPU unit 30 are transferred and stored. It has been. The voltage offset value and the current offset value transferred and stored in the offset storage unit 27 are used for instantaneous value calculation in the voltage calculation unit 21 and the current calculation unit 22.

  Further, the computing unit 20 is also provided with an FFT computing unit 28 that performs an FFT computation on digital signals input from a plurality of systems of input units 10 and divides the digital signal into a real part and an imaginary part.

  By implementing, for example, three systems of the input unit 10 and the calculation unit 20, the three phases can be measured simultaneously in parallel.

  The CPU unit 30 includes a CPU 31, an operation unit 32, a display unit 33, and the like that are connected to each other via a bus. The CPU 31 controls the overall operation of the apparatus. The operation unit 32 sets and inputs measurement conditions, offset processing conditions, and the like. The display unit 33 displays measurement conditions, offset processing conditions, measurement results, and the like.

  Further, the CPU unit 30 is provided with a measurement data storage unit 34, a measurement value calculation unit 35, a voltage offset storage unit 36, a current offset storage unit 37, an offset processing unit 38, and the like.

  As described above, the average value stored in the average value storage unit 26 is transferred and stored in the measurement data storage unit 34 in response to an interrupt from the CPU 31, and the real number unit calculated by the FFT calculation unit 28 is also stored. And imaginary part data, various calculation results in the measurement value calculation unit 35, and the like are also stored.

  The measurement value calculation unit 35 transfers various power, power factor, phase difference, etc. based on the voltage value, current value, average value of power value, data of real part and imaginary part, etc. transferred and stored in the measurement data storage part 34. Various parameters of the load circuit, harmonic content of voltage / current / active power, total harmonic distortion, and the like are calculated, and the calculation results are stored in the measurement data storage unit 34.

  In the voltage offset storage unit 36, when the voltage measurement range is changed according to the change of the voltage input signal, each input system measured in a state where the input terminal of the voltage divider 15 connected to the outside of the voltage input terminal is short-circuited. Stores the voltage offset value.

  In the current offset storage unit 37, when the current measurement range is changed in accordance with the change of the current input signal, each input system measured with the input terminal of the shunt 16 connected to the outside of the current input terminal short-circuited. Stores the current offset value.

  The offset processing unit 38 stores the average value of the voltage value and the current value transferred and stored in the measurement data storage unit 34 in the voltage offset value and current offset storage unit 37 stored in the voltage offset storage unit 36. DC offset compensation calculation processing of the voltage measurement value and the current measurement value based on the current offset value is performed. Specifically, the voltage offset value is subtracted from the average value of the voltage measurement values, and the current offset value is subtracted from the average value of the current measurement values.

The CPU 30 is also provided with a communication unit for transferring various data between the device and an external device, but not shown.

  FIG. 5 is a flowchart for explaining the flow of the harmonic measurement operation in the configuration of FIG. First, prior to the start of harmonic measurement, various parameters including measurement conditions are set (step S1).

  When the setting of various parameters of the measurement system for measuring harmonics is completed, it is determined whether or not a measurement start button (not shown) provided on the operation unit 32 has been pressed (step S2). When the measurement start button is pressed, harmonic measurement for the input signal is started, and the measured data of the harmonics measured is displayed on the display 33 (step S3).

  Each time harmonic measurement data is displayed, it is determined whether or not a measurement stop button (not shown) provided on the operation unit 32 has been pressed (step S4).

  In this way, the harmonic measurement operation is repeatedly executed until a depression of a measurement stop button (not shown) provided in the operation unit 32 is detected.

  When the depression of the measurement stop button is detected, the process returns to step S1 to wait for various parameter settings for performing the next measurement.

  In step S2, the process returns to step S1 until the measurement start button is detected to be depressed.

  Non-Patent Document 1 describes a configuration of a power measurement device that has harmonic measurement and can measure the efficiency of a three-phase inverter with a single unit.

  Patent Document 1 describes a power measurement device configured to compensate for a measurement error caused by a phase added by an input generation unit or the like.

  FIG. 6 is a block diagram showing an example of a conventional configuration in which the input unit is configured to be divided into a voltage measurement function and a current measurement function, and shows an example of the voltage measurement function. In FIG. 6, a plurality of attenuators 42 having different attenuation amounts are connected to an input terminal 41 for analog input signals. An amplifier 44 is connected to the output terminal of the attenuator 42 via a selector 43, and an A / D converter 45 is connected to the output terminal of the amplifier 44.

  The A / D converter 45 converts the analog signal output from the amplifier 44 into a digital signal according to the period of the sampling clock output from the clock generator 46.

  The range setting unit 46 switches the attenuation amount of the attenuator 42 and the gain of the amplifier 44 in association with each other so that a predetermined range is obtained.

Hisashi Iwase, Osamu Ito, Katsuya Tachibana, “Precision Power Analyzer WT3000”, Yokogawa Technical Report, Yokogawa Electric Corporation, January 20, 2005, Vol. No. 49 1 (2005) p. 17-20

JP 2000-338149 A

  By the way, as an important parameter in power measurement, there is a phase difference between voltage and current. In general, the phase difference is expressed by a phase angle (Deg), but the phase difference in the measuring instrument is nothing but a time delay. In a power measurement apparatus that measures power by measuring voltage and current simultaneously, it is essential to increase the measurement accuracy to make the delay difference between the voltage measurement channel and the current measurement channel zero.

  Expected to be analyzed as zero phase difference by inputting a zero phase difference signal to the power measurement device, but in reality, the attenuator constituting the input unit 10, the characteristics of the amplifier, the path length difference of the switching circuit As a result, the delay difference between the voltage and current channels changes, and this affects the measurement accuracy as a phase difference error.

  In recent years, with the development of inverter control technology, there is an increasing demand for power analysis and evaluation at a frequency higher than the conventional commercial frequency. When the frequency becomes high, the propagation delay of the measurement system affects as an error factor of the phase difference, and the influence cannot be ignored.

  Therefore, for example, although consideration is given so as to reduce the phase difference in the circuit wiring arrangement, a delay difference may occur depending on measurement conditions such as range switching.

  In order to cancel this delay difference, it is conceivable to switch and adjust the delay element for each range of the input signal. However, when there are a large number of ranges, many types of delay elements are required. Furthermore, a switching circuit or the like is required, and an increase in cost and deterioration of signal quality are expected.

  In addition, it is conceivable to adjust the delay of a digital signal obtained by converting an analog input signal by an A / D converter using a FIFO memory or the like. However, canceling a delay difference equal to or less than the sampling clock period of the A / D converter is not possible. Can not.

  The present invention solves such a problem, and an object of the present invention is to reduce a phase difference between a voltage and a current, which is an error factor in power measurement, that is, an input delay difference.

  An object is to minimize the phase difference with a resolution equal to or less than the sampling period without causing disturbance to the analog signal to be measured.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a power measurement apparatus comprising: a voltage measurement channel and a current measurement channel having a plurality of attenuators with different attenuation amounts; and A / D conversion means for converting a voltage or current input in each measurement channel into a digital signal.
A calculation unit configured by an FPGA and calculating power based on the voltage and current output from each measurement channel;
A range setting unit that switches the attenuation amount of the attenuator in conjunction with switching of the measurement range;
In conjunction with the range setting change of the range setting unit, variable delay means for delaying the timing of the sampling clock of the A / D conversion means ,
In the range setting unit, a compensation value for compensating a delay difference in each measurement channel is set as a delay amount to be set in the variable delay means,
The variable delay means uses a phase shift function of a PLL built in the FPGA.

  As a result, the phase difference can be minimized with a resolution equal to or lower than the sampling period without giving disturbance to the analog signal to be measured, and the measurement accuracy can be improved.

It is a block diagram which shows one Example of this invention. It is a wave form diagram which shows an example of the delay difference between the channels of a voltage and an electric current. It is explanatory drawing of the phase difference between the channels of a voltage and an electric current. It is a block diagram which shows an example of the conventional electric power measurement apparatus. 5 is a flowchart for explaining a flow of harmonic measurement operation in the configuration of FIG. 4. It is a block diagram which shows the structural example of the conventional voltage measurement function.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals are given to portions common to FIG. The difference between FIG. 1 and FIG. 6 is the presence or absence of the variable delay circuit 48 in the output system of the clock generator 47.

  A variable delay circuit 48 is provided in the clock terminal system of the A / D converter 45 of FIG. The variable delay circuit 48 delays the clock signal input from the clock generator 47 to the clock terminal of the A / D converter 45 for a predetermined time in conjunction with the range setting change of the range setting unit 46.

  In the range setting unit 46, a compensation value for compensating for a delay difference between the voltage and current channels obtained in advance in each measurement channel is set as a delay amount to be set in the variable delay circuit 48.

  Then, the sampling timing is changed by changing the phase of the clock of the A / D converter 45 in accordance with the delay amount of the variable delay circuit 48, the delay difference between the voltage and current channels is canceled, and the phase difference is zero. Is realized.

  Such a phase change of the clock can be easily set to a desired value with a resolution equal to or less than the sampling period by using, for example, a phase shift function of a PLL built in the FPGA.

  For example, when a voltage waveform and a current waveform are input to an A / D converter, if the current waveform reaches the A / D converter with a delay, the sampling timing of the voltage waveform is delayed according to the delay. As a result, the delay between the output data of the A / D converters is cancelled.

  In the embodiment of the voltage measurement function shown in FIG. 1, sampling is performed by changing the phase of the clock of the A / D converter 45 according to the delay amount of the variable delay circuit 48 according to the delay of the current waveform. The phase difference is made zero by canceling the delay difference between the voltage and current channels.

  FIG. 2 is a waveform diagram showing an example of the delay difference between the voltage and current channels. In FIG. 2, the current waveform I is delayed with respect to the voltage waveform V by a phase difference of 10 degrees.

  Therefore, the phase of the clock for sampling the voltage is shifted by 10 degrees according to the phase difference of 10 degrees between the voltage and current channels. Thereby, as shown in FIG. 3, the current waveform I and the voltage waveform V are sampled in the same phase.

  Since the delay amount for each range is usually known and unchanged, the phase difference between the voltage waveform and the current waveform can always be minimized by appropriately selecting the phase shift amount for each range setting.

  Moreover, although the example of the voltage measurement function block is shown in the above-described embodiment, a current measurement function block is also necessary for power measurement.

  In addition, by preparing a plurality of devices having the same configuration, it can be applied to single-phase power measurement and multi-phase power measurement.

  According to such a configuration, since the analog signal is not modified, timing adjustment can be performed without being affected by external effects such as attenuation and distortion due to a delay element, and the measurement accuracy can be improved.

  As described above, according to the present invention, it is possible to reduce an input delay difference that is a phase difference between a voltage and a current, which causes an error in power measurement, and to realize a power measurement device that can obtain an accurate power measurement result. it can.

41 Terminal 41
42 Attenuator 43 Selector 44 Amplifier 45 A / D Converter 46 Range Setting Unit 47 Clock Generation Unit 48 Variable Delay Circuit

Claims (1)

In a power measurement apparatus comprising: a voltage measurement channel and a current measurement channel having a plurality of attenuators with different attenuation amounts; and A / D conversion means for converting a voltage or current input in each measurement channel into a digital signal.
A calculation unit configured by an FPGA and calculating power based on the voltage and current output from each measurement channel;
A range setting unit that switches the attenuation amount of the attenuator in conjunction with switching of the measurement range;
In conjunction with the range setting change of the range setting unit, variable delay means for delaying the timing of the sampling clock of the A / D conversion means ,
In the range setting unit, a compensation value for compensating for a delay difference in each measurement channel is set as a delay amount to be set in the variable delay means,
The variable delay means uses a phase shift function of a PLL built in the FPGA.

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