JP6316145B2 - Processing apparatus and weight time measuring method - Google Patents

Description

  Embodiments described herein relate generally to a processing apparatus and a weight time measuring method.

  In an apparatus in which a main board having a processor and a peripheral board having a memory are combined, the bus wait time for the processor to access the memory varies depending on the combination of the main board and the peripheral board. This is due to the fact that the wiring buffer is different for each combination of the main board and the peripheral board. However, the conventional apparatus sometimes cannot improve the processing speed of the combined substrates.

JP 2004-220502 A JP 2004-326690 A

  The problem to be solved by the present invention is to provide a processing apparatus and a wait time measuring method capable of improving the processing speed of a combined substrate.

A processing apparatus according to an embodiment is a processing apparatus having a main board having a processor and a peripheral board having a plurality of memories, and includes a storage unit, a designation information reading unit, a trial unit, a wait time measuring unit, and a switching A part . The storage unit is provided on the peripheral board, and stores designation information that designates some or all of the plurality of memories. The designation information reading unit is provided on the main board and reads designation information from the peripheral board. The trial unit is provided on the main board, refers to the designation information read by the designation information reading unit, selects the memory designated by the designation information, and selects while changing the wait time of the bus for accessing the memory The data is written to the selected memory, and then the data is read from the selected memory. The wait time measurement unit is provided on the main board, and determines the wait time when the data read by the trial unit and the written data match as the wait time of the designated memory. The switching unit is provided on the main board, and switches the operation mode of the trial unit between a first operation mode and a second operation mode. The trial unit refers to the designation information in the first operation mode, selects the memory designated by the designation information, measures the wait time for the selected memory, and performs the second operation. In the mode, the wait time is measured for all the memories without referring to the designation information .

The block diagram of the processing apparatus in one Embodiment. FIG. 3 is a diagram of a memory map in one embodiment. 6 is a flowchart illustrating a wait time measurement mode in a case where a wait time during a write process and a wait time during a read process are individually set according to an embodiment. 9 is a flowchart illustrating a wait time measurement mode in the case where a wait time during a write process and a wait time during a read process are integrally set according to an embodiment. 6 is a flowchart illustrating a diagnosis mode when a wait time during a write process and a wait time during a read process are individually set according to an embodiment. 6 is a flowchart illustrating a diagnosis mode when a wait time during a write process and a wait time during a read process are set together in one embodiment.

Hereinafter, a processing apparatus and a wait time measuring method according to an embodiment will be described with reference to the drawings.
FIG. 1 is a configuration diagram of a processing apparatus 1 according to an embodiment. The processing device 1 is incorporated in, for example, an information processing device, a ticket gate, a checkout machine, an IC card charging machine, a mail sorting machine, or the like. The processing device 1 executes predetermined information processing. The predetermined information processing is, for example, image signal processing or audio signal processing. The ticket checker in which the processing device 1 is incorporated executes processing based on data recorded on an IC (Integrated Circuit) card or ticket. The checkout machine in which the processing device 1 is incorporated executes processing based on data such as electronic money and the amount of cash that has been input. The IC card charging machine in which the processing device 1 is incorporated executes processing for charging data such as electronic money, a commuter pass and a ticket to the IC card. The mail sorting machine in which the processing device 1 is incorporated executes sorting processing for mails and the like.

A configuration of the processing apparatus 1 will be described.
The processing apparatus 1 includes a peripheral substrate 10 and a main substrate 20. The processing apparatus 1 measures the wait time of a bus for accessing the memory of the peripheral substrate 10 from the main substrate 20 in a state where the peripheral substrate 10 and the main substrate 20 are combined. The wait time may be expressed in units such as microseconds, or may be expressed as the number of cycles of the clock signal.

  The peripheral board 10 includes at least one memory, a connector 13, and a storage unit 14. In FIG. 1, the peripheral substrate 10 includes a memory 11 and a memory 12. The peripheral board 10 may include more memories. Below, the case where the peripheral board | substrate 10 is provided with the memory 11 and the memory 12 as an example is demonstrated.

  The memory 11 includes, for example, a volatile storage medium (temporary storage medium) such as a RAM (Random Access Memory) and a register. The memory 11 may have a non-volatile storage medium (non-temporary storage medium) such as a flash memory. The same applies to the memory 12.

  The connector 13 is a connector for connecting the peripheral board 10 to the main board 20. That is, the connector 13 connects the memory 11, the memory 12, and the storage unit 14 to the main board 20.

  The storage unit 14 includes a nonvolatile storage medium (non-temporary storage medium) such as a flash memory. The storage unit 14 stores a memory map. This memory map is a memory map for a plurality of memories including the memory 11 and the memory 12 of the peripheral board 10. The storage unit 14 transfers the memory map to the main board 20 in accordance with a read enable signal output from the main board 20.

  FIG. 2 is a diagram of a memory map in one embodiment. The memory map includes information indicating the number of tables and table data. This memory map includes table data for each memory. That is, the number of tables represents the number of memories of the peripheral board 10. For example, when the number of memories on the peripheral board 10 is 2, the number of tables is 2.

  The table data M11 includes flag information of the table data M11, bus width information of the table data M11, start address information of the table data M11, and end address information of the table data M11. The flag information of the table data M11 includes information indicating that it is the head of the table data M11. The flag information of the table data M11 includes designation information that designates the memory 11. The designation information is determined, for example, when the peripheral substrate 10 is manufactured, and indicates whether or not the memory 11 needs to measure the wait time. The bus width information of the table data M11 is the bus width of the bus for accessing the memory 11. The bus width is 16 bits, for example. The start address information of the table data M11 is information representing the head address of the memory 11 when the memory 11 is accessed. The end address information of the table data M11 is information representing the final address of the memory 11 when the memory 11 is accessed.

  The table data M12 includes flag information of the table data M12, bus width information of the table data M12, start address information of the table data M12, and end address information of the table data M12. The flag information of the table data M12 includes information indicating the head of the table data M12. Further, the flag information of the table data M12 includes designation information for designating the memory 12. The designation information is determined, for example, when the peripheral substrate 10 is manufactured, and indicates whether or not the memory 12 needs to measure the wait time. The bus width information of the table data M12 is the bus width of the bus for accessing the memory 12. The start address information of the table data M12 is information representing the head address of the memory 12 when the memory 12 is accessed. The end address information of the table data M12 is information representing the final address of the memory 12 when the memory 12 is accessed.

  The main board 20 includes a connector 21, a switching unit 22, a memory 23, a processing unit 24, and a presentation unit 25. The connector 21 is a connector for connecting the peripheral board 10 to the main board 20.

  The switching unit 22 specifies the operation mode of the processing unit 24. The switching unit 22 is, for example, a DIP (Dual In-line Package) switch. The switching unit 22 outputs a signal for switching the operation mode of the processing unit 24 in accordance with an operation by the operator. The operation modes include, for example, a normal mode, a wait time measurement mode that is a first mode, and a diagnostic mode that is a second mode.

  The memory 23 includes, for example, a nonvolatile storage medium (non-temporary storage medium) such as a ROM (Read Only Memory) or a flash memory. The memory 23 may include, for example, a volatile storage medium (temporary storage medium) such as a RAM or a register. The memory 23 may temporarily store data stored in the memory 11 or the memory 12 of the peripheral substrate 10 based on control by the processing unit 24.

  The processing unit 24 is a software function unit that functions when a processor such as a CPU (Central Processing Unit) executes a program stored in the memory 23. The processing unit 24 may be a hardware function unit such as an LSI (Large Scale Integration) or an ASIC (Application Specific Integrated Circuit).

  The processing unit 24 includes a designation information reading unit 24a, a trial unit 24b, a wait time measurement unit 24c, a chip select pin CS0, and a chip select pin CS1. The chip select pin CS0 of the processing unit 24 is connected to the memory 11 of the peripheral substrate 10. When accessing the memory 11, the processing unit 24 can select the memory 11 by changing the output voltage of the chip select pin CS0. When writing data to the memory 11, the processing unit 24 outputs an address signal, a data signal, a chip select signal, and a write enable signal to the memory 11. When reading data from the memory 11, the processing unit 24 outputs an address signal, a chip select signal, and a read enable signal to the memory 11.

  The chip select pin CS1 of the processing unit 24 is connected to the memory 12 of the peripheral substrate 10. When accessing the memory 12, the processing unit 24 can select the memory 12 by changing the output voltage of the chip select pin CS1. When writing data into the memory 12, the processing unit 24 outputs an address signal, a data signal, a chip select signal, and a write enable signal to the memory 12. When reading data from the memory 12, the processing unit 24 outputs an address signal, a chip select signal, and a read enable signal to the memory 12.

  When the processing unit 24 is reset and activated in the normal mode, the processing unit 24 executes a predetermined process while being connected to the peripheral board 10. This predetermined process may be any process and is not limited to a specific process. This predetermined processing is, for example, predetermined information processing such as image processing. This predetermined process is a process based on data such as electronic money, for example, when the processing apparatus 1 is incorporated in a ticket gate.

  The designation information reading unit 24 a acquires the memory map from the storage unit 14 and stores the memory map in the memory 23 when it is reset and activated in the wait time measurement mode that is the first mode. Thereafter, the trial unit 24 b refers to the designation information included in the memory map stored in the memory 23. The trial unit 24b selects a memory designated by the designation information from a plurality of memories of the peripheral board 10. In other words, the trial unit 24b selects a memory that is designated by the designation information that the wait time needs to be measured. The wait time measurement unit 24 c measures the wait time of the bus for accessing the selected memory in a state where the peripheral board 10 is connected to the main board 20.

  The wait time measuring unit 24c determines whether the data has been read correctly. That is, the wait time measurement unit 24c determines whether the written data matches the read data. The wait time measurement unit 24c causes the presentation unit 25 to present the measured wait time when the data is correctly read.

  When the data is not read correctly, the trial unit 24b extends the wait time and executes data writing and reading again. The wait time measurement unit 24c performs another match check. When the wait time is not correctly read out even if the wait time is set to the longest time, the wait time measurement unit 24c causes the presentation unit 25 to present error information based on the wait time.

  The designation information reading unit 24a acquires the memory map from the storage unit 14 when it is reset and started in the diagnosis mode that is the second mode. The trial unit 24b does not refer to the designation information when activated in the diagnosis mode. The wait time measuring unit 24c diagnoses all the memories on the peripheral substrate 10 with the peripheral substrate 10 connected to the main substrate 20 to determine whether or not all the memories on the peripheral substrate 10 are accessible.

  The trial unit 24b writes predetermined data to all the memories on the peripheral board 10 while changing the wait time of the bus for accessing the selected memory. The trial unit 24b may write different data for each address of the selected memory. Thereafter, the trial unit 24b reads data from a memory selected from the plurality of memories of the peripheral substrate 10.

  The wait time measuring unit 24c determines whether the data has been read correctly. That is, the wait time measurement unit 24c determines whether the written data matches the read data. The wait time measurement unit 24c causes the presentation unit 25 to present information based on the wait time when the data is correctly read. When the data is not read correctly, the trial unit 24b extends the wait time and executes data writing and reading again. The wait time measurement unit 24c performs another match check. The wait time measurement unit 24c causes the presentation unit 25 to present error information based on the wait time when the wait time is not correctly read out even when the longest time is set.

  The presenting unit 25 presents the bus wait time when the data is correctly read out by the wait time measuring unit 24c. The presentation unit 25 may present error information based on the wait time. The error information is information indicating that the trial unit 24b cannot access the memory 11 or the memory 12 of the peripheral board 10. The presentation unit 25 is, for example, a 7-segment LED (Light Emitting Diode). The presentation unit 25 may have a liquid crystal screen, for example.

The operation of the processing apparatus 1 will be described.
FIG. 3 is a flowchart showing the wait time measurement mode in the case where the wait time during the writing process and the read wait time are individually set. That is, when the wait time during the writing process and the read wait time can be individually set as the specifications of the processing unit 24, the trial unit 24b performs the wait time measurement which is the first mode designated by the switching unit 22. As the process based on the mode, the process shown in FIG. 3 is executed.

The trial unit 24b is activated in the wait time measurement mode that is the first mode (step S101).
The designation information reading unit 24a receives the memory map information from the storage unit 14 of the peripheral board 10 (step S102).
The trial unit 24b minimizes the wait time during the writing process for the memory designated by the designation information included in the flag information among the memory 11 and the memory 12 of the peripheral board 10 (step S103). The shortest wait time is determined in advance as the specifications of the processing unit 24, bus, and memory. The trial unit 24b may minimize the wait time during the writing process for only a specific address of the designated memory.

The trial unit 24b maximizes the wait time during the read process for the memory designated by the designation information included in the flag information among the memory 11 and the memory 12 of the peripheral board 10 (step S104). The longest wait time is determined in advance as the specifications of the processing unit 24, bus, and memory.
The trial unit 24 b writes data to a predetermined address of a memory selected from the designated memory among the memory 11 and the memory 12 of the peripheral substrate 10. The predetermined address may be any address and is not limited to a specific address. Next, the trial unit 24b reads the written data (step S105).

  The wait time measuring unit 24c determines whether the written data has been read correctly. In other words, the wait time measuring unit 24c determines whether the written data and the read data match (step S106).

  If the written data does not match the read data (step S106: NO), the trial unit 24b increases the wait time during the writing process by a predetermined time (step S107). The predetermined time (time increment) is determined in advance as the specification of the processing unit 24. This predetermined time is expressed by, for example, an integral multiple of the clock cycle. The trial unit 24b returns the process to step S105.

When the written data matches the read data (step S106: YES), the wait time measurement unit 24c determines the wait time at that time as the wait time at the time of the writing process (step S108).
The trial unit 24b minimizes the wait time during the reading process for the designated memory out of the memory 11 and the memory 12 of the peripheral board 10 (step S109).

The trial unit 24 b writes data to a predetermined address of a memory selected from the designated memory among the memory 11 and the memory 12 of the peripheral substrate 10. The trial unit 24b reads the written data from the selected memory (step S110).
The wait time measuring unit 24c determines whether the written data has been read correctly. That is, the wait time measurement unit 24c determines whether the written data matches the read data (step S111).

  If the written data does not match the read data (step S110: NO), the trial unit 24b increases the wait time during the read process by a predetermined time (step S112). The predetermined time (time increment) is determined in advance as the specification of the processing unit 24. This predetermined time is expressed by, for example, an integral multiple of the clock cycle. The trial unit 24b returns the process to step S110.

  When the written data matches the read data (step S111: YES), the wait time measurement unit 24c uses the wait time when the written data matches the read data as the read processing time. The wait time is determined (step S113).

The wait time measurement unit 24c causes the presentation unit 25 to present the result of measuring the wait time during the determined write process and read process. The presentation unit 25 presents the wait time measured by the wait time measurement unit 24c (step S114).
The wait time measurement unit 24c determines whether or not the measurement of the wait time has been completed for all the memories designated by the designation information (step S113). When there is a memory that has not been measured among the designated memories, that is, when there is a memory that has not been measured (step S113: NO), the wait time measurement unit 24c returns the process to step S104. .
When the measurement results are presented for all the specified memories (step S113: YES), the trial unit 24b ends the process illustrated in FIG.

  FIG. 4 is a flowchart showing a wait time measurement mode in the case where the wait time at the time of writing and the wait time at the time of reading are set together. When the write processing wait time and the read wait time cannot be individually set as the specifications of the processing unit 24, the trial unit 24b performs processing based on the wait time measurement mode specified by the switching unit 22 as a process. 4 is executed.

The process of step S201 is the same as the process of step S101 shown in FIG.
The process in step S202 is the same as the process in step S102 shown in FIG.
The trial unit 24b minimizes the wait time during the writing process and the reading process for the designated memory out of the memory 11 and the memory 12 of the peripheral substrate 10 (step S203).
The process in step S204 is the same as the process in step S105 shown in FIG.
The process of step S205 is the same as the process of step S106 shown in FIG.

  When the written data and the read data do not match (step S205: NO), the trial unit 24b lengthens the wait time during the write process and the read process by a predetermined time (step S206). The predetermined time (time increment) is determined in advance as the specification of the processing unit 24. This predetermined time is expressed by, for example, an integral multiple of the clock cycle. The trial unit 24b returns the process to step S204.

  When the written data matches the read data (step S205: YES), the wait time measuring unit 24c determines the wait time when the written data matches the read data at the time of the writing process and The wait time for the read process is determined (step S207).

  The wait time measurement unit 24c causes the presentation unit 25 to present the result of measuring the wait time during the determined write process and read process. The presentation unit 25 presents the wait time measured by the wait time measurement unit 24c (step S208).

The wait time measurement unit 24c determines whether or not the presentation unit 25 has presented the measurement results for all specified memories (step S209). When there is a memory that does not present the measurement result among the designated memories, that is, when there is a memory that has not been measured (step S209: NO), the trial unit 24b returns the process to step S204.
When the measurement results are presented for all the specified memories (step S209: YES), the trial unit 24b ends the process illustrated in FIG.

  FIG. 5 is a flowchart showing a diagnosis mode in the case where the wait time during the writing process and the wait time during the reading process are individually set. When the wait time during the writing process and the read wait time can be individually set as the specifications of the processing unit 24, the trial unit 24b is shown in FIG. 5 as a process based on the diagnosis mode specified by the switching unit 22. Execute the process.

The trial unit 24b starts up in the diagnosis mode and copies data to the memory 23 of the main board 20 (step S301).
The designation information reading unit 24a receives the memory map information from the storage unit 14 of the peripheral board 10 (Step S202).
The trial unit 24b minimizes the wait time during the writing process for all the memories of the peripheral substrate 10 (step S303).

The trial unit 24b maximizes the wait time during the reading process for all the memories of the peripheral substrate 10 (step S304).
The trial unit 24b writes data to predetermined addresses in all the memories of the peripheral board 10. The trial unit 24b reads the written data from all the memories of the peripheral board 10 (step S305).

  The wait time measuring unit 24c determines whether the written data has been read correctly. That is, the wait time measurement unit 24c determines whether the written data matches the read data (step S306).

  If the written data does not match the read data (step S306: NO), the trial unit 24b increases the wait time during the writing process by a predetermined time (step S307). The predetermined time (time increment) is determined in advance as the specification of the processing unit 24. This predetermined time is expressed by, for example, an integral multiple of the clock cycle. The trial unit 24b returns the process to step S305.

When the written data matches the read data (step S306: YES), the wait time measurement unit 24c determines the wait time at that time as the wait time for the write process (step S308).
The trial unit 24b minimizes the wait time during the reading process for all the memories of the peripheral substrate 10 (step S309).

The trial unit 24 b writes data to a predetermined address of a memory selected from the designated memory among the memory 11 and the memory 12 of the peripheral substrate 10. The trial unit 24b reads the written data from the selected memory (step S310).
The wait time measuring unit 24c determines whether the written data has been read correctly. That is, the wait time measurement unit 24c determines whether the written data and the read data match (step S311).

  If the written data does not match the read data (step S311: NO), the trial unit 24b lengthens the wait time during the read process by a predetermined time (step S312). The predetermined time (time increment) is determined in advance as the specification of the processing unit 24. This predetermined time is expressed by, for example, an integral multiple of the clock cycle. The trial unit 24b returns the process to step S310.

  When the written data matches the read data (step S311: YES), the wait time measurement unit 24c determines the wait time at that time as the wait time for the read process (step S313).

The wait time measurement unit 24c causes the presentation unit 25 to present the result of measuring the wait time. The presenting unit 25 presents the wait time measured by the wait time measuring unit 24c (step S314).
The wait time measurement unit 24c determines whether measurement results have been presented for all the memories of the peripheral substrate 10 (step S315).

  When the measurement results are presented for all the specified memories (step S315: YES), the wait time measurement unit 24c determines whether or not the number of times the processing from step S304 to step S311 has been performed is within a predetermined number. (Step S316). This predetermined number of times is, for example, three times. Note that the wait time measurement unit 24c does not determine whether or not the number of times is within a predetermined number of times, but determines whether or not the number of times the processing from step S304 to step S315 has been performed is equal to or more than the predetermined number of times. Good.

  When it is determined that the number of executions of the processing from step S304 to step S315 is within a predetermined number (step S316: YES), the trial unit 24b stores the data in the memory of the main board 20 in the memory of the peripheral board 10. Write back (step S317). The trial unit 24b ends the process illustrated in FIG.

  When it is determined that the number of executions of the processing from step S304 to step S315 is not within the predetermined number (step S316: NO), the wait time measurement unit 24c displays error information on the presentation unit 25 (step S316). The trial unit 24b ends the process illustrated in FIG.

  When there is a memory that does not present the measurement result among the designated memories, that is, when there is a memory that has not been measured (step S315: NO), the trial unit 24b returns the process to step S304.

  FIG. 6 is a flowchart showing a diagnostic mode in the case where the wait time during the writing process and the wait time during the reading process are set together. When the wait time during the writing process and the read wait time cannot be individually set as the specifications of the processing unit 24, the trial unit 24b performs processing based on the diagnosis mode designated by the switching unit 22 as shown in FIG. The process to represent is executed.

The process in step S401 is the same as the process in step S301 shown in FIG.
The process of step S402 is the same as the process of step S302 shown in FIG.
The trial unit 24b minimizes the wait time during the writing process and the reading process for all the memories of the peripheral substrate 10 (step S403).
The process in step S404 is the same as the process in step S305 shown in FIG.
The processing in step S405 is the same as the processing in step S306 shown in FIG.

  If the written data does not match the read data (step S405: NO), the trial unit 24b increases the wait time during the writing process and the reading process by a predetermined time (step S406). The predetermined time (time increment) is determined in advance as the specification of the processing unit 24. This predetermined time is expressed by, for example, an integral multiple of the clock cycle. The trial unit 24b returns the process to step S404.

  When the written data matches the read data (step S405: YES), the wait time measuring unit 24c determines the wait time when the written data matches the read data at the time of the writing process and The wait time for the read process is determined (step S407).

  The wait time measurement unit 24c causes the presentation unit 25 to present the result of measuring the wait time during the determined write process and read process. The presentation unit 25 presents the wait time measured by the wait time measurement unit 24c (step S408).

  The wait time measurement unit 24c determines whether or not the presentation unit 25 has presented the measurement results for all specified memories (step S409). When there is a memory that does not present the measurement result among the designated memories, that is, when there is a memory that has not been measured (step S409: NO), the trial unit 24b returns the process to step S404.

  When the measurement results are presented for all the specified memories (step S409: YES), the wait time measurement unit 24c determines whether or not the number of times the processing from step S404 to step S409 has been performed is within a predetermined number. (Step S410). This predetermined number of times is, for example, three times. Note that the wait time measurement unit 24c does not determine whether or not the number of times is within a predetermined number of times, but determines whether or not the number of times the processing from step S404 to step S409 has been performed is equal to or more than the predetermined number of times. Good.

  When it is determined that the number of executions of the processing from step S404 to step S409 is within a predetermined number (step S410: YES), the trial unit 24b stores the data in the memory of the main board 20 in the memory of the peripheral board 10. Write back (step S411). The trial unit 24b ends the process illustrated in FIG.

  When it is determined that the number of times the processing from step S404 to step S409 has been executed is not within the predetermined number (step S410: NO), the wait time measurement unit 24c causes the presentation unit 25 to display error information (step S411). The trial unit 24b ends the process illustrated in FIG.

  When there is a memory that does not present the measurement result among the designated memories, that is, when there is a memory that has not been measured (step S409: NO), the trial unit 24b returns the process to step S404.

  As described above, the processing apparatus 1 according to the embodiment is a processing apparatus including the main substrate 20 having a processor and the peripheral substrate 10 having a plurality of memories, and includes a storage unit 14, a specified information reading unit 24a, A trial unit 24b and a wait time measurement unit 24c are provided. The storage unit 14 is provided in the peripheral substrate 10 and stores designation information for designating a part or all of the plurality of memories of the peripheral substrate 10. The designation information reading unit 24 a is provided on the main board 20 and reads designation information from the peripheral board 10. The trial unit 24b is provided on the main board 20 and refers to the designation information read by the designation information reading unit 24a. The trial unit 24b selects the memory designated by the designation information. The trial unit 24b writes data to the selected memory while changing the wait time of the bus for accessing the memory. The trial unit 24b reads data from the selected memory. The wait time measuring unit 24 c is provided on the main board 20. The wait time measuring unit 24c determines the wait time when the data read by the trial unit 24b matches the written data as the specified memory wait time.

  The wait time measuring method of the embodiment is a wait time measuring method in the processing apparatus 1 having the main substrate 20 having a processor and the peripheral substrate 10 having a plurality of memories, and includes a reading step and a determining step. In the reading step, the designation information reading unit 24 a is provided on the main board 20 and reads the designation information from the peripheral board 10. The trial unit 24b is provided on the main board 20 and refers to the designation information read by the designation information reading unit 24a. The trial unit 24b selects the memory designated by the designation information. The trial unit 24b writes data to the selected memory while changing the wait time of the bus for accessing the memory. The trial unit 24b reads data from the selected memory. In the determining step, the wait time measuring unit 24c determines the wait time when the data read by the trial unit 24b matches the written data as the wait time of the designated memory.

  With this configuration, the trial unit 24b refers to the designation information. The trial unit 24b selects the memory designated by the designation information. The trial unit 24b writes data to the selected memory while changing the wait time of the bus for accessing the memory. The trial unit 24b reads data from the selected memory. The processing apparatus 1 and the weight time measuring method of the embodiment can improve the processing speed of the combined substrates.

  The processing apparatus 1 and the wait time measuring method of the embodiment can set the wait time only for a memory that needs to set the wait time for a plurality of memories. The processing apparatus 1 and the wait time measuring method of the embodiment can reduce the time required for setting the wait time. The processing apparatus 1 and the wait time measuring method according to the embodiment can be started in the diagnosis mode and inspect all the memories on the peripheral board 10 when inspecting a memory defect.

The processing apparatus 1 of the embodiment can be expressed as follows.
A processing apparatus 1 having a main substrate 20 having a processor and a peripheral substrate 10 having a plurality of memories,
A storage unit 14 provided on the peripheral substrate 10 for storing designation information for selecting some or all of the plurality of memories of the peripheral substrate 10;
A designation information reading unit 24a provided on the main board 20 for reading the designation information from the peripheral board 10,
A trial unit 24b that is provided on the main board 20, refers to the designation information, selects a memory designated by the storage unit 14, and accesses the selected memory to obtain the shortest wait time;
A wait time measurement unit 24c that is provided on the main board 20 and determines the wait time when the data read by the trial unit 24b matches the written data as the wait time of the designated memory;
A processing apparatus comprising:

  According to the processing apparatus 1 of at least one embodiment described above, it is a trial unit 24b of a processing apparatus having a main substrate having a processor and a peripheral substrate having a plurality of memories. By selecting the memory specified by the above, and changing the wait time of the bus for accessing the memory, writing the data to the selected memory and then reading the data from the selected memory, the combination unit is provided. The processing speed in the processed substrate can be improved.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Processing apparatus, 10 ... Peripheral board | substrate, 11 ... Memory, 12 ... Memory, 13 ... Connector, 14 ... Memory | storage part, 20 ... Main board | substrate, 21 ... Connector, 22 ... Switching part, 23 ... Memory, 24 ... Control part, 24 ... Processing unit, 24a ... Specified information reading unit, 24b ... Trial unit, 24c ... Wait time measuring unit, 25 ... Presentation unit, M11 ... Table data, M12 ... Table data, CS0 ... Chip select pin, CS1 ... Chip select pin

Claims (5)

A processing apparatus having a main substrate having a processor and a peripheral substrate having a plurality of memories,
A storage unit that is provided on the peripheral substrate and stores designation information that designates some or all of the plurality of memories;
A designation information reading unit provided on the main board and reading the designation information from the peripheral board;
Provided on the main board, referring to the designation information read by the designation information reading unit, selecting a memory designated by the designation information, while changing a wait time of a bus for accessing the memory, A trial unit that writes data to the selected memory and then reads the data from the selected memory;
A wait time measurement unit that is provided on the main board and determines the wait time when the data read by the trial unit and the written data match, the wait time of the designated memory;
A switching unit that is provided on the main board and switches the operation mode of the trial unit between a first operation mode and a second operation mode;
With
The trial unit refers to the designation information in the first operation mode, selects the memory designated by the designation information, measures the wait time for the selected memory, and performs the second operation. The processing apparatus that measures the wait time for all the memories without referring to the designation information in the mode . The processing device according to claim 1 , wherein the trial unit writes different data to the memory for each address of the memory. Wherein provided on the main board further includes a presentation unit for presenting the wait time determined by the wait time measuring unit, the processing apparatus according to claim 1 or claim 2. The wait time measurement unit determines that the trial unit cannot access the memory if the read data does not match the written data even if the trial unit accesses the memory a predetermined number of times or more. The processing apparatus according to any one of claims 1 to 3 . A wait time measuring method in a processing apparatus having a main substrate having a processor and a peripheral substrate having a plurality of memories,
Wait time of a bus for reading designation information for designating a part or all of the plurality of memories, referring to the read designation information, selecting a memory designated by the designation information, and accessing the memory while changing the a trial step of the write data to the memory selected, reading the data from said memory the selected,
A wait time measurement step for determining the wait time when the read data and the written data match with the designated memory wait time;
A switching step of switching the operation mode in the trial step between the first operation mode and the second operation mode,
The designation information is referred to in the first operation mode, the memory designated by the designation information is selected, the wait time is measured for the selected memory, and the designation information is designated in the second operation mode. Measuring the wait time for all the memories without referring to
Wait time measurement method.

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