JP6316620B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor, and more particularly to a semiconductor device and a method for manufacturing the same.

  With the development of semiconductor manufacturing technology, miniaturization and high integration of semiconductor elements are required.

U.S. Pat. No. 8,288,816 U.S. Pat. No. 8,278,167

  The present invention has been made to meet the demands of the prior art, and an object of the present invention is to provide a semiconductor device that can be highly integrated by a simple process and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor device capable of reducing the chip area and a manufacturing method thereof.

  Another object of the present invention is to provide a semiconductor device capable of reducing a thermal burden and a manufacturing method thereof.

In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate having an upper surface and a lower surface opposite thereto, an upper circuit disposed on the upper surface of the semiconductor substrate, and a lower surface of the semiconductor substrate. A lower circuit disposed above; a vertical connection contact that electrically connects the upper circuit and the lower circuit through the semiconductor substrate; and the upper circuit and the lower circuit that pass through the semiconductor substrate. look including a an alignment key to retrieve the vertical alignment, the semiconductor substrate includes a arranged insulating film between the lower circuit and the upper circuit, the alignment key may be vertically through the insulating film It is characterized by .

  The upper circuit may include a cell array having cell transistors, and the lower circuit may include a peripheral circuit having peripheral transistors. The cell transistor may be vertically symmetric with respect to the semiconductor substrate and facing in the opposite direction to the peripheral transistor.

  In one embodiment, the cell array further includes a bit line electrically connected to the cell transistor, and the lower circuit further includes a metal line electrically connected to the peripheral transistor. it can. The connection contact may electrically connect the bit line and the metal wiring.

  In one embodiment, the support substrate attached on the lower circuit, the via penetrating the support substrate and connected to the metal wiring, and the support substrate disposed on the support substrate and connected to the via. And a pad. The metal wiring may be disposed between the semiconductor substrate and the support substrate.

  A method of manufacturing a semiconductor device according to another embodiment of the present invention provides a semiconductor substrate having a first surface and a second surface opposite to the first surface, penetrating the semiconductor substrate from the first surface to the first surface. Forming an insulating region extending toward two surfaces and not reaching the second surface; extending through the insulating region from the first surface toward the second surface; Forming an unaligned alignment key and a connection contact; forming a first circuit electrically connected to the connection contact on the first surface of the semiconductor substrate; and a support substrate on the first circuit. Forming a third surface exposing the insulating region, the alignment key, and the connection contact, and forming a third surface on the third surface of the semiconductor substrate by recessing the second surface of the semiconductor substrate. Second time to be electrically connected with the contact Including forming a.

  A semiconductor device according to another embodiment of the present invention includes a semiconductor substrate having an upper surface and a lower surface opposite to the upper surface, a cell array having cell transistors provided on the lower surface of the semiconductor substrate, and an upper surface of the semiconductor substrate. A peripheral circuit having peripheral transistors provided above; an alignment key extending from the top surface to the bottom surface to vertically align the cell array with the peripheral circuit; and extending from the first surface to the second surface. A connection contact electrically connecting the cell array to the peripheral circuit, and the cell transistor and the peripheral transistor are vertically symmetric with respect to the semiconductor substrate and facing in opposite directions.

  In another embodiment, the cell array further includes a bit line electrically connected to the cell transistor, and the peripheral circuit further includes a metal line electrically connected to the peripheral transistor, The connection contact may electrically connect the bit line to the metal wiring.

  In other embodiments, the cell array may further include a capacitor provided on the cell transistor, and the capacitor may be electrically connected to the cell transistor.

  A semiconductor device according to another embodiment of the present invention includes a semiconductor substrate having an upper surface and a lower surface opposite to the upper surface, an insulating region extending from the upper surface to the lower surface through the semiconductor substrate, and the insulating region An insulating alignment key extending from the upper surface to the lower surface through the conductive region, a conductive connection contact extending from the upper surface to the lower surface through the insulating region, and provided on the upper surface of the semiconductor substrate. A first circuit electrically connected to the connection contact; and a second circuit provided on the lower surface of the semiconductor substrate and electrically connected to the connection contact; A first circuit is vertically aligned with the second circuit.

In another embodiment, one of the first circuit and the second circuit includes a cell array having cell transistors, and the other includes a peripheral circuit having peripheral transistors. the a cell transistor and the peripheral transistor, Ru obtain a vertical symmetrical facing away around the semiconductor substrate.

  According to the present invention, the cell array and the peripheral circuit are separately disposed on both sides of the semiconductor substrate, thereby improving the degree of integration or reducing the chip area. Furthermore, the cell array and the peripheral circuit can be precisely vertically aligned, the thermal burden can be reduced, and the respective characteristics can be maximized, so that the electrical characteristics are improved.

It is sectional drawing which showed the manufacturing method of the semiconductor element by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by one Embodiment of this invention. It is sectional drawing which showed a part of FIG. It is sectional drawing which showed the modification of FIG. It is sectional drawing which showed the modification of FIG. It is sectional drawing which showed the semiconductor element different from this embodiment for the comparison. It is sectional drawing which showed the semiconductor element different from this embodiment for the comparison. It is sectional drawing which showed the semiconductor element different from this embodiment for the comparison. It is sectional drawing which showed a part of FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by other embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by other embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by other embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by other embodiment of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element by other embodiment of this invention. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. It is sectional drawing which showed the modification of FIG. It is sectional drawing which showed the modification of FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. It is sectional drawing which showed the modification of FIG. It is sectional drawing which showed the modification of FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the modification of FIG. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. It is sectional drawing which showed the manufacturing method of the image sensor by one Embodiment of this invention. 1 is a block diagram illustrating a memory card including a semiconductor device according to an embodiment of the present invention. 1 is a block diagram illustrating an information processing system to which a semiconductor element according to an embodiment of the present invention is applied. 1 is a block diagram illustrating an information processing system to which an image sensor according to an embodiment of the present invention is applied.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

  Advantages of the present invention over the prior art will become apparent through the detailed description and appended claims with reference to the accompanying drawings. In particular, the invention is apparent from the claims. The present invention may also be best understood by referring to the following detailed description in conjunction with the accompanying drawings. In the drawings, like reference numerals designate like elements throughout the various views.

<Embodiment 1>
1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing a part of FIG. 7 and 8 are cross-sectional views showing modifications of FIG.

  Referring to FIG. 1, a semiconductor substrate 100 having a first surface 100 a and a second surface 100 b opposite to the first surface 100 a is provided, and a field region 103 is formed in the semiconductor substrate 100. The semiconductor substrate 100 is a substrate containing silicon. The field region 103 has a trench shape that is filled with an insulator that extends from the first surface 100a to the second surface 100b and does not reach the second surface 100b.

  Referring to FIG. 2, the peripheral circuit 300 is formed on the first surface 100 a of the semiconductor substrate 100. Peripheral circuit 300 includes metal wiring 306. When the peripheral circuit 300 is formed, an alignment key 110 and a connection contact 107 are formed to vertically penetrate the field region 103 in parallel with each other. The alignment key 110 and the connection contact 107 are extended from the first surface 100a toward the second surface 100b. The alignment key 110 and the connection contact 107 may not reach the second surface 100b. The connection contact 107 is connected to the metal wiring 306 and is electrically connected to the peripheral circuit 300. The alignment key 110 includes an insulator, for example, and may not be electrically connected to the peripheral circuit 300.

  Referring to FIG. 3, a support substrate 80 is attached on the peripheral circuit 300 and the semiconductor substrate 100 is inverted. The peripheral circuit 300 and the semiconductor substrate 100 are sequentially stacked on the support substrate 80 in an inverted form. Therefore, the metal wiring 306 of the peripheral circuit 300 is adjacent to the support substrate 80, and the second surface 100b of the semiconductor substrate 100 faces upward. The support substrate 80 does not ask | require the kind. For example, the support substrate 80 is a silicon substrate or a non-silicon substrate (eg, glass or resin substrate).

  Referring to FIG. 4, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100 b is recessed by chemical mechanical polishing, grinding, etch back, or the like in a state where the semiconductor substrate 100 is supported by the support substrate 80. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c. The field region 103 may be exposed through the third surface 100c or may not be exposed.

  Referring to FIG. 5, the cell array 200 that is electrically connected to the connection contact 107 is formed on the third surface 100 c of the semiconductor substrate 100. The cell array 200 includes a memory circuit such as a DRAM and a flash, a logic circuit such as a central processing unit CPU and an application processor AP, a photodiode of a CMOS image sensor (CMOS Image Sensor), and the like. The cell array 200 is vertically aligned with the peripheral circuit 300 by the alignment key 110 and electrically connected to the peripheral circuit 300 by the connection contact 107. Through the series of steps, the semiconductor device 1 is manufactured in which the peripheral circuit 300 is disposed under the first surface 100a of the semiconductor substrate 100 and the cell array 200 is disposed over the third surface 100c. The semiconductor element 1 has a COP (Cell On Peripheral) structure in which a cell array 200 is stacked on a peripheral circuit 300 on a support substrate 80.

  The metal wiring 306 is disposed between the support substrate 80 and the semiconductor substrate 100, for example, adjacent to the support substrate 80. The heat generated in the semiconductor element 1 is more discharged in the direction B toward the support substrate 80 through the metal wiring 306 than in the direction A toward the cell array 200. The support substrate 80 serves as a heat sink. Therefore, most of the heat generated in the semiconductor device 1 is discharged toward the support substrate 80, whereby the cell array 200 and the peripheral circuit 300 are free from malfunction due to thermal stress or minimized.

  According to this embodiment, the process of forming the cell array 200 and the process of forming the peripheral circuit 300 are separated. Therefore, the process recipe can be appropriately adjusted to meet the characteristics of the cell array 200 and the peripheral circuit 300, such as design rules, heat budget, and deposition conditions.

  Referring to FIG. 6, the cell array 200 can include a cell transistor 205 covered with an insulating film 208, and the peripheral circuit 300 includes a peripheral transistor 305 covered with an insulating film 308. The cell transistor 205 has a structure in which the peripheral transistor 305 is disposed upside down. The cell transistor 205 disposed on the third surface 100c of the semiconductor substrate 100 faces upward, and the peripheral transistor 305 disposed on the first surface 100a of the semiconductor substrate 100 faces downward. The cell transistor 205 and the peripheral transistor 305 may be vertically symmetric. As used herein, “vertical symmetry” refers to a back-to-back arrangement. For example, “vertical symmetry” means that the cell array 200 defined by the formation direction and the lower region of the peripheral circuit 300 are opposed to each other on the third surface 100c and the first surface 100a of the semiconductor substrate 100. The cell array 200 defined by the above and the upper region of the peripheral circuit 300 are directed in opposite directions.

  Referring to FIG. 7, it is possible to manufacture a semiconductor device 1 a further including a via 92 that penetrates the support substrate 80 and is connected to the metal wiring 306, and a pad 94 that is connected to the via 92 on the support substrate 80. In this case, heat is more easily discharged toward the support substrate 80. An external device such as a printed circuit board or another semiconductor element is electrically connected to the semiconductor element 1 a by being connected to the pad 94.

  Referring to FIG. 8, the support substrate 80 is removed. Then, vias 92 connected to the metal wiring 306 through the insulating film (308 in FIG. 6) constituting the peripheral circuit 300 and pads 94 connected to the vias 92 are formed on the insulating film 308 to form the semiconductor element. 1b can be manufactured.

<Comparison between Embodiment 1 and General Example>
9 to 11 are sectional views showing semiconductor elements different from the present embodiment for comparison. FIG. 12 is a cross-sectional view showing a part of FIG.

  Referring to FIG. 9, the semiconductor element 9a includes a cell array 20 and a peripheral circuit 30 disposed on any one surface of the semiconductor substrate 10, for example, the first surface 10a. In contrast, according to the present embodiment, the peripheral circuit 300 may be disposed on the first surface 100a of the semiconductor substrate 100 and the cell array 200 may be disposed on the third surface 100c as illustrated in FIG. As shown in FIG. 5, the cell array 200 and the peripheral circuit 300 may have an increased number of net dies and integration and / or may be reduced as compared with the cell array 20 and the peripheral circuit 30 of FIG. 9. Have a large area.

  The present invention is not intended to be limited to this, and as an example only, does the cell array 200 of the present embodiment have twice the degree of integration or twice the number of net dies compared to the general cell array 20? Or occupy 1/2 times the area. Similarly, the peripheral circuit 300 of the present embodiment has twice the degree of integration, twice the number of net dies, or occupies 1/2 the area as compared to the general peripheral circuit 30.

  Referring to FIG. 10, the semiconductor element 9 b is formed on the first cell array 21 and the first peripheral circuit 31, which are horizontally disposed on the first surface 10 a of the semiconductor substrate 10, on the first cell array 21 and the first peripheral circuit 31. The second cell array 22 and the second peripheral circuit 32 that are vertically stacked may be included. In this case, in order to form the second cell array 22 and the second peripheral circuit 32, a step of forming or attaching a single crystal semiconductor film is further required. Furthermore, a plurality of through-electrodes 21a and 22a for electrically connecting the first cell array 21 and the second cell array 22 stacked vertically and / or the first peripheral circuit 31 and the second peripheral circuit 32 stacked vertically. Further, a process of forming a plurality of through electrodes 31a and 32a for electrically connecting the two is required. Unlike this, the present embodiment forms the peripheral circuit 300 and the cell array 200 on both surfaces 100a and 100c of the semiconductor substrate 100 as shown in FIG. Accordingly, it is not necessary to separately form a single crystal semiconductor film or to attach the single crystal semiconductor film and to form a through electrode.

  Referring to FIG. 11, the semiconductor element 9 c includes a peripheral circuit 30 and a cell array 20 that are vertically stacked sequentially on the first surface 10 a of the semiconductor substrate 10 or in the reverse order. In this case, as shown in FIG. 12, the single crystal semiconductor film 12 for forming the cell array 20 must be formed on or attached to the peripheral circuit 30. A process for forming the alignment key 11 is required after the single crystal semiconductor film 12 is formed or attached thereon. Unlike this, the present embodiment forms the peripheral circuit 300 and the cell array 200 on both surfaces 100a and 100c of the semiconductor substrate 100 as shown in FIG. Accordingly, it is not necessary to separately form or attach a single crystal semiconductor film. As shown in FIG. 11, the metal wiring 36 is disposed between the peripheral circuit 30 and the cell array 20, so that heat is discharged in the cell array direction A and the peripheral circuit direction B. As a result, the semiconductor element 9c has a greater thermal stress applied to the cell array 20 and the peripheral circuit 30 than the semiconductor element 1 of the present embodiment in which the support substrate 80 plays a heat sink.

  In the semiconductor element 9 c, as shown in FIG. 12, the peripheral circuit 30 includes the peripheral transistor 35 covered with the insulating film 38, and the cell array 20 includes the cell transistor 25 covered with the insulating film 28. Since the cell array 20 is vertically stacked on the peripheral circuit 30, the peripheral transistor 35 faces upward on the semiconductor substrate 10, and the cell transistor 25 faces upward on the single crystal semiconductor film 12. In other words, the cell transistor 25 and the peripheral transistor 35 are arranged in a back-to-front form unlike the back-to-back arrangement of the present embodiment.

<Embodiment 2>
13 to 19 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

  Referring to FIG. 13, a semiconductor substrate 100 having a first surface 100 a and a second surface 100 b opposite to the first surface 100 a is provided, and a field region 103 is formed in the semiconductor substrate 100.

  Referring to FIG. 14, a cell transistor layer 210 including cell transistors is formed on the first surface 100 a of the semiconductor substrate 100. When the cell transistor layer 210 is formed, an alignment key 110 and a connection contact 107 are formed to vertically penetrate the field region 103 in parallel with each other. The alignment key 110 and the connection contact 107 are perpendicular to the second surface 100b from the first surface 100a and may not reach the second surface 100b. The connection contact 107 is electrically connected to the cell transistor layer 210.

  Referring to FIG. 15, the first support substrate 81 is attached on the cell transistor layer 210 and the semiconductor substrate 100 is inverted. The cell transistor layer 210 and the semiconductor substrate 100 are sequentially stacked in an inverted form on the first support substrate 81. The first support substrate 81 includes a suitable material. For example, the first support substrate 81 may be a silicon substrate or a non-silicon substrate (eg, a glass substrate).

  Referring to FIG. 16, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100 b is recessed in a state where the semiconductor substrate 100 is supported by the first support substrate 81. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 17, a peripheral circuit 300 including a peripheral transistor electrically connected to the connection contact 107 is formed on the third surface 100 c of the semiconductor substrate 100. Peripheral circuit 300 may be aligned with cell transistor layer 210 by alignment key 110. The peripheral circuit 300 further includes a metal wiring 306 connected to the connection contact 107. The peripheral circuit 300 is electrically connected to the cell transistor layer 210 by the connection contact 107.

  Referring to FIG. 18, a second support substrate 82 is attached on the peripheral circuit 300, and the semiconductor substrate 100 is inverted again. The metal wiring 306 is disposed between the second support substrate 82 and the semiconductor substrate 100. The second support substrate 82 includes a suitable material. For example, the second support substrate 82 may be a silicon substrate or a non-silicon substrate (eg, glass or resin substrate). The first support substrate 81 is removed.

  Referring to FIG. 19, a capacitor layer 220 including a capacitor electrically connected to the cell transistor is formed on the cell transistor layer 210. A cell array 200 including a cell transistor layer 210 and a capacitor layer 220 is formed on the first surface 100 a of the semiconductor substrate 100. Through the series of steps, the semiconductor device 2 in which the cell array 200 is disposed on the first surface 100a of the semiconductor substrate 100 and the peripheral circuit 300 is disposed on the third surface 100c is manufactured. The semiconductor element 2 has a COP (Cell On Peripheral) structure in which the cell array 200 is stacked on the peripheral circuit 300 on the second support substrate 82.

  According to this embodiment, the thermal burden can be reduced by separating the transistor process and the capacitor process. For example, the thermal burden applied to the capacitor is suppressed by performing the process of forming the capacitor layer 220 as a low temperature process after the process of forming the cell transistor layer 210 and the peripheral circuit 300 as a high temperature process, or Can be minimized.

  Furthermore, as described with reference to FIG. 6, the cell transistors of the cell array 200 and the peripheral transistors of the peripheral circuit 300 are arranged in a back-to-back manner, and will be described with reference to FIG. 7 or FIG. 8. As described above, the via 92 and the pad 94 that are electrically connected to the metal wiring 306 can be further formed.

<Embodiment 3>
20 to 24 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

  Referring to FIG. 20, a semiconductor substrate 100 having a first surface 100 a and a second surface 100 b opposite to the first surface 100 a is provided, and a field region 103 is formed in the semiconductor substrate 100.

  Referring to FIG. 21, the cell array 200 is formed on the first surface 100 a of the semiconductor substrate 100. When the cell array 200 is formed, an alignment key 110 and a connection contact 107 are formed to vertically penetrate the field region 103 in parallel with each other. The alignment key 110 and the connection contact 107 are perpendicular to the second surface 100b from the first surface 100a and may not reach the second surface 100b. The connection contact 107 is electrically connected to the cell array 200.

  Referring to FIG. 22, a support substrate 80 is attached on the cell array 200 and the semiconductor substrate 100 is inverted. The cell array 200 and the semiconductor substrate 100 are sequentially stacked in an inverted form on the support substrate 80.

  Referring to FIG. 23, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100 b is polished in a state where the semiconductor substrate 100 is supported by the support substrate 80. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 24, the peripheral circuit 300 that is electrically connected to the connection contact 107 is formed on the third surface 100 c of the semiconductor substrate 100. Peripheral circuit 300 is aligned with cell array 200 by alignment key 110. Peripheral circuit 300 includes metal wiring 306 connected to connection contact 107. Peripheral circuit 300 is electrically connected to cell array 200 by connection contact 107. Through the series of steps, the semiconductor device 3 is manufactured in which the cell array 200 is disposed below the first surface 100a of the semiconductor substrate 100 and the peripheral circuit 300 is disposed above the second surface 100b. The semiconductor element 3 has a POC (Peripheral on Cell) structure in which a peripheral circuit 300 is stacked on a cell array 200 on a support substrate 80.

  According to the present embodiment, the metal wiring 306 is disposed in the uppermost layer of the semiconductor element 3, whereby heat generated in the semiconductor element 3 is exhausted to the outside of the semiconductor element 3. Most of the heat generated in the semiconductor element 3 is discharged outward. Therefore, the cell array 200 and the peripheral circuit 300 can eliminate or minimize the malfunction due to the thermal stress.

<Manufacturing Example 1 of Semiconductor Memory Element>
25 to 29 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 30 and 31 are sectional views showing modifications of FIG.

  Referring to FIG. 25, a semiconductor substrate 100 having a first surface 100 a and a second surface 100 b opposite to the first surface 100 a is provided, and a field region 103 is formed in the semiconductor substrate 100. The semiconductor substrate 100 may be a silicon substrate, a single crystal silicon substrate doped with impurities (eg, p-type dopant), or an SOI substrate. A field region 103 is formed and an element isolation film 302 is further formed. The field region 103 and the element isolation film 302 have a trench shape that is filled with an insulator that extends from the first surface 100a to the second surface 100b and does not reach the second surface 100b. The field region 103 has a deeper depth than the element isolation film 302.

  Referring to FIG. 26, the peripheral circuit 300 is formed on the first surface 100 a of the semiconductor substrate 100. The peripheral circuit 300 is formed by the peripheral transistor 305 including the gate 304 on the first surface 100 a, the metal wiring 306 electrically connected to the peripheral transistor 305, and the insulating film 308 covering the peripheral transistor 305 and the metal wiring 306. Forming. When the peripheral circuit 300 is formed, the alignment key 110 and the connection contact 107 are formed. The alignment key 110 and the connection contact 107 extend vertically from the first surface 100a to the second surface 100b through the field region 103 and spaced vertically from each other. The connection contact 107 is electrically connected to the peripheral circuit 300 by being connected to the peripheral transistor 305 or the metal wiring 306. According to an example, the connection contact 107 can be formed simultaneously with the metal wiring 306. The alignment key 110 can be made of an insulator.

  Referring to FIG. 27, a support substrate 80 is attached on the peripheral circuit 300, and the semiconductor substrate 100 is inverted. The peripheral circuit 300 and the semiconductor substrate 100 are sequentially stacked on the support substrate 80 in an inverted form. The metal wiring 306 is adjacent to the support substrate 80 and is directed downward, and the second surface 100b of the semiconductor substrate 100 is directed upward.

  Referring to FIG. 28, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100b is recessed by etch back, chemical mechanical polishing, grinding, or the like in a state where the semiconductor substrate 100 is supported by the support substrate 80. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 29, the cell array 200 is formed on the third surface 100 c of the semiconductor substrate 100. The cell array 200 includes a cell transistor 205 including a recessed gate 204 under the third surface 100c, a bit line 206 and a capacitor 209 electrically connected to the cell transistor 205, a cell transistor 205, and a bit line. It includes forming an insulating film 208 covering 206 and the capacitor 209. The cell array 200 may be a memory cell array. The cell array 200 is formed in alignment with the peripheral circuit 300 by the alignment key 110. By connecting the bit line 206 to the connection contact 107, the cell array 200 and the peripheral circuit 300 are electrically connected. According to this embodiment, the peripheral transistor 305 is formed on the first surface 100a of the semiconductor substrate 100, and the cell transistor 205 is formed on the third surface 100c. The peripheral transistor 305 and the cell transistor 205 are arranged back to back as shown in FIG.

  According to the present embodiment, the COP (Cell On Peripheral) semiconductor element 1000 in which the cell array 200 is stacked on the peripheral circuit 300 on the support substrate 80 is formed in the same or similar manner as described with reference to FIGS. Is done. The metal wiring 306 is disposed adjacent to the support substrate 80, so that the support substrate 80 can serve as a heat sink.

  As a modification, as shown in FIG. 30, a semiconductor device 1000 a can be manufactured that further includes a via 92 that is connected to the metal wiring 306 through the support substrate 80, and a pad 94 that is connected to the via 92. . Heat is more easily discharged to the support substrate 80 through the via 92.

  As another modification, as shown in FIG. 31, the support substrate 80 is removed, the via 92 connected to the metal wiring 306 through a part of the insulating film 308, and the via 92 connected to the insulating film 308. The pad 94 can be formed to manufacture the semiconductor element 1000b.

<Manufacturing Example 2 of Semiconductor Memory Device>
32 to 38 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. 39 and 40 are sectional views showing a modification of FIG.

  Referring to FIG. 32, a semiconductor substrate 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a is provided. A field region 103 having a deep depth and an element isolation having a shallow depth are provided in the semiconductor substrate 100. A film 202 is formed.

  Referring to FIG. 33, the cell transistor layer 210 is formed on the first surface 100 a of the semiconductor substrate 100. Forming the cell transistor layer 210 includes a cell transistor 205 including a recessed gate 204 under the first surface 100a, a bit line 206 electrically connected to the cell transistor 205, and the cell transistor 205 and the bit line 206. Forming an insulating film 208 covering the substrate. When the cell transistor layer 210 is formed, an alignment key 110 and a connection contact 107 are formed to vertically penetrate the field region 103 in parallel with each other. The connection contact 107 is connected to the bit line 206 and is electrically connected to the cell transistor layer 210. According to an example, the connecting contact 107 can be formed simultaneously with the bit line 206.

  Referring to FIG. 34, a first support substrate 81 is attached on the cell transistor layer 210, and the semiconductor substrate 100 is inverted. The cell transistor layer 210 and the semiconductor substrate 100 are sequentially stacked in an inverted form on the first support substrate 81.

  Referring to FIG. 35, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100 b is recessed in a state where the semiconductor substrate 100 is supported by the first support substrate 81. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 36, the peripheral circuit 300 that is electrically connected to the connection contact 107 is formed on the third surface 100 c of the semiconductor substrate 100. Forming the peripheral circuit 300 includes forming the peripheral transistor 305 including the gate 304 on the third surface 100 c of the semiconductor substrate 100, the metal wiring 306 electrically connected to the peripheral transistor 305, and the peripheral transistor 305 and the metal wiring 306. It includes forming the insulating film 308 to be covered. Peripheral circuit 300 is aligned with cell transistor layer 210 by alignment key 110. The metal wiring 306 is connected to the connection contact 107 and is electrically connected to the cell transistor 205. The peripheral circuit 300 is electrically connected to the cell transistor layer 210 by the connection contact 107.

  Referring to FIG. 37, a second support substrate 82 is attached on the peripheral circuit 300, and the semiconductor substrate 100 is inverted again. The metal wiring 306 is disposed between the semiconductor substrate 100 and the second support substrate 82. The first support substrate 81 is removed.

  Referring to FIG. 38, a capacitor 209 electrically connected to the cell transistor 205 is formed. A cell array 200 including a cell transistor 205, a bit line 206, and a capacitor 209, that is, a memory cell array is formed on the first surface 100 a of the semiconductor substrate 100. According to the series of steps, the cell array 200 is disposed on the first surface 100a of the semiconductor substrate 100 and the peripheral circuit 300 is disposed on the third surface 100c in the same or similar manner as described in FIGS. The semiconductor device 2000 to be manufactured is manufactured. The semiconductor element 2000 has a COP (Cell On Peripheral) structure in which the cell array 200 is stacked on the peripheral circuit 300 on the second support substrate 82. The semiconductor element 2000 is substantially the same as the semiconductor element 1000 of FIG.

  According to the present embodiment, the thermal burden applied to the capacitor 209 is reduced by performing the process of forming the capacitor 209 as a low temperature process after the process of forming the cell transistor 205 and the peripheral transistor 305 as a high temperature process. it can. The cell transistor 205 is formed on the first surface 100a of the semiconductor substrate 100, and the peripheral transistor 305 is formed on the third surface 100c. The cell transistor 205 and the peripheral transistor 305 are arranged back to back as shown in FIG.

  As a modification, as shown in FIG. 39, a semiconductor device 2000a can be manufactured that further includes a via 92 that penetrates through the second support substrate 82 and is connected to the metal wiring 306, and a pad 94 that is connected to the via 92. . Heat is more easily discharged through the vias 92 toward the second support substrate 82.

  As another modification, as shown in FIG. 40, the second support substrate 82 is removed, and the semiconductor element 2000b in which the via 92 partially penetrates the insulating film 308 and is connected to the metal wiring 306 can be manufactured.

<Manufacturing Example 3 of Semiconductor Memory Device>
41 to 45 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention.

  Referring to FIG. 41, a semiconductor substrate 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a is provided, and a field region 103 having a deep depth and an element isolation having a shallow depth are provided in the semiconductor substrate 100. A film 202 is formed.

  Referring to FIG. 42, the cell array 200 is formed on the first surface 100 a of the semiconductor substrate 100. The formation of the cell array 200 includes a cell transistor 205 including a recessed gate 204 under the first surface 100a, a bit line 206 electrically connected to the cell transistor 205, and an insulation covering the cell transistor 205 and the bit line 206. Forming a film 208. When the cell array 200 is formed, an alignment key 110 and a connection contact 107 are formed to vertically penetrate the field region 103 in parallel with each other. The connection contact 107 is electrically connected to the cell transistor 205. According to one example, the connecting contact 107 is formed simultaneously with the bit line 206.

  Referring to FIG. 43, a support substrate 80 is attached on the cell array 200, and the semiconductor substrate 100 is inverted. The cell array 200 and the semiconductor substrate 100 are sequentially stacked on the support substrate 80 in an inverted form.

  Referring to FIG. 44, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100b is recessed by etch back, chemical mechanical polishing, grinding, or the like in a state where the semiconductor substrate 100 is supported by the support substrate 80. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 45, the peripheral circuit 300 is formed on the third surface 100 c of the semiconductor substrate 100. The peripheral circuit 300 is formed by the peripheral transistor 305 including the gate 304 on the third surface 100 c, the metal wiring 306 electrically connected to the peripheral transistor 305, and the insulating film 308 covering the peripheral transistor 305 and the metal wiring 306. Forming. The peripheral circuit 300 is formed in alignment with the cell array 200 by the alignment key 110. The metal wiring 306 is connected to the connection contact 107 and is electrically connected to the bit line 206 or the cell transistor 205. Peripheral circuit 300 is electrically connected to cell array 200 by connection contact 107. When the peripheral circuit 300 is formed, a thermal process applied to the capacitor 209 can be minimized by adopting a low temperature process or appropriately adjusting a process recipe.

  Through the series of processes, the semiconductor element 3000 is manufactured in which the peripheral transistor 305 is disposed on the third surface 100c of the semiconductor substrate 100 and the cell transistor 205 is disposed on the first surface 100a. The semiconductor element 3000 has a POC (Peripheral On Cell) structure in which the peripheral circuit 300 is stacked on the cell array 200 on the support substrate 80. The peripheral transistor 305 and the cell transistor 205 are arranged back to back as shown in FIG.

  According to the present embodiment, since the metal wiring 306 is disposed on the uppermost layer of the semiconductor element 3000, heat dissipation is easily performed. The cell array 200 and the peripheral circuit 300 can eliminate or minimize malfunction caused by thermal stress.

<Image sensor manufacturing example 1>
46 to 50 are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. FIG. 51 is a cross-sectional view showing a modification of FIG.

  Referring to FIG. 46, a semiconductor substrate 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a is provided, and a field region 103 having a deep depth and an element isolation having a shallow depth are provided in the semiconductor substrate 100. A film 302 is formed. The semiconductor substrate 100 is, for example, a silicon substrate doped with impurities (eg, p-type dopant).

  47, the peripheral transistor 305 including the gate 304 on the first surface 100a of the semiconductor substrate 100, the metal wiring 306 electrically connected to the peripheral transistor 305, and the peripheral transistor 305 and the metal wiring 306 are covered. A peripheral circuit 300 including the insulating film 308 is formed. When the peripheral circuit 300 is formed, an alignment key 110 and a connection contact 107 extending from the first surface 100a toward the second surface 100b through the field region 103 are vertically spaced apart from each other in parallel. The connection contact 107 is electrically connected to the peripheral circuit 300 by being connected to the peripheral transistor 305 or the metal wiring 306. According to an example, the connection contact 107 can be formed simultaneously with the metal wiring 306.

  Referring to FIG. 48, a support substrate 80 is attached on the peripheral circuit 300, and the semiconductor substrate 100 is inverted. The peripheral circuit 300 and the semiconductor substrate 100 are sequentially stacked in an inverted form on the support substrate 80. The support substrate 80 is a silicon substrate or a non-silicon substrate (eg, glass or resin substrate), regardless of the type.

  Referring to FIG. 49, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100b is recessed by etch back, chemical mechanical polishing, grinding, or the like in a state where the semiconductor substrate 100 is supported by the support substrate 80. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 50, the pixel array 500 is formed on the third surface 100 c of the semiconductor substrate 100. Forming the pixel array 500 includes forming an element isolation film 502, a pixel transistor 505, a photodiode 509, a connection wiring 506, and an insulating film 508. The pixel transistor 505 may include a transfer transistor 504a, a reset transistor 504b, a source follower transistor 504c, and a selection transistor 504d. The pixel array 500 is aligned with the peripheral circuit 300 by the alignment key 110. The photodiode 509 has a first doping region 509a formed by implanting a first conductivity type impurity (eg, n-type dopant) into the semiconductor substrate 100, and a second conductivity type impurity (eg, p-type) in the first doping region 509a. A second doping region 509b formed by implanting a dopant). The connection wiring 506 electrically connects the pixel transistor 505 and the connection contact 107. The pixel array 500 is electrically connected to the peripheral circuit 300 through the connection contact 107.

  According to the present embodiment, a CMOS image sensor having a COP (Cell On Peripheral) structure in which a pixel array 500 is stacked on a peripheral circuit 300 on a support substrate 80 in the same or similar manner as described with reference to FIGS. 4000 is formed. The peripheral transistor 305 is formed on the first surface 100a of the semiconductor substrate 100, and the pixel transistor 505 is formed on the third surface 100c. Accordingly, the peripheral transistor 305 and the pixel transistor 505 are arranged back to back as shown in FIG.

  As another example, as illustrated in FIG. 51, the transfer transistor 504 a is formed on the third surface 100 c of the semiconductor substrate 100, and the reset transistor 504 b, the source follower transistor 504 c, and the selection transistor 504 d are the first transistors of the semiconductor substrate 100. A CMOS image sensor 4000a is manufactured by forming on the surface 100a. For example, as described in FIG. 47, when the peripheral circuit 300 is formed, the reset transistor 504b, the source follower transistor 504c, the selection transistor 504d, and the connection wiring 506 are formed. 50, when the pixel array 500 is formed, the transfer transistor 504a, the photodiode 509, and the second connection wiring 507 electrically connected to the connection contact 107 and the transfer transistor 504a are formed.

<Image sensor manufacturing example 2>
52 to 57 are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention.

  Referring to FIG. 52, a semiconductor substrate 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a is provided. A field region 103 having a deep depth and an element isolation having a shallow depth are provided in the semiconductor substrate 100. A film 502 is formed. The semiconductor substrate 100 is, for example, a silicon substrate doped with impurities (eg, p-type dopant).

  Referring to FIG. 53, the pixel array 500 is formed on the first surface 100 a of the semiconductor substrate 100. Forming the pixel array 500 includes forming a pixel transistor 505, a photodiode 509, a connection wiring 506, and an insulating film 508. When the pixel array 500 is formed, an alignment key 110 and a connection contact 107 extending from the first surface 100a toward the second surface 100b are formed through the field regions 103 so as to be vertically spaced apart from each other in parallel. The connection contact 107 is electrically connected to the pixel array 500 by being connected to the pixel transistor 505 or the connection wiring 506. According to an example, the connection contact 107 is formed simultaneously with the connection wiring 506. The pixel transistor 505 includes a transfer transistor 504a, a reset transistor 504b, a source follower transistor 504c, and a selection transistor 504d. The photodiode 509 includes a first doping region 509a doped with a first conductivity type impurity (eg, n-type dopant) and a second doping region 509b doped with a second conductivity type impurity (eg, p-type dopant). To do. The connection wiring 506 electrically connects the pixel transistor 505 and the connection contact 107.

  Referring to FIG. 54, a first support substrate 81 is attached on the pixel array 500, and the semiconductor substrate 100 is inverted. The pixel array 500 and the semiconductor substrate 100 are sequentially stacked in an inverted form on the first support substrate 81.

  Referring to FIG. 55, the second surface 100b of the semiconductor substrate 100 is recessed to expose the third surface 100c. As an example, the second surface 100 b is recessed by etch back, chemical mechanical polishing, grinding, or the like in a state where the semiconductor substrate 100 is supported by the first support substrate 81. The alignment key 110 and the connection contact 107 are exposed by the third surface 100c.

  Referring to FIG. 56, the peripheral transistor 305 including the gate 304 on the first surface 100 a of the semiconductor substrate 100, the metal wiring 306 electrically connected to the peripheral transistor 305, and the insulation covering the peripheral transistor 305 and the metal wiring 306. A peripheral circuit 300 including the film 308 is formed. Peripheral circuit 300 is aligned with pixel array 500 by alignment key 110. The metal wiring 306 is connected to the connection contact 107 and electrically connected to the connection wiring 506. The peripheral circuit 300 is electrically connected to the pixel array 500 by connection contacts 107. According to the present embodiment, a POC (Peripheral On Cell) structure in which the peripheral circuit 300 is stacked on the pixel array 500 on the first support substrate 81 can be obtained in the same or similar manner as described in FIGS. .

  Referring to FIG. 57, if the first support substrate 81 is removed, the CMOS image sensor 5000 is manufactured. Optionally, a second support substrate 82 is attached on the peripheral circuit 300. The CMOS image sensor 5000 is substantially the same as the CMOS image sensor 4000 of FIG. 51, the transfer transistor 504a is formed on the first surface 100a of the semiconductor substrate 100, and the reset transistor 504b, the source follower transistor 504c, and the selection transistor 504d are the third ones of the semiconductor substrate 100. Formed on the surface 100c.

<Application example>
FIG. 58 is a block diagram illustrating a memory card including a semiconductor device according to an embodiment of the present invention.

  Referring to FIG. 58, a memory 1210 including at least one of the semiconductor devices 1 to 3000a according to the embodiment of the present invention is applied to a memory card 1200. As an example, the memory card 1200 includes a memory controller 1220 that controls general data exchange between the host 1230 and the memory 1210. The SRAM 1221 can be used as an operation memory of the central processing unit 1222. The host interface 1223 includes a data exchange protocol for the host 1230 connected to the memory card 1200. The error correction code 1224 can detect and correct an error included in data read from the memory 1210. Memory interface 1225 interfaces with memory 1210. The central processing unit 1222 performs various control operations for exchanging data of the memory controller 1220.

  FIG. 59 is a block diagram showing an information processing system to which a semiconductor element according to an embodiment of the present invention is applied.

  Referring to FIG. 59, the information processing system 1300 includes a memory system 1310 including at least one of the semiconductor devices 1 to 3000a according to an embodiment of the present invention. The information processing system 1300 includes mobile devices and computers. As an example, the information processing system 1300 includes a memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 that are electrically connected to the system bus 1360. The memory system 1310 includes a memory 1311 and a memory controller 1312, and is configured substantially in the same manner as the memory card 1200 of FIG. The memory system 1310 stores data processed by the central processing unit 1330 or data input from the outside. The information processing system 1300 is provided as a memory card, a semiconductor disk device (Solid State Disk), a camera image sensor (Camera Image Sensor), and other application chipsets (Application Chipset). As an example, the memory system 1310 includes a semiconductor disk device SSD, and in this case, the information processing system 1300 stores a large amount of data in the memory system 1310 stably and reliably.

  FIG. 60 is a block diagram showing an information processing system to which an image sensor according to an embodiment of the present invention is applied.

  Referring to FIG. 60, the information processing system 1400 includes a central processing unit 1420, an image sensor 1410 that communicates with the central processing unit 1420 through a bus 1470, an input / output device 1430, a RAM 1440, a compact disk drive 1450, and a hard disk drive 1460. . The image sensor 1410 includes at least one of CMOS image sensors 4000, 4000a, and 5000 according to an embodiment of the present invention. The image sensor 1410 receives control signals or data signals from the central processing unit 1420 or other devices 1440 to 1460 of the information processing system 1400. Image sensor 1410 provides a signal that defines an image to central processing unit 1420 based on a control signal or data signal, and central processing unit 1420 processes the signal received from image sensor 1410.

  In summary, in order to obtain a high degree of integration, a semiconductor element is formed in a three-dimensional structure. In order to manufacture a semiconductor element having a three-dimensional structure, it is common to stack another semiconductor element on a semiconductor substrate or to form a single crystal semiconductor film on the semiconductor substrate. However, forming the electrical connection between the stacked semiconductor devices has problems such as the complexity of forming the electrical connection, difficulty in fine alignment, and progress of the process under a heat budget. Occur. For example, in order to deposit a single crystal semiconductor film on a cell array in a conventional stacked structure, it is necessary to form a peripheral circuit on the cell array. In addition, it is necessary to form deep vertical contacts to electrically connect the peripheral circuit to the cell array, and it is difficult to ensure alignment between the cell array and the peripheral circuit.

  The present embodiment provides that the cell array and the peripheral circuit are separately disposed on both sides of the semiconductor substrate. Therefore, the degree of integration is improved and the chip area is reduced. Further, the cell array and the peripheral circuit can be precisely aligned vertically, the thermal burden can be reduced, and the characteristics of the cell array and the peripheral circuit can be maximized, so that the electrical characteristics of the semiconductor element are improved.

  The foregoing detailed description is not intended to limit the invention to the disclosed embodiments, but can be used in various other combinations, modifications, and environments without departing from the spirit of the invention. It should be understood that the appended claims include other implementations.

1, 2, 3, 1000, 1000a, 1000b, 2000, 2000a, 2000b, 3000 Semiconductor element 20, 200 Cell array 30, 300 Peripheral circuit 80 Support substrate 81 First support substrate 82 Second support substrate 92 Via 94 Pad 100 Semiconductor substrate 100a First surface 100b Second surface 100c Third surface 103 Field region 107 Connection contact 110 Alignment key 205 Cell transistor 206 Bit line 208, 308, 508 Insulating film 209 Capacitor 210 Cell transistor layer 220 Capacitor layer 202, 302, 502 Element isolation Membrane 305 Peripheral transistor 306 Metal wiring 500 Pixel array 504a Transfer transistor 504b Reset transistor 504c Source follower transistor 504d Select Njisuta 505 pixel transistor 506 connecting line 509 photodiode 1200 memory card 1210,1311 memory 1220,1312 memory controller 1221 SRAM
1222, 1330, 1420 Central processing unit 1223 Host interface 1224 Error correction code 1225 Memory interface 1230 Host 1300, 1400 Information processing system 1310 Memory system 1320 Modem 1340, 1440 RAM
1350 User interface 1360 System bus 1410 Image sensor 1430 Input / output device 1450 Compact disk drive 1460 Hard disk drive 1470 Bus 4000, 4000a, 5000 CMOS image sensor

Claims (10)

A semiconductor substrate having an upper surface and a lower surface opposite to the upper surface;
An upper circuit disposed on an upper surface of the semiconductor substrate;
A lower circuit disposed on a lower surface of the semiconductor substrate;
A vertical connection contact passing through the semiconductor substrate and electrically connecting the upper circuit and the lower circuit;
An alignment key penetrating the semiconductor substrate to vertically align the upper circuit and the lower circuit,
The semiconductor substrate includes an insulating film disposed between the upper circuit and the lower circuit, and the alignment key vertically penetrates the insulating film ,
The semiconductor device according to claim 1, wherein the alignment key includes an insulator . The upper circuit includes a cell array having cell transistors,
The lower circuit includes a peripheral circuit having a peripheral transistor,
The semiconductor device of claim 1, wherein the cell transistor is vertically symmetric with respect to the semiconductor substrate in a direction opposite to the peripheral transistor. The cell array further includes a bit line electrically connected to the cell transistor,
The lower circuit further includes a metal wiring electrically connected to the peripheral transistor,
The semiconductor device of claim 2, wherein the connection contact electrically connects the bit line and the metal wiring. A support substrate attached on the lower circuit;
A via penetrating the support substrate and connected to the metal wiring;
A pad disposed on the support substrate and connected to the via;
The metal wiring is disposed between the semiconductor substrate and the support substrate ,
The semiconductor device according to claim 3, wherein the metal wiring is disposed adjacent to the support substrate . Providing a semiconductor substrate having a first surface and a second surface opposite to the first surface;
Forming an insulating region extending through the semiconductor substrate from the first surface toward the second surface and not reaching the second surface;
Forming an alignment key and a connecting contact extending from the first surface to the second surface through the insulating region and spaced apart in parallel to each other and not reaching the second surface;
Forming a first circuit electrically connected to the connection contact on a first surface of the semiconductor substrate;
Forming a support substrate on the first circuit;
Recessing the second surface of the semiconductor substrate to form a third surface exposing the insulating region, the alignment key, and the connection contact;
See containing and forming a second circuit which is the connection contact electrically connected on the third surface of the semiconductor substrate,
The method of manufacturing a semiconductor device , wherein the alignment key includes an insulator . A semiconductor substrate having an upper surface and a lower surface opposite to the upper surface;
A cell array having cell transistors provided on a lower surface of the semiconductor substrate;
A peripheral circuit having a peripheral transistor provided on an upper surface of the semiconductor substrate;
An alignment key extending from the upper surface to the lower surface to vertically align the cell array with the peripheral circuit;
A connection contact extending from the upper surface to the lower surface to electrically connect the cell array to the peripheral circuit,
Wherein the cell transistor and the peripheral transistor, Ri vertical symmetry (a vertically symmetric) der facing away around the semiconductor substrate,
The semiconductor device according to claim 1, wherein the alignment key includes an insulator . The cell array further includes a bit line electrically connected to the cell transistor,
The peripheral circuit further includes a metal wiring electrically connected to the peripheral transistor,
The semiconductor device of claim 6, wherein the connection contact electrically connects the bit line to the metal wiring. The cell array further includes a capacitor provided on the cell transistor,
The semiconductor device of claim 6, wherein the capacitor is electrically connected to the cell transistor. A semiconductor substrate having an upper surface and a lower surface opposite to the upper surface;
An insulating region extending from the upper surface to the lower surface through the semiconductor substrate;
And an alignment key of the extended insulating from the upper surface to the lower surface through the insulating region,
A connecting contact extended conductive to the lower surface from the upper surface through the insulating region,
A first circuit provided on an upper surface of the semiconductor substrate and electrically connected to the connection contact;
A second circuit provided on a lower surface of the semiconductor substrate and electrically connected to the connection contact;
The semiconductor device according to claim 1, wherein the alignment key vertically aligns the first circuit with the second circuit. Of the first circuit and the second circuit,
Any one includes a cell array having cell transistors;
The other one includes a peripheral circuit having peripheral transistors,
The semiconductor device of claim 9, wherein the cell transistor and the peripheral transistor are vertically symmetrical with respect to the semiconductor substrate as a center.

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