JP6320282B2 - エッチング方法 - Google Patents
エッチング方法 Download PDFInfo
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- JP6320282B2 JP6320282B2 JP2014246745A JP2014246745A JP6320282B2 JP 6320282 B2 JP6320282 B2 JP 6320282B2 JP 2014246745 A JP2014246745 A JP 2014246745A JP 2014246745 A JP2014246745 A JP 2014246745A JP 6320282 B2 JP6320282 B2 JP 6320282B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
- H05H1/00—Generating plasma; Handling plasma
- H05H1/24—Generating plasma
- H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
- H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Electromagnetism (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Drying Of Semiconductors (AREA)
- Plasma Technology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (13)
- 被処理体に対するプラズマ処理によって、シリコン原子及び酸素原子を含む第1領域を該第1領域とは異なる材料から構成された第2領域に対して選択的にエッチングする方法であって、該被処理体は、凹部を画成する前記第2領域、該凹部を埋め、且つ前記第2領域を覆うように設けられた前記第1領域、及び前記凹部の上に開口を提供し前記第1領域上に設けられたマスクを有し、
該方法は、
フルオロカーボンガスを含み酸素ガスを含まない処理ガスのプラズマを生成することにより、前記被処理体上にフルオロカーボン含有膜を形成する工程と、
前記フルオロカーボン含有膜に含まれるフルオロカーボンのラジカルにより前記第1領域をエッチングする工程と、
を各々が含む1回以上のシーケンスを実行する工程と、
前記フルオロカーボン含有膜の膜厚を低減させる工程と、
を含み、
前記1回以上のシーケンスを実行する工程と前記膜厚を低減させる工程との交互の繰り返しが実行される、方法。 - 前記膜厚を低減させる工程では、三フッ化窒素ガスのみを含む処理ガスのプラズマが生成される、請求項1に記載の方法。
- 前記膜厚を低減させる工程では、三フッ化窒素ガス及び希ガスを含む処理ガスのプラズマが生成される、請求項1に記載の方法。
- 前記交互の繰り返しに含まれる一部の前記膜厚を低減させる前記工程において、三フッ化窒素ガス及び希ガスを含む処理ガスのプラズマが生成され、
前記交互の繰り返しに含まれる他の一部の前記膜厚を低減させる前記工程において、三フッ化窒素ガスのみを含む処理ガスのプラズマが生成される、
請求項1に記載の方法。 - 前記膜厚を低減させる工程では、酸素ガスのみを含む処理ガスのプラズマが生成される、請求項1に記載の方法。
- 前記膜厚を低減させる工程では、酸素ガス及び希ガスを含む処理ガスのプラズマが生成される、請求項1に記載の方法。
- 前記交互の繰り返しに含まれる一部の前記膜厚を低減させる前記工程において、酸素ガス及び希ガスを含む処理ガスのプラズマが生成され、
前記交互の繰り返しに含まれる他の一部の前記膜厚を低減させる前記工程において、酸素ガスのみを含む処理ガスのプラズマが生成される、
請求項1に記載の方法。 - 前記フルオロカーボン含有膜を形成する工程では、前記被処理体を収容した処理容器内の圧力が2.666Pa以下の圧力に設定される、請求項1〜7の何れか一項に記載の方法。
- 前記フルオロカーボン含有膜を形成する工程では、100V以上、300V以下の実効バイアス電圧が生じるプラズマ生成用の高周波電力が用いられる、請求項1〜8の何れか一項に記載の方法。
- 前記フルオロカーボン含有膜を形成する工程では、容量結合型のプラズマ処理装置が用いられ、該プラズマ処理装置の上部電極のシリコン製の電極板に正イオンを引き込むための電圧が印加される、請求項1〜9の何れか一項に記載の方法。
- 前記第1領域をエッチングする工程では、希ガスのプラズマが生成される、請求項1〜10の何れか一項に記載の方法。
- 前記第1領域は、酸化シリコン、酸窒化ケイ素、又は炭素含有酸化ケイ素から構成されている、請求項1〜11の何れか一項に記載の方法。
- 前記第2領域は、シリコン、炭素、窒化シリコン、又は金属から構成されている、請求項1〜12の何れか一項に記載の方法。
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014246745A JP6320282B2 (ja) | 2014-12-05 | 2014-12-05 | エッチング方法 |
| PCT/JP2015/082646 WO2016088575A1 (ja) | 2014-12-05 | 2015-11-20 | エッチング方法 |
| CN201580060311.XA CN107078050B (zh) | 2014-12-05 | 2015-11-20 | 蚀刻方法 |
| KR1020177012095A KR102418244B1 (ko) | 2014-12-05 | 2015-11-20 | 에칭 방법 |
| US15/527,360 US10090191B2 (en) | 2014-12-05 | 2015-11-20 | Selective plasma etching method of a first region containing a silicon atom and an oxygen atom |
| TW104140016A TWI671815B (zh) | 2014-12-05 | 2015-12-01 | 蝕刻方法 |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014246745A JP6320282B2 (ja) | 2014-12-05 | 2014-12-05 | エッチング方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016111177A JP2016111177A (ja) | 2016-06-20 |
| JP6320282B2 true JP6320282B2 (ja) | 2018-05-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2014246745A Active JP6320282B2 (ja) | 2014-12-05 | 2014-12-05 | エッチング方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10090191B2 (ja) |
| JP (1) | JP6320282B2 (ja) |
| KR (1) | KR102418244B1 (ja) |
| CN (1) | CN107078050B (ja) |
| TW (1) | TWI671815B (ja) |
| WO (1) | WO2016088575A1 (ja) |
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| JP2016111177A (ja) | 2016-06-20 |
| TW201631656A (zh) | 2016-09-01 |
| KR102418244B1 (ko) | 2022-07-07 |
| CN107078050A (zh) | 2017-08-18 |
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