JP6330566B2 - Circuit device and electronic device - Google Patents

Description

  The present invention relates to a circuit device, an electronic device, and the like.

  As a motor driver for driving a direct current motor or a stepping motor, one using an H bridge circuit is known. This H-bridge circuit has first to fourth transistors (switch elements) for driving, and the first, fourth, second, and third transistors are electrically coupled to the motor. Connected to the corner. In the charge period, the first and fourth transistors are turned on. As a result, the positive side (+) terminal of the motor is set to a high potential voltage, and the negative side (−) terminal is set to a low potential voltage. On the other hand, in the decay period, the second and third transistors are turned on. As a result, the positive terminal of the motor is set to a low potential voltage, and the negative terminal is set to a high potential voltage.

  In this H-bridge circuit, if an overcurrent flows due to, for example, a motor failure or a short circuit of a terminal, the IC of the motor driver may be destroyed due to the overcurrent. Therefore, the motor driver is provided with an overcurrent detection circuit. The first to fourth transistors of the bridge circuit have an on-resistance, and a voltage drop due to the on-resistance occurs at the drain node (a positive terminal or a negative terminal of the motor). The overcurrent detection circuit detects an overcurrent by monitoring a voltage drop at the drain node. That is, when a large current flows through the bridge circuit, the voltage at the drain node greatly drops due to the on-resistance. Therefore, the overcurrent detection circuit determines that an overcurrent has flowed when the voltage drop exceeds a predetermined value. As a conventional technique of such an overcurrent detection circuit, there is a technique disclosed in Patent Document 1.

Japanese Patent Laid-Open No. 2005-136453

  As described above, when the on-resistance of the transistor is used to detect the overcurrent, there is a problem that the on-resistance varies when the transistor is turned on from off, and the overcurrent cannot be detected accurately. That is, when the transistor is turned on from off, the gate voltage rises transiently, but the on-resistance is high when the gate voltage does not rise sufficiently. Therefore, the voltage drop becomes large even with a small current, and although it is actually a small current, it may be erroneously detected as an overcurrent, and the operation of the motor driver may be stopped.

  According to some aspects of the present invention, it is possible to provide a circuit device, an electronic device, and the like that can accurately detect an overcurrent of a bridge circuit.

  One embodiment of the present invention includes a bridge circuit including a first transistor on a high side and a second transistor on a low side, a first driver circuit that drives the first transistor, and the second A pre-driver having a second driver circuit for driving the transistor, and a switch having a first switch element having one end connected to a first node between the first transistor and the second transistor A circuit, a switching control circuit that outputs a first switch control signal for controlling on / off of the first switch element based on an output of the first driver circuit, and other than the first switch element A detection circuit for detecting a current of the bridge circuit based on a voltage at an end node; and an on / off control signal of the bridge circuit. A control circuit that outputs to the first driver circuit and the second driver circuit and stops the on / off operation of the bridge circuit when a current is detected by the detection circuit, and the switching control circuit Relates to a circuit arrangement that activates the first switch control signal when it is determined that the on-resistance of the first transistor is less than a given first on-resistance.

  According to one aspect of the present invention, the first switch control signal becomes active when it is determined that the on-resistance of the first transistor of the bridge circuit is less than a given first on-resistance, and the switch circuit The first switch element is turned on, and the voltage of the first node between the first transistor and the second transistor is input to the detection circuit via the first switch element. As a result, when it is determined that the on-resistance of the first transistor of the bridge circuit is smaller than the given first on-resistance, the overcurrent is detected, and the overcurrent of the bridge circuit is accurately detected. It becomes possible to do.

  In one embodiment of the present invention, when the on-resistance when the gate-source voltage of the first transistor is maximum is RonM1, and the given first on-resistance is RG1, RG1 ≦ 2 × RonM1 may be used.

  Immediately after the first transistor is turned on, the on-resistance is very large, and the voltage at the first node drops greatly when only a small current flows, which may be erroneously detected as an overcurrent. In this regard, according to one aspect of the present invention, the on-resistance of the first transistor of the bridge circuit is at most twice RonM1 during the period when the first switch element of the switch circuit is on. Since RonM1 is the minimum value of the on-resistance, it is less than twice the minimum value. As a result, overcurrent can be detected in a state where the on-resistance of the first transistor is sufficiently small, and the detection accuracy of the overcurrent is improved.

  In one embodiment of the present invention, the switching control circuit includes a first comparison circuit that compares a voltage based on an output of the first driver circuit with a first reference voltage, and the first comparison circuit. The first switch control signal may be activated based on the result of the comparison.

  Since the on-resistance of the first transistor of the bridge circuit changes according to the output of the first driver circuit, the voltage based on the output of the first driver circuit is compared with the first reference voltage, so that the first The first switch control signal can be activated by detecting that the on-resistance of the transistor has reached a given first on-resistance.

  In one embodiment of the present invention, when the first transistor is turned on by setting the threshold voltage of the first transistor to Vth1 with reference to the high-potential side power supply voltage of the bridge circuit, the first driver circuit When the output voltage is VDR1 and the first reference voltage is Vref1, Vref1 = (VDR1−Vth1) / 2 + Vth1.

  The first reference voltage Vref1 is an intermediate voltage between the gate-source voltage VDR1 for turning on the first transistor and the threshold voltage Vth1 of the first transistor. According to one aspect of the present invention, the on-resistance of the first transistor when the output of the first driver circuit becomes the first reference voltage Vref1 is set to a given first on-resistance. As a result, overcurrent can be detected in a state where the on-resistance of the first transistor is sufficiently small, and the detection accuracy of the overcurrent is improved.

  In one embodiment of the present invention, the switch circuit includes a second switch element having one end connected to the first node, and the detection circuit includes a node at the other end of the second switch element. A current of the bridge circuit is detected based on a voltage, and the switching control circuit outputs a second switch control signal for controlling on / off of the second switch element, and an on-resistance of the second transistor The second switch control signal may be activated when it is determined that is less than a given second on-resistance.

  According to one aspect of the present invention, the second switch control signal is activated when it is determined that the on-resistance of the second transistor of the bridge circuit is less than a given second on-resistance, and the switch circuit The second switch element is turned on, and the voltage of the first node between the first transistor and the second transistor is input to the detection circuit via the second switch element. As a result, when it is determined that the on-resistance of the second transistor of the bridge circuit is smaller than the given second on-resistance, the overcurrent is detected, and the overcurrent of the bridge circuit is accurately detected. It becomes possible to do.

  In one embodiment of the present invention, when the on-resistance when the gate-source voltage of the second transistor is maximum is RonM2, and the given second on-resistance is RG2, RG2 ≦ 2 × RonM2 may be used.

  Immediately after the second transistor is turned on, the on-resistance is very large, and the voltage at the first node rises greatly only when a small current flows, which may be erroneously detected as an overcurrent. In this regard, according to one aspect of the present invention, the ON resistance of the second transistor of the bridge circuit is at most twice RonM2 during the period when the second switch element of the switch circuit is ON. Since RonM2 is the minimum value of the on-resistance, it is equal to or less than twice the minimum value. As a result, overcurrent can be detected in a state where the on-resistance of the second transistor is sufficiently small, and the detection accuracy of the overcurrent is improved.

  In one embodiment of the present invention, the switching control circuit includes a second comparison circuit that compares a voltage based on an output of the second driver circuit with a second reference voltage, and the second comparison circuit. The second switch control signal may be activated based on the result of the comparison.

  Since the on-resistance of the second transistor of the bridge circuit changes according to the output of the second driver circuit, the voltage based on the output of the second driver circuit is compared with the second reference voltage, so that the second A second switch control signal can be activated by detecting that the on-resistance of the transistor has reached a given second on-resistance.

  In one embodiment of the present invention, the threshold voltage of the second transistor is set to Vth2, the voltage output from the second driver circuit when the second transistor is turned on is set to VDR2, and the second reference voltage is set. Vref2 may be Vref2 = (VDR2-Vth2) / 2 + Vth2.

  The second reference voltage Vref2 is an intermediate voltage between the voltage VDR2 for turning on the second transistor and the threshold voltage Vth2 of the second transistor. According to one aspect of the present invention, the on-resistance of the second transistor when the output of the second driver circuit becomes the second reference voltage Vref2 is set to a given second on-resistance. As a result, overcurrent can be detected in a state where the on-resistance of the second transistor is sufficiently small, and the detection accuracy of the overcurrent is improved.

  In one embodiment of the present invention, the detection circuit may be configured such that a difference between a voltage at a source node of the first transistor and a voltage at a node at the other end of the first switch element is greater than a first predetermined value. A difference between a voltage at a node at the other end of the second switch element and a voltage at a source node of the second transistor is greater than a second predetermined value. A current detection signal is activated when at least one of the second determination circuit and the output of the first determination circuit and the output of the second determination circuit becomes active. And a detection signal output circuit.

  The first predetermined value corresponds to the detected value of the overcurrent flowing through the first transistor, and the second predetermined value corresponds to the detected value of the overcurrent flowing through the second transistor. According to one aspect of the present invention, an overcurrent detection signal can be activated when it is determined that an overcurrent has flowed in one of the first transistor and the second transistor. Thereby, each transistor can be reliably protected from destruction due to overcurrent.

  In one embodiment of the present invention, the bridge circuit is an H-bridge circuit having a third transistor on the high side and a fourth transistor on the low side, and the pre-driver is the third transistor. A third driver circuit that drives the fourth transistor, and a fourth driver circuit that drives the fourth transistor, wherein the control circuit sends an on / off control signal for the bridge circuit to the third driver circuit. Output to the fourth driver circuit, the switch circuit including a third switch element having one end connected to a second node between the third transistor and the fourth transistor; A fourth switch element having one end connected to the node of the second switch element, wherein the switching control circuit turns on and off the third switch element. A third switch control signal to be controlled and a fourth switch control signal to control on / off of the fourth switch element, and the on-resistance of the third transistor is a given third on-state. The third switch control signal is activated when it is determined that the resistance is smaller than the resistance, and the fourth switch is activated when it is determined that the on-resistance of the fourth transistor is smaller than a given fourth on-resistance. A switch control signal is activated, and the detection circuit calculates a current of the bridge circuit based on a voltage at a node at the other end of the third switch element and a voltage at a node at the other end of the fourth switch element. It may be detected.

  In this way, the bridge circuit is configured as an H bridge circuit, and the overcurrent flowing through the first to fourth transistors included in the H bridge circuit can be accurately detected, and the H bridge circuit can be protected from destruction.

  According to another aspect of the present invention, there is provided a bridge circuit including a first transistor on a high side and a second transistor on a low side, a first driver circuit that drives the first transistor, A pre-driver having a second driver circuit for driving two transistors, and a switch circuit having a switch element having one end connected to a first node between the first transistor and the second transistor; A switching control circuit for outputting a switch control signal for controlling on / off of the switch element based on an output of the second driver circuit, and the bridge based on a voltage at a node at the other end of the switch element. A detection circuit for detecting a circuit current; and an on / off control signal for the bridge circuit. And a control circuit that outputs to the second driver circuit and stops the on / off operation of the bridge circuit when a current is detected by the detection circuit, and the switching control circuit includes the second control circuit. The present invention relates to a circuit device that activates the switch control signal when it is determined that the on-resistance of a transistor has become smaller than a given on-resistance.

  Still another embodiment of the present invention relates to an electronic apparatus including the circuit device described above.

The structural example of a circuit apparatus. FIG. 2A is an operation explanatory diagram of the charge period. FIG. 2B is an operation explanatory diagram of the decay period. Explanatory drawing of a chopping operation | movement. The comparative structural example of an overcurrent detection circuit. 5A and 5B are timing charts of a comparative configuration example of the overcurrent detection circuit. 2 is a configuration example of an overcurrent detection circuit according to the present embodiment. The timing chart of the overcurrent detection circuit of this embodiment. Example of on-resistance characteristics of the high-side transistor. The timing chart of the overcurrent detection circuit of this embodiment. 3 is a detailed configuration example of a first comparison circuit of a switching control circuit. 4 is a detailed configuration example of a second comparison circuit of the switching control circuit. 3 shows a detailed configuration example of a first determination circuit of a detection circuit. 4 is a detailed configuration example of a second determination circuit of the detection circuit. 3 is a detailed configuration example of a detection signal output circuit of a detection circuit. The 1st delay circuit of the modification of a switching control circuit. The 2nd delay circuit of the modification of a switching control circuit. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Circuit Configuration of Circuit Device FIG. 1 shows a configuration example of a circuit device according to this embodiment. The circuit device according to the present embodiment includes a bridge circuit 10, a control circuit 20, a chopping current detection circuit 30, a pre-driver 40, a register unit 50, and an overcurrent detection circuit 60.

  The bridge circuit 10 includes high-side transistors Q1 and Q3 and low-side transistors Q2 and Q4. The bridge circuit 10 is a circuit that outputs a drive current to a motor 100 (for example, a DC motor or a stepping motor), and has an H-bridge circuit configuration in FIG.

  The high-side transistors Q1 and Q3 are, for example, P-type (first conductivity type in a broad sense), and the low-side transistors Q2, Q4 are, for example, N-type (second conductivity type in a broad sense) transistors. . The high-side transistor is a transistor connected to the higher potential power supply side than the low-side transistor. The low-side transistor is a transistor connected to the low-potential power supply side rather than the high-side transistor. Note that all of the transistors Q1, Q2, Q3, and Q4 may be N-type transistors. A body diode (parasitic diode) (not shown) exists between the source and drain of Q1, Q2, Q3, and Q4.

  The sources of the high-side transistors Q1 and Q3 are connected to the node of the high-potential-side power supply VBB (first power supply). The sources of the low-side transistors Q2 and Q4 are connected to a node N3 to which one end of the sense resistor RS is connected. The node N3 is connected to one end of a sense resistor RS, which is an external component, via a terminal TMC of the circuit device.

  The drain of the transistor Q1 and the drain of the transistor Q2 are connected to a node N1 connected to one end of the external motor 100 (drive target in a broad sense). The node N1 is connected to one end of the motor 100 via a terminal TMA of the circuit device.

  The drain of the transistor Q3 and the drain of the transistor Q4 are connected to a node N2 connected to the other end of the motor 100. The node N2 is connected to the other end of the motor 100 via a terminal TMB of the circuit device.

  The chopping current detection circuit 30 detects a current flowing through the bridge circuit 10. For example, the charge current in the charge period is detected by detecting the voltage VS at one end of the sense resistor RS. Specifically, the chopping current detection circuit 30 includes a reference voltage generation circuit 32, a D / A conversion circuit 34, and a comparison circuit 36 (comparator).

  The reference voltage generation circuit 32 generates a constant reference voltage VRF. The D / A conversion circuit 34 receives the reference voltage VRF and generates a reference voltage VR that changes variably based on the setting data DRF. The setting data DRF is stored in the register unit 50. For example, the setting data DRF is written into the register unit 50 from an external controller (for example, a microcomputer). In the comparison circuit 36, a reference voltage VR is input to a first input terminal (non-inverting input terminal), and a voltage VS that is a voltage at one end of the sense resistor RS is input to a second input terminal (inverting input terminal). The detection result signal RQ is output. For example, as described later, the chopping current is determined by the reference voltage VR input to the comparison circuit 36. Therefore, the torque of the motor 100 can be controlled by changing the setting data DRF to change the reference voltage VR.

  The control circuit 20 performs on / off control of the high-side transistors Q1 and Q3 and the low-side transistors Q2 and Q4 based on the detection result of the chopping current detection circuit 30. Specifically, the control signals IN1, IN2, IN3, and IN4 are generated as PWM signals that are switched from the charge period to the decay period when the detection result signal RQ from the chopping current detection circuit 30 becomes active.

  The pre-driver 40 has driver circuits PR1, PR2, PR3, and PR4. The driver circuits PR1, PR2, PR3, and PR4 buffer the control signals IN1, IN2, IN3, and IN4 from the control circuit 20, and drive the drive signals DG1, DG2, DG3, and DG4 to the transistors Q1, Q2, Q3, and Q4. Output to the gate.

  The overcurrent detection circuit 60 detects an overcurrent based on the voltage V1 of the node N1 and the voltage V2 of the node N2 of the bridge circuit 10, and when detecting that an overcurrent has flowed into the bridge circuit 10, 20 is notified. When this notification is given, the control circuit 20 stops the driving operation of the bridge circuit 10. That is, the control signals IN1, IN2, IN3, and IN4 that turn off the transistors Q1 to Q4 of the bridge circuit 10 are output. As a situation where an overcurrent occurs, for example, a short circuit between the terminal TMA and the terminal TMB connecting the motor 100, a short circuit between the terminal TMA or the terminal TMB and the ground (or power supply), a failure of the motor 100 (inside the motor 100) Short circuit), destruction of the transistors Q1 to Q4 of the bridge circuit 10 can be considered.

  The circuit device shown in FIG. 1 is composed of, for example, an IC chip, and terminals TMA, TMB, TMC, and TMD correspond to IC chip package terminals or pads on a semiconductor substrate. In this case, the circuit device that is an IC chip is mounted on a circuit board (printed board or the like), and a sense resistor RS that is an external circuit component is also mounted on the circuit board. The sense resistor RS and the terminals TMC and TMD are electrically connected by wiring on the circuit board.

  Next, the operation of the bridge circuit 10 of the circuit device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 2A, in the charge period, the transistors Q1 and Q4 are turned on. As a result, the charge current IC flows from the power source VBB on the high potential side to the power source VSS (GND) on the low potential side via the transistor Q1, the motor 100 (motor coil), and the transistor Q4.

  On the other hand, in the decay period, as shown in FIG. 2B, the transistors Q2 and Q3 are turned on, and a decay current ID flows from the power supply VSS to the power supply VBB via the transistor Q2, the motor 100, and the transistor Q3. These charge current IC and decay current ID both flow from the positive terminal of the motor 100 to the negative terminal.

  As described in FIG. 1, the sense resistor RS is provided between the node N3 to which the sources of the transistors Q2 and Q4 are connected and the node of the power supply VSS, and the comparison circuit 36 is connected to the voltage VS of the node N3. The reference voltage VR is compared. As shown in FIG. 3, the control circuit 20 controls the chopping operation that keeps the chopping current ICP flowing through the bridge circuit 10 constant. Specifically, the control circuit 20 controls the pulse width of the PWM signals (IN1 to IN4) so that the chopping current ICP is constant, and on / off of the transistors Q1 to Q4 is controlled based on the PWM signal. The

  For example, when the driving of the motor 100 is started at the timing t0 in FIG. 3, the charging period shown in FIG. 2A is entered, the transistors Q1 and Q4 are turned on, and the transistors Q2 and Q3 are turned off. As a result, a drive current (charge current IC) flows from the power supply VBB to the power supply VSS via the transistor Q1, the motor 100, and the transistor Q4. When the driving current of the motor 100 reaches the chopping current ICP at the timing t1, the period is switched to the decay period TD1. Specifically, when the drive current increases and the voltage VS at the node N3 exceeds the reference voltage VR, the comparison result signal RQ of the comparison circuit 36 changes from low level to high level, and switches to the decay period TD1 at timing t1. The driving current of the motor 100 at the timing t1 is the chopping current ICP, and the chopping current ICP is detected by detecting the voltage VS.

  When switching to the decay period TD1, as shown in FIG. 2B, the transistors Q2 and Q3 are turned on and the transistors Q1 and Q4 are turned off. As a result, a drive current (decay current ID) flows from the power supply VSS to the power supply VBB via the transistor Q2, the motor 100, and the transistor Q3. In the decay period TD1, as shown in FIG. 3, the drive current of the motor 100 decreases with time.

  The control circuit 20 detects that a predetermined time has elapsed from the start of the decay period TD1, using a timer (counter circuit), for example, and switches from the decay period TD1 to the charge period TC1. In the charging period TC1, when the driving current of the motor 100 increases and reaches the chopping current ICP, the driving period is switched again to the decay period TD2. Thereafter, by repeating this, control is performed such that the chopping current ICP that is the peak current of the drive current is constant, and the torque of the motor 100 is kept constant.

  In addition, although the case where the bridge circuit 10 is an H bridge type was demonstrated above, this embodiment is not limited to this, The bridge circuit 10 may be a half bridge type. In this case, the transistors Q3 and Q4 are not provided as the bridge circuit 10, but the transistors Q1 and Q2 are provided. In the above description, the case where the circuit device is a motor driver that drives the motor 100 has been described as an example. However, the driving target of the circuit device according to the present embodiment is not limited to the motor 100 and includes an inductor (coil). Various elements and devices can be driven. Further, FIG. 1 illustrates an example in which the on / off control of the transistors Q1 to Q4 of the bridge circuit 10 is performed by detecting the voltage VS at one end of the sense resistor RS, but the present embodiment is not limited to this. For example, the current flowing through the bridge circuit 10 may be detected without using the sense resistor RS, and on / off control of the transistors Q1 to Q4 may be performed.

2. Comparative Example of Overcurrent Detection Circuit FIG. 4 shows a comparative configuration example of the overcurrent detection circuit 60. The overcurrent detection circuit 60 in FIG. 4 includes a switch circuit 62 and a detection circuit 64.

  The switch circuit 62 includes first to fourth switch elements SW1 to SW4 whose gates are connected to the outputs of the driver circuits PR1 to PR4. One ends of the switch elements SW1 and SW2 are connected to the drain nodes N1 of the transistors Q1 and Q2 of the bridge circuit 10, and one ends of the switch elements SW3 and SW4 are connected to the drain nodes N2 of the transistors Q3 and Q4 of the bridge circuit 10. . The switch elements SW1 and SW3 are, for example, P-type transistors, and the switch elements SW2, SW4 are, for example, N-type transistors. Note that the switch elements SW1 to SW4 may be configured by a transfer gate or the like.

  As shown in FIG. 4, since the outputs of the driver circuits PR1 to PR4 are “L”, “L”, “H”, and “H” in the charge period, the switch elements SW1 and SW4 are turned on and the switch element SW2 is turned on. , SW3 is turned off. At this time, the voltage V1 of the drain node N1 of the transistor Q1 is output as the voltage SQ1 from the other end of the switch element SW1, and the voltage V2 of the drain node N2 of the transistor Q4 is output as the voltage SQ4 from the other end of the switch element SW4. Is output.

  When the on-resistances of the transistors Q1 and Q4 are Ron1 and Ron4, the voltage SQ1 = V1 = VBB−Ron1 · IC and the voltage SQ4 = V2 = VS + Ron4 · IC. When the current IC flowing through the bridge circuit 10 increases due to overcurrent, the drop width Ron1 · IC of the voltage SQ1 and the rise width Ron4 · IC of the voltage SQ4 increase. The detection circuit 64 determines that an overcurrent has passed through the bridge circuit 10 when at least one of the fall width Ron1 · IC of the voltage SQ1 and the rise width Ron4 · IC of the voltage SQ4 exceeds a predetermined value, and the detection signal DET Activate When the detection signal DET becomes active, the control circuit 20 sets the drive signals DG1 to DG4 of the bridge circuit 10 to “H”, “L”, “H”, “L”, and turns off all the transistors Q1 to Q4. And the current flowing through the bridge circuit 10 is stopped.

  On the other hand, in the decay period, the switch elements SW2 and SW3 are turned on, and the switch elements SW1 and SW4 are turned off. At this time, the voltage V1 of the drain node N1 of the transistor Q2 is output as the voltage SQ2 from the other end of the switch element SW2, and the voltage V2 of the drain node N2 of the transistor Q3 is output as the voltage SQ3 from the other end of the switch element SW3. Is output. When the on-resistances of the transistors Q2 and Q3 are Ron2 and Ron3, the voltage SQ2 = V1 = VS−Ron2 · ID and the voltage SQ3 = V2 = VBB + Ron3 · ID. The detection circuit 64 determines that an overcurrent has passed through the bridge circuit 10 when at least one of the fall width Ron2 · ID of the voltage SQ2 and the rise width Ron3 · ID of the voltage SQ3 exceeds a predetermined value, and the detection signal DET Activate Since it is considered that the current flowing through the bridge circuit in the decay period is not larger than that flowing through the bridge circuit during the charge period, it is possible to omit overcurrent detection during the decay period.

  As described above, in the comparative example of FIG. 4, the gates of the switch elements SW1 to SW4 are connected to the outputs of the driver circuits PR1 to PR4. Therefore, in the comparative example, there is a possibility that the overcurrent is erroneously detected and the driving operation is stopped unnecessarily. This will be described below.

  FIGS. 5A and 5B are timing charts of the comparative example of FIG. 4 taking the charge period as an example. In FIG. 5A, 42V is a voltage of the power supply VBB of the bridge circuit 10, and 37V is a bias voltage VHB generated by a bias circuit (not shown) built in the circuit device. In FIG. 5B, 0V is a voltage (ground voltage) of the power supply VSS, and 5V is a bias voltage VLB generated by a bias circuit (not shown) built in the circuit device.

  As shown in FIG. 5A, the gate voltage (drive signal DG1) of the transistor Q1 of the bridge circuit 10 is 42V (H level) in the decay period and 37V (L level) in the charge period. When the threshold voltage of the P-type transistor is, for example, Vth1 = 1.5V, the switch circuit 62 when the gate voltage of the transistor Q1 becomes VBB−Vth1 = 40.5V (the gate-source voltage is Vth = 1.5V). The switch element SW1 is also turned on.

  When the gate voltage of the transistor Q1 is sufficiently asymptotic to 37V, the on-resistance Ron1 is, for example, 1Ω. However, immediately after the transistor Q1 is turned on, the gate-source voltage is near the threshold voltage Vth1, so the on-resistance Ron1 is higher than 1Ω. The switch element SW1 of the switch circuit 62 is turned on when the on-resistance Ron1 is high. If the on-resistance Ron1 is high, the charge current IC flowing through the bridge circuit 10 is also small. However, since the voltage drop width due to the on-resistance is Ron1 · IC, even if the charge current IC is small, it exceeds a predetermined value and the detection circuit 64 It may be detected and the driving operation of the bridge circuit 10 may be stopped. For example, when an overcurrent is detected at IC = 1.5 A, it is determined that an overcurrent is normally caused by a voltage drop of Ron1 · IC = 1Ω · 1.5A = 1.5V. On the other hand, if the on-resistance Ron1 = 10Ω, for example, immediately after the transistor Q1 is turned on, an overcurrent is determined as Ron1 / 1.5V = 10Ω / 1.5V = 150 mA.

  The above is the high side, but the same applies to the low side. That is, as shown in FIG. 5B, the gate voltage (drive signal DG4) of the transistor Q4 of the bridge circuit 10 is 5V (H level) in the decay period and 0V (L level) in the charge period. If the threshold voltage of the N-type transistor is Vth4 = 1.5V, for example, the switch element SW4 of the switch circuit 62 is also turned on when the gate voltage (gate-source voltage) of the transistor Q4 becomes Vth4 = 1.5V. . Since the switch element SW4 is turned on when the transistor Q4 on-resistance Ron4 is high, the detection circuit 64 actually detects the overcurrent even though the charge current IC is small, and the driving operation of the bridge circuit 10 is performed. There is a possibility to stop.

  If the overcurrent cannot be accurately detected as described above, for example, the detection threshold (1.5 V (1.5 A) in the above example) is increased to prevent the drive operation from being stopped due to erroneous detection. However, considering the safety of preventing the bridge circuit 10 from being destroyed, it is desirable that the detection threshold is as low as possible within a range in which no erroneous detection occurs. In the comparative example of FIG. 4, in the transition period between the charge period and the decay period as described above, there is a possibility that an overcurrent due to a short circuit or the like is actually detected as an overcurrent even if it does not flow through the bridge circuit 10. Therefore, the detection threshold cannot be lowered.

3. Overcurrent Detection Circuit According to this Embodiment FIG. 6 shows a configuration example of an overcurrent detection circuit 60 according to this embodiment that can solve the above-described problems. The overcurrent detection circuit 60 of this embodiment includes a switch circuit 62, a detection circuit 64, and a switching control circuit 66. In addition, the same code | symbol is attached | subjected to the component same as the component mentioned above, and description is abbreviate | omitted suitably.

  First, a configuration for detecting an overcurrent flowing through the high-side transistors Q1 and Q3 of the bridge circuit 10 will be described.

  The switch circuit 62 includes a first switch element SW1 having one end connected to the first node N1 between the first transistor Q1 and the second transistor Q2. The detection circuit 64 detects the current (overcurrent) of the bridge circuit 10 based on the voltage SQ1 of the node at the other end of the first switch element SW1. The control circuit 20 outputs the on / off control signals IN1 and IN2 of the bridge circuit 10 to the first driver circuit PR1 and the second driver circuit PR2, and when a current (overcurrent) is detected by the detection circuit 64 The on / off operation of the bridge circuit 10 is stopped.

  Then, the switching control circuit 66 outputs a first switch control signal CT1 for controlling on / off of the first switch element SW1 based on the output (drive signal DG1) of the first driver circuit PR1. At this time, when it is determined that the on-resistance of the first transistor Q1 is smaller than the given first on-resistance, the first switch control signal CT1 is activated.

  The switch circuit 62 includes a third switch element SW3 having one end connected to the second node N2 between the third transistor Q3 and the fourth transistor Q4. The detection circuit 64 detects the current (overcurrent) of the bridge circuit 10 based on the voltage SQ3 of the node at the other end of the third switch element SW3. The control circuit 20 outputs the on / off control signals IN3 and IN4 of the bridge circuit 10 to the third driver circuit PR3 and the fourth driver circuit PR4, and when a current (overcurrent) is detected by the detection circuit 64 The on / off operation of the bridge circuit 10 is stopped.

  The switching control circuit 66 outputs a third switch control signal CT3 for controlling on / off of the third switch element SW3 based on the output (drive signal DG3) of the third driver circuit PR3. At this time, when it is determined that the on-resistance of the third transistor Q3 is smaller than the given third on-resistance, the third switch control signal CT3 is activated. A given third on-resistance is for example equal to a given first on-resistance.

  Hereinafter, the operation of the overcurrent detection circuit 60 will be described by taking as an example the case of detecting the overcurrent flowing through the transistor Q1 during the charge period. The operation is the same when detecting an overcurrent flowing through the transistor Q3 during the decay period.

  FIG. 7 shows a timing chart of the overcurrent detection circuit 60 of the present embodiment. As shown in FIG. 7, when switching from the decay period to the charge period, the gate voltage (drive signal DG1) of the transistor Q1 of the bridge circuit 10 becomes smaller than VBB-Vth1 (the gate-source voltage is the threshold voltage Vth1). The transistor Q1 is turned on, the gate voltage (drive signal DG1) is lowered, and the on-resistance Ron1 is reduced. When the on-resistance Ron1 of the transistor Q1 becomes smaller than a given first on-resistance RG1, the switch element SW1 of the switch circuit 62 is turned on.

  On the other hand, when the charge period is switched to the decay period, the gate voltage (drive signal DG1) of the transistor Q1 increases and the on-resistance Ron1 increases, so that the on-resistance Ron1 of the transistor Q1 is larger than a given first on-resistance RG1. When this happens, the switch element SW1 of the switch circuit 62 is turned off.

  In the comparative example of FIG. 4 and FIG. 5, the on / off control of the switch element SW1 is performed by the drive signal DG1 of the transistor Q1, but in this embodiment, a switching control circuit is provided between the driver circuit PR1 and the gate of the switch element SW1. 66 is provided. The switching control circuit 66 performs on / off control of the switch element SW1, thereby delaying the timing at which the switch element SW1 of the switch circuit 62 is turned on from the timing at which the transistor Q1 of the bridge circuit 10 is turned on. it can.

  That is, after the transistor Q1 is turned on, the switch element SW1 of the switch circuit 62 can be turned on at the timing when the on-resistance Ron1 becomes a given first on-resistance RG1. Thus, after the on-resistance Ron1 of the transistor Q1 becomes sufficiently small, the voltage V1 = SQ1 = VBB−Ron1 · IC of the drain node N1 of the transistor Q1 can be input to the detection circuit 64. Since the on-resistance Ron1 is sufficiently small, a large current needs to flow through the bridge circuit 10 in order for the voltage drop Ron1 · IC of the drain node N1 to exceed a predetermined value, so that erroneous detection of overcurrent can be suppressed. In the comparative example of FIG. 4 and FIG. 5, it was necessary to increase the detection threshold (1.5 A) in order to avoid operation stop due to erroneous detection, but in this embodiment, while setting a threshold that does not cause destruction, Operation stop due to erroneous detection can be suppressed.

  Note that “when judged” is not limited to actually making any judgment, and includes a case where it is considered that the on-resistance has become smaller than a given first on-resistance indirectly although no judgment is made. As an example of actual determination, there is an example in which the gate voltage (drive signal DG1) of the transistor Q1 and the reference voltage are compared as will be described later. As an example in which the determination is not performed, the edge of the switch control signal CT1 is delayed from the edge of the gate voltage (drive signal DG1) of the transistor Q1, as described later, and an on-resistance is indirectly given by the delay time. There is an example in which it is considered that the resistance is smaller than the on-resistance.

  Now, the given first on-resistance RG1 described above is specifically set as follows. That is, as shown in FIG. 7, a given first on-resistance RG1 has an on-resistance RonM1 (1Ω) when the gate-source voltage of the transistor Q1 becomes maximum (VBB−DG1 = VBB−VHB = 5V). ), RG1 ≦ 2 × RonM1.

  FIG. 8 shows an example of on-resistance characteristics of the high-side transistor Q1 (Q3). The horizontal axis of FIG. 8 shows the gate-source voltage. In the example of FIG. 8, the on-resistance RonM1 is about 1.7Ω when the gate-source voltage of the transistor Q1 reaches a maximum of 5V. In this case, a given first on-resistance RG1 is set to 2 × 1.7Ω or less. For example, about 2Ω (≦ 2 × 1.7Ω), which is an on-resistance when the gate-source voltage is 4.5 V, may be set to a given first on-resistance RG1.

  In this way, during the period in which the switch element SW1 of the switch circuit 62 is on (overcurrent detection period), the variation of the on-resistance Ron1 of the transistor Q1 can be less than twice the minimum value RonM1. For example, consider a case where the charge current IC ≧ 1.5 A is detected as an overcurrent when the transistor Q1 is completely turned on (when Ron1 = RonM1). If the normal charge current is, for example, IC = 0.5A, it is determined as an overcurrent when 1.0A further flows. Since the voltage drop is Ron1 · IC, in the case of Ron1 = 2 × RonM1, the charge current IC is allowed to be about 1.5A / 2 = 0.75A. Since the on-resistance Ron1 is twice, the normal charge current is IC = 0.5 A / 2 = 0.25 A, and when 0.5 A further flows, it is determined as an overcurrent. That is, at least 0.5 A is secured as an allowable range for detecting overcurrent. As described above, since the error of the on-resistance Ron1 is reduced during the overcurrent detection period, the overcurrent detection error (the difference between 1A and 0.5A in the above example) is reduced, and erroneous detection is suppressed.

  As described above, in the present embodiment, it is detected that the on-resistance Ron1 of the transistor Q1 is smaller than the given first on-resistance RG1, but this is specifically realized by the following configuration.

  That is, the switching control circuit 66 includes a first comparison circuit CPA1 that compares a voltage based on the output (drive signal DG1) of the first driver circuit PR1 with the first reference voltage. Then, the switching control circuit 66 activates the first switch control signal CT1 based on the comparison result (output signal CPQ1) by the first comparison circuit CPA1.

  Specifically, the switching control circuit 66 includes an OR circuit OR1. The OR circuit OR1 outputs the logical sum of the output of the first driver circuit PR1 and the output of the first comparison circuit CPA1 as the first switch control signal CT1. As shown in FIG. 7, when VSS is used as a reference, the first reference voltage is, for example, 37.5 V (> 37 V = VHB). When VBB is used as a reference, the first reference voltage is 4.5V (> 5V). In this case, when the voltage of the drive signal DG1 is equal to or lower than the first reference voltage 37.5V (VBB-DG1 ≧ 4.5V), the output signal CPQ1 of the first comparison circuit CPA1 becomes L level (active), The first switch control signal CT1 that is the output signal of the OR circuit OR1 becomes L level (active).

  In this way, it is possible to detect that the on-resistance Ron1 of the transistor Q1 has become smaller than the given first on-resistance RG1 by voltage detection by the comparison circuit CPA1. The given first on-resistance RG1 is the on-resistance of the transistor Q1 when the voltage based on the output of the first driver circuit PR1 becomes equal to the first reference voltage with reference to the voltage of the power supply VBB. The voltage based on the output of the first driver circuit PR1 is, for example, a voltage DGD1 obtained by resistance-dividing between the power supply VBB and the output of the first driver circuit PR1 (drive signal DG1), as will be described later with reference to FIG. Note that the voltage based on the output of the first driver circuit PR1 is not limited thereto, and may be the output itself of the first driver circuit PR1.

  In addition, when detecting the overcurrent flowing through the transistor Q3, it is detected that the on-resistance Ron3 of the transistor Q3 is smaller than a given third on-resistance. Specifically, this is realized by the following configuration. .

  That is, the switching control circuit 66 compares the voltage based on the output (drive signal DG3) of the third driver circuit PR3 with a third reference voltage (for example, equal to the first reference voltage), the third comparison circuit CPA3. Have Then, the switching control circuit 66 activates the third switch control signal CT3 based on the comparison result (output signal CPQ3) by the third comparison circuit CPA3. Specifically, the switching control circuit 66 includes an OR circuit OR3. The OR circuit OR3 outputs a logical sum of the output of the third driver circuit PR3 and the output of the first comparison circuit CPA3 as the third switch control signal CT3.

  In the above description, the first reference voltage is 4.5 V with reference to the voltage 42 V of the power supply VBB. However, the first reference voltage is the L level of the gate-source voltage from the threshold voltage Vth1 = 1.5 V of the transistor Q1. Various selections are possible within the range of (VBB-VHB = 5V). For example, on the basis of the voltage 42V (source voltage of the transistor Q1) of the high potential side power supply VBB of the bridge circuit, the voltage output by the first driver circuit PR1 when turning on the first transistor Q1 is VDR1, and the first When the reference voltage of Vref1 is Vref1, Vref1 = (VDR1-Vth1) / 2 + Vth1.

  In this embodiment, since VDR1 = VBB−VHB, Vref1 = ((VBB−VHB) −Vth1) / 2 + Vth1. As shown in FIG. 8, the reference voltage Vref1 is an intermediate voltage between the threshold voltage Vth1 and the L level (VBB-VHB). The on-resistance characteristic with respect to the gate-source voltage has a steep slope in the vicinity of the threshold voltage Vth1. On the other hand, in the section from the intermediate voltage to the L level (VHB), the slope is gentle, and the on-resistance is asymptotic to the minimum value. Therefore, by setting the intermediate voltage as the reference voltage Vref1, detection of overcurrent can be started when the on-resistance is sufficiently close to the minimum value. In the example of FIG. 8, when Vref1 = ((VBB−VHB) −Vth1) / 2 + Vth1, the on-resistance Ron1 is about 3.5Ω (2 × RonM1), which is about twice the minimum value of 1.7Ω (RonM1). It has become.

  Next, a configuration for detecting an overcurrent flowing through the low-side transistors Q2 and Q4 of the bridge circuit 10 will be described.

  As shown in FIG. 6, the switch circuit 62 includes a second switch element SW2 having one end connected to the first node N1 between the first transistor Q1 and the second transistor Q2. The detection circuit 64 detects the current (overcurrent) of the bridge circuit 10 based on the voltage SQ2 at the node at the other end of the second switch element SW2.

  Then, the switching control circuit 66 outputs a second switch control signal CT2 for controlling on / off of the second switch element SW2. At this time, the switching control circuit 66 activates the second switch control signal CT2 when it is determined that the on-resistance of the second transistor Q2 is smaller than a given second on-resistance.

  The switch circuit 62 includes a fourth switch element SW4 having one end connected to the second node N2 between the third transistor Q3 and the fourth transistor Q4. The detection circuit 64 detects the current (overcurrent) of the bridge circuit 10 based on the voltage SQ4 of the node at the other end of the fourth switch element SW4.

  Then, the switching control circuit 66 outputs a fourth switch control signal CT4 for controlling on / off of the fourth switch element SW4. At this time, the switching control circuit 66 activates the fourth switch control signal CT4 when it is determined that the on-resistance of the fourth transistor Q4 is smaller than a given fourth on-resistance. A given fourth on-resistance is, for example, equal to a given second on-resistance.

  Hereinafter, the operation of the overcurrent detection circuit 60 will be described by taking as an example the case of detecting the overcurrent flowing through the transistor Q2 during the decay period. The operation is the same when detecting an overcurrent flowing through the transistor Q4 during the charging period.

  FIG. 9 shows a timing chart of the overcurrent detection circuit 60 of the present embodiment. As shown in FIG. 9, when the gate voltage (drive signal DG2) of the transistor Q2 of the bridge circuit 10 becomes lower than the threshold voltage Vth2 when the charge period is switched to the decay period, the transistor Q2 is turned on, and the gate voltage As the (drive signal DG2) decreases, the on-resistance Ron2 decreases. When the on-resistance Ron2 of the transistor Q2 becomes smaller than a given second on-resistance RG2, the switch element SW2 of the switch circuit 62 is turned on.

  On the other hand, when switching from the decay period to the charge period, the gate voltage (drive signal DG2) of the transistor Q2 increases and the on-resistance Ron2 increases, so that the on-resistance Ron2 of the transistor Q2 is larger than a given second on-resistance RG2. When this happens, the switch element SW2 of the switch circuit 62 is turned off.

  According to the above, the voltage V1 = SQ2 = VS−Ron2 · ID of the drain node N1 of the transistor Q2 can be input to the detection circuit 64 after the on-resistance Ron2 of the transistor Q2 becomes sufficiently small. Since the on-resistance Ron2 is sufficiently small, a large current needs to flow through the bridge circuit 10 in order for the voltage drop Ron2 · ID of the drain node N2 to exceed a predetermined value, so that it is possible to suppress erroneous detection of overcurrent.

  Now, the given second on-resistance RG2 described above is specifically set as follows. That is, when the on-resistance when the gate-source voltage of the second transistor Q2 is maximum (DG2-VSS = VLB-VSS = 5V) is RonM2, and the given second on-resistance is RG2, Ron2 ≦ 2 × RonM2.

  In this way, during the period in which the switch element SW2 of the switch circuit 62 is on (overcurrent detection period), the variation of the on-resistance Ron2 of the transistor Q2 can be less than twice the minimum value RonM2. As described in the overcurrent detection of the transistor Q1, the error of the on-resistance Ron2 is reduced during the overcurrent detection period, so that the detection error of the overcurrent is reduced and erroneous detection is suppressed.

  The configuration for detecting that the on-resistance Ron2 of the transistor Q2 is smaller than a given second on-resistance RG2 is specifically realized as follows.

  That is, the switching control circuit 66 includes a second comparison circuit CPA2 that compares the voltage based on the output (drive signal DG2) of the second driver circuit PR2 with the second reference voltage. Then, the switching control circuit 66 activates the second switch control signal CT2 based on the comparison result (output signal CPQ2) by the second comparison circuit CPA2.

  Specifically, the switching control circuit 66 includes an AND circuit AN2. The AND circuit AN2 outputs a logical product of the output of the second driver circuit PR2 and the output of the second comparison circuit CPA2 as the second switch control signal CT2. As shown in FIG. 9, the second reference voltage is, for example, 4.5V (<5V = VLB). In this case, when the voltage of the drive signal DG2 becomes equal to or higher than the second reference voltage 4.5V, the output signal CPQ2 of the second comparison circuit CPA2 becomes H level (active) and is the output signal of the AND circuit AN2. The second switch control signal CT2 becomes H level (active).

  In this way, it is possible to detect that the on-resistance Ron2 of the transistor Q2 is smaller than the given second on-resistance RG2 by detecting the voltage using the comparison circuit CPA2. The given second on-resistance RG2 is the on-resistance of the transistor Q2 when the voltage based on the output of the second driver circuit PR2 becomes equal to the second reference voltage. The voltage based on the output of the second driver circuit PR2 is, for example, a voltage DGD2 obtained by resistance-dividing between the output (drive signal DG2) of the first driver circuit PR2 and the power supply VSS, as will be described later with reference to FIG. The voltage based on the output of the second driver circuit PR2 is not limited to this, and may be the output itself of the second driver circuit PR2.

  When detecting the overcurrent flowing through the transistor Q4, it is detected that the on-resistance Ron4 of the transistor Q4 is smaller than a given fourth on-resistance. Specifically, this is realized by the following configuration. .

  That is, the switching control circuit 66 compares the voltage based on the output (drive signal DG4) of the fourth driver circuit PR4 with a fourth reference voltage (for example, equal to the second reference voltage), the fourth comparison circuit CPA4. Have Then, the switching control circuit 66 activates the fourth switch control signal CT4 based on the comparison result (output signal CPQ4) by the fourth comparison circuit CPA4. Specifically, the switching control circuit 66 includes an AND circuit AN4. The AND circuit AN4 outputs the logical product of the output of the fourth driver circuit PR4 and the output of the fourth comparison circuit CPA4 as the fourth switch control signal CT4.

  In the above description, the second reference voltage is 4.5 V. However, the second reference voltage can be variously selected in the range from the threshold voltage Vth2 of the transistor Q2 to the H level (VLB) of the gate voltage. For example, when the voltage of the low potential side power supply VSS of the bridge circuit is used as a reference, the voltage output by the second driver circuit PR2 when turning on the second transistor Q2 is VDR2, and the second reference voltage is Vref2. Vref2 = (VDR2−Vth2) / 2 + Vth2.

  In this embodiment, since VDR2 = VLB, Vref2 = (VLB−Vth2) / 2 + Vth2. The reference voltage Vref2 is an intermediate voltage between the threshold voltage Vth2 and the H level (VLB). In the same manner as described for the reference voltage Vref1 in FIG. 8, by setting the intermediate voltage between the threshold voltage Vth2 and the H level as the reference voltage Vref2, the overcurrent is detected when the on-resistance is sufficiently close to the minimum value. You can start.

  Next, a detailed configuration of the detection circuit 64 will be described. The detection circuit 64 includes first to fourth determination circuits CPB1 to CPB4 and a detection signal output circuit DTQ.

  In the first determination circuit CPB1, the difference between the voltage of the source node of the first transistor Q1 (the voltage of the power supply VBB) and the voltage SQ1 of the node at the other end of the first switch element SW1 is less than the first predetermined value. Determine whether it is larger. The difference is VBB−SQ1 = Ron1 · IC, which corresponds to a voltage drop due to the on-resistance Ron1. When this difference is larger than the first predetermined value, the first determination circuit CPB1 activates the output CBQ1.

  The second determination circuit CPB2 determines whether the difference between the voltage SQ2 at the other end of the second switch element SW2 and the voltage VS at the source node N3 of the second transistor Q2 is greater than a second predetermined value. Determine. The difference is VS−SQ2 = Ron2 · ID, which corresponds to a voltage drop due to the on-resistance Ron2. When this difference is larger than the second predetermined value, the second determination circuit CPB2 activates the output CBQ2.

  In the third determination circuit CPB3, the difference between the voltage of the source node of the third transistor Q3 (voltage of the power supply VBB) and the voltage SQ3 of the node at the other end of the third switch element SW3 is greater than the third predetermined value. Determine whether it is larger. The third predetermined value is equal to the first predetermined value, for example. The difference is SQ3−VBB = Ron3 · ID, which corresponds to a voltage drop due to the on-resistance Ron3. When this difference is larger than the third predetermined value, the third determination circuit CPB3 activates the output CBQ3.

  The fourth determination circuit CPB4 determines whether the difference between the voltage SQ4 at the other end of the fourth switch element SW4 and the voltage VS at the source node N4 of the fourth transistor Q4 is greater than a fourth predetermined value. Determine. For example, the fourth predetermined value is equal to the second predetermined value. The difference is SQ4−VS = Ron4 · IC, which corresponds to a voltage drop due to the on-resistance Ron4. When this difference is larger than the fourth predetermined value, the fourth determination circuit CPB4 activates the output CBQ4.

  The detection signal output circuit DTQ activates the current (overcurrent) detection signal DET when at least one of the outputs CBQ1 to CBQ4 of the first to fourth determination circuits CPB1 to CPB4 becomes active. . That is, if any one of the outputs CBQ1 to CBQ4 becomes active, it can be determined that an overcurrent has passed through the bridge circuit 10.

  For example, the first determination circuit CPB1 is realized by a determination circuit (comparator) described later in FIG. 12, and the detection signal output circuit DTQ is realized by an OR circuit described later in FIG. In this case, for example, the first predetermined value is the voltage SQ1 when the output CBQ1 of the determination circuit of FIG. 12 becomes the threshold voltage of the N-type transistor TG1 of the OR circuit of FIG.

4). Comparison Circuit of Switching Control Circuit FIG. 10 shows a detailed configuration example of the first comparison circuit CPA1 (high-side comparison circuit) of the switching control circuit 66. The third comparison circuit CPA3 can be configured similarly.

  The first comparison circuit CPA1 includes resistance elements RC1 and RC2, a reference voltage generation circuit VRC1, and a comparator CPC1.

  The reference voltage generation circuit VRC1 outputs a reference voltage VRH. The reference voltage VRH is input to the first input terminal (positive terminal) of the comparator CPC1. The resistance elements RC1 and RC2 perform resistance division between the voltage of the power supply VBB and the gate voltage (drive signal DG1) of the first transistor Q1. The voltage DGD1 obtained by resistance division is input to the second input terminal (negative electrode terminal) of the comparator CPC1. The comparator CPC1 compares the reference voltage VRH with the voltage DGD1, outputs an L level (inactive) output signal CPQ1 when DGD1> VRH, and outputs an H level (active) when DGD1 ≦ VRH. The signal CPQ1 is output.

  When the resistance values of the resistance elements RC1 and RC2 are rc1 and rc2, DGD1 = VBB− {rc2 / (rc1 + rc2)} (VBB−DG1). If the voltage of the drive signal DG1 when DGD1 = VRH is the detection level VDETH, VDETH = VBB-{(rc1 + rc2) / rc2} (VBB-VRH) is obtained. This VDETH is set so that the on-resistance Ron1 of the transistor Q1 becomes a given first on-resistance RG1 when DG1 = VDETH.

  FIG. 11 shows a detailed configuration example of the second comparison circuit CPA2 (low-side comparison circuit) of the switching control circuit 66. The fourth comparison circuit CPA4 can be configured similarly.

  The second comparison circuit CPA2 includes resistance elements RD1 and RD2, a reference voltage generation circuit VRD1, and a comparator CPD1.

  The reference voltage generation circuit VRD1 outputs a reference voltage VRL. The reference voltage VRL is input to the first input terminal (positive terminal) of the comparator CPC1. The resistance elements RD1 and RD2 perform resistance division between the gate voltage (drive signal DG2) of the second transistor Q2 and the voltage of the power supply VSS. The voltage DGD2 obtained by the resistance division is input to the second input terminal (negative terminal) of the comparator CPD1. The comparator CPD1 compares the reference voltage VRL with the voltage DGD2, outputs an L level (inactive) output signal CPQ2 when DGD2> VRL, and outputs an H level (active) when DGD2 ≦ VRL. Signal CPQ2 is output.

  When the resistance values of the resistance elements RD1 and RD2 are rd1 and rd2, DGD2 = {rd1 / (rd1 + rd2)} DG2. When the voltage of the drive signal DG2 when DGD2 = VRL is the detection level VDETL, VDETL = {(rd1 + rd2) / rd1} VRL is obtained. This VDETL is set so that the on-resistance Ron2 of the transistor Q2 becomes a given second on-resistance RG2 when DG2 = VDETL.

5. FIG. 12 shows a detailed configuration example of the first determination circuit CPB1 (high-side determination circuit) of the detection circuit 64.

  The first determination circuit CPB1 includes resistance elements RE1 and RE2, bipolar transistors BPE1 and BPE2, P-type transistors TE1 and TE2, and N-type transistors TE3 to TE6.

  The bias voltage NBH is supplied to the gates of the N-type transistors TE3 and TE4, and the bias voltage NBL is supplied to the gates of the N-type transistors TE5 and TE6. The P-type transistor is connected in a current mirror. These transistors TE1 to TE6 supply a bias current to the collectors of the bipolar transistors BPE1 and BPF2.

  The other end of the first switch element SW1 of the switch circuit 62 (that is, the drain of the first transistor Q1 of the bridge circuit 10) is connected to the emitter of the bipolar transistor BPE1. Further, the node of the power supply VBB is connected through the resistance element RE1. The node of the power supply VBB is connected to the emitter of the bipolar transistor BPE2 via the resistance element RE2. When the first switch element SW1 is on, when the drain voltage V1 of the first transistor Q1 decreases, the voltage SQ1 at the other end of the first switch element SW1 decreases. At this time, the collector voltage of the bipolar transistor BPE1 decreases. Since the base of the bipolar transistor BPE2 is connected to the collector of the bipolar transistor BPE1, the base current of the bipolar transistor BPE2 increases. Then, the collector current of the bipolar transistor BPE2 increases and the voltage of the output CBQ1 increases.

  This output CBQ1 is input to the gate of an N-type transistor TG1 of a detection signal output circuit, which will be described later with reference to FIG. 14. When the voltage of the output CBQ1 exceeds the threshold voltage of the N-type transistor TG1, the N-type transistor TG1 is turned on. . When the voltage SQ1 when the voltage of the output CBQ1 becomes the threshold voltage of the N-type transistor TG1 is SQDET1, the N-type transistor TG1 is turned off when SQ1> SQDET1, and the N-type transistor TG1 is turned on when SQ1 ≦ SQDET1. .

  Let IDETH be the current flowing through the transistor Q1 when the voltage of the output CBQ1 becomes the threshold voltage of the N-type transistor TG1. Since the source-drain voltage of the transistor Q1 is Ron1 · IDETH, SQDET1 = VBB−Ron1 · IDETH. For example, the resistance values of the resistance elements RE1 and RE2 are adjusted to determine SQDET1 so that the IDETH becomes a desired overcurrent detection value.

  FIG. 13 shows a detailed configuration example of the fourth determination circuit CPB4 (low-side comparison circuit) of the detection circuit 64.

  The fourth determination circuit CPB4 includes resistance elements RF1 to RF4, bipolar transistors BPF1 to BPF5, and P-type transistors TF1 to TF3.

  A bias voltage PB is supplied to the gates of the P-type transistors TF1 and TF2, and a bias current is supplied to the collectors of the bipolar transistors BPF1 and BPF2 by the transistors TF1 and TF2.

  The source node N3 (voltage VS) of the fourth transistor Q4 of the bridge circuit 10 is connected to the emitter of the bipolar transistor BPF1 via the resistance element RF1. The other end of the fourth switch element SW4 of the switch circuit 62 (that is, the drain of the fourth transistor Q4) is connected to the emitter of the bipolar transistor BPF2 via the resistance element RF2. When the fourth switch element SW4 is on, when the drain voltage V2 of the fourth transistor Q4 increases, the voltage SQ4 at the other end of the fourth switch element SW4 increases. At this time, since the bipolar transistors BPF1 and BPF2 are current mirror connected, the base potential of the bipolar transistor BPF2 does not change. Therefore, the base current of the bipolar transistor BPE2 is reduced, and the collector current is reduced. Since the bias current is constant, the base current of the bipolar transistor BPF3 increases.

  The node of the bias voltage VLB is connected to the collector of the bipolar transistor BPF3 via the resistance element RF3. Further, the gate of the P-type transistor TF3 is connected. The drain of the P-type transistor TF3 is a node of the output CBQ4. A node of the power source VSS is connected to the drain via the resistance element RF4. When the base current of the bipolar transistor BPF3 increases, the collector current increases and the gate voltage of the P-type transistor TF3 decreases. Since the drain current of the P-type transistor TF3 increases, the voltage of the output CBQ4 increases.

  This output CBQ4 is input to the gate of an N-type transistor TG4 of a detection signal output circuit, which will be described later with reference to FIG. 14. When the voltage of the output CBQ4 exceeds the threshold voltage of the N-type transistor TG4, the N-type transistor TG4 is turned on. . When the voltage SQ4 when the voltage of the output CBQ4 becomes the threshold voltage of the N-type transistor TG4 is SQDET4, the N-type transistor TG4 is turned off when SQ4> SQDET4, and the N-type transistor TG4 is turned on when SQ4 ≦ SQDET4. .

  Let IDETL be the current flowing through the transistor Q4 when the voltage of the output CBQ4 becomes the threshold voltage of the N-type transistor TG4. Since the source-drain voltage of the transistor Q4 is Ron4 · IDETL, SQDET4 = VS + Ron4 · IDETL. For example, the resistance values of the resistance elements RF1 and RF2 are adjusted to determine SQDET4 so that the IDETL becomes a desired overcurrent detection value.

  FIG. 14 shows a detailed configuration example of the detection signal output circuit DTQ of the detection circuit 64. The detection signal output circuit DTQ includes a resistance element RG, N-type transistors TG1 to TG4, and an inverter ING.

  A node of the bias voltage VLB is connected to one end of the resistance element RG. The other ends of the resistance elements RG are commonly connected to the drains of the N-type transistors TG1 to TG4, and connected to the input terminal of the inverter ING. A node of the power source VSS is commonly connected to sources of the N-type transistors TG1 to TG4. The detection signal output circuit DTQ becomes a logical sum circuit with respect to the outputs CBQ1 to CBQ4 of the first to fourth determination circuits CPB1 to CPB4. That is, when one of the outputs CBQ1 to CBQ4 becomes active (exceeds the threshold voltage of the N-type transistors TG1 to TG4) and even one of the N-type transistors TG1 to TG4 is turned on, the L level is input to the inverter ING. The detection signal DET becomes high level (active).

6). Modification Example of Switching Control Circuit Next, a modification example of the switching control circuit 66 will be described. In the modification, the first to fourth comparison circuits CPA1 to CPA4 are replaced with first to fourth delay circuits. That is, after the drive signals DG1 to DG4 become active, the first to fourth switch control signals CT1 to CT4 become active with a delay. This delay time is set to a time when it is determined that the on-resistances of the first to fourth transistors Q1 to Q4 of the bridge circuit 10 are smaller than the given first to fourth on-resistances.

  FIG. 15 shows a detailed configuration example of the first delay circuit (high-side delay circuit). The third delay circuit can be configured similarly.

  The first delay circuit includes P-type transistors TK1 and TK3, N-type transistors TK2 and TK4, resistance elements RK1 and RK2, and a capacitor CK.

  The P-type transistor TK1 and the N-type transistor TK2 constitute a first inverter, and the P-type transistor TK3 and the N-type transistor TK4 constitute a second inverter. The resistance element RK1 and the capacitor CK constitute a low-pass filter and are driven by the first inverter. The delay time is basically determined by the time constant of the low-pass filter. The delay time also depends on the ON resistance of the transistors TK1 to TK4 and the resistance value of the resistance element RK2. For example, the timing later than the timing at which the on-resistance of the first transistor Q1 of the bridge circuit 10 becomes a given first on-resistance (RG1 in FIG. 7) (timing at which DG1 = 37.5V in the example of FIG. 7). Thus, the delay time is determined in consideration of the tolerance so that the output signal CPQ1 of the first delay circuit becomes active.

  FIG. 16 shows a detailed configuration example of the second delay circuit (low-side delay circuit). The fourth delay circuit can be configured similarly.

  The second delay circuit includes P-type transistors TJ1 and TJ3, N-type transistors TJ2 and TJ4, resistance elements RJ1 and RJ2, and a capacitor CJ.

  The P-type transistor TJ1 and the N-type transistor TJ2 constitute a first inverter, and the P-type transistor TJ3 and the N-type transistor TJ4 constitute a second inverter. The resistance element RJ1 and the capacitor CJ constitute a low-pass filter and are driven by the first inverter. The delay time is basically determined by the time constant of the low-pass filter. The delay time also depends on the ON resistance of the transistors TJ1 to TJ4 and the resistance value of the resistance element RJ2. For example, a timing later than the timing at which the on-resistance of the second transistor Q2 of the bridge circuit 10 becomes a given second on-resistance (RG2 in FIG. 9) (timing at which DG2 = 4.5V in the example of FIG. 9). Thus, the delay time is determined in consideration of the tolerance so that the output signal CPQ1 of the first delay circuit becomes active.

7). Electronic Device FIG. 17 shows a configuration example of an electronic device to which the circuit device (motor driver) of this embodiment is applied. The electronic device includes a processing unit 300, a storage unit 310, an operation unit 320, an input / output unit 330, a circuit device 200, a bus 340 connecting these units, and a motor 280. In the following description, a printer that controls the head and paper feeding by motor drive will be described as an example. However, the present embodiment is not limited to this and can be applied to various electronic devices.

  The input / output unit 330 is configured by an interface such as a USB connector or a wireless LAN, and receives image data and document data. The input data is stored in the storage unit 310 which is an internal storage device such as a DRAM. When the printing instruction is received by the operation unit 320, the processing unit 300 starts a printing operation of data stored in the storage unit 310. The processing unit 300 sends an instruction to the circuit device 200 (motor driver) according to the print layout of the data, and the circuit device 200 rotates the motor 280 based on the instruction to move the head and feed the paper.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configurations and operations of the bridge circuit, overcurrent detection circuit, circuit device, and electronic device are not limited to those described in the present embodiment, and various modifications can be made.

10 bridge circuit, 20 control circuit, 30 chopping current detection circuit,
32 reference voltage generation circuit, 34 D / A conversion circuit, 36 comparator,
40 pre-driver, 50 register section, 60 overcurrent detection circuit,
62 switch circuit, 64 detection circuit, 66 switching control circuit,
100 motor, 200 circuit device, 280 motor 300 processing unit, 310 storage unit, 320 operation unit, 330 input / output unit, 340 bus,
AN2, AN4 AND circuit, CPA1-CPA4 comparison circuit,
CPB1-CPB4 determination circuit, CT1-CT4 switch control signal,
DG1 to DG4 drive signal (driver circuit output), DTQ detection signal output circuit,
IC charge current, ID decay current, N1 first node, N2 second node,
OR1, OR3 OR circuit, PR1 to PR4 driver circuit,
Q1-Q4 transistors, RG1 given first on-resistance,
RG2 a given second on-resistance, SW1-SW4 switch element,

Claims (12)

A bridge circuit having a first transistor on the high side and a second transistor on the low side;
A pre-driver having a first driver circuit for driving the first transistor and a second driver circuit for driving the second transistor;
A switch circuit having a first switch element having one end connected to a first node between the first transistor and the second transistor;
A switching control circuit for outputting a first switch control signal for controlling on / off of the first switch element based on an output of the first driver circuit;
A detection circuit that detects a current of the bridge circuit based on a voltage of a node at the other end of the first switch element;
Control for outputting an on / off control signal of the bridge circuit to the first driver circuit and the second driver circuit, and stopping an on / off operation of the bridge circuit when a current is detected by the detection circuit. Circuit,
Including
The switching control circuit includes:
The circuit device, wherein the first switch control signal is activated when it is determined that the on-resistance of the first transistor is smaller than a given first on-resistance. In claim 1,
When the on-resistance when the gate-source voltage of the first transistor becomes maximum is RonM1, and the given first on-resistance is RG1,
RG1 ≦ 2 × RonM1 circuit device. In claim 1 or 2,
The switching control circuit includes:
A first comparison circuit that compares a voltage based on the output of the first driver circuit with a first reference voltage;
The circuit device characterized in that the first switch control signal is activated based on a result of comparison by the first comparison circuit. In claim 3,
The threshold voltage of the first transistor is set to Vth1 with reference to the high-potential-side power supply voltage of the bridge circuit, and the voltage output by the first driver circuit when turning on the first transistor is set to VDR1. When the first reference voltage is Vref1,
Vref1 = (VDR1−Vth1) / 2 + Vth1 In any one of Claims 1 thru | or 4,
The switch circuit is
A second switch element having one end connected to the first node;
The detection circuit includes:
Detecting the current of the bridge circuit based on the voltage of the node at the other end of the second switch element;
The switching control circuit includes:
Outputting a second switch control signal for controlling on / off of the second switch element;
2. The circuit device according to claim 1, wherein the second switch control signal is activated when it is determined that the on-resistance of the second transistor is smaller than a given second on-resistance. In claim 5,
When the on-resistance when the gate-source voltage of the second transistor is maximized is RonM2, and the given second on-resistance is RG2,
RG2 ≦ 2 × RonM2 circuit device. In claim 5 or 6,
The switching control circuit includes:
A second comparison circuit that compares a voltage based on the output of the second driver circuit with a second reference voltage;
The circuit device characterized in that the second switch control signal is activated based on a result of comparison by the second comparison circuit. In claim 7,
When the threshold voltage of the second transistor is Vth2, the voltage output by the second driver circuit when turning on the second transistor is VDR2, and the second reference voltage is Vref2.
Vref2 = (VDR2−Vth2) / 2 + Vth2 In any of claims 5 to 8,
The detection circuit includes:
A first determination circuit that determines whether or not a difference between a voltage at a source node of the first transistor and a voltage at a node at the other end of the first switch element is greater than a first predetermined value;
A second determination circuit that determines whether or not a difference between a voltage at a node at the other end of the second switch element and a voltage at a source node of the second transistor is greater than a second predetermined value;
A detection signal output circuit that activates a current detection signal when at least one of the output of the first determination circuit and the output of the second determination circuit becomes active;
A circuit device comprising: In any one of Claims 1 thru | or 9,
The bridge circuit is
An H-bridge circuit having a third transistor on the high side and a fourth transistor on the low side;
The pre-driver is
A third driver circuit for driving the third transistor; and a fourth driver circuit for driving the fourth transistor;
The control circuit includes:
Outputting an on / off control signal of the bridge circuit to the third driver circuit and the fourth driver circuit;
The switch circuit is
A third switch element having one end connected to a second node between the third transistor and the fourth transistor; and a fourth switch element having one end connected to the second node. Have
The switching control circuit includes:
A third switch control signal for controlling on / off of the third switch element; and a fourth switch control signal for controlling on / off of the fourth switch element; and Activating the third switch control signal when it is determined that the on-resistance of a transistor is less than a given third on-resistance, and the on-resistance of the fourth transistor is less than a given fourth on-resistance If it is determined that the fourth switch control signal is activated,
The detection circuit includes:
A circuit device that detects a current of the bridge circuit based on a voltage at a node at the other end of the third switch element and a voltage at a node at the other end of the fourth switch element. A bridge circuit having a first transistor on the high side and a second transistor on the low side;
A pre-driver having a first driver circuit for driving the first transistor and a second driver circuit for driving the second transistor;
A switch circuit having a switch element having one end connected to a first node between the first transistor and the second transistor;
A switching control circuit for outputting a switch control signal for controlling on / off of the switch element based on the output of the second driver circuit;
A detection circuit that detects a current of the bridge circuit based on a voltage of a node at the other end of the switch element;
Control for outputting an on / off control signal of the bridge circuit to the first driver circuit and the second driver circuit, and stopping an on / off operation of the bridge circuit when a current is detected by the detection circuit. Circuit,
Including
The switching control circuit includes:
The circuit device, wherein the switch control signal is activated when it is determined that the on-resistance of the second transistor is smaller than a given on-resistance.   An electronic apparatus comprising the circuit device according to claim 1.

Images