JP6340800B2 - EUV exposure mask and manufacturing method thereof - Google Patents

Description

  The present invention relates to an EUV exposure mask used in a semiconductor manufacturing apparatus using EUV lithography using extreme ultraviolet (EUV) as a light source and a manufacturing method thereof.

  In recent years, with the miniaturization and high performance of semiconductor devices, there has been an increasing demand for miniaturization of photolithography technology. EUV lithography using an EUV near 13.5 nm, which is shorter in wavelength than the conventional ArF excimer laser beam having a wavelength of 193 nm, as a light source has been proposed. Since EUV lithography has a short light source wavelength and very high light absorption, it needs to be performed in a vacuum.

In the EUV wavelength region, the refractive index of most substances is slightly smaller than 1. For this reason, the EUV lithography cannot use a transmission type refractive optical system which has been used conventionally, and becomes a reflection optical system. Therefore, the photomask used as the original plate must be a reflective mask because a conventional transmission mask cannot be used. (Hereinafter, in this specification, a reflective mask used in EUV lithography is referred to as an EUV exposure mask, EUV mask, or simply mask.)
As shown in FIG. 3, the mask blank that is the basis of such an EUV exposure mask is formed on a low thermal expansion substrate 7 with a multilayer reflective layer 2 (Mo and Si approximately having a high reflectance with respect to the exposure light source wavelength). 40 cycles or more = 80 or more layers in total with a period of 7 nm), a protective layer 3 of a multilayer reflective layer (Ru or the like is about 2.5 nm), and an exposure light absorption layer 4 are sequentially formed. Further, a back surface conductive layer 5 is formed on the back surface of the substrate 7 to be fixed to an electrostatic chuck in the exposure machine.

  There is also an EUV mask having a structure having a buffer layer between the protective layer 3 of the multilayer reflective layer 2 and the absorption layer 4. When processing from a mask blank to a mask for EUV, the absorption layer 4 is partially removed by EB (electron beam) lithography and etching technology, and in the case of a structure having a buffer layer, this is also removed. Then, a circuit pattern 10 composed of the reflection part is formed. The light image reflected by the reflection type EUV exposure mask produced in this way is projected onto the semiconductor substrate via the reflection optical system.

  Since EUV light cannot use a refractive optical system that utilizes the transmission of light as described above, the optical system of the exposure machine is also of a reflective type. For this reason, it is impossible to perform deflection separation using a transmissive beam splitter. Therefore, the reflective mask has a drawback that the incident light to the mask and the reflected light cannot be designed on the same axis. For this reason, in an exposure method using a reflective optical system, irradiation is performed at an incident angle (usually 6 degrees) tilted by a predetermined angle from the vertical direction with respect to the mask surface. Since the reflection intensity at the shadowed portion is smaller than that at the non-shadowed portion, the contrast is lowered, and the transferred pattern is blurred in the edge portion and deviated from the design size. End up. This is called shadowing (projection effect) and is one of the fundamental problems of the reflective mask.

In order to prevent such blurring of the pattern edge portion and deviation from the design dimension, it is effective to reduce the height of the pattern by reducing the film thickness of the absorption layer 4. When becomes smaller, the light shielding property in the absorbing layer 4 is lowered, and the transfer contrast is lowered, thereby lowering the accuracy of the transfer pattern. That is, if the absorption layer is too thin, the contrast necessary for maintaining the accuracy of the transfer pattern cannot be obtained. That is, since the thickness of the absorption layer 4 is too thick or too thin, it is currently in the range of about 50 to 90 nm, and the reflectance of the EUV light at the absorption layer is 0.5 to 2. %.

  On the other hand, when a circuit pattern is baked on a semiconductor wafer using an EUV mask, chips having a plurality of circuit patterns are formed on one wafer, but an area where chip peripheral portions overlap between adjacent chips May exist. This is because the chips are arranged at a high density in order to increase the number of chips that can be taken per wafer as much as possible.

  In this case, this region is exposed multiple times (multiple exposure). The outer peripheral portion of the chip subjected to multiple exposure is also the outer peripheral portion on the mask, and is usually a portion of the absorption layer. However, as described above, since the reflectance of EUV light on the absorption layer 4 is about 0.5 to 2%, there is a problem that the outer peripheral portion of the chip is exposed by multiple exposure. For this reason, it has become necessary to provide a region (hereinafter referred to as a light-shielding frame) having a higher light-shielding property of EUV light than a normal absorption layer on the outer periphery of the chip on the mask.

  Therefore, as shown in FIG. 3, by forming a groove 11 (hereinafter referred to as a light shielding frame) dug from the absorption layer 4 to the multilayer reflective layer 2 of the EUV mask, the reflectance of the multilayer reflective layer 2 is lowered. A reflection type mask having a different structure has been proposed (see, for example, Patent Document 1).

  However, in the light shielding frame 11 of the type in which the absorption layer 4 and the multilayer reflective layer 2 are simply dug, the circuit pattern portion 10 on the inner side of the light shielding frame 11 and the outer side of the light shielding frame are electrically floating and can be electrically connected. Not. When this mask is used in an EUV exposure machine, photoelectrons are emitted from materials such as metals (mainly Ta, Mo, Si, etc.) used for the EUV mask due to the photoelectric effect of EUV light (extreme ultraviolet light), and electrically Charges positively (charges up). This causes a problem that foreign matter in the exposure machine is attached and transfer defects are induced. Further, even in a length measurement SEM or electron beam inspection machine using an electron beam in the mask manufacturing process, negative charging occurs when the electron beam is irradiated, and there is a problem that the electron beam inspection cannot be performed.

  In Patent Document 1, as a countermeasure against such charging at the time of exposure, a structure in which several layers (including at least Mo having conductivity) of the lowermost layer of the multilayer reflective layer 2 are left, or Ta or the base layer of the multilayer reflective layer 2 is used. A structure in which one conductive layer containing Cr is provided in advance has been proposed.

  However, in the method of leaving several layers of the multilayer reflective layer, the etching rate when the multilayer reflective layer is dug by dry etching or wet etching is not uniform in the mask plane, and thus the number of layers to be left cannot be made uniform. Originally, in a region having a light shielding frame for reducing the EUV reflectivity to zero as much as possible, a multilayer reflective layer is left excessively, and there is a problem that the EUV reflectivity is increased. For example, the reflectance when two periods of Mo / Si remain is about 1.8% in calculation, far exceeding the EUV reflectance standard of 0.3% or less of the EUV mask shading frame. End up. In addition, the structure in which the conductive layer is previously provided on the base of the multilayer reflective layer increases the number of processes when the mask blank is manufactured, and thus has a problem that the possibility of occurrence of a defect that is difficult to correct due to foreign matter or the like increases. Yes.

  The EUV mask blank reflectivity (hereinafter referred to as EUV reflectivity) of the EUV mask blank directly affects the throughput (production capacity) of the semiconductor chip manufacturing, and is desired to be as high as possible, but is currently known. As the material and the combination thereof, the above-described multilayer reflection layer of Si and Mo is the best. In order to increase the essential ability to generate reflectivity, it is important that the interface between Si and Mo be formed exactly. For this reason, a method is employed in which Si and Mo are alternately formed (mainly sputtering) without breaking the vacuum in the same vacuum chamber.

  In general vacuum film formation (sputtering method), since the material after film formation has a strong internal stress, the stress of the material is adjusted and stabilized by heat treatment (annealing) of the substrate. It is common. In a mask blank for EUV exposure, heat treatment after film formation causes mixing (diffusion) of materials of Si and Mo, and the interface between Si and Mo becomes dull, leading to a decrease in EUV light reflectance. Active heat treatment is not possible.

  Thus, although EUV exposure mask blanks and EUV masks are vulnerable to heat, EUV light has energy compared to conventional exposure wavelengths (ArF excimer laser, KrF excimer laser, i-line, g-line, etc.). In addition, the EUV light also has a high absorption of energy into the mask material, so that the temperature of the EUV mask rises significantly during exposure. As a result, there arises a problem that the EUV reflectance is lowered while the exposure is repeated.

  In addition, an increase in the temperature of the mask during exposure also causes thermal expansion of the mask, thereby reducing the positional accuracy of the mask pattern, and as a result, reducing the overlay accuracy (referred to as overlay accuracy) of the wafer pattern. Therefore, a low thermal expansion substrate is used in a known EUV exposure mask blank so that the mask position accuracy does not deteriorate even if there is a slight temperature change, but the mask blank is a multilayer made of Si and Mo on the surface side of the substrate. Since there is a reflective layer and an absorption layer made of Ta material, even if only the substrate has low thermal expansion, thermal expansion of those materials other than the substrate is inevitable, and the mask is still deformed. There arises a problem that the wafer overlay accuracy is lowered.

  In order to solve such a problem, the mask chuck of the EUV exposure apparatus uses a radiation cooling method, a method using a Peltier element (Patent Document 2), or a method using a refrigerant in order to keep the mask temperature constant. (Patent Document 3) has been proposed. In the current EUV exposure machine, the mask chuck is of an electrostatic chuck type, and a cooling coolant is allowed to flow in the mask chuck to keep the mask chuck temperature constant, thereby keeping the mask temperature constant. Has been taken.

  However, in the mask cooling method of the current exposure apparatus, in order to cool only the back surface of the EUV mask, in the conventional mask structure, the substrate itself has a thickness of 6.35 mm. The mask surface (pattern surface) directly irradiated with EUV light is not sufficiently cooled, resulting in a problem that the temperature becomes high. As a result, mixing of the multilayer reflective layer on the mask surface side occurs, resulting in a decrease in reflectivity, a decrease in mask pattern position accuracy due to thermal expansion of the material on the mask surface, and a further decrease in overlay accuracy. There is.

JP 2009-212220 A JP 09-92613 A Japanese Patent Laid-Open No. 09-306834

  The present invention has been made in order to solve the above-described problems. The object of the present invention is to prevent the projection effect from occurring, to eliminate the need to form a light shielding band, and to increase the mask temperature during exposure with EUV light. An object of the present invention is to provide an EUV exposure mask having a structure that does not.

The invention according to claim 1 for achieving the above object includes an absorbent layer on one main surface of the board, a multilayer reflective layer reaches to a predetermined depth in the substrate through said absorber layer circuit is obtained by the EUV exposure mask, characterized in that a pattern.

The invention of claim 2 is obtained by said absorbing layer and the multilayer reflective layer and the EUV exposure mask according to claim 1, characterized in that a protective layer covering the.

According to a third aspect of the present invention, the circuit pattern has a line width of 100 nm or less, a depth of 280 nm or more, and an Mo / Si layer in the inside at a period of 7 nm and 40 cycles or more. The EUV exposure mask according to claim 1 or claim 2 .

Further, an invention according to claim 4, wherein the substrate is a carbon-based material, solid metallic materials, solid metal material alloy claims 1 to 3, characterized in that either a conductive solid material The EUV exposure mask according to any one of the above.

In the invention according to claim 5 , the substrate is made of at least one of C, Ag, Cu, Au, Al, Si, Ni, Fe, Pt, W, Cr, Ti, Ru, Ta, and Mo. 5. The EUV exposure mask according to claim 4 , wherein the mask is included.

The invention of claim 6 is the thermal conductivity of the substrate, 50 W / EUV as claimed in any one of claims 5, characterized in that (m · K) or more at a This is an exposure mask.

The invention according to claim 7
An EUV exposure mask manufacturing method comprising a circuit pattern comprising a multilayer reflective layer that reflects EUV light on one main surface of a substrate,
(1) to one said board absorption layer is provided on a main surface of a step of forming a for embedding the circuit pattern, the buried trench reaches to a predetermined depth of the substrate through said absorbing layer,
(2) forming a multilayer reflective layer in the buried groove;
This is a method for manufacturing an EUV exposure mask characterized by comprising:

EUV exposure mask according to the present invention, the multilayer reflective film is formed by cutting into the substrate portion of the circuit pattern portion, the thickness of only the absorption layer's amount that bite is thinner than the conventional type mask. For this reason, the projection effect is suppressed, and the displacement and distortion of the wiring pattern are reduced. In addition, since the multilayer reflective film does not exist on the outer peripheral portion other than the circuit pattern, the reflectance is lowered and the influence of multiple exposure is reduced.

  Further, since the reflectance of the outer periphery is appropriately controlled, it is not necessary to form a light shielding frame. As a result, mask processing is simplified, and at the same time, the circuit pattern is not electrically floated by the light shielding frame. If charging is prevented, there will be no adverse effects due to charging at the time of measurement of the line width, etc. by the length measuring SEM using an electron beam, at the time of circuit pattern inspection by an electron beam inspection machine, and at the time of EUV exposure by EUV lithography, High quality masks can be stably manufactured in various aspects.

  Furthermore, the mask according to the present invention has a high thermal conductivity and a small thickness. Therefore, since it becomes possible to cool the mask surface efficiently during EUV exposure, it is possible to suppress EUV reflectivity reduction and mask deformation caused by heat generation during exposure, and maintain the quality of the EUV mask. The effect is that a high-quality semiconductor device can be manufactured.

It is a cross-sectional view of the EUV exposure mask blank that is used to produce the EUV exposure mask of the present invention. It is the top view and sectional drawing explaining an example of the mask structure for EUV exposure which becomes this invention. It is sectional drawing of EUV mask provided with the conventional type light-shielding zone. It is a process flowchart explaining the manufacturing method of the EUV mask which becomes this invention. It is sectional process drawing explaining the manufacturing method of the EUV mask which becomes this invention. It is a SEM image comparison figure of a line pattern. (A) Conventional EUV mask, (b) EUV mask according to the present invention. It is a schematic sectional drawing which shows the mode of the heating experiment of a mask surface. It is a figure which shows the elapsed time change of the mask surface temperature in the heating experiment of a mask surface.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Although described as a layer in the present invention, the layer may be a film.

An embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view of an EUV exposure mask blank used for manufacturing the EUV exposure mask of the present invention, and FIG. 2A is a schematic plan view of the EUV exposure mask of the present invention. 2 (b) is a schematic sectional view.

  As shown in FIGS. 2A and 2B, the circuit pattern 10 has a structure in which the multilayer reflective layer 2 is embedded in the substrate 1 in a pattern, and the surface opposite to the surface having the circuit pattern 10 is the back surface. A conductive layer 5 is provided. Therefore, the multiple reflection layer 2 has a structure that exists only in a portion corresponding to the circuit pattern 10. Further, depending on the material of the substrate 1, since the entire substrate has conductivity, the back surface conductive layer may not be provided as shown in FIG. Further, in order to improve the selectivity at the time of etching, as shown in FIG. 2D, a structure in which the absorption layer 4 is a laminated structure and the upper layer is a sacrificial layer 14 may be used. FIG. 3 shows a comparison of the structure of a conventional EUV mask having a known light-shielding band.

Next, the manufacturing method of this mask is shown in FIGS. Here, FIG. 4 shows a process flowchart, and FIG. 5 shows a processing state in each process in a sectional view.
First, a mask blank for EUV exposure is prepared. In order to obtain the etching selectivity, a mask blank 30 was prepared in which the upper layer of the absorption layer 4 was the sacrificial layer 14. In the embodiment, the wavelength of EUV light is configured based on, for example, 13.5 nm. As a material for the substrate 1 of the mask blank 30, an aluminum alloy having a purity of 99.7%, which is a conductive material, was used. Moreover, the aluminum alloy was processed into 6 inches (152.4 mm) × 6 inches (152.4 mm) and a thickness of 0.25 inches (6.35 mm) by machining.

Tantalum silicide is formed as the absorption layer 4 to a thickness of 70 nm on the main surface of the EUV mask 101 where the circuit pattern 10 is to be formed by sputtering, and the sacrificial layer 14 is formed thereon. For the sacrificial layer 14, it is necessary to select a material that can sufficiently ensure an etching selection ratio with the substrate 1. Here, molybdenum nitride silicide (MoSiN) is formed as the sacrificial layer 14 with a thickness of 5 to 100 nm by a sputtering apparatus. Further, chromium nitride (CrN) is formed as a back conductive layer 5 on the surface opposite to the surface on which the circuit pattern is formed by magnetron sputtering so as to be laminated (S0).

  The absorption layer 4 of the mask blank 30 is made of a nitrogen compound (TaN) of tantalum (Ta) having a high absorption rate with respect to EUV light. As other materials, tantalum boron nitride (TaBN), tantalum silicon (TaSi), tantalum (Ta), and oxides thereof (TaBON, TaSiO, TaO) may be used.

  The sacrificial layer 14 of the mask blank 30 is made of a material that can obtain a large selection ratio with the substrate 1. In dry etching, there are metals that do not undergo an etching reaction depending on the selection of a gas type such as a fluorine-based gas or a chlorine-based gas. Therefore, the sacrificial layer is first etched and a circuit pattern is formed on the sacrificial layer. Then, the substrate is etched using the sacrificial layer as a mask, and the substrate is etched deeply by 280 nm or more. Examples of the material for the sacrificial layer include materials containing C, Ag, Cu, Au, Al, Si, Ni, Fe, Pt, W, Cr, Ti, Ru, Ta, and Mo, oxides, and nitrides thereof. is there.

  In this embodiment, an aluminum alloy is used for the substrate 1. However, since the aluminum alloy is etched with a chlorine-based gas, the sacrificial layer 14 does not react with the chlorine-based metal and can be etched with a fluorine-based metal or metal. It is preferable to consist of a compound, for example, a silicon containing material is mentioned. Further, as a metal containing silicon and a metal other than silicon, an alloy of a transition metal and silicon is considered, and as the transition metal, titanium, vanadium, cobalt, nickel, zirconium, niobium, molybdenum, hafnium, tantalum. One or more selected from tungsten and tungsten are suitable materials, and molybdenum is particularly preferred from the viewpoint of dry etching processability.

  Next, a guide 15 of a multilayer reflective layer embedding groove for embedding the multilayer reflective layer 2 to be the circuit pattern 10 is formed in the sacrificial layer 14. That is, a circuit pattern is formed using a chemical amplification system or non-chemical amplification system resist that reacts with an electron beam. In this embodiment, a positive chemically amplified resist 9 (FEP171: FUJIFILM Electronics Materials) is applied to the sacrificial layer 14 with a film thickness of 300 nm (S1), and a predetermined circuit pattern is applied to an electron beam drawing apparatus (JBX9000: JEOL). ), And after performing PEB at 110 ° C. for 10 minutes, spray development (SFG3000: Sigma Meltech) is performed with an alkaline solution or the like (S2).

  The sacrificial layer 14 is etched by gas plasma using fluorine-based gas or chlorine-based gas using a dry etching apparatus with the pattern of the resist 9 thus formed as a mask (S3). Here, since the sacrificial layer 14 is made of molybdenum nitride silicide (MoSiN), etching is performed using fluorine-based plasma. For the evaluation pattern used instead of the circuit pattern, a chip of a 1: 1 line & space pattern with a dimension of 200 nm was arranged in the center of the mask with 6 faces. The size of the pattern region was 10 cm × 10 cm over the entire surface of the chip 6. At this time, the interval between the scribe lines between the chips was 5 mm.

  Using the resist 9 and the sacrificial layer 14 as a mask, the absorption layer 4 and the substrate 1 are etched by chlorine-based plasma, and the circuit pattern is further etched deeply to form a multilayer reflective layer buried groove (S4). Here, the depth of the multi-layer reflective layer embedding groove is 100 nm or less and the height from the absorption layer 4 to the bottom surface of the etched substrate 1 is 280 nm or more.

  Next, the multilayer reflective layer 2 for EUV exposure is produced. Molybdenum (Mo) of 4.2 nm and silicon (Si) of 2.8 nm are alternately formed by an ion beam sputtering apparatus for 40 cycles or more, and a total of 80 layers or more are formed so that the uppermost layer is silicon (Si) ( S5). In this example, the multilayer reflective layer 2 was formed with a film thickness of 300 nm.

  Next, the multilayer reflective layer 2 ′ laminated on the sacrificial layer 14 and the sacrificial layer 14 are peeled by surface polishing using a CMP (Chemical Mechanical Polishing) apparatus (S <b> 6). At this time, the sacrificial layer 14 may remain if the circuit pattern is exposed on the surface with a desired size. After that, if necessary, cleaning with ultrapure water, organic alkaline chemicals, surfactants, etc. in which acid / alkali chemicals, ozone gas, hydrogen gas, etc. are dissolved, and spin drying using centrifugal force are performed.

Finally, Ru is deposited as a protective layer 3 on the upper layer by 2 to 3 nm. The protective layer 3 needs to be made of a material having resistance to washing against acids and alkalis, and generally Ru (ruthenium) or Si (silicon) is used. The protective layer 3 is resistant to acids and alkalis, and other materials may be used as long as the protective layer 3 is not highly absorbing to EUV light.
When the sacrificial layer 14 is completely removed by the above steps, the EUV exposure mask 101 with a new structure (FIG. 2B) is used. When the sacrificial layer is left, the EUV exposure mask 102 with a new structure (FIG. 2D) is used. )) Is completed.

Since the substrate of the EUV exposure mask blank used for manufacturing the EUV exposure mask of the present invention needs to be a material for efficiently releasing the heat generated in the mask during exposure with the EUV exposure machine, A metal material, a carbon material, or a compound thereof having high thermal conductivity is desirable.

  In order to satisfy the purpose, the thermal conductivity of the substrate needs to be 50 W / (m · K) or more. Incidentally, since the thermal conductivity of a low thermal expansion substrate used for a general EUV mask blank is about 1 to 1.5 W / (m · K), the substrate used in the present invention is at least 30 times or more. Has thermal conductivity.

  Materials include C, Ag, Cu, Au, Al, Si, Ni, Fe, Pt, W, Cr, Ti, Ru, Ta, and Mo. For example, the material containing C has several structures, and typical examples include diamond and graphite. Thermal conductivity is the highest for diamond, 1000 W / (m · K) or more, and about 500 W / (m · K) for graphite. Among metal materials, Ag (420), Cu (398), Au (320), Al (236), and the like have high thermal conductivity.

  In this mask structure, the outermost surface is in the state of the protective layer 3, and in a region other than the circuit pattern 10 in which the multilayer reflective layer 2 is embedded, the multilayer reflective layer is provided below the absorption layer (including the sacrificial layer). Since it is not formed, the reflectance with respect to EUV light is low, and a high contrast can be obtained between the circuit pattern and the rest.

  Since the EUV mask produced by the present invention does not have a thick absorption film like the conventional EUV mask, the projection effect due to the absorption layer does not occur, so that problems such as misalignment and distortion of the exposure pattern due to exposure are reduced. It became possible.

  The circuit pattern outer periphery of both the new structure reflective mask 101 of the present invention (FIG. 2B) using the substrate 1 produced in this example and the EUV mask 301 (FIG. 3) having a conventional light shielding band. The dimension of the part was measured with a length measuring SEM. As a result, in the existing EUV mask, the drift of the SEM image due to charge-up is large, and in the setting for pattern dimension measurement in which images are taken in order up and down, the pattern becomes diagonal as shown in FIG. Could not be measured accurately. On the other hand, in the EUV mask 101 (FIG. 2B) using the substrate 1 of the present embodiment, even if the same region is measured, the influence of drift is not seen as shown in FIG. I was able to measure.

  In order to evaluate the heat dissipation of the surface of the mask of the present invention, a situation similar to that inside the exposure apparatus was simulated and an experiment was conducted. As shown in FIG. 7, the EUV mask 101 of the present invention is placed so that the back surface of the mask is in contact with a cool plate 20 maintained at 23 degrees Celsius, and heated by an infrared heater 21 disposed at a distance of about 30 cm from the mask surface. The temperature of the mask surface at that time was measured with the infrared radiation thermometer 22.

  FIG. 8 shows the measurement results of the mask surface temperature with respect to the elapsed time using the EUV mask having the conventional structure and the EUV mask having the structure of the present invention. With an EUV mask with a conventional structure, the surface temperature increases with the lapse of time, reaches 50 degrees after about 10 minutes, exceeds 140 degrees after about 70 minutes, and the temperature continues to rise. I understood. On the other hand, in the EUV mask of the present invention, almost no temperature increase was observed with respect to the elapsed time, and the surface temperature at the start of the experiment was kept constant.

  The present invention is not limited to the above-described embodiment as it is, and can be modified and embodied without departing from the gist of the present invention. Various inventions can be envisaged by appropriately combining the matters shown in the specification.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Multilayer reflective layer 3 Protective layer 4 Absorbing layer 5 Back surface conductive layer 7 Low thermal expansion substrate 9 Resist 10 Circuit pattern 11 Shading band 14 Sacrificial layer 15 Guide 20 Cool plate 30 Mask blank 21 Infrared heater 22 Radiation thermometer 101 New structure EUV exposure mask 102 EUV exposure mask 301 with a sacrificial layer Existing reflective frame for EUV exposure with light shielding frame

Claims (7)

Comprises an absorbent layer on one main surface of the board, mask for EUV exposure, characterized in that a circuit pattern made of a multilayer reflective layer reaches to a predetermined depth in the substrate through said absorber layer. The absorbent layer and the multilayer reflective layer and the EUV exposure mask according to claim 1, characterized in that a protective layer covering the. 3. The EUV exposure according to claim 1, wherein the circuit pattern has a line width of 100 nm or less, a depth of 280 nm or more, and an Mo / Si layer provided therein at a cycle of 7 nm and 40 cycles or more. mask. The substrate is a carbon-based material, a solid metal material, for EUV exposure according solid metal material alloy claim 1, characterized in that either a conductive solid material in any one of claims 3 mask. The substrate, at least, wherein C, Ag, Cu, Au, Al, Si, Ni, Fe, Pt, W, Cr, Ti, Ru, Ta, in claim 4, characterized in that it comprises one of Mo EUV exposure mask. The thermal conductivity of the substrate, 50 W / EUV exposure mask according to any one of claims 1 to 5, characterized in that it is (m · K). An EUV exposure mask manufacturing method comprising a circuit pattern comprising a multilayer reflective layer that reflects EUV light on one main surface of a substrate,
(1) to one said board absorption layer is provided on a main surface of a step of forming a for embedding the circuit pattern, the buried trench reaches to a predetermined depth of the substrate through said absorbing layer,
(2) forming a multilayer reflective layer in the buried groove;
A process for producing an EUV exposure mask, comprising: