JP6341066B2 - Timer control program, timer control method, and information processing apparatus - Google Patents

Description

  The present invention relates to a timer control program, a timer control method, and an information processing apparatus.

  As a method of controlling a large number of timers, the current slot updated for each time slice is held, a timer request is registered in the timer slot advanced by the designated number of slots + 1 from the current slot, and processed after the designated timer time elapses There is a way to do it. Here, the time slice is a predetermined unit time, and the number of designated slots is an integer obtained by rounding up the time before timeout / the decimal point of the time slice. In addition, the timer slots are arranged at time slice intervals and are places where timer requests are registered.

  FIG. 26 is a diagram for explaining conventional timer control. As shown in FIG. 26, a plurality of timer slots are arranged at intervals of time slices on the timer track, and the timer track pointed to by the current slot shifts to the right for each time slice. A timer request is registered in the timer slot, and when the current slot transitions to the timer slot in which the timer request is registered, the registered timer request is timed out. Here, the timeout process is a process performed when the timer time specified by the timer request has elapsed.

  For example, assume that the time slice is 100 msec (milliseconds) and the current slot is 1. At this time, if there is a 200 msec timer request, the number of designated slots is 2, rounded up to the nearest 200/100, and the timer request is registered in the 4 timer slots which are advanced by 2 + 1 = 3. When the current slot becomes 4, the timer request registered in the 4 timer slot is taken out, and a time-out process is performed.

  When the timer request registered in the timer slot is completed, the task that performs timer processing pauses for the time slice, and when the time slice time elapses, the task that wakes up and registers the timer request registered in the next timer slot. Process.

  In addition, as a conventional technique for controlling a plurality of timers, the number of timers obtained by dividing the monitoring time by the allowable error of the timer is provided, and the timers are sequentially started while being shifted by the allowable error time. There is a technique for processing all timer activation requests that occur during the timing.

JP-A-7-200361

  However, the timer control shown in FIG. 26 has a problem that an error occurs by the amount of time slice. FIG. 27 is a diagram for explaining the problem of the timer control shown in FIG. Since the current slot is updated after the time slice elapses, a timer error of the amount of time slice occurs at the maximum when the timer is registered immediately after the time slice pause and when the timer is registered immediately before the time slice wakes up. Here, the time slice suspension means that the timer control is suspended for the time slice.

  FIG. 27A shows a case where the timer is registered immediately after the time slice pause, and FIG. 27B shows a case where the timer is registered immediately before the time slice wakes up. As shown in FIG. 27A, when a timer whose designated timer value is 200 msec is registered after 10 msec from the start of the time slice pause, for example, immediately after the time slice pause, the registered timer is processed after 290 msec. Here, the designated timer value is the time designated by the timer request, and the timer value is the time until timeout.

  On the other hand, as shown in FIG. 27B, when a timer with a specified timer value of 200 msec is registered after 90 msec from the start of the time slice pause, for example, as soon as the time slice wakes up, the registered timer is processed after 210 msec. The That is, the maximum time slice error occurs due to the elapsed time slice at the time of timer registration. Here, the time slice elapsed time is the elapsed time from the start of the time slice pause to the timer registration. Note that if the time slice is shortened in order to improve timer accuracy, the load of timer control increases.

  In one aspect, an object of the present invention is to reduce a timer error caused by a time slice elapsed time at the time of timer registration.

  The timer control program disclosed in the present application is a timer control program that controls a timer using a plurality of timer slots in one aspect. The timer control program divides the time slots into N (N is an integer of 2 or more). The timer control program causes the computer to execute a process of determining, from the current slot, the timer value, and the time slice elapsed time, a timer slot in which a timer timeout process is woken up from a timer slot having a time interval smaller than the time slice. Then, the timer control program causes the computer to execute processing for registering the timer request in the determined timer slot. In addition, the timer control program executes processing for determining whether or not there is a timer slot to which a timer request is registered between the current slot and a timer slot after the current slice by the time slice. Let If the timer slot exists, the timer control program performs a process of transitioning the current slot to a position advanced by P time slices (P is an integer not less than 1 and not more than N-1) according to the position of the registered timer slot. Let the computer run.

  According to one embodiment, it is possible to reduce a timer error due to the time slice elapsed time at the time of timer registration.

FIG. 1 is a diagram for explaining the information communication system according to the embodiment. FIG. 2 is a diagram for explaining a method of realizing a virtual band. FIG. 3 is a diagram illustrating a configuration of software executed by the communication control apparatus according to the embodiment. FIG. 4 is a diagram for explaining timer registration. FIG. 5 is a diagram for explaining timer processing. FIG. 6 is a diagram for explaining the difference between the timer control method in which the time slice is 50 msec and the timer control method according to the embodiment. FIG. 7 is a diagram for explaining a method of specifying the time slice elapsed time. FIG. 8 is a diagram for explaining the registration position of the timer request when the timer slot is divided into four. FIG. 9 is a diagram for explaining timer processing when the timer slots are divided into four. FIG. 10 is a diagram for explaining the difference between the timer control method for setting the time slice to 25 msec and the timer control method according to the embodiment. FIG. 11 is a diagram for explaining the delay of the timer process. FIG. 12 is a diagram for explaining a problem due to a delay in timer processing. FIG. 13 is a diagram illustrating the execution priority based on the number of tasks waiting to be executed. FIG. 14 is a diagram illustrating execution priorities based on timer errors. FIG. 15 is a diagram illustrating advantages and disadvantages of each factor of changing execution priority. FIG. 16 is a flowchart showing a flow of processing for starting and using a timer for each connection. FIG. 17 is a flowchart showing a flow of processing for starting and using a timer for each message. FIG. 18 is a flowchart showing the flow of the timer registration process. FIG. 19 is a flowchart showing the flow of the timer registration process when the timer slots are divided into N parts. FIG. 20 is a flowchart showing the flow of timer processing. FIG. 21 is a flowchart showing the flow of the inter-slot timer process. FIG. 22 is a diagram illustrating an example of a timer management table. FIG. 23 is a diagram illustrating an example of timer registration processing using the timer management table illustrated in FIG. 24 is a diagram showing an example of timer processing using the timer management table shown in FIG. FIG. 25 is a diagram illustrating a hardware configuration of the communication control device. FIG. 26 is a diagram for explaining conventional timer control. FIG. 27 is a diagram for explaining the problem of the timer control shown in FIG.

  Embodiments of a timer control program, a timer control method, and an information processing apparatus disclosed in the present application will be described below in detail with reference to the drawings. Note that this embodiment does not limit the disclosed technology. In the embodiment, a case where the time slice is mainly 100 msec and the designated timer value designated by the timer request is 200 msec will be described as an example.

  First, an information communication system according to an embodiment will be described. FIG. 1 is a diagram for explaining the information communication system according to the embodiment. As shown in FIG. 1, the information communication system 1 includes an information processing system 2 and a communication control device 3 and communicates with another information communication system 4.

  For example, the information communication system 1 is a basic system of a financial institution, and the other information communication system 4 is a system of another financial institution, a terminal device, an ATM (Automated Teller Machine), or the like. The information processing system 2 and the communication control device 3 are connected by, for example, a LAN (Local Area Network), and the information communication system 1 and the other information communication system 4 are, for example, a WAN (Wide Area Network). Connected with.

  When the information communication system 1 communicates with another information communication system 4, the information communication system 1 may limit the band so that one communication does not occupy the band. In this case, the information communication system 1 maintains the quality of each communication by providing a virtual band for each connection. FIG. 1 shows a case where the virtual bandwidth is large, medium, and small.

  FIG. 2 is a diagram for explaining a method of realizing a virtual band. As shown in FIG. 2, the communication control device 3 does not immediately respond to the transmission message with a response message to the transmission message, but uses a timer for each connection to hold the response message within a specified time. Control the amount of messages per hit. In using such a timer, since a timer is used for each connection, timers on the order of thousands to tens of thousands are used.

  Next, a configuration of software executed by the communication control device 3 according to the embodiment will be described. FIG. 3 is a diagram illustrating a configuration of software executed by the communication control device 3 according to the embodiment. The communication control device 3 has a CPU and a memory, and executes the tasks shown in FIG. Here, a task is an execution unit executed by the CPU, and is, for example, a process.

  As shown in FIG. 3, the tasks executed by the communication control device 3 include a transmission control task 31, a telegram control task 32, a transmission control task 33, a timer registration task 51, and a timer processing task 52. It is. The timer control program 5 is a program that performs timer control, and is realized by a timer registration task 51, a timer processing task 52, and a timer management table 53.

  Information used for timer control is registered in the timer management table 53. Information used by the timer registration task 51 and the timer processing task 52 is registered in the timer management table 53. The timer management table 53 is stored in the memory. Details of the timer management table 53 will be described later.

  The transmission control task 31 controls communication with the information processing system 2 and establishes a connection. For example, the transmission control task 31 requests timer registration for each connection in order to monitor connection establishment.

  The message control task 32 relays messages transmitted and received between the information processing system 2 and the information communication system 4. For example, the message control task 32 requests timer registration for each message in order to monitor the response of the transmitted message.

  The transmission control task 33 controls communication with the information communication system 4 and establishes a connection. For example, the transmission control task 33 requests timer registration for each connection in order to monitor connection establishment.

  The timer registration task 51 is activated when timer registration is requested, and specifies a timer slot to wake up the timeout processing of the timer for which registration is requested based on the current slot, the designated timer value, and the time slice elapsed time. Then, the timer registration task 51 registers a timer in the specified timer slot.

  FIG. 4 is a diagram for explaining timer registration. As shown in FIG. 4A, the timer control program 5 divides the timer slot into N. Therefore, if the original number of timer slots is M, the number of timer slots is M × N. In FIG. 4A, N = 2, the original timer slot is indicated by a black circle, and the timer slot added by division is indicated by a patterned circle. The 0 timer slot and the M timer slot represent the same timer slot.

  When the timer registration task 51 is requested to register the timer, if the time slice elapsed time is smaller than 1/2 of the time slice, as shown in FIG. 4B, the current slot + the number of designated slots + 1/2 Register the timer in the timer slot. In FIG. 4B, since the current slot is 1 and the time slice elapsed time is less than 50 msec, a 200 msec timer is registered in the 3.5 timer slot.

  On the other hand, when the time slice elapsed time is ½ or more of the time slice, the timer registration task 51 registers the timer in the current slot + the number of designated slots + 1 timer slots as shown in FIG. In FIG. 4C, since the current slot is 1 and the time slice elapsed time is 50 msec or more, a 200 msec timer is registered in 4 timer slots.

  As a timer process, the timer process task 52 performs a timeout process by causing the current slot to transition with a variable pause time based on the time obtained by dividing the time slice into N parts. Specifically, the timer processing task 52 determines the difference between the current slot and the next integer timer slot when there is no timer registration between the current slot and the next integer timer slot. Let time be rest time. Then, the timer processing task 52 changes the current slot to the next integer timer slot after the pause time.

  FIG. 5 is a diagram for explaining timer processing. As shown in FIG. 5A, when the current slot is 1 and there is no timer request in the 1.5 timer slot, the timer processing task 52 pauses for 100 msec. Then, the timer processing task 52 shifts the current slot to a timer slot of 2 which is the next integer. That is, the timer processing task 52 advances N current slots at a time. When the current slot is 2 and there is no timer request in the 2.5 timer slot, the timer processing task 52 transitions the current slot to the next 3 timer slot which is the next integer after 100 msec pause.

  On the other hand, if there is a timer slot for which timer registration has been performed between the current slot and the next integer timer slot, the timer processing task 52 determines the difference between the current slot and the first timer slot for which timer registration has been performed. Is the rest time. Then, the timer processing task 52 changes the current slot to the first timer slot in which the timer registration is performed after the pause time. As shown in FIG. 5B, when the current slot is 3, and there is a timer request in the 3.5 timer slot, the timer processing task 52 pauses for 50 msec. Then, the timer processing task 52 transitions the current slot to the timer slot of 3.5 which is the first timer slot in which the timer registration is performed, and performs a timeout process. That is, the timer processing task 52 advances one current slot at a time.

  In this way, the timer processing task 52 changes the pause time based on whether or not there is a timer slot for which timer registration has been performed between the current slot and the next integer timer slot. Therefore, the timer processing task 52 can always prevent the timer processing task from operating N times as in the case where the time slice is set to 1 / N.

  FIG. 6 is a diagram for explaining the difference between the timer control method in which the time slice is 50 msec and the timer control method according to the embodiment. FIG. 6A shows a timer control method for setting a time slice to 50 msec, and FIG. 6B shows a timer control method according to the embodiment.

  As shown in FIG. 6A, in the timer control method in which the time slice is set to 50 msec, timer processing is performed every 50 msec. On the other hand, in the timer control method according to the embodiment, as shown in FIG. 6B, a timer request is registered in a timer slot newly added by dividing the timer slot into two, that is, a timer slot such as 0.5. The timer process is performed after 50 msec pause only when it is set. Therefore, the timer control method according to the embodiment can always prevent the timer processing task 52 from operating twice.

  FIG. 7 is a diagram for explaining a method of specifying the time slice elapsed time. The timer processing task 52 acquires and stores a pause start time X immediately before pause. The timer registration task 51 acquires a timer registration time Y at the time of timer registration. Then, the timer registration task 51 specifies the time slice elapsed time by calculating the difference Y−X between the timer registration time Y and the suspension start time X.

  Then, when the timer registration time Y−pause start time X <time slice / 2, the timer registration task 51 registers the timer in the current slot + the number of designated slots + 1/2 timer slots. The timer registration task 51 registers the timer in the current slot + the number of designated slots + 1 timer slots when the timer registration time Y−pause start time X ≧ time slice / 2.

  FIG. 8 is a diagram for explaining the registration position of the timer request when the timer slot is divided into four. As shown in FIG. 8A, when the timer slots are divided into four, 1.25, 1.5, 1.75, 2.25, 2.5, 2.75, 3.25, 3.5 A timer slot such as 3.75 is added.

  Then, as shown in FIG. 8B, when the time slice elapsed time at the time of timer registration is 0 to less than time slice × 1/4, the timer registration task 51 has a timer of current slot + number of designated slots + 1/4. Register the timer in the slot. Also, the timer registration task 51 registers the timer in the timer slot of the current slot + the number of designated slots + 2/4 when the elapsed time slice at the time of timer registration is time slice × 1/4 or more and less than time slice × 2/4. .

  The timer registration task 51 registers the timer in the timer slot of the current slot + the number of designated slots + 3/4 when the time slice elapsed time at the time of timer registration is equal to or greater than time slice × 2/4 and less than time slice × 3/4. . In addition, when the elapsed time slice at the time of timer registration is equal to or greater than time slice × 3/4 and less than the time slice, the timer registration task 51 registers the timer in the current slot + number of designated slots + 1 timer slots.

  When the value of the current slot is an integer, the timer processing task 52 pauses as follows. When a timer request exists in the timer slot of the current slot + 1/4, the timer processing task 52 pauses for time slice × 1/4, and when a timer request exists in the timer slot of the current slot + 2/4, Pause for slice x 2/4. In addition, when there is a timer request in the timer slot of the current slot +3/4, the timer processing task 52 pauses for time slice × 3/4, and enters the time slot of current slot + 1/4 to current slot + 3/4. If there is no timer request, pause for a time slice.

  FIG. 9 is a diagram for explaining timer processing when the timer slots are divided into four. Here, as shown in FIG. 9A, an example will be described in which the current slot is 1 and timer requests exist in the 3.25 and 3.75 timer slots.

  When there is no timer request between the current slot and the current slot + 1, the timer processing task 52 pauses for the time slice and then advances four current slots. For example, as shown in FIG. 9B, when the current slot is 1, there is no timer slot in which a timer request exists between the timer slots 1 and 2, so that the timer processing task 52 is suspended for 100 msec. After that, the current slot is advanced by four. Similarly, when the current slot is 2, there is no timer slot for which a timer request exists between the timer slots 2 and 3, so that the timer processing task 52 pauses for 100 msec and then advances the current slot by 4 times. .

  On the other hand, when a timer request exists between the current slot and the current slot + 1, the timer processing task 52 specifies the latest timer registration position between the timer slots. For example, as shown in FIG. 9C, the timer processing task 52 specifies 3.25 as the timer registration position. Then, the timer processing task 52 pauses for time slice × 1/4 = 25 msec and then changes only one current slot to process the timer request registered in the 3.25 timer slot.

  Next, since the timer request is registered at 3.75, the timer processing task 52 determines the difference between the timer registration position 3.75 and the current slot position 3.25 as shown in FIG. Is paused for 50 msec multiplied by a time slice. Then, the timer processing task 52 pauses for 50 msec, transitions two current slots, and processes the timer request registered in the 3.75 timer slot.

  Since there is no timer request between the 3.75 and 4 timer slots, the timer processing task 52 pauses for 25 msec as shown in FIG. Transition.

  As described above, the timer processing task 52 determines whether or not there is a timer slot in which a timer request is registered between the current slot and a timer slot that is a time slice after the current slot. Then, when there is a timer slot in which the timer request is registered, the timer processing task 52 changes the current slot to a position advanced by P time slices according to the position of the registered timer slot. Here, P is an integer of 1 to N-1. Therefore, the timer control program 5 can reduce the timer error due to the time slice elapsed time at the time of timer registration.

  FIG. 10 is a diagram for explaining the difference between the timer control method for setting the time slice to 25 msec and the timer control method according to the embodiment. FIG. 10A shows a timer control method for setting a time slice to 25 msec, and FIG. 10B shows a timer control method according to the embodiment.

  As shown in FIG. 10A, in the timer control method in which the time slice is set to 25 msec, timer processing is performed every 25 msec. On the other hand, in the timer control method according to the embodiment, timer processing is performed after a variable time suspension based on 25 msec only when a timer request is registered in a timer slot newly added by dividing the timer slot into four.

  For example, in FIG. 10B, when the current slot is 3 and 3.75, the timer process is performed after pausing for 25 msec, and when the current slot is 3.25, the timer process is performed after pausing for 50 msec. Done. Therefore, the timer control method according to the embodiment can always prevent the timer processing task 52 from operating four times.

  Next, the delay of the timer process will be described. In a device that requires timer accuracy, when the device is in a high load state, the processing of the timer processing task 52 is delayed. As a result, the delay time is added to the timer time, and the timer accuracy deteriorates.

  FIG. 11 is a diagram for explaining the delay of the timer process. As shown in FIG. 11 (a), when a timer request is registered in 4 timer slots in a situation where the current slot is 1, in a situation where the load on the apparatus is low, as shown in FIG. Is updated every 100 msec. Therefore, a time-out occurs within an error of 100 msec from the designated designated timer value.

  On the other hand, when the load on the device increases, a processing delay of the timer processing task occurs, so that the current slot is updated every 120 msec, for example, as shown in FIG. To do. The reason why the processing delay of the timer processing task occurs is that when a command is issued to pause for 100 msec for an OS (Operating System), the pause time is only guaranteed at least 100 msec. In FIG. 11, the number of divisions between timer slots is N = 1.

  FIG. 12 is a diagram for explaining a problem due to a delay in timer processing. As shown in FIG. 12, when a delay occurs in the timer process of the communication control device 3, the timing for returning a response message to the transmission source is extended, so that the next message transmission from the transmission source is also delayed. As a result, the amount of communication decreases, causing a problem that the bandwidth cannot be used to the maximum (the bandwidth is wasted).

  Therefore, the communication control device 3 dynamically changes the execution priority of the timer processing task 52, which has been fixed in the past, according to the device load or the actual timer error. The communication control device 3 does not cause a delay in the timer processing by assigning a high priority to the timer processing task 52 in a high load state or a state where the error is large. Further, in order not to unduly consume CPU resources, the communication control device 3 assigns a normal priority to the timer processing task 52 in a low load state or a state with a small error so that the execution priority of the timer processing task 52 is given. Avoid situations where the degree is always high.

  Specifically, the timer processing task 52 periodically acquires the status of the communication control device 3. The monitoring cycle can be determined by the user. Further, the user can select device load or timer accuracy as the status of the communication control device 3.

When the apparatus load is used as the execution priority change factor, the timer control program 5 dynamically changes the execution priority by any of the following methods. The timer control program 5 uses the number of tasks waiting for execution as the device load.
(1) While the device load exceeds the threshold, the execution priorities of the timer processing task 52 and the timeout processing task are periodically increased by a fixed value. Here, the timeout process task is a task that is woken up by the timer process task 52 and performs the timeout process.
(2) The execution priority of the timer processing task 52 and the timeout processing task is uniquely determined according to the device load.

  In the method (1), the timer control program 5 causes the user to set a threshold value for the number of tasks waiting to be executed. The timer processing task 52 periodically monitors the number of tasks waiting for execution of the communication control device 3. Then, the timer processing task 52 increases the execution priority of the timer processing task 52 and the timeout processing task while the number of tasks waiting for execution exceeds the threshold, thereby reducing the operation delay of the timer processing task 52 in a high load state. Suppress and improve timer accuracy. In addition, when the number of tasks waiting for execution falls below the threshold, the timer processing task 52 returns the timer processing task 52 and the timeout processing task to the normal priority level, thereby suppressing unjustified consumption of CPU resources.

  When the number of tasks waiting to be executed in the apparatus exceeds the number of CPU cores, there is a possibility that task execution delay occurs. For this reason, in the method (2), the processing task 52 uniquely determines the execution priority based on the number of tasks waiting for execution exceeding the number of CPU cores. When the number of tasks waiting for execution exceeds the number of CPU cores, the processing task 52 can specify the execution priority range up to a value obtained by multiplying the number of tasks waiting for execution by the number of CPU cores by one or more load factors (for example, 2). The execution priority setting stage is obtained by dividing by. Here, the execution priority setting stage is the number of execution tasks for increasing the execution priority by one. Then, the processing task 52 calculates the execution priority from the execution priority setting stage.

That is,
Execution priority setting stage = (CPU core number × load coefficient−CPU core number) / (maximum execution priority−normal execution priority value)
Then,
Execution priority = (number of waiting tasks−number of CPU cores) / execution priority setting stage.

  For example, assuming that the number of CPU cores is 4, the load coefficient is 2, the normal execution priority value is 0, and the maximum execution priority value is 20, the execution priority setting stage = (4 × 2−4) / (20 −0) = 0.2, and execution priority = (number of tasks waiting to be executed−4) /0.2. FIG. 13 is a diagram illustrating the execution priority based on the number of tasks waiting to be executed. For example, when the number of tasks waiting for execution is 5, the execution priority = (5-4) /0.2=5, and when the number of tasks waiting for execution is 6, the execution priority = (6-4) / 0. 2 = 10.

  When timer accuracy is used as a change factor of execution priority, the timer registration task 51 sets an allowable error value for each timer at the time of timer registration. The allowable error value is managed by a value divided by the designated slot number calculated by the designated timer value / time slice. For example, when the specified timer value is 1000 msec, the allowable error is 200 msec, and the time slice is 10 msec, 1000 (specified timer value) / 10 (time slice) = 100, 200 (allowable error) / 100 = 2 msec. Therefore, the permissible error per time slice of the timer is 2 msec.

  There are a plurality of timers in the timer track, and different tolerances may be set for each timer. However, since the timer processing task 52 evaluates only one tolerance, the timer registration task 51 is registered. The minimum error in the finished timer is adopted as the timer accuracy. When the timer employed as the minimum error is canceled or timed out, the timer registration task 51 employs the allowable error value of the timer having the second smallest allowable error.

The timer control program 5 dynamically changes the execution priority by any of the following methods.
(1) While the timer error exceeds the threshold, the execution priorities of the timer processing task 52 and the timeout processing task are periodically increased by a fixed value.
(2) The execution priority of the timer processing task 52 and the timeout processing task is uniquely determined by the timer error.

  In the method (1), the timer processing task 52 monitors the elapsed time from immediately before the time slice suspension to after the time-out processing for the time slice. Then, the timer processing task 52 increases the execution priority of the timer processing task 52 and the timeout processing task while the elapsed time exceeds the time slice + the allowable error value. Therefore, the timer processing task 52 can suppress the operation delay of the timer processing task 52 in a high load state and improve the timer accuracy.

  In the method (2), the timer processing task 52 sets the execution priority to the normal value when the elapsed time is up to the time slice, and sets the execution priority to the maximum value when the same timer error as the allowable error occurs. To do. Then, the timer processing task 52 divides the interval in the designated range of the execution priority, and obtains a timer error for increasing the execution priority by 1 as an execution priority setting stage. Then, the timer processing task 52 calculates the execution priority from the execution priority setting stage.

That is,
Execution priority setting stage = tolerance per time slice / (maximum execution priority-normal execution priority)
Then,
Execution priority = (timer error per time slice) / execution priority setting stage.

  For example, when the specified timer value is 1000 msec, the allowable error is 200 msec, the time slice is 10 msec, and the error per time slice is 1.5 msec (the specified timer value error is 150 msec), the execution priority setting stage = 2 msec / 20 = 0.1 msec, execution priority = timer error / 0.1 = 15. FIG. 14 is a diagram illustrating execution priorities based on timer errors. Here, the execution priority normal value is 0, and the execution priority maximum value is 20. For example, if the error per time slice is 0.1 msec, the execution priority = 0.1 / 0.1 = 1.

  The user decides which of the number of tasks waiting for execution and the timer error to adopt as a change factor of the execution priority based on the advantages and disadvantages of each. FIG. 15 is a diagram illustrating advantages and disadvantages of each factor of changing execution priority.

  As shown in FIG. 15, the number of tasks waiting to be executed has an advantage that it is possible to detect an antecedent (an increase in the number of tasks waiting to be executed) before the occurrence of a timer error and to suppress the occurrence of errors in advance. . On the other hand, the number of tasks waiting for execution has a drawback that the CPU processing resources 52 may be unfairly consumed because the execution priority of the timer processing task 52 may be changed even in a situation where no timer error occurs.

  The timer error has an advantage that the CPU resource can be efficiently used to eliminate the timer error because the execution priority of the timer processing task 52 is changed when the timer error occurs. On the other hand, the timer error has a disadvantage that the timer error until the timer error occurrence is detected cannot be suppressed because the execution priority of the timer processing task 52 is changed when the timer error occurs.

  Next, a flow of processing using a timer will be described with reference to FIGS. 16 and 17. FIG. 16 is a flowchart showing a flow of processing for starting and using a timer for each connection. Here, a case where the transmission control task 31 establishes a connection will be described.

  As shown in FIG. 16, the transmission control task 31 requests connection establishment (step S1), and starts a timer for monitoring connection establishment (step S2). Then, the transmission control task 31 determines whether or not the connection establishment is completed (step S3), and if completed, stops the timer (step S4) and performs a connection establishment success process (step S5).

  On the other hand, if the connection establishment has not been completed, the transmission control task 31 determines whether or not the monitoring timer has timed out (step S6), and if it has not timed out, returns to step S3. If the timeout has occurred, the transmission control task 31 performs a connection establishment failure process (step S7).

  In this way, the transmission control task 31 can monitor connection establishment using a timer.

  FIG. 17 is a flowchart showing a flow of processing for starting and using a timer for each message. As shown in FIG. 17, the message control task 32 transmits a message (step S11) and starts a timer that monitors reception of a response message (step S12). Then, the message control task 32 determines whether or not a response message has been received (step S13), and if received, stops the timer (step S14) and performs a message transmission success process (step S15).

  On the other hand, if the response message has not been received, the message control task 32 determines whether or not the monitoring timer has timed out (step S16), and if it has not timed out, returns to step S13. When the time-out occurs, the message control task 32 performs a message transmission failure process (step S17).

  As described above, the message control task 32 can monitor the transmission of the message using the timer.

  Next, a timer registration process flow will be described. FIG. 18 is a flowchart showing the flow of the timer registration process. Here, the division number N between the timer slots is 2. As shown in FIG. 18, the timer registration task 51 acquires the current time as the timer registration time (step S21), and acquires the suspension start time of the timer processing task 52 from the timer management table 53 (step S22).

  Then, the timer registration task 51 determines whether or not the timer registration time-pause start time is less than time slice / 2 (step S23). As a result, if it is less than time slice / 2, the timer registration task 51 performs timer registration in the timer slot equal to the current slot + the number of designated slots + 1/2 (step S24). On the other hand, if it is not less than time slice / 2, the timer registration task 51 performs timer registration in the current slot + number of designated slots + 1 timer slot (step S25).

  Then, the timer registration task 51 performs timer registration in the allowable error order timer queue (step S26), and determines whether or not the allowable error specified by the timer registration request is the minimum allowable error in the registration timer ( Step S27). As a result, if it is the minimum allowable error, the allowable error of the timer is set as an allowable timer error value (step S28). Here, the permissible error order timer queue is a queue of timers sorted in the permissible error order, and the permissible timer error value is an error specified for the timer error for each timer registration.

  As described above, the timer registration task 51 can reduce the timer error by specifying the timer slot in which the timer registration is performed based on the timer registration time-pause start time and time slice / 2.

  Next, a flow of timer registration processing when the timer slots are divided into N will be described. FIG. 19 is a flowchart showing the flow of the timer registration process when the timer slots are divided into N parts. As shown in FIG. 19, the timer registration task 51 acquires the current time as the timer registration time (step S31), and acquires the suspension start time of the timer processing task 52 from the timer management table 53 (step S32).

  Then, the timer registration task 51 sets the time slice / N as the time slot between slots (step S33), and sets the current time-pause start time as the time slice elapsed time (step S34). Then, the timer registration task 51 sets [time slice elapsed time / inter-slot time slice] / N to the inter-slot registration position (step S35). Here, [X] is a value obtained by rounding up the decimal part of X. Then, the timer registration task 51 sets the current slot + the number of designated slots + the inter-slot registration position (step S36).

  Then, the timer registration task 51 performs timer registration in the allowable error order timer queue (step S37), and determines whether or not the allowable error specified in the timer registration request is the minimum allowable error in the registration timer ( Step S38). As a result, when it is the minimum allowable error, the allowable error of the timer is set as an allowable timer error value (step S39).

  As described above, the timer registration task 51 can reduce the timer error by specifying the timer slot in which the timer registration is performed based on the time slice elapsed time and the inter-slot time slice.

  Next, the flow of timer processing will be described. FIG. 20 is a flowchart showing the flow of timer processing. The timer processing task 52 stores the current time as the suspension start time (step S41), and determines whether or not the timer has been registered within the range of the current slot + 1 (step S42).

  As a result, if the timer has not been registered, the timer processing task 52 pauses for a time slice (step S43), and if the timer has been registered, performs an interslot timer process (step S44). Here, the inter-slot timer process is a process of a timer request registered in a timer slot added by division between timer slots.

  Then, the timer processing task 52 transitions the current slot (step S45), and performs a timer request timeout process registered in the transition destination timer slot (step S46). Then, the timer processing task 52 determines whether or not the apparatus status monitoring interval has elapsed (step S47), and if not, returns to step S41.

  On the other hand, when the device status monitoring interval has elapsed, the timer processing task 52 checks the load status or timer error (step S48), and determines the execution priority change mode (step S49). As a result, in the increase mode, the timer processing task 52 determines whether or not the load situation or the timer error is equal to or greater than a threshold (step S50).

  As a result, the timer processing task 52 increases the execution priority by a fixed value when it is equal to or greater than the threshold (step S51), and returns the execution priority to the default when it is not equal to or greater than the threshold (step S52). On the other hand, when the execution priority change mode is the unique determination mode, the timer processing task 52 changes the execution priority to the execution priority obtained from the load status or the timer error (step S53).

  FIG. 21 is a flowchart showing the flow of the inter-slot timer process. As shown in FIG. 21, the timer processing task 52 initializes the in-slot position to 1 (step S61), and initializes the pause time to time slice / N (step S62). Then, the timer processing task 52 determines whether or not the in-slot position has reached N (step S63), and if it has reached N, sleeps for a pause time (step S64).

  On the other hand, when the position in the slot has not reached N, the timer processing task 52 determines whether or not there is a timer request in the timer slot at the position in the slot (step S65). Sleep for time (step S66). The timer processing task 52 performs time-out processing for the timer request (step S67), adds 1 to the position in the slot (step S68), and returns to step S62.

  On the other hand, if there is no timer request in the timer slot at the position in the slot, the timer processing task 52 adds the time slice / N to the pause time (step S69). The timer processing task 52 adds 1 to the position in the slot (step S70), and returns to step S63.

  As described above, the timer processing task 52 can process the timer request registered in the timer slot added within the time slice interval by performing the inter-slot timer processing.

  Next, details of the timer management table 53 will be described. FIG. 22 is a diagram illustrating an example of the timer management table 53. As shown in FIG. 22, the timer management table 53 includes an unused timer queue 61, a timer pool management queue 62, a suspension start time 63, a current slot 64, a timer track 65, the number of timer slots before division ( M) 66. The timer management table 53 includes an inter-slot division number (N) 67, an allowable error value 68, a load coefficient value 69, an allowable error order timer queue 70, and a timer queue 71 for one minute or longer.

  The unused timer queue 61 is a FIFO (First In First Out) queue that manages unused timers. Here, the timer is a cell that stores a timer request. The timer pool management queue 62 is a FIFO queue for managing timer cell pools. The pause start time 63 is a time set immediately before the timer processing task 52 pauses.

  The current slot 64 is a pointer indicating the current position of the timer slot. The timer track 65 is a set table of timer slots and includes M × N timer slots. Each timer slot is an area in which a timer request to be timed out is registered. The timer track 65 includes a 60 second timer slot. A timer request with a specified timer value less than 60 seconds is registered in the corresponding timer slot. The pre-division timer slot number 66 is the number of timer slots before division between timer slots. The slot division number 67 is the number of divisions between timer slots. In the timer management table 53 shown in FIG. 22, the number identifying the timer slot after division is an integer, so the number identifying the timer slot is multiplied by N.

  The allowable error value 68 is the minimum value among the allowable errors specified for the timer error for each timer registration. The load coefficient value 69 is an allowable value of the device load designated for each device. The allowable error order timer queue 70 is a queue of timers sorted in the allowable error order. The one-minute or more timer queue 71 is a queue in which timers having a specified timer value of 60 seconds or more are temporarily registered.

  FIG. 23 is a diagram showing an example of timer registration processing using the timer management table 53 shown in FIG. FIG. 23 shows processing when registering a timer request with a specified timer value of 200 msec in the state where the current slot 64 is 1. Further, the number of divisions between slots is 67 = 2.

  As shown in FIG. 23, when the timer registration process is started, the timer registration task 51 acquires an unused timer from the unused timer queue 61 (t1), and acquires the current time from the OS 81 as the timer registration time (t2). . Then, the timer registration task 51 acquires the suspension start time 63 (t3), and compares the timer registration time-pause start time 63 with the time slice / 2.

  As a result, when the timer registration time-pause start time 63 is less than time slice / 2, the timer registration task 51 registers the timer in the timer slot of (1 + 2 + 1/2) × 2 = 7 (t4). On the other hand, when the timer registration time-pause start time 63 is equal to or greater than time slice / 2, the timer registration task 51 registers the timer in the timer slot of (1 + 2 + 1) × 2 = 8 (t5).

  Then, the timer registration task 51 updates the timer error value 68 as necessary, registers the timer registered timer in the allowable error order timer queue 70 (t6), and completes the timer registration process.

  FIG. 24 is a diagram showing an example of timer processing using the timer management table 53 shown in FIG. FIG. 24 shows a state where the current slot 64 is six. Further, the number of divisions between slots is 67 = 2. As shown in FIG. 24, the timer processing task 52 acquires the current time as the suspension start time 63 (t11), and stores the suspension start time 63 (t12).

  When there is a timer slot in which a timer request is registered between the current slot 64 and the timer slot of the current slot 64 + 2, the timer processing task 52 performs inter-slot timer processing (t13). On the other hand, when there is no timer slot in which the timer request is registered between the current slot 64 and the timer slot of the current slot 64 + 2, the timer processing task 52 performs time slice suspension (t14).

  Then, the timer processing task 52 performs a current slot transition that advances the current slot 64 by two (t15). In FIG. 24, the current slot 64 transitions from 6 to 8. Then, the timer processing task 52 issues a timeout notification to the timeout processing task 82 regarding the timer request registered in the eight timer slots (t16).

  When the timer accuracy is used as the execution priority change factor, the timer processing task 52 acquires the current time as the timer processing completion time (t17), and uses the apparatus load as the execution priority change factor. Acquires the load status (t18). Then, the timer processing task 52 determines the execution priority value from the load status or the timer error (t19), and requests the OS 81 to change the execution priority of the timer processing task 52 and the timeout processing task 82 (t20).

  Next, a hardware configuration of the communication control device 3 that executes software such as the timer control program 5 will be described. FIG. 25 is a diagram illustrating a hardware configuration of the communication control device 3. As illustrated in FIG. 25, the communication control device 3 includes a CPU 91, an HDD (Hard Disk Drive) 92, a memory 93, and a LAN interface 94.

  The CPU 91 is a central processing unit that reads a program from the memory 93 and executes it. The HDD 92 is a disk device that stores programs and data. The memory 93 is a RAM (Random Access Memory) that stores a program and a program execution result. The LAN interface 94 is an interface for connecting the communication control device 3 to the information processing system 2 or the like via a LAN. The timer control program 5 and the like executed in the communication control device 3 are stored in the HDD 92, read out to the memory 93, and executed by the CPU 91.

  As described above, in the embodiment, the timer control program 5 divides the timer slot into N and adds the timer slot. Then, the timer registration task 51 registers the timer request by identifying the timer slot from which the time-out process should be woken up based on the current slot, the designated timer value, and the time slice elapsed time from the timer slots at the time slice / N time interval. To do. Then, when a timer request is registered between the current slot and the timer slot of current slot + 1, the timer processing task 52 performs inter-slot timer processing. On the other hand, when a timer request is not registered between the current slot and the timer slot of current slot + 1, the timer processing task 52 pauses for a time slice and transitions to the next timer slot as in the conventional case. . Therefore, the timer control program 5 can reduce the timer error due to the time slice elapsed time at the time of timer registration.

  In the embodiment, the timer processing task 52 dynamically changes the execution priority of the timer processing task 52 and the timeout processing task 82 based on the load status or timer accuracy of the communication control device 3. Therefore, the timer control program 5 can suppress deterioration of timer accuracy even when the communication control device 3 is in a high load state.

  In the embodiment, the timer processing task 52 calculates an increase in execution priority or a value of execution priority of the timer processing task 52 and the timeout processing task 82, and changes the calculated execution priority to the calculated execution priority. Therefore, the timer control program 5 can flexibly change the execution priority.

  In the embodiments, the communication control apparatus has been described. However, the present invention is not limited to this, and the present invention is similarly applied to other apparatuses that include a processor and a memory such as an information processing apparatus and use a timer. Can do.

  In the embodiment, the case where the timer slots are equally divided into N has been described. However, the present invention is not limited to this, and the same applies to the case where the timer slots are divided into N different sizes. Can be applied.

1,4 Information communication system 2 Information processing system 3 Communication control device 5 Timer control program 31, 33 Transmission control task 32 Message control task 51 Timer registration task 52 Timer processing task 53 Timer management table 61 Unused timer queue 62 Timer pool management queue 63 Pause start time 64 Current slot 65 Timer track 66 Number of timer slots before division 67 Number of divisions between slots 68 Permissible error value 69 Load factor value 70 Permissible error order timer queue 71 Timer queue 81 minutes or more 81 OS
82 Timeout processing task 91 CPU
92 HDD
93 Memory 94 LAN interface

Claims (6)

In a timer control program that controls a timer using a plurality of timer slots,
The time slots are divided into N (N is an integer of 2 or more),
A current slot indicating a current timer slot among the plurality of timer slots, a timer value specified by a timer registration request, and a time slice pause start time from a time slice pause time to the timer registration From the time slice elapsed time indicating the time, determine the timer slot in which the timer timeout process is woken up, register the timer request in the determined timer slot,
If there is a timer slot to which a timer request is registered between the current slot and the timer slot that is the time slice after the current slot, P time slices corresponding to the position of the registered timer slot are present. (P is an integer of 1 or more and N-1 or less) A timer control program that causes a computer to execute a process in which the current slot transitions to an advanced position.   If there is no timer slot in which a timer is registered between the current slot and the timer slot after the time slice from the current slot, the current slot transitions to a position advanced by N time slices. The timer control program according to claim 1, wherein:   The computer further includes a process of changing the priority of the process of transitioning to the timer slot in which the timer request is registered or the process of transitioning to the timer slot after the time slice based on the load status of the computer or an error of the timer. The timer control program according to claim 2, wherein the timer control program is executed. Further causing the computer to execute a process of calculating the amount of increase in the priority or a process of calculating the priority using a predetermined calculation formula,
The timer control program according to claim 3, wherein the changing process is changed to the priority calculated by the calculating process. In a timer control method for controlling a timer using a plurality of timer slots,
Computer
The time slots are divided into N (N is an integer of 2 or more),
A current slot indicating a current timer slot among the plurality of timer slots, a timer value specified by a timer registration request, and a time slice pause start time from a time slice pause time to the timer registration From the time slice elapsed time indicating the time, determine the timer slot in which the timer timeout process is woken up, register the timer request in the determined timer slot,
If there is a timer slot to which a timer request is registered between the current slot and the timer slot that is the time slice after the current slot, P time slices corresponding to the position of the registered timer slot are present. (P is an integer greater than or equal to 1 and less than or equal to N-1) A timer control method characterized by executing a process in which the current slot transitions to an advanced position. In an information processing apparatus having a memory and a processor connected to the memory,
In the processor,
When executing the process of controlling the timer using a plurality of timer slots, the time slots are divided into N (N is an integer of 2 or more),
A current slot indicating a current timer slot among the plurality of timer slots, a timer value specified by a timer registration request, and a time slice pause start time from a time slice pause time to the timer registration From the time slice elapsed time indicating the time, determine the timer slot in which the timer timeout process is woken up, register the timer request in the determined timer slot,
If there is a timer slot to which a timer request is registered between the current slot and the timer slot that is the time slice after the current slot, P time slices corresponding to the position of the registered timer slot are present. (P is an integer equal to or greater than 1 and equal to or less than N−1) An information processing apparatus that causes the current slot to transition to an advanced position.

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