JP6342794B2 - 配線基板及び配線基板の製造方法 - Google Patents
配線基板及び配線基板の製造方法 Download PDFInfo
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Description
なお、添付図面は、便宜上、特徴を分かりやすくするために特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。また、断面図では、各部材の断面構造を分かりやすくするために、一部の部材のハッチングを梨地模様に代えて示し、一部の部材のハッチングを省略している。
図1(a)に示すように、配線基板10は、第1基板11と、第2基板12と、電子部品40と、接続部材60,70と、封止樹脂80とを有している。この配線基板10は、第1基板11と第2基板12との間に電子部品40を内蔵した電子部品内蔵型の配線基板である。
基板本体20は、コア基板21と、コア基板21の貫通孔21Xに形成された貫通電極22と、コア基板21の上下面に積層された絶縁層23,24と、それら絶縁層23,24に形成された配線25,26及びビア配線27,28とを有している。基板本体20に設けられた貫通電極22、配線25,26及びビア配線27,28は、配線パターン30と配線パターン32とを電気的に接続している。なお、コア基板21の材料としては、例えば、補強材であるガラスクロス(ガラス織布)にエポキシ樹脂を主成分とする熱硬化性の絶縁性樹脂を含浸させ硬化させた、いわゆるガラスエポキシ樹脂を用いることができる。絶縁層23,24の材料としては、例えば、エポキシ系樹脂やポリイミド系樹脂などの絶縁性樹脂を用いることができる。貫通電極22、配線25,26及びビア配線27,28の材料としては、例えば、銅(Cu)や銅合金を用いることができる。
第2基板12は、コア基板51と、コア基板51の貫通孔51Xに形成された貫通電極52と、最上層の配線パターン53と、ソルダレジスト層54と、最下層の配線パターン55と、ソルダレジスト層56とを有している。配線パターン53と配線パターン55とは貫通電極52を介して電気的に接続されている。コア基板51の材料としては、例えば、ガラスエポキシ樹脂などの絶縁性樹脂を用いることができる。
次に、図2(b)に示す工程では、部品接続用パッドP1上に接続部材60を搭載(接合)するとともに、接続用パッドP2上に接続部材70を搭載(接合)する。以下に、接続部材60,70の搭載方法の一例について詳述する。
次いで、図4(a)に示す工程では、接続部材60,70がセットされた振込治具90と第1基板11とを位置合わせした後に、図3(b)に示した状態とは上下逆さまになるように振込治具90を反転させる。このとき、振込治具90の開口部90Xが部品接続用パッドP1及び接続用パッドP2と平面視で重なる位置に振込治具90が配置される。続いて、上記吸着機構(図示略)による開口部90X内の空気の吸気を止めて吸着をオフ状態とすることで、吸着保持されていた接続部材60,70を、フラックス91が塗布された部品接続用パッドP1上及び接続用パッドP2上にそれぞれ落下させる。これにより、ソルダレジスト層31の開口部31X内に塗布されたフラックス91上に接続部材60が搭載(仮止め)され、ソルダレジスト層31の開口部31Y内に塗布されたフラックス91上に接続部材70が搭載(仮止め)される。なお、本工程では、接続部材60,70全体が略柱状に形成されており、図1(b)に示した膨出部63及び膨出部73が未だ形成されていない。このため、本工程では、接続部材60と電極端子42とは物理的及び電気的に接続されていない。
次に、図5(a)に示す工程では、第2基板12を準備する。第2基板12は、公知の製造方法により製造することが可能であるが、その概略について、図5(a)を参照しながら簡単に説明する。なお、図5(a)において、同図に示す構造体は図1(a)とは上下反転して描かれている。
次いで、第2基板12の上方、具体的にはソルダレジスト層56の上方に、チップキャパシタ40及び接続部材60,70が搭載された第1基板11を配置する。具体的には、接続部材60(部品接続用パッドP1)と部品接続用パッドP5とが対向するように、且つ、接続部材70(接続用パッドP2)と接続用パッドP6とが対向するように、第1基板11を位置決めする。
以上説明した本実施形態によれば、以下の効果を奏することができる。
(1)部品接続用パッドP1上に形成した接続部材60の半田層62の下端部に、コア部61から平面方向に広がり、電子部品40の電極端子42と接合される膨出部63を形成するようにした。このように半田層62の一部を平面方向に広げることにより、その半田層62(膨出部63)を介して、部品接続用パッドP1と電極端子42とを電気的に接続するようにした。これにより、近接して配置された部品接続用パッドP1と電極端子42とを電気的に接続する接続配線の配線長を、ワイヤボンディング実装する場合に比べて短くすることができる。このため、部品接続用パッドP1と電極端子42との間の信号(データ)の伝送速度を高速化することができる。
なお、上記実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・上記実施形態では、第1基板11にチップキャパシタ40を搭載するようにした。これに限らず、他の電子部品(例えば、チップキャパシタ以外のチップ部品や半導体チップ等)を第1基板11に搭載するようにしてもよい。
・図7及び図8に示した半導体チップ100では、回路形成面の外周領域に電極端子101を形成した。これに限らず、例えば図9に示すように、半導体チップ100Aの回路形成面(ここでは、下面)の外周領域よりも内側の領域に電極端子101を形成するようにしてもよい。この場合には、例えば、電極端子101と電気的に接続された接続配線102が、電極端子101から半導体チップ100Aの側面まで引き回されている。この接続配線102は、平面視において部品接続用パッドP1,P5と近接した位置に設けられている。そして、接続配線102は、接続部材60を介して、部品接続用パッドP1及び部品接続用パッドP5と電気的に接続されている。これにより、電極端子101が、接続部材60及び接続配線102を介して、部品接続用パッドP1及び部品接続用パッドP5と電気的に接続される。このように、電極端子101が回路形成面の内側の領域に形成されている場合であっても、接続配線102を形成することにより、その接続配線102と接続部材60を介して、電極端子101と部品接続用パッドP1,P5とを電気的に接続することができる。なお、接続配線102の材料としては、例えば、銀や銀合金を用いることができる。
・上記実施形態及び上記各変形例において、部品接続用パッドP1,P5と電子部品(チップキャパシタ40及び半導体チップ100,100A)の電極端子42,101との接続、及び接続用パッドP2,P6間の接続に、接続部材60,70以外の接続方法を併用してもよい。
まず、図12(a)に示す工程では、銅等の金属からなる柱状のコア部61と、そのコア部61の外周面全面を被覆する半田層62とを有する接続部材60を準備する。また、銅等の金属からなる柱状のコア部61Aと、そのコア部61Aの外周面全面を被覆する半田層62Aとを有する接続部材60Aを準備する。このとき、半田層62は、コア部61の外周面全面を均一の厚さで被覆するように形成され、半田層62Aは、コア部61Aの外周面全面を均一の厚さで被覆するように形成されている。
・上記実施形態及び上記各変形例の第2基板12において、最外層の配線パターン53,55よりも内層の構造については特に限定されない。すなわち、第2基板12は、少なくとも、最外層の配線パターン53,55が基板内部を通じて相互に電気的に接続された構造を有していれば十分であるため、最外層の配線パターン53,55よりも内層の構造については特に限定されない。例えば、コア基板51の構造及び材質は特に限定されない。また、コア基板51上に下層配線とその下層配線を覆う絶縁層とを所要の層数形成するようにしてもよい。あるいは、第2基板12を、コア基板51を含まないコアレス基板としてもよい。
11 第1基板
12 第2基板
30 配線パターン
40 電子部品(チップ部品)
41 本体部
42 電極端子(接続端子)
55 配線パターン
60 接続部材(第1接続部材)
61 コア部(第1コア部)
62 半田層(第1半田層)
63 膨出部(第1膨出部)
60A 接続部材(第2接続部材)
61A コア部(第2コア部)
62A 半田層(第2半田層)
63A 膨出部(第2膨出部)
80 封止樹脂
100,100A 半導体チップ(電子部品)
101 電極端子(接続端子)
P1 部品接続用パッド(第1パッド)
P5 部品接続用パッド(第2パッド)
P10 接続用パッド(第1パッド)
P11 接続用パッド(第3パッド)
Claims (5)
- 第1基板の最上層に形成された第1パッドと、
前記第1基板の上面に搭載された電子部品と、
前記電子部品に形成され、平面視において前記第1パッドと近接した位置に設けられた接続端子と、
前記第1パッド上に形成され、前記第1パッドと前記接続端子とを電気的に接続する接続部材と、
前記第1基板の上に搭載された第2基板と、を有し、
前記接続部材は、柱状のコア部と、前記コア部の周囲を被覆し、前記第1パッドと接合される半田層とを有し、
前記半田層は、前記コア部から平面方向に広がり、前記接続端子と接合される膨出部を有し、
前記電子部品は、前記第1基板と前記第2基板との間に設けられ、
前記第2基板の最下層には、前記第1パッドと対向する位置に第2パッドが設けられ、
前記接続部材は、前記第2パッドと接合され、前記第1パッドと前記第2パッドと前記接続端子とを電気的に接続することを特徴とする配線基板。 - 前記電子部品は、本体部と前記本体部の対向する側面を被覆する電極端子とを有するチップ部品であり、
前記接続端子は、前記チップ部品の電極端子であることを特徴とする請求項1に記載の配線基板。 - 前記電子部品は、回路形成面とは反対側の面を前記第1基板に向けた状態で前記第1基板上に搭載された半導体チップであり、
前記接続端子は、前記半導体チップの回路形成面に形成された電極端子であることを特徴とする請求項1に記載の配線基板。 - 前記電子部品は、回路形成面を前記第1基板に向けた状態で前記第1基板上に搭載された半導体チップであり、
前記接続端子は、前記半導体チップの回路形成面に形成された電極端子であることを特徴とする請求項1に記載の配線基板。 - 最上層に形成された第1パッドを有する第1基板を準備する工程と、
前記第1基板の上面に電子部品を搭載し、前記電子部品に形成された電極端子を、平面視において前記第1パッドと近接した位置に配置する工程と、
柱状のコア部と、前記コア部の周囲を被覆する半田層とを有する接続部材を準備する工程と、
前記第1パッド上に前記接続部材を搭載する工程と、
前記半田層を溶融し、前記第1基板の上面から上方に盛り上がるように、且つ前記コア部から平面方向に広がるように形成され、前記電極端子と接合される膨出部を前記半田層の下端部に形成する工程と、
最下層に形成された第2パッドを有する第2基板を準備する工程と、
前記膨出部を有する前記接続部材が搭載された前記第1基板を、前記第1パッドが前記第2パッドと対向するように位置合わせする工程と、
前記半田層を前記第2パッドに接合し、前記第2基板上に前記第1基板を固定する工程と、を有することを特徴とする配線基板の製造方法。
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| JP7476980B2 (ja) * | 2020-11-16 | 2024-05-01 | 株式会社村田製作所 | 回路モジュール及び大型回路システム |
| KR20230124544A (ko) * | 2020-12-25 | 2023-08-25 | 나믹스 가부시끼가이샤 | 구리 부재, 프린트 배선판용 도체, 프린트 배선판용 부재, 프린트 배선판, 프린트 회로판 및 그들의 제조 방법 |
| JPWO2022138681A1 (ja) * | 2020-12-25 | 2022-06-30 | ||
| US11791276B2 (en) * | 2021-04-08 | 2023-10-17 | Qualcomm Incorporated | Package comprising passive component between substrates for improved power distribution network (PDN) performance |
| US20240096858A1 (en) * | 2022-09-15 | 2024-03-21 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
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| JPH08316629A (ja) * | 1995-05-16 | 1996-11-29 | Nec Shizuoka Ltd | 半田柱によるマルチ・チップ・モジュール基板の 半田付処理方法 |
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| WO2004034759A1 (ja) * | 2002-10-08 | 2004-04-22 | Dai Nippon Printing Co., Ltd. | 部品内蔵配線板、部品内蔵配線板の製造方法 |
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| EP2290682A3 (en) | 2005-12-14 | 2011-10-05 | Shinko Electric Industries Co., Ltd. | Package with a chip embedded between two substrates and method of manufacturing the same |
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| JP5443849B2 (ja) * | 2009-06-26 | 2014-03-19 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
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| US9818681B2 (en) | 2017-11-14 |
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