JP6351073B2 - Communication input / output device - Google Patents

Description

  The present invention relates to a data communication technique, and more particularly to a memory access control technique used in a communication input / output device that inputs and outputs communication data (frame data).

Conventionally, for example, a configuration as disclosed in Patent Document 1 has been proposed as a communication input / output device that is used in data communication such as the Internet to input / output communication data such as Ethernet (registered trademark) frame data. ing. FIG. 24 is a block diagram showing a configuration of a conventional communication input / output device (built-in memory).
This communication input / output device includes a multiplexing device MUX, a recording device MEM, and a demultiplexing device DEMUX.

The MUX adds the queue designation information corresponding to the output destination of the frame data to the input frame data by the queue designation information addition section provided for each input port, and then multiplexes it by the multiplexing section. Output.
The MEM receives the frame data output from the MUX by time division multiplexing by the write control unit, refers to the queue designation information and the queue map added to each frame data, and stores the frame data in the built-in data memory. Of the queues logically provided for each output destination, the frame data is written to the queue address corresponding to the queue designation information. Further, in response to a read instruction from the DEMUX, the MEM reads frame data from the corresponding queue by the read control unit and outputs the frame data to the DEMUX.

  The DEMUX reads out the frame data from the output destination queue corresponding to the priority output port in the MEM based on the priority control logic for each output port by the reading unit, and distributes the frame data to the corresponding output port by the distribution unit. The data is converted into the communication speed of the output port by a speed conversion unit provided for each output.

  FIG. 25 is an explanatory diagram showing the correspondence between queues and output ports, and shows the case where the number of output ports is three. In FIG. 25A, queues and output ports are associated one-to-one, but as illustrated in FIG. 25B, one frame data is associated with a plurality of output ports. Can be handled when In addition, as shown in FIG. 25C, a queue corresponding to the read priority can be associated with each output port.

JP 2011-0101095 A

  In such a communication input / output device, the storage capacity required by the MEM increases as the output system increases, so a DRAM is used as a data memory. However, since DRAM access has a waiting time due to the activation of the row address in each bank, in some cases, the effective throughput of the DRAM access is extremely reduced to follow the processing speed of frame data. There is a problem that communication quality is deteriorated because communication cannot be performed.

  In general, in a DRAM, when writing data to an arbitrary row address of an arbitrary bank, it is necessary to activate the row address in the bank. When accessing a different row address of the same bank, the row address is Since it is necessary to activate a new row address after waiting for the used access to be completed, a relatively large waiting time occurs due to the activation of the row address in accessing the same bank. Specifically, this is a case where accesses to different row addresses in the same bank are continuous. As other conditions for waiting time, there are a case where writing is performed in the same bank after reading and a case where reading is performed from the same bank after writing.

  Therefore, these waiting times cause a decrease in effective throughput related to DRAM access. Therefore, in particular, in communication I / O devices, short frame data may be input continuously in bursts. In such a case, when frequently accessing different row addresses in the same bank The effective throughput may be extremely reduced.

  An object of the present invention is to provide a memory access control technique capable of suppressing such a decrease in effective throughput related to DRAM access.

  In order to achieve such an object, the communication input / output device according to the present invention adds queue designation information indicating a queue corresponding to an output system to which the communication data is to be output to communication data that is sequentially input. And the communication data transferred from the multiplexing device are temporarily stored in a write target queue designated by the queue designation information among a plurality of queues logically formed in a data memory. Multiplex that reads out the communication data from the queue to be read corresponding to the output system selected from the queue and the output system selected based on the priority control logic from the queue, converts it to the communication speed of the output port corresponding to the output system, and outputs it A communication input / output device comprising a separation device, wherein the recording device comprises a DRAM having a plurality of row addresses for each bank, and the queue and A write target row address corresponding to the write target queue in the bank when the communication data is written to the write target queue and the data memory storing the communication data of the queue with a corresponding individual row address Is selected as a write target bank, the communication data is written, and if there is no bank in which the write target row address is active, the write target row address is inactive. And a DRAM access unit for writing the communication data after activating the write target row address by selecting the bank in the activated state as the write target bank.

  In addition, according to an example of the configuration of the communication input / output device according to the present invention, the DRAM access unit may use a column address when writing the communication data of the queue to the bank for each combination of the queue and the bank. A bank management memory for storing a write pointer value to be used; when writing the communication data, a write pointer value corresponding to a combination of the write target row address and the write target bank is read from the bank management memory; The communication data is acquired and written to the column address composed of the write pointer value among the write target row addresses of the write target bank.

In addition, one configuration example of the communication input / output device according to the present invention includes: a queue control memory that stores queue control information used when the recording device controls writing / reading to / from the queue of the data memory; based on the queue control information in the queue control memory, and the manual writing to write object queue that instructs the DRAM access unit writing control section of the communication data transferred from the multiplexer, the queue control memory A read control unit that instructs the DRAM access unit to read communication data from the read target queue based on the queue control information, and transfers the read communication data to the demultiplexing device. For each virtual storage address used on the virtual data memory, the memory writes to the virtual storage address. A subsequent address indicating a virtual storage address of communication data subsequent to the communication data stored, and for each of the queues, a queue head address indicating the start and end of the virtual storage address in which the communication data of the queue is written, and A queue final address is stored, a next write address indicating a virtual storage address to which communication data is to be written next is stored in common with each queue, and the write control unit stores the communication in the write target queue. When writing data, the DRAM access unit is instructed to write the communication data to the write target virtual address consisting of the next write address, and the subsequent queue address of the write target queue and the subsequent queue end address before writing Each of the address and the next write address is updated, and the read control unit reads the read target key. When reading the communication data from-, the DRAM access unit is instructed to read the communication data for the read target virtual address consisting of the queue start address of the read target queue, and the queue start address and next write address of the read target queue are read. , And a subsequent address related to the new next write address, and the DRAM access unit writes the communication data corresponding to the write target virtual address in response to the communication data write instruction for the write target virtual address. Address management memory for recording, and in response to a read instruction of the communication data for the read target virtual address, the bank corresponding to the read target virtual address is determined by reading from the address management memory It is.

  Also, in one configuration example of the communication input / output device according to the present invention, the recording device uses, for each queue, the number of virtual storage addresses on the virtual data memory used by the queue. Queue use address number memory for storing the number of addresses, and when writing the communication data to the write target queue, based on the data length of the communication data, the required address number indicating the number of virtual storage addresses required for writing Calculate the remaining number of addresses indicating the number of virtual storage addresses that can be used for writing based on the number of used addresses in the queue to be written or each queue acquired from the queue used address number memory By comparing the number of addresses with the number of remaining addresses, it is determined whether or not the communication data can be written. It is obtained so as to further include an access arbitration unit for instructing the writing of the communication data to the write control unit.

  According to the present invention, in a recording device for temporarily storing communication data transferred from a multiplexing device in a write target queue designated by queue designation information among a plurality of queues logically formed in a data memory, Even when the data memory is composed of a DRAM, the number of activations of the row address can be reduced. For this reason, it is possible to suppress a decrease in effective throughput related to DRAM access.

1 is a block diagram illustrating a configuration of a communication input / output device according to a first embodiment. FIG. 1 is a block diagram illustrating a configuration of a recording apparatus according to a first embodiment. It is an example of the storage image of virtual data memory. It is a storage example of an address queue management memory. This is a storage example of a queue head / end address memory. It is a storage example of a queue use address number memory. 1 is a block diagram showing a configuration of a DRAM access unit according to a first embodiment. FIG. It is a storage example of a bank management memory. It is a storage example of an address management memory. It is explanatory drawing which shows the write-in operation | movement in a write-control part. It is explanatory drawing which shows the read-out operation | movement in a read control part. It is explanatory drawing which shows the queue control information immediately before data P2-1 reading (immediately after writing data P2-3). It is explanatory drawing which shows the change of the queue control information at the time of data P2-1 reading. It is explanatory drawing which shows the queue control information immediately after reading data P2-1 (just before reading data P2-2). It is explanatory drawing which shows the change of the queue control information at the time of data P2-2 reading. It is explanatory drawing which shows the queue control information immediately after reading data P2-2 (just before writing data P2-4). It is explanatory drawing which shows the change of the queue control information at the time of data P2-4 writing. It is explanatory drawing which shows the queue control information immediately after data P2-4 writing. It is a flowchart which shows the DRAM write processing concerning 1st Embodiment. 3 is a flowchart showing DRAM read processing according to the first embodiment; It is a block diagram which shows the structure of the access arbitration part concerning 2nd Embodiment. It is an example of a structure of the address number information for determination. It is a flowchart which shows the writability determination processing concerning 2nd Embodiment. It is a block diagram which shows the structure of the conventional input / output device for communication (built-in memory). It is explanatory drawing which shows a response | compatibility with a queue and an output port.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a communication input / output device 1 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of the communication input / output device according to the first embodiment.

  The communication input / output device 1 is a communication input / output device for inputting / outputting communication data such as Ethernet (registered trademark) frame data, which is used in Internet communication or the like. The communication data input from the port is separated for each output system to which the communication data is to be output, converted to the communication speed of the output port corresponding to the output system, and output.

  As shown in FIG. 1, the communication input / output device 1 includes a multiplexer (MUX) 10, a demultiplexer (DEMUX) 20 with a built-in memory access control function, and a recording device (MEM) with a built-in access control function. 30. In the following, a case where communication data input / output by the communication input / output device 1 is frame data will be described as an example. However, the present invention is not limited to this, and various types of communication data such as packets and ATM cells are converted into frame data. It is also possible to input / output in the same manner as in FIG.

The multiplexing device 10 has a function of multiplexing the frame data sequentially input from the outside by adding queue designation information corresponding to the output system to which the frame data is to be output.
The recording device 30 writes the frame data transferred from the multiplexing device 10 into a write target designated by the queue designation information added to the frame data among a plurality of queues logically formed in the data memory. It has a function to temporarily store in a queue.
The demultiplexer 20 reads the frame data temporarily stored in the read target queue from the read target queue corresponding to the output system selected based on the priority control among the queues in the recording device 30, and corresponds to the output system. It has a function of converting and outputting the communication speed of the output port.

  In this embodiment, in the recording apparatus 30, the data memory 31A is composed of a DRAM having a plurality of row addresses for each bank, the frame data of the queue is stored at the row address corresponding to the queue, and the DRAM access unit When the frame data is written into the write target queue, 31B selects the bank in which the write target row address corresponding to the write target queue is activated as the write target bank, and selects the frame data. When there is no bank in which the write target row address is in the activated state, the bank in which the write target row address is in the inactive state is selected as the write target bank, and the write target row address is selected. The frame data is written after activation.

  In this embodiment, as shown in FIG. 1, a case where two input ports Pin0 and Pin1 are provided as the input port Pin and two output ports Pout0 and Pout1 are provided as the output port Pout will be described as an example. However, the number of input ports Pin and output ports Pout is not limited to this. Three or more of either one or both of the input port Pin and the output port Pout can be provided, and the number of input ports and the number of output ports may be different. Note that the number of input ports may be one.

[Multiplexer]
Next, with reference to FIG. 1, the multiplexing apparatus 10 used in the communication input / output apparatus 1 according to the present embodiment will be described in detail.
The multiplexing apparatus 10 includes a queue designation information adding unit 11 and a multiplexing unit 12 as main circuit units.

  The queue designation information adding unit 11 is provided for each of the input ports Pin0 and Pin1, and for frame data input from the corresponding input port Pin, queue designation information corresponding to the output destination of the frame data, and the frame It has a function of adding data frame length information (Byte) and outputting it to the multiplexing unit 12. At this time, for example, when outputting frame data to the multiplexing unit 12, the frame length information may be added by counting the number of bytes from the beginning to the end of the frame data as the frame length.

Multiplexing unit 12 is provided in common with each queue designation information adding unit 11, multiplexes the frame data output from each queue designation information adding unit 11 in a time division manner, and outputs it to recording apparatus 30. It has a function.
In the multiplexer 10, the designation of the queue corresponding to the output destination of the frame data may be realized by a bridge function such as IEEE802.1D. Specifically, the output port search by MAC address learning and the VLAN-ID are used. The output port can be specified (see Patent Document 1).

[Demultiplexer]
Next, the demultiplexer 20 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG.
The demultiplexer 20 is provided with a reading unit 21, a distribution unit 22, and speed conversion units 23 and 24 as main circuit units.

The reading unit 21 refers to the accumulation status of each queue acquired from the recording device 30 and the reading stop instruction signal output from the speed conversion units 23 and 24, and the frame data based on the priority control logic for each of the output ports Pout0 and Pout1. A function for selecting an output system to be output with priority, a function for outputting a read request for reading frame data from a read target queue corresponding to the output system, and a transfer from the recording apparatus 30 in response thereto The frame data is output to the distribution unit 22.
For priority control logic, for example, if the capacity of each queue is the same, general priority control such as reading from the queue with the largest amount of communication data stored in the queue among readable queues. Logic may be used (see Patent Document 1).

In addition, when the reading unit 21 outputs a read request to the recording device 30, the reading unit 21 instructs the recording device 30 with read data amount information indicating the data amount of the read data in addition to the queue designation information that specifies the queue to be read. To do.
For the read data amount information, for example, when the data accumulation amount of the queue to be read is equal to or less than a preset threshold value, a value equal to the data accumulation amount is output as the read data amount information. May be output as read data amount information.

The distribution unit 22 has a function of distributing the frame data output from the reading unit 21 to the speed conversion units 23 and 24 of the corresponding output port based on the queue designation information added to the frame data. Yes.
The speed converters 23 and 24 are provided for each output port, and according to the function of converting the frame data distributed from the distribution unit 22 into the communication speed of the output port and outputting the same, and the output status of the frame data A function of outputting a reading stop instruction signal to the reading unit 21.
The queue designation information added to the frame data is deleted by the distribution unit 22 or the speed conversion units 23 and 24.

[Recording device]
Next, the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG. FIG. 2 is a block diagram illustrating a configuration of the recording apparatus according to the first embodiment.

  As shown in FIG. 2, the recording device 30 includes, as main circuit units, a data memory 31A, a DRAM access unit 31B, a queue control memory 32, a write control unit 33, a read control unit 34, and a queue use address number memory 35. And an access arbitration unit 36 are provided.

  The data memory 31A is composed of a general DRAM (DRAM chip) having a plurality of row addresses for each bank, and has a function of storing frame data of the queue at the row address corresponding to the queue. doing. Specifically, the data memory 31A may be configured by one or a plurality of DRAM chips to correspond to the queues of each output system. In addition to the configuration in which each output system has one queue, It is also possible to have a plurality of queues in one output system. In this embodiment, the queue corresponds to the row address, and one DRAM chip is shared by a plurality of queues.

The data memory 31A is provided with a plurality of storage areas having unique storage addresses. Each queue is configured by arbitrarily connecting virtual storage areas of a virtual data memory having a virtual storage address equivalent to the storage address of the data memory 31A regardless of whether the virtual storage addresses are continuous / discontinuous or in ascending / descending order. Yes. The virtual storage address is used for managing frame data independent of the actual row address, column address (Column Address), and bank number used for accessing the DRAM, and is used in a virtual memory space. Address information.
FIG. 3 is an example of a storage image of the virtual data memory. Here, an image in the case where the data written from the write control unit 33 is stored for each virtual storage area having a unique virtual storage address ADM (0 to N: N is an integer of 2 or more) is shown. ing.

  At this time, if one frame is longer than the data size for one virtual address, one frame is divided into a plurality of data D in accordance with the data size for one virtual address, and written to a plurality of different virtual storage addresses. For example, in the case of FIG. 3, the virtual storage addresses 0, 1, and 4 store the data P1-1, P1-2, and P1-3 of the queue P1, and the virtual storage addresses 2, 3, and 5 Data P2-1, P2-2, and P2-3 of the queue P2 are stored. The order relation of these data and the correspondence relation with the frame are managed by an address queue management memory described later. When one frame is shorter than the data size of the virtual storage area, the frame data is stored in one virtual storage area.

  The DRAM access unit 31B, in response to a DRAM write instruction from the write control unit 33, writes frame data to the write target row address corresponding to the write target queue in the data memory 31A, and the read control unit 34. Has a function of reading frame data from a write target row address corresponding to a read target queue in the data memory 31A in accordance with a DRAM read instruction from the.

  When writing the frame data, the DRAM access unit 31B selects the bank in which the write target row address corresponding to the write target queue is activated among the banks of the DRAM as the write target bank, and writes the frame data. If there is no bank in which the function and the write target row address are activated, the bank in which the write target row address is deactivated is selected as the write target bank. A function of writing frame data after activating the address.

  The DRAM access unit 31B also stores a write target bank as a bank corresponding to the designated virtual storage address when writing the frame data, and corresponds to the designated virtual storage address when reading the frame data. A function for identifying a bank to be read from a bank and, when a read target row address corresponding to a read target queue is in an activated state in the read target bank, frame data is read from the read target row address of the read target bank; When the read target bank is not in the read target row address activated state, the read target row address of the read target bank is activated and then the frame data is read.

The queue control memory 32 is composed of a semiconductor memory such as an SRAM chip, for example, and has a function of storing various queue control information used when controlling writing / reading of frame data to / from each queue formed on the data memory 31A. Have.
The queue control memory 32 includes a plurality of storage units composed of registers and memories. The main storage units include a free address register (VAR, UAR) 32A, an address queue management memory (QM) 32B, and a queue head / end address. A memory (SAR, LAR) 32C and a work address register (TMPV, TMPL) 32D are provided. In the following description, register names are sometimes used as variable names for easy understanding.

  The empty address register (VAR, UAR) 32A has a function of storing the next write address VAR and the unwritten address UAR in common to each queue. Among them, VAR (Valid Address Register) is address information indicating a virtual storage address to which the frame data is to be written next when the frame data received from the multiplexing apparatus 10 is written next. UAR (Unused Address Register) is a storage address indicating the head (young number) of unused virtual storage addresses to which no data has been written yet after initialization.

  In this embodiment, when writing frame data, the virtual storage addresses are basically used in order from the youngest. For virtual storage addresses that have become empty due to reading of frame data, the unused virtual storage addresses are used. It shall be reused with priority. The order of the virtual storage addresses to be reused may be any order, for example, the virtual storage addresses that have recently become empty, and may be reused in order, and is not limited to the lowest number.

The address queue management memory (QM) 32B has a function of storing a subsequent virtual address ADD (ADDress) and a pointer PN (Pointer of QM) for each virtual storage address ADM.
FIG. 4 is a storage example of the address queue management memory. Among these, ADD is a virtual storage address in which communication data subsequent to the communication data written to the virtual storage address is stored. PN is information (frame end flag: EoF) indicating whether or not the data stored at the virtual storage address includes the final data of the frame data.

The queue head / last address memory (SAR, LAR) 32C has a function of storing a queue head address SAR (Start Address register of PM) and a queue last address LAR (Last Address register of PM) for each queue. .
FIG. 5 shows a storage example of the queue head / end address memory. Here, SAR and LAR are stored for each queue ID (queue number) for identifying the queue. Among these, the SAR is address information indicating the head of the virtual storage address where the frame data of the queue is written. LAR is address information indicating the final virtual storage address in which the frame data of the queue is written.

The work address register (TMPV, TMPL) 32D has a function of storing a work next write address TMPV (Temporary register for VAR) and a work queue final address TMPL (Temporary register for LAR) in common with each queue. Have.
Among these, TMPV is address information indicating the next write address VAR of the queue in which writing / reading was performed immediately before. TMPL is address information indicating the queue final address LAR immediately before (before update) the queue in which writing was last performed. These are used to temporarily hold address information because of the processing procedure of each data write / read operation, but may also be used for the next write / read operation.

  The write control unit 33 writes the frame data in which the write target queue and the virtual storage address (TMPV) are specified based on the queue control information in the queue control memory 32 in accordance with the write instruction from the access arbitration unit 36. Has a function of outputting a DRAM write instruction for instructing to the DRAM access unit 31B.

  The read control unit 34 specifies the read target queue and the virtual storage address (SAR) based on the queue control information in the queue control memory 32 according to the read instruction from the access arbitration unit 36, and starts the head from the read target queue. It has a function of outputting a DRAM read instruction for instructing reading of data to the DRAM access unit 31B and a function of transferring the data to the demultiplexing device 20 together with a frame end flag and queue designation information.

The queue use address number memory 35 includes a semiconductor memory such as an SRAM chip, for example, and stores the virtual address number NK used by the frame data stored in the queue for each queue, and the demultiplexer 20. And a function of outputting the number NK of virtual addresses in the designated queue in response to a request from the access arbitration unit 36.
FIG. 6 is a storage example of the queue use address number memory. Here, for each queue ID (queue number) for identifying a queue, the number NK of virtual addresses of the queue is stored.

  The access arbitration unit 36 receives the frame data transferred from the multiplexer 10 and divides the frame data into a plurality of data D with a data size of one virtual address based on the frame length information added to the frame data. The function of calculating the number of times of writing by this, and writing to the write target queue designated by the queue designation information added to the frame data for each data D by the number of times of writing is instructed. A function of outputting a write instruction to the write control unit 33 and a function of adding the number of virtual addresses increased by writing the frame data to the number of virtual addresses NK of the write target queue in the queue use address number memory 35. Have.

  Further, in response to a read request from the demultiplexer 20, the access arbitration unit 36 divides the data amount specified by the read data amount information of the read request by the data size for one virtual address, thereby reducing the number of reads. A function for calculating, a function for outputting to the read control unit 34 a read instruction for instructing reading of frame data from the read target queue designated by the queue designation information of the read request, and the frame data Read out at a readable timing by arbitrating the conflict between the function of subtracting the number of virtual addresses that are reduced by reading from the virtual address number NK of the write target queue in the queue use address number memory 35 and the writing of frame data. And a function of outputting instructions.

[DRAM access section]
Next, the DRAM access unit 31B used in the recording apparatus 30 according to the present embodiment will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of the DRAM access unit according to the first embodiment.
The DRAM access unit 31B includes, as main circuit units, a FIFO memory 51, an activation processing unit 52, an access type determination unit 53, a bank management memory 54, an address management memory 55, a DRAM writing unit 56, and a DRAM reading unit 57. Is provided.

  The FIFO memory 51 is composed of a general FIFO memory. The FIFO memory 51 has a function of storing a DRAM write instruction from the write control unit 33 and a DRAM read instruction from the read control unit 34 in a mixed manner, and a row by the activation processing unit 52. After the address activation is completed, it has a function of reading the accumulated DRAM write instruction or DRAM read instruction in the order of input and outputting it to the access type determination unit 53. At this time, as information for determining the access type, information indicating whether it is a DRAM write instruction from the write control unit 33 or a DRAM read instruction from the read control unit 34 is combined with each instruction. The information may also be output to the access type determination unit 53 by writing into the FIFO memory 51.

  When the access arbitration unit 36 shown in FIG. 21 is used, the DRAM write instruction from the write control unit 33 and the DRAM read instruction from the read control unit 34 should not be input at the same time. Are simultaneously input, the writing of the DRAM writing instruction to the FIFO memory 51 may be prioritized and the writing of the DRAM reading instruction to the FIFO memory 51 may be waited.

  When the DRAM write instruction is stored in the FIFO memory 51, the activation processing unit 52 activates the write target row address corresponding to the write target queue specified by the DRAM write instruction in the bank of the DRAM. A function for selecting a bank in a state as a write target bank and, if the write target bank is not writable, selects another bank whose write target row address is in an activated state as a new write target bank If there is no function and a bank in which the write target row address is activated, and there is no writable bank in which the write target row address is activated, the write target row address is A function to select a bank in an inactive state as a write target bank and activate the write target row address.

At this time, when selecting the write target bank, not only the presence / absence of an empty area, but also the bank in which the data related to the write target queue exists in the write target row address of the write target bank You may make it select as.
In addition, with regard to whether or not writing to each bank is possible, for example, in the bank management memory 54, write enable / disable information indicating whether or not write is possible is stored for each bank, and write enable / disable is determined based on this write enable / disable information. You may do it.

  In the bank management memory 54, when writable information is stored for each bank (for each queue designation information), the initial value of the writable information is writable. For example, the updated write pointer value WP corresponds to When the read pointer value RP is the same as the read pointer value RP, writing is disabled (no free area). In addition, it is only necessary to enable writing when data is read in the write disabled state and the read pointer value RP is updated to a value different from the write pointer value WP.

  In addition, when the DRAM read instruction is accumulated in the FIFO memory 51, the activation processing unit 52 specifies a read target bank corresponding to the virtual storage address specified by the DRAM read instruction by the address management memory 55, and When the read target row address corresponding to the read target queue designated by the DRAM read instruction in the read target bank is not activated, the function of activating the read target row address in the read target bank, and the read target When a row address different from the read target row address is in the activated state in the bank, the read target row address is activated in response to the completion of access to the row address.

  The access type determination unit 53 distributes the DRAM write instruction output from the FIFO memory 51 to the DRAM write unit 56 and distributes the DRAM read instruction output from the FIFO memory 51 to the DRAM read unit 57. It has a function to output.

  The bank management memory 54 is composed of a semiconductor memory such as an SRAM chip, for example, and stores a write pointer value WP that is used as a column address when writing communication data of the queue into the bank for each combination of the queue and the bank. And a function of storing a read pointer value RP used as a column address when reading communication data of the queue from the bank for each combination of the queue and the bank.

  FIG. 8 shows a storage example of the bank management memory. Here, a write pointer value WP and a read pointer value RP are stored for each combination of a queue ID (queue number) for identifying a queue and a bank number for identifying a bank. It is assumed that the initial value of the write pointer value WP and the read pointer value RP are the same value.

  For example, in the queue P2, in the bank # 0, the write pointer value is WP2 # 0, and when the bank # 0 is the write target bank, the new frame data in the queue P2 is stored in the column address indicated by the WP2 # 0. Will be written. In the queue P2, the read pointer value is RP2 # 1 in the bank # 1, and when the bank # 1 is the read target bank, the frame data in the queue P2 is read from the column address indicated by the RP2 # 1. Become.

The address management memory 55 is composed of a semiconductor memory such as an SRAM chip, for example, and has a function of storing a bank number of a bank in which frame data corresponding to the virtual storage address is written for each virtual storage address.
FIG. 9 is a storage example of the address management memory. Here, for each virtual storage address ADM, the bank number of the bank in which the frame data associated with the virtual storage address is written is stored. For example, the frame data associated with the virtual storage address “2” is written in the bank number “# 1”, and when reading the frame data, the bank corresponding to this bank number becomes the bank to be read.

  The DRAM writing unit 56 has a function of acquiring a write pointer value WP from the bank management memory 54 based on a combination of a write target row address and a write target bank in the input DRAM write instruction, and a write target A function for writing frame data (data D) designated by a DRAM write instruction to a column address consisting of a write pointer value WP, among the write target row addresses of a bank, and a data length corresponding to one virtual storage address The write target bank is written as the bank of the virtual storage address designated by the DRAM write instruction in the address management memory 55 and the function of updating the write pointer value WP in the bank management memory 54 by the pointer value to be It has a function.

At this time, if a plurality of column addresses are required for writing frame data (data D) for one storage address, the burst mode, which is a function of the DRAM, is used to write to consecutive column addresses. The writing time can be shortened.
Further, when the EoF value (PN) is also written to the data memory 31A, it may be performed simultaneously with the writing of the frame data.

  The DRAM reading unit 57 has a function of acquiring the read pointer value RP from the bank management memory 54 based on the combination of the read target row address and the read target bank in the input DRAM read instruction, and the read target row address of the read target bank. Of these, only the function of reading frame data (data D) from the column address consisting of the read pointer value RP and outputting it to the read control unit 34 together with the queue designation information, and the pointer value corresponding to the data length of one virtual storage address. And a function of updating the read pointer value RP in the bank management memory 54.

At this time, when a plurality of column addresses are required for reading frame data (data D) for one virtual storage address, reading is performed from successive column addresses using the burst mode which is a function of the DRAM. The time required for reading can be shortened.
When the EoF value (PN) is written in the data memory 31A, the EoF value may be read simultaneously with the reading of the frame data.

  The read EoF value may be output to the read control unit 34 together with the frame data and the queue designation information. If the EoF value is not written in the data memory 31A, the EoF value is written in the address queue management memory (QM) 32B, and the read control unit 34 outputs this EoF value together with the queue designation information to the DRAM access unit 31B. The EoF value received via the address type determination unit 53 may be output to the read control unit 34 together with the frame data read from the data memory 31A by the DRAM reading unit 57.

[Operation of First Embodiment]
Next, the operation of the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described with reference to FIGS.
FIG. 10 is an explanatory diagram showing a write operation in the write control unit. FIG. 11 is an explanatory diagram showing a read operation in the read control unit.

[Write operation]
First, a writing operation in the writing control unit 33 of the recording device 30 will be described with reference to FIG.
The write control unit 33 executes the processing operation of FIG. 10 in response to a write instruction from the access arbitration unit 36. When new data is written to the write target queue, from the viewpoint of sharing the storage address of the data memory 31A by each queue, the main change in the queue control information is that the queue related to the write target queue before and after the write. The final address LAR, the subsequent virtual address ADD related to the queue final address before writing, and the next write address VAR common to each queue are changed. In the case of the first writing to the write target queue, the queue head address SAR regarding the write target queue also changes.

  For this reason, in the processing operation of FIG. 10, the write control unit 33 writes the specified data to the next write address VAR (outputs the write instruction), updates the queue final address LAR related to the write target queue, The subsequent virtual address ADD related to the queue final address is updated, and the next write address VAR common to each queue is updated. In the case of the first writing to the write target queue, the queue head address related to the write target queue is also updated. Details of these updates will be described later based on an operation example.

  At this time, the write control unit 33 accesses the queue control memory 32 to execute steps W1 to W7 shown in FIG. That is, in the order of LAR retention (W1), LAR, SAR update (W2), VAR retention (W3), ADD update (W4), VAR update (W5), PN update (W6), and data output (W7). Execute the process. In addition, although the processing order of FIG. 10 considers processing efficiency, another processing order may be sufficient.

[Read operation]
Next, with reference to FIG. 11, a reading operation in the reading control unit 34 of the recording apparatus 30 will be described.
The read control unit 34 executes the processing operation of FIG. 11 in response to a read instruction from the access arbitration unit 36. When new data is read from the read target queue, from the viewpoint of sharing the storage address of the data memory 31A by each queue, the main change in the queue control information is that the queue head address related to the read target queue before and after the read. The SAR, the next write address VAR common to each queue, and the subsequent virtual address ADD relating to the new next write address VAR change.

  Therefore, in the processing operation of FIG. 11, the read control unit 34 reads the EoF (End of Frame: frame end flag) for the queue head address SAR related to the read target queue, updates the queue head address SAR related to the read target queue, The next write address VAR common to the queue is updated, the subsequent virtual address ADD related to the read virtual storage address is updated, and a read instruction is output. Details of these updates will be described later based on an operation example.

  At this time, the read control unit 34 accesses the queue control memory 32 to execute steps R1 to R5 shown in FIG. That is, processing is executed in the order of EoF output (R1), VAR retention (R2), VAR update (R3), SAR update (R4), subsequent virtual address update (R5), and read instruction output. In addition, although the processing order of FIG. 11 considers processing efficiency, another processing order may be sufficient.

[Operation example]
Next, referring to FIG. 12 to FIG. 18, for the frame data writing operation and reading operation in recording apparatus 30, queue P2 is set as a read / write target queue, and data P2-3 is written to this queue P2. An example will be described in which the data P2-1 and P2-2 are read and then the data P2-4 is written.

  FIG. 12 is an explanatory diagram showing queue control information immediately before reading data P2-1 (immediately after writing data P2-3). Here, queue control information immediately before reading data P2-1, that is, immediately after writing data P2-3 is shown. In this state, the data P1-1, P1-2, and P1-3 of the queue P1 are written in the virtual storage address “0, 1, 4” in the virtual data memory, and the virtual storage addresses “2, 3, 4” are stored. 5 "is written data P2-1, P2-2, P2-3 of the queue P2. The virtual storage addresses “6 to N” are unused.

  Therefore, the next write address VAR is “6”, and the unwritten address UAR is also “6”. Further, the subsequent virtual address ADD related to the virtual storage address “0, 1” becomes “1, 4” according to the order of the data P1-1, P1-2, P1-3 of the queue P1, and the data P2- of the queue P2 The subsequent virtual address ADD relating to the virtual storage address “2, 3” is “3, 5” in accordance with the order of 1, P2-2 and P2-3. The pointer PN of the virtual storage address “0, 2” is “0”, and it can be seen that the data P1-1 and P2-1 do not include the end of the frame.

  Further, the queue head address SAR of the queue P1 indicates the virtual storage address “0” of the data P1-1, and the queue final address LAR indicates the virtual storage address “4” of the data P1-3. Further, the queue head address SAR of the queue P2 indicates the virtual storage address “2” of the data P2-1, and the queue final address LAR indicates the virtual storage address “5” of the data P2-3. Note that “5” and “3” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

  In the state shown in FIG. 12, when the data P2-1 in the queue P2 is read, the queue control information changes as shown in FIG. FIG. 13 is an explanatory diagram showing changes in queue control information when reading data P2-1.

  First, as shown in FIG. 13A, the data P2-1 is read from the read target virtual address “2” indicated by the queue head address SAR regarding the queue P2, and therefore the data D of the read target virtual address “2” is empty. The data regarding the queue P2 becomes two, P2-2 and P2-3. As a result, as shown in FIG. 13B, P2-2 becomes the head data of the queue P2, and the queue head position changes from the virtual storage address “2” to “3”, so the queue head address SAR regarding the queue P2 is changed. Is updated from “2” to “3”.

  Further, since the data D of the read target virtual address “2” is in an empty state, as shown in FIG. 13C, this virtual storage address “2” becomes the writing position of the next data. As a result, the next write address VAR is updated from “6” to “2”. Accordingly, in order to maintain the order relationship between the old primary write address VAR “6” and the new primary write address VAR “2”, the virtual storage address “2” as shown in FIG. Is updated from “3” to “6”.

  As a result, the queue control information changes to the state shown in FIG. FIG. 14 is an explanatory diagram showing queue control information immediately after reading data P2-1 (just before reading data P2-2). Note that “6” and “3” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

  In the state shown in FIG. 14, when the data P2-2 in the queue P2 is read, the queue control information changes as shown in FIG. FIG. 15 is an explanatory diagram showing changes in queue control information at the time of reading data P2-2.

  First, as shown in FIG. 15A, the data P2-2 is read from the read target virtual address “3” indicated by the queue head address SAR regarding the queue P2, and therefore the data D of the read target virtual address “3” is empty. The data regarding the queue P2 becomes one of P2-3. As a result, as shown in FIG. 15B, P2-3 becomes the head data of the queue P2, and the queue head position changes from the virtual storage address “3” to “5”. Therefore, the queue head address SAR regarding the queue P2 is changed. Is updated from “3” to “5”.

  Further, since the data D of the read target virtual address “3” is in an empty state, as shown in FIG. 15C, this virtual storage address “3” becomes a writing position of the next data. As a result, the next write address VAR is updated from “2” to “3”. Accordingly, in order to maintain the order relationship between the old next write address VAR “2” and the new next write address VAR “3”, as shown in FIG. The subsequent virtual address ADD of “5” is updated from “5” to “2”.

  As a result, the queue control information changes to the state shown in FIG. FIG. 16 is an explanatory diagram showing queue control information immediately after reading data P2-2 (just before writing data P2-4). Note that “2” and “3” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

  In the state shown in FIG. 16, when the data P2-4 of the queue P2 is written, the queue control information changes as shown in FIG. FIG. 17 is an explanatory diagram showing a change in queue control information when writing data P2-4.

  First, as shown in FIG. 17A, since the data P2-4 is written to the write target virtual address “3” indicated by the next write address VAR, as shown in FIG. Becomes the new final data of the queue P2, and the queue final position changes from the virtual storage address “5” to “3”, so the queue final address LAR of the queue P2 is updated from “5” to “3”.

In addition, since P2-4 follows P2-3 which was the queue final data before writing, as shown in FIG. 17C, the succeeding virtual of the virtual storage address “5” of P2-3 The virtual storage address “3” of P2-4 is set as the address.
Since P2-4 is written to the next write address VAR before writing, as shown in FIG. 17D, the next write address VAR is changed from “3” to the subsequent virtual address “3”. The address is updated to “2”.

  As a result, the queue control information changes to the state shown in FIG. FIG. 18 is an explanatory diagram showing the queue control information immediately after the data P2-4 is written. Note that “3” and “5” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

[DRAM write operation]
Next, with reference to FIG. 19, a DRAM write operation in the DRAM access unit 31B according to the present embodiment will be described. FIG. 19 is a flowchart showing the DRAM write processing according to the first embodiment.
The DRAM access unit 31B executes the DRAM write process of FIG. 19 in response to a DRAM write instruction from the write control unit 33.

First, the activation processing unit 52 specifies a write target row address corresponding to the write target queue specified by the DRAM write instruction stored in the FIFO memory 51 (step 100), and the write target row address is determined. The presence / absence of an activated bank is confirmed (step 101).
Here, when there is a bank in which the write target row address is in an activated state (step 101: YES), the activation processing unit 52 confirms whether or not writing is possible for the write target row address of the bank (step 101). 102) When there is an empty area in the write target row address and writing is possible (step 102: YES), the bank is set as a write target bank in the DRAM write instruction (step 103), and the activation process is performed. Complete.

After completing the activation processing in the activation processing unit 52, a DRAM write instruction is output from the FIFO memory 51 and input to the DRAM writing unit 56 via the access type determination unit 53.
The DRAM writing unit 56 acquires the corresponding write pointer value WP from the bank management memory 54 based on the combination of the write target row address corresponding to the input DRAM write instruction and the write target bank (step 104) The frame data (data D) designated by the DRAM write instruction is written to the column address consisting of the write pointer value WP among the write target row addresses of the write target bank (step 105).

  Thereafter, the DRAM writing unit 56 updates the write pointer value WP in the bank management memory 54 by the pointer value corresponding to the data length for one virtual storage address (step 106), and the address management memory 55. Among them, the bank to be written is stored as the bank of the virtual storage address designated by the DRAM write instruction (step 107), and the series of DRAM write processing is completed.

In step 102, if there is no empty area in the write target row address and writing is not possible (step 102: NO), the activation processing unit 52 selects another bank in which the write target row address is in the activated state. Is confirmed (step 110).
Here, when there is another bank in which the write target row address is in an activated state (step 110: YES), the activation processing unit 52 returns to step 102 and performs writing in the bank as described above. Check availability.

  When there is no other bank in which the write target row address is in an activated state (step 110: NO), the activation processing unit 52 selects any bank in which the write target row address is in an inactivated state. Is selected (step 111), the write target row address is activated in the bank (step 112), the process proceeds to step 103, and the DRAM write instruction is set as the write target bank (step 103). Complete the activation process.

  In step 101, when there is no bank in which the write target row address is in an activated state (step 101: NO), the activation processing unit 52 proceeds to step 110 and performs the write target as described above. A bank whose row address is in an inactive state is activated.

  Therefore, when writing frame data to the DRAM constituting the data memory 31A, the bank in which the write target row address is activated is preferentially selected as the write target bank from among the banks of the DRAM. This reduces the probability that writing to different row addresses in the same bank will occur. For this reason, the number of times of waiting for the activation of the row address at the time of writing the frame data and the completion of the access to the different row address is reduced, and the decrease in the effective throughput of the DRAM access is suppressed.

[DRAM read operation]
Next, with reference to FIG. 20, a DRAM read operation in the DRAM access unit 31B according to the present embodiment will be described. FIG. 20 is a flowchart showing the DRAM read processing according to the first embodiment.
The DRAM access unit 31B executes the DRAM read process of FIG. 20 in response to a DRAM read instruction from the read control unit 34.

First, the activation processing unit 52 specifies a read target row address corresponding to the read target queue specified by the DRAM read instruction stored in the FIFO memory 51 (step 150), and reads the read target row from the address management memory 55. A read target bank corresponding to the address is acquired (step 151).
Next, the activation processing unit 52 confirms whether or not the read target row address is in the activated state in the read target bank (step 152). If the read target row address is in the activated state (step 152: YES), Complete the activation process.

After completing the activation process in the activation processing unit 52, a DRAM read instruction is output from the FIFO memory 51 and input to the DRAM read unit 57 via the access type determination unit 53.
The DRAM read unit 57 acquires the corresponding read pointer value RP from the bank management memory 54 based on the combination of the read target row address corresponding to the input DRAM read instruction and the read target bank (step 153).

  Thereafter, the DRAM reading unit 57 reads frame data (data D) from the column address composed of the read pointer value RP among the read target row addresses of the read target bank (step 154), and data for one virtual storage address. The read pointer value RP in the bank management memory 54 is updated by the pointer value corresponding to the length (step 155), and a series of DRAM read processing ends.

In step 152, if the read target row address of the read target bank is not activated (step 152: NO), the activation processing unit 52 confirms whether a different row address is activated in the read target bank. (Step 156).
Here, when a different row address is not in the activated state (step 156: NO), the activation processing unit 52 activates the read target row address of the read target bank (step 157) and completes the activation process. As a result, the DRAM reading unit 57 performs reading from the activated read target row address.

  In step 156, if a different row address is in an activated state (step 156: YES), the activation processing unit 52 waits until access to the different row address is completed (step 158), and then step 157. Then, the read target row address is activated as described above.

  As described above, when reading frame data from the DRAM constituting the data memory 31A, since the frame data to be read is written in a specific bank, the row address is in an activated state as in writing. A bank cannot be selected arbitrarily. Therefore, a waiting time occurs when reading from different row addresses in the same bank or reading from the same bank after writing. For reading from different row addresses in the same bank, a processing interval may be provided so that, for example, writing is inserted between the two row addresses so that reading from different row addresses does not continue.

[Effect of the first embodiment]
As described above, according to the present embodiment, in the recording device 30, the data memory 31A is constituted by a DRAM having a plurality of row addresses for each bank, and the frame data of the queue is stored at the row address corresponding to the queue. When the DRAM access unit 31B writes the frame data to the write target queue, the bank in which the write target row address corresponding to the write target queue is activated is selected as the write target bank. When the frame data is written and there is no bank in which the write target row address is activated, the bank in which the write target row address is inactivated is selected as the write target bank and The frame data is written after the target row address is activated.

  In general, in a DRAM, when writing data to an arbitrary row address of an arbitrary bank, it is necessary to activate the row address in the bank. When accessing a different row address of the same bank, the row address is Since it is necessary to activate a new row address after waiting for the used access to be completed, a relatively large waiting time occurs due to the activation of the row address in accessing the same bank. Specifically, this is a case where accesses to different row addresses in the same bank are continuous. As other conditions for waiting time, there are a case where writing is performed in the same bank after reading and a case where reading is performed from the same bank after writing.

According to the present embodiment, when writing frame data to the DRAM constituting the data memory 31A, the bank in which the write target row address is activated is preferentially set as the write target bank among the banks of the DRAM. Selected.
This can reduce the probability of writing to different row addresses in the same bank. Therefore, it is possible to reduce the number of times of waiting for the activation of the row address at the time of writing the frame data and the completion of the access to the different row address, and it is possible to suppress the decrease in the effective throughput related to the DRAM access.

  In particular, in communication input / output devices, short frame data may be input continuously in bursts. According to the present invention, individual row addresses are assigned to the queues of the respective output systems. Therefore, in such a case, writing to the same row address is repeatedly performed, and the number of times of activation due to the change of the row address can be reduced. Therefore, even in such a case, since it is possible to suppress a decrease in effective throughput related to DRAM access, it is possible to sufficiently follow the processing speed of frame data and to reduce deterioration in communication quality.

  In the present embodiment, the bank access memory 54 stores a write pointer value used as a column address when writing the communication data of the queue to the bank for each combination of the queue and the bank in the DRAM access unit 31B. When the communication data is written, the write pointer value corresponding to the combination of the write target row address and the write target bank is acquired from the bank management memory 54, and the write target row address of the write target bank is acquired. Of these, the communication data may be written to a column address consisting of the write pointer value.

  As a result, even when individual row addresses are assigned to the queues of each output system, a plurality of queues can share each bank, and the row address is activated when writing frame data to an arbitrary queue. Regardless of which bank in the state is selected, the column address to be used in the bank can be specified very quickly, and the effective throughput of DRAM access can be improved.

  In the present embodiment, the recording device 30 stores, for each virtual storage address, a subsequent address indicating a virtual storage address of communication data subsequent to the communication data written to the virtual storage address, and for each queue, Stores the queue head address and queue end address indicating the beginning and end of the virtual storage address where the communication data of the queue is written, and the next indicates the virtual storage address where the communication data is to be written next in common for each queue. The write address may be stored.

  In addition to this, when the write control unit 33 writes communication data to the write target queue (performs a write instruction), the write control unit 33 writes the communication data to the write target virtual address including the next write address. When the read control unit 34 reads communication data from the read target queue (performs a read instruction) by updating the queue final address of the target queue, the subsequent virtual address related to the queue final address before writing, and the next write address, respectively. The communication data is read from the read target virtual address consisting of the queue start address of the read target queue, and the subsequent virtual address relating to the queue start address, the next write address, and the new next write address of the read target queue is updated. You may make it do.

  As a result, the frame data of each queue is sequentially written to the virtual storage address in the free state, and the virtual storage address from which the frame data has been read out is managed again as a free state. Further, the virtual storage address of the frame data is managed in the order of writing for each queue. A virtual storage address in an empty state can be shared by a plurality of queues, and the use efficiency of the memory can be improved as compared with a case where a fixed address range is secured in advance for each conventional queue. It becomes possible. For this reason, it is not necessary to increase the memory capacity, and as a result, an increase in circuit scale and cost can be suppressed.

In addition, this embodiment has a feature that it is not necessary to set an initial value such as an ADD value in the QM. In the present embodiment, only the VAR and UAR need to set initial values when the communication input / output device is activated (see “Initialization” in FIG. 10). Therefore, the scale of the circuit for performing the initial setting or the scale of the software for performing the initial setting is extremely small, and the time required for the initial setting is extremely small.
In FIG. 12 and the like, the case where the PN for storing the EoF value is mounted in the QM is illustrated, but the PN can also be mounted in the DRAM.

[Second Embodiment]
Next, a communication input / output device 1 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 21 is a block diagram illustrating a configuration of an access arbitration unit according to the second embodiment.

  In the communication input / output device 1 according to the first embodiment, when the virtual storage address of the virtual data memory is shared by a plurality of queues, for example, a large amount of frame data related to a specific output system is input. In this case, the virtual storage address of the virtual data memory may be occupied by the queue of the output system. Such occupation of the storage address is not limited to the first embodiment, and can occur in any configuration as long as the storage address is shared by a plurality of queues. Therefore, when such a storage address occupancy occurs, the queues of other output systems cannot use a sufficient number of storage addresses, frame data is easily discarded, and communication quality deteriorates.

  The purpose of this embodiment is to avoid occupying a storage address by a specific queue when such storage addresses are shared by a plurality of queues. In the recording apparatus 30, the access arbitration unit 36 has a write target queue. When the frame data is written into (instructed to write), the necessary address number indicating the number of virtual storage addresses required for writing is calculated based on the data length of the frame data and obtained from the queue use address number memory 35 Calculate the number of remaining addresses indicating the number of virtual storage addresses that can be used for writing based on the number of virtual addresses used for the write target queue or each queue, and compare the required number of addresses with the number of remaining addresses To determine whether or not the frame data can be written. Te is obtained so as to direct the writing of the frame data.

  As shown in FIG. 21, in this embodiment, the access arbitration unit 36 includes, as main circuit units, a write enable / disable determination unit 41, a write FIFO 42, a read reception unit 43, a read FIFO 44, and a priority control unit. 45, a queue use address number updating unit 46, and an instruction output unit 47 are provided.

  The write enable / disable determining unit 41 includes queue designation information and frame length information added to the frame data transferred from the multiplexing device 10, determination address number information set in advance for each queue, Based on the number of used virtual addresses, the function for determining whether or not writing is possible and the frame data corresponding to one virtual address of the storage area provided in the data memory 31A according to the determination result of writing enable And a write instruction in which queue designation information is added to the obtained data, respectively, is written into the write FIFO 42.

The determination address number information includes the maximum number of virtual addresses NKmax that can be used in the write target queue specified by the queue specification information, and the minimum guaranteed virtual address number that is guaranteed to be used for the write target queue. NKmin.
FIG. 22 is a configuration example of the determination address number information. Here, a maximum virtual address number NKmax and a minimum guaranteed virtual address number NKmin are set for each queue ID for identifying a queue. The determination address number information is stored in, for example, an internal memory (not shown) of the queue use address number update unit 46 or the access arbitration unit 36.

  The read receiving unit 43 calculates the number of reads to the data memory 31A based on the read data amount information of the read request output from the multiplexer / demultiplexer 20, and uses the queue designation information of the read request as a read instruction for the number of read times. It has a function of writing to the read FIFO 44. In this calculation, a value obtained by dividing the data amount indicated by the read data amount information by the data size per virtual address of the data memory 31A is used as the number of readings, and if there is a remainder, 1 may be added to the number of readings.

  The priority control unit 45 reads a write instruction or a read instruction from the write FIFO 42 or the read FIFO 44 and outputs it to the queue use address number update unit 46, and both the write FIFO 42 and the read FIFO 44 In the case where there are a write instruction and a read instruction, it has a function of preferentially reading the write instruction from the write FIFO 42.

  When a write instruction is input from the priority control unit 45, the queue use address number update unit 46 uses the virtual address of the write target queue corresponding to the queue designation information of the write instruction in the queue use address number memory 35. The function of adding 1 to the number and outputting the write instruction to the instruction output unit 47, and when a read instruction is input from the priority control unit 45, the queue designation of the read instruction in the queue use address number memory 35 It has a function of subtracting 1 from the number of used virtual addresses of the read target queue corresponding to the information and outputting the read instruction to the instruction output unit 47.

  The instruction output unit 47 outputs a write instruction to the write control unit 33 when a write instruction is input from the queue use address number update unit 46, and the read instruction when a read instruction is input. Is output to the reading control unit 34.

[Operation of Second Embodiment]
Next, with reference to FIG. 23, a write determination operation at the time of writing frame data will be described as the operation of the access arbitration unit 36 according to the present embodiment. FIG. 23 is a flowchart illustrating a write permission / inhibition determination process according to the second embodiment.
The access arbitration unit 36 of the recording device 30 determines whether or not writing is possible for each frame data transferred from the multiplexing device 10 based on the writeability determination processing in FIG.

  First, the access arbitration unit 36 acquires the used virtual address number NK for all the queues from the queue used address number memory 35 (step 200), and calculates the total virtual address number NKA used by all the queues (step 201). ) The required virtual address number NF required for writing the target frame data to be written is calculated (step 202).

Thereafter, by subtracting NKA from the total address number NA of the virtual storage addresses of the virtual data memory, a remaining address number NR indicating the number of virtual storage addresses that can be used for writing the target frame data is calculated (step 203). NF and NR are compared (step 204).
Here, if NF> NR (step 204: YES), the access arbitration unit 36 determines that writing is not possible, discards the target frame data (step 213), and ends the write determination processing for the target frame data. To do.

On the other hand, when NF ≦ NR (step 204: NO), the access arbitration unit 36 obtains the maximum virtual address number NKmax of the designated write target queue from the queue use address number memory 35 or the like (step 205), The remaining address number NR is calculated by subtracting NK from NKmax (step 206), and NF and NR are compared (step 207).
Here, if NF> NR (step 207: YES), the access arbitration unit 36 determines that writing is not possible, discards the target frame data (step 213), and ends the write determination processing for the target frame data. To do.

  On the other hand, when NF ≦ NR (step 207: NO), the access arbitration unit 36 acquires the minimum guaranteed virtual address number NKmin for all the queues from the queue use address number memory 35 (step 208), and collects all the queues collectively. The total guaranteed virtual address number NAmin to be guaranteed at least is calculated (step 209). At this time, if the queue use virtual address number NK of an arbitrary queue is equal to or greater than the minimum guaranteed virtual address number, the queue use virtual address number NK is added as the guaranteed virtual address number of the queue, and the queue use virtual address number NK Is less than the minimum guaranteed virtual address number, the minimum guaranteed virtual address number NKmin is added as the guaranteed virtual address number of the queue.

Thereafter, the access arbitration unit 36 calculates the remaining address number NR by subtracting NAmin from NA (step 210), and compares NF and NR (step 211).
Here, when NF> NR (step 211: YES), the access arbitration unit 36 determines that writing is not possible, discards the target frame data (step 213), and terminates the write determination processing related to the target frame data. To do.

On the other hand, when NF ≦ NR (step 211: NO), the access arbitration unit 36 determines that the target frame data can be written (step 212), and ends the write determination process for the target frame data.
Thereafter, the access arbitration unit 36 divides the target frame data into data sizes corresponding to one virtual address according to the determination of whether or not writing is possible, and issues a write instruction in which queue designation information is added to the obtained data, respectively. The data is written in the write FIFO 42.

[Effect of the second embodiment]
As described above, according to the present embodiment, in the recording apparatus 30, the queue use address number memory 35 stores the use address number indicating the number of virtual storage addresses used by the queue for each queue. When the unit 36 writes communication data to the write target queue (performs a write instruction), the unit 36 calculates the required number of addresses indicating the number of virtual storage addresses required for writing based on the data length of the communication data. Based on the number of used virtual addresses of the write target queue or each queue acquired from the used address number memory 35, the number of remaining addresses indicating the number of virtual storage addresses that can be used for the write is calculated, and the required number of addresses and Whether the communication data can be written is determined by comparing the number of remaining addresses, and the write control unit 3 determines whether the communication data can be written. It is obtained so as to direct the writing of the communication data to.

  Therefore, since the number of virtual storage addresses used by each queue is limited, occupation of the virtual storage address by a queue corresponding to an arbitrary output system can be suppressed. For this reason, even when a large amount of frame data related to a specific output system is input, it is possible for the queues of other output systems to use a sufficient number of virtual storage addresses. As a result, it becomes possible to suppress the discarding of frame data and the deterioration of communication quality due to this, and as a countermeasure, it is not necessary to increase the memory capacity, and as a result, the increase in circuit scale and cost is suppressed. Is possible.

Note that NKA and NAmin in the present embodiment can be calculated (added, subtracted, etc.) simultaneously when updating the queue use address number memory.
In the present embodiment, when the access arbitration unit configured as shown in FIG. 21 is used, it may be erroneously determined that writing is possible if write instruction data exists in the write FIFO. In order to prevent erroneous determination, use a value obtained by adding the number of virtual addresses in the write FIFO (the number of write instructions) to the information of the queue used address number memory as the used virtual address number of each queue, A value obtained by subtracting the number of virtual addresses (the number of write instructions) in the write FIFO may be used as NA or NKmax.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

In each of the above embodiments, when the communication input / output device 1 processes a multicast frame, a multicast output system is provided as one of the output systems, and a plurality of multicast frames are provided in the distribution unit 22 in the demultiplexer 20. It is also possible to provide a means for outputting to the speed converter 23 and to allocate a part of the queues logically formed in the data memory of the recording device 30 as a queue corresponding to this multicast output system.
As a result, a multicast frame input from the outside to the multiplexing device 10 is temporarily stored in a queue corresponding to the multicast output system in the data memory, and a plurality of multicast frames are read from the queue by the demultiplexing device 20. Output from the output port.

  DESCRIPTION OF SYMBOLS 1 ... Communication input / output device, 10 ... Multiplexer, 11 ... Queue designation information addition part, 12 ... Multiplexing part, 20 ... Demultiplexing device, 21 ... Reading part, 22 ... Distribution part, 23, 24 ... Speed Conversion unit, 30 ... recording device, 31A ... data memory, 31B ... DRAM access unit, 32 ... queue control memory, 33 ... write control unit, 34 ... read control unit, 35 ... queue usage address number memory, 36 ... access arbitration 41: Write enable / disable determining unit, 42 ... Write FIFO, 43 ... Read acceptance unit, 44 ... Read FIFO, 45 ... Priority control unit, 46 ... Queue use address number update unit, 47 ... Instruction output unit, DESCRIPTION OF SYMBOLS 51 ... FIFO memory, 52 ... Activation processing part, 53 ... Access type determination part, 54 ... Bank management memory, 55 ... Address management memory, 56 ... DRAM writing part, 57 ... DRAM reading part.

Claims (4)

A multiplexing device that multiplexes by adding queue designation information indicating a queue corresponding to an output system to which the communication data is to be output, and the communication data transferred from the multiplexing device. Corresponding to a recording device for temporarily storing in a queue to be written designated by the queue designation information among a plurality of queues logically formed in the data memory, and an output system selected based on the priority control logic among the queues A communication input / output device comprising: a demultiplexer that reads the communication data from the read target queue and converts the communication data into a communication speed of an output port corresponding to the output system;
The recording device includes:
The data memory, which comprises a DRAM having a plurality of row addresses for each bank, stores communication data of the queue at individual row addresses corresponding to the queue,
When writing the communication data to the write target queue, the bank in which the write target row address corresponding to the write target queue is activated among the banks is selected as the write target bank, and the communication data is selected. When there is no bank in which the write target row address is in the activated state, the bank in which the write target row address is in the inactive state is selected as the write target bank, and the write target row address is selected. And a DRAM access section for writing the communication data after activating the communication input / output device. The communication input / output device according to claim 1,
The DRAM access unit
For each combination of the queue and the bank, a bank management memory for storing a write pointer value used as a column address when writing communication data of the queue to the bank,
When writing the communication data, a write pointer value corresponding to a combination of the write target row address and the write target bank is acquired from the bank management memory, and the write target row address of the write target bank is acquired. An input / output device for communication, wherein the communication data is written to a column address consisting of the write pointer value. The communication input / output device according to claim 1 or 2,
The recording device includes:
A queue control memory for storing queue control information used when controlling writing / reading to / from the queue of the data memory;
Based on the queue control information in the queue control memory, said write statement that instructs to write to the DRAM access unit to the target queue write control unit of the communication data transferred from the multiplexer,
A read control unit that instructs the DRAM access unit to read communication data from the read target queue based on queue control information in the queue control memory, and transfers the read communication data to the demultiplexer; ,
The queue control memory stores a subsequent address indicating a virtual storage address of communication data subsequent to the communication data written to the virtual storage address for each virtual storage address used on the virtual data memory, and for each queue , Storing a queue head address and a queue last address indicating the head and end of the virtual storage address in which the communication data of the queue is written, and a virtual storage address to which communication data is to be written next in common to each of the queues Stores the next write address indicating
When writing the communication data to the write target queue, the write control unit instructs the DRAM access unit to write the communication data to the write target virtual address composed of the next write address, and the write target Update the queue last address, the subsequent address for the queue last address before writing, and the next write address,
When reading the communication data from the read target queue, the read control unit instructs the DRAM access unit to read the communication data for the read target virtual address consisting of the queue head address of the read target queue, and Update the subsequent addresses for the queue's head address, next write address, and new next write address,
The DRAM access unit has an address management memory for recording a write target bank corresponding to a write target virtual address in response to a write instruction of the communication data with respect to the write target virtual address. An input / output device for communication, wherein the communication data read instruction is determined by reading a bank corresponding to the read target virtual address from the address management memory. The communication input / output device according to claim 3 ,
The recording device includes:
A queue use address number memory for storing a use address number indicating the number of virtual storage addresses on the virtual data memory used by the queue for each queue;
When writing the communication data to the write target queue, the necessary address number indicating the number of virtual storage addresses required for writing is calculated based on the data length of the communication data, and obtained from the queue use address number memory Based on the number of addresses used in the write target queue or each of the queues, the number of remaining addresses indicating the number of virtual storage addresses that can be used for the write is calculated, and the required number of addresses and the number of remaining addresses are compared. An access arbitration unit that determines whether or not the communication data can be written, and instructs the write control unit to write the communication data according to the determination of whether or not writing is possible. I / O device.

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