JP6398285B2 - Output circuit - Google Patents

Description

  The present invention relates to an output circuit. More specifically, the present invention relates to an output circuit in a semiconductor integrated circuit that interfaces with a circuit that operates at a voltage higher than a power supply voltage.

  Conventional examples of output circuits, input / output circuits, and input circuits will be described. FIG. 6 is a diagram illustrating an example of a conventional output circuit. The output circuit of FIG. 6 realizes a three-state output of a high level (hereinafter, H level) output, a low level (hereinafter, L level) output, and a high impedance state. FIG. 7 is a diagram illustrating an example of a conventional input / output circuit. The input / output circuit of FIG. 7 is a combination of the three-state output circuit of FIG. 6 and an input. FIG. 8 is a diagram illustrating an example of a conventional input circuit. The input circuit of FIG. 8 fixes the output of the three-state output circuit to a high impedance state and is used only as an input.

  In the above output circuit, input / output circuit, and input circuit, when a potential higher than its own power supply voltage is applied to the input / output terminal in the output high impedance state, current flows from the input terminal or output terminal to the power supply voltage, gate There are problems such as destruction of the transistor element due to voltage application exceeding the breakdown voltage between the source, between the gate and the drain, and between the gate and the back gate.

  In contrast, for example, Patent Document 1 discloses an output circuit having a tolerant function corresponding to a potential equal to or higher than the power supply voltage of the output circuit. FIG. 9 is a diagram illustrating an example of an output circuit having a conventional tolerant function. In FIG. 9, the circuit 10 implements a tolerant function. By adding an inverter 11, a NAND circuit 12, and a NOR circuit 13 to this, a three-state output circuit 20 is obtained.

  However, in the output circuit having the conventional tolerant function as shown in FIG. 9, when the OEB signal shown in FIGS. 6 and 7 is set to the H level, or when the output circuit is high impedance as shown in FIG. When a potential in the vicinity of the power supply voltage of the output circuit is applied to the output terminal, a leakage current flows from the power supply voltage to the output terminal as indicated by arrow a in FIG. 9, and from the output terminal to the power supply voltage as indicated by arrow b. There was a problem of flowing.

  Therefore, an object of the present invention is to provide an output circuit capable of preventing a leakage current that flows when a potential in the vicinity of the power supply voltage of the output circuit is applied to the output terminal.

  In order to achieve such an object, an output circuit according to the present invention includes a first circuit connected between an output terminal and a power supply voltage in an output circuit having a tolerant function corresponding to a potential equal to or higher than the power supply voltage of the output circuit. A leakage current prevention unit that has a P-channel transistor and allows a gate signal of the first P-channel transistor to be input via another P-channel transistor, an N-channel transistor, and an N-channel depletion transistor It is provided.

  According to the present invention, it is possible to prevent a leakage current that flows when a potential near the power supply voltage of the output circuit is applied to the output terminal.

It is a figure which shows the output circuit which concerns on 1st Embodiment. It is a figure which shows the output circuit which concerns on 2nd Embodiment. It is a figure which shows the N channel depletion type transistor which provided the resistive element. It is a figure which shows the output circuit which concerns on 3rd Embodiment. It is a figure which shows the output circuit which concerns on 4th Embodiment. It is a figure which shows the example of the conventional output circuit. It is a figure which shows the example of the conventional input / output circuit. It is a figure which shows the example of the conventional input circuit. It is a figure which shows an example of the output circuit which has the conventional tolerant function.

  Hereinafter, the configuration according to the present invention will be described in detail based on embodiments shown in the drawings.

[Example of basic configuration of output circuit]
Prior to the description of the output circuit according to the present embodiment, a basic configuration example (FIG. 9) of the output circuit 20 as a premise will be described. The output circuit 20 of FIG. 9 has a tolerant function realized by the circuit 10, and an inverter 11, a NAND circuit 12, and a NOR circuit 13 are added to the circuit 10 to form a three-state output circuit 20. Note that the transistor is, for example, a MOS transistor, and unless otherwise specified, is an enhancement type transistor.

  The operation of the circuit 10 of the output circuit 20 shown in FIG. 9 will be described. First, the L level output will be described. In the circuit 10, for example, when the power supply voltage VCC is 3V, a signal of 3V is input to the nodes NNP4 and NNN4. The signal of the node NNP4 becomes the gate input of the transistor PP2 by the transistor NN7 and the transistor PP4, and turns off the transistor PP2. The transistor NN1 is always on. The signal of the node NNN4 becomes the gate input of the transistor NN2, turns on the transistor NN2, and the output potential becomes L level by the transistors NN1 and NN2.

  Next, the H level output will be described. In the circuit 10, a signal of the ground potential GND is input to the nodes NNP4 and NNN4. The signal at the node NNP4 becomes the gate input of the transistor PP2 by the transistors NN7 and PP4 and turns on the transistor PP2. Further, the signal at the node NNN4 becomes the gate input of the transistor NN2, and the transistor NN2 is turned off, so that the potential of the output terminal becomes H level.

  Next, the high impedance output will be described. In this case, a signal of 3V is input to the node NNP4 of the circuit 10, and a signal of the ground potential GND is input to the node NNN4. The signal at the node NNP4 becomes the gate input of the transistor PP2 by the transistors NN7 and PP4, and turns off the transistor PP2. The signal at the node NNN4 becomes the gate input of the transistor NN2, and turns off the transistor NN2. Therefore, the output terminal becomes high impedance.

  In the circuit 10, when 5V is applied to the output terminal while the output is in a high impedance state, the transistor PP3 is turned on and the node NNP3 becomes 5V. Further, since the node NNP0 becomes approximately 5V by the transistors PP2 and PP3, the transistors PP2 and PP5 are turned off. Therefore, current flow from the output terminal to the power supply voltage VCC is prevented. Further, the transistors NN7 and PP4 prevent a current from flowing from the node NNP3 to the node NNP4 and a potential rise at the node NNP4.

  In this state, the potential difference between the gate-source, the gate-drain, and the gate-back gate generated in the transistors PP2, PP3, PP4, PP5, and NN7 is 2 V, and does not exceed the breakdown voltage of each transistor. Further, since the potential of the node NNN1 is approximately 3V, there is no problem with the withstand voltages of the transistors NN1 and NN2. Thus, the circuit 10 realizes a tolerant function.

  However, the output circuit 20 shown in FIG. 9 has a problem that leakage current flows when a potential in the vicinity of the power supply voltage of the output circuit is applied to the output terminal in a high impedance state.

  That is, in the output circuit 20 shown in FIG. 9, in the output high impedance state where a signal of 3V is inputted to the node NNP4 of the circuit 10 and a signal of the ground potential GND is inputted to the node NNN4, it becomes the gate input of the transistor PP4. If the potential of the output terminal is low enough to turn on the transistor PP4, the 3V potential of the node NNP4 propagates to the node NNP3 through the transistor PP4 and turns off the transistor PP2. However, when the potential of the output terminal serving as the gate input of the transistor PP4 is low with respect to the power supply voltage that does not sufficiently turn on the transistor PP4, the node NNP4 does not sufficiently propagate to the node NNP3.

  If the potential of the output terminal connected to the drain of the transistor PP3 is high enough to turn on the transistor PP3 with respect to the power supply voltage that is the gate potential of the transistor PP3, the transistor PP3 is turned on and the output terminal is turned on. Is propagated to the node NNP3 through the transistor PP3, and the transistor PP2 is turned off. However, when the potential of the output terminal connected to the drain of the transistor PP3 is high with respect to the power supply voltage that does not sufficiently turn on the transistor PP3, the potential of the output terminal does not sufficiently propagate to the node NNP3. End up.

  As a result of these operations, the gate input potential of the transistor PP2 becomes unstable. As shown in FIG. 9, when the output terminal is at a low potential with respect to the power supply voltage, the arrow a is indicated. When the output terminal is at a high potential, the arrow b is indicated. Leakage current flows in the direction shown through the transistor PP2. Further, since the transistor PP2 is a transistor for driving an external load, the size of the transistor PP2 is large and the leakage current is also large.

[First Embodiment]
FIG. 1 is a diagram illustrating an example of an output circuit 100 according to the first embodiment.

  In order to prevent the leakage current from flowing in and out through the transistor PP2 described so far, the output circuit 100 according to the present embodiment has a tolerant function corresponding to a potential higher than the power supply voltage of the output circuit (output circuit 100). The first P-channel transistor (transistor PP2) is connected between the output terminal and the power supply voltage VCC, and the gate signal of the first P-channel transistor is transferred to another P-channel transistor. A leakage current prevention unit (leakage current prevention circuit 110) that allows input via a channel type transistor (transistor PP4), an N channel type transistor (transistor NN7), and an N channel depletion type transistor (transistor ND) is provided. .

  The leakage current prevention unit is characterized in that the circuit 10 shown in FIG. 9 is provided with a transistor ND which is an N-channel depletion type transistor, and is connected between the output terminal and the power supply voltage VCC (between the drain and source). A first P-channel transistor (transistor PP2) whose gate is connected to the first node (node NNP3) and whose back gate is connected to the second node (node NNP0), and between the output terminal and the first node. A second P-channel transistor (transistor PP3) having a gate connected to the power supply voltage VCC and a back gate connected to the second node, both of which are signals to the first node and the leakage current prevention unit Is connected to the third node (node NNP4) to which is input, the gate is connected to the output terminal, and the back gate is connected to the second node. A third P-channel transistor (transistor PP4), an N-channel transistor (transistor NN7) whose gate is connected to the power supply voltage VCC and a back gate is connected to the ground potential, a gate is the power supply voltage VCC, and a back gate is the ground potential. And an N channel depletion type transistor (transistor ND). In addition, the code | symbol in embodiment and an application example are shown in a parenthesis.

  Hereinafter, the connection of the circuit configuration of the leakage current prevention circuit 110 will be described with reference to FIG. In addition, about the structure similar to the output circuit 20 shown in FIG. 9, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

  The transistor PP2 has a drain connected to the output terminal, a source connected to the power supply voltage VCC, a gate connected to the node NNP3, and a back gate connected to the node NNP0.

  The transistor PP3 has a drain and a source connected to the output terminal, a node NNP3, a gate connected to the power supply voltage VCC, and a back gate connected to the node NNP0.

  The transistor PP4 has a drain and a source connected to the node NNP3 and the node NNP4, a gate connected to the output terminal, and a back gate connected to the node NNP0.

  The transistor NN7 has a drain and a source connected to the nodes NNP3 and NNP4, a gate connected to the power supply voltage VCC, and a back gate connected to the ground potential.

  Further, the transistor ND has a drain and a source connected to the nodes NNP3 and NNP4, a gate connected to the power supply voltage VCC, and a back gate connected to the ground potential.

  In the leakage current prevention circuit 110 shown in FIG. 1 in the high impedance state, the transistor NN7 cannot propagate the 3V potential of the node NNP4 to the node NNP3 as it is, and the node NNP3 is lowered by about the threshold voltage of the transistor. Potential (ie, “3V-threshold voltage”).

  The transistor ND normally has a threshold voltage of 0 V to −0. Since it is several volts, it is possible to propagate the 3V potential of the node NNP4 to the node NNP3 as it is.

  For this reason, the gate potential of the transistor PP2 can be stabilized regardless of the potential of the output terminal. Therefore, in the output circuit 100 shown in FIG. 1, it is possible to prevent the occurrence of leakage current through the transistor PP2 as indicated by the arrows a and b in the output circuit 20 shown in FIG.

  As described above, according to the output circuit according to the present embodiment, the gate input potential of the transistor PP2 can be stabilized and the occurrence of leakage current through the transistor PP2 can be prevented, and the output circuit is connected to the output terminal. The leakage current that flows when a potential in the vicinity of the power supply voltage is applied can be prevented.

[Second Embodiment]
Hereinafter, other embodiments of the output circuit according to the present invention will be described. In addition, the description about the same point as the said embodiment is abbreviate | omitted suitably.

  FIG. 2 is a diagram illustrating an example of the output circuit 200 according to the second embodiment. In FIG. 2, the NAND circuit 12 of FIG. 1 is shown at the transistor level.

  In the output circuit 200, when the potential of the output terminal is higher than the power supply voltage, the path of the transistor PP3 of the leakage current prevention circuit 110, the transistor ND, and the P-channel transistor P0 of the NAND circuit 12 as shown by the arrow c. Some leakage current occurs.

  Here, if the threshold voltage of the transistor ND is 0 V, the leakage current indicated by arrows a and b in the output circuit 20 of FIG. 9 is prevented, and the leakage current indicated by arrow c in FIG. In consideration of variations in the manufacturing process, it is difficult to fix the threshold voltage of the transistor ND at 0V.

  Therefore, in order to reduce the leakage current indicated by the arrow c, the transistor ND preferably has a resistance portion. For example, the resistance value of the transistor ND can be increased by increasing the gate length of the transistor ND and scaling the gate width to be small.

  Further, as shown in FIGS. 3A to 3C, the resistance element 14 is connected to one or both of the drain and the source of the transistor ND, and is connected to the nodes NNP3 and NNP4 via the resistance element 14. Thus, the resistance value of the transistor ND may be increased.

  According to the output circuit 200 described above, the leakage current indicated by the arrow c can also be reduced.

[Third Embodiment]
FIG. 4 is a diagram showing a main part of the output circuit 300 according to the third embodiment. FIG. 4 shows a configuration example when the output circuit 100 shown in FIG. 1 is applied to a circuit in which the output of the three-state output circuit shown in FIG. 8 is fixed to a high impedance state and used only as an input. . In this case, the node NNP4 is connected to the power supply voltage VCC as shown in FIG.

[Fourth Embodiment]
FIG. 5 is a diagram showing a main part of the output circuit 400 according to the fourth embodiment. This output circuit 400 includes a plurality of transistors PP2 of the leakage current prevention circuit 110, and performs on / off control with different gate signals. In this case, for example, as shown in FIG. 5, the leakage current prevention circuit 110 is configured for each of the three transistors PP2 (PP2, PP2A, PP2B). The other transistors are shown with suffixes A and B.

  FIG. 5 shows an example in which three transistors PP2 (PP2, PP2A, PP2B) are provided and three leakage current prevention circuits are configured, but the number of transistors PP2 is not limited to this.

  The above-described embodiment is a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Circuit 11 Inverter 12 NAND circuit 13 NOR circuit 14 Resistance element 20,100,200,300,400 Output circuit

JP 2002-353800 A

Claims (6)

In an output circuit having a tolerant function corresponding to a potential higher than the power supply voltage of the output circuit,
A first P-channel transistor connected between the output terminal and the power supply voltage, and the gate signal of the first P-channel transistor is transmitted to another P-channel transistor, an N-channel transistor and an N-channel transistor; With a leakage current prevention unit that allows input via a depletion type transistor ,
The leakage current prevention unit
A first P-channel transistor connected between an output terminal and a power supply voltage, having a gate connected to a first node and a back gate connected to a second node;
A second P-channel transistor connected between an output terminal and the first node, having a gate connected to a power supply voltage and a back gate connected to the second node;
Both are connected between the first node and a third node to which a signal to the leakage current prevention unit is input,
A third P-channel transistor as the other P-channel transistor having a gate connected to the output terminal and a back gate connected to the second node;
The N-channel transistor having a gate connected to a power supply voltage and a back gate connected to a ground potential;
The N-channel depletion type transistor having a gate connected to a power supply voltage and a back gate connected to a ground potential;
Output circuit comprising: a. The N-channel depletion type transistor reduces a leakage current generated from an output terminal to the outside of the leakage current prevention unit via the second P-channel type transistor, the N-channel depletion type transistor, and the third node. The output circuit according to claim 1 , further comprising a resistance unit. The output circuit according to claim 2 , wherein the N-channel depletion type transistor has a resistance element connected to a drain and / or a source, and is connected to each node via the resistance element. The output circuit according to any one of claims 1 to 3, wherein the third node is connected to an output of a NAND circuit. The output circuit according to any one of claims 1 to 3 , wherein the third node is connected to a power supply voltage. Two or more leakage current prevention units are provided,
The output circuit according to any one of the gate signals of the first P-channel transistor of each leak current prevention unit from claim 1, characterized in that the on-off control to 5.

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