JP6399486B2 - Operational amplifier circuit - Google Patents

Description

The present invention relates to an operational amplifier circuit, and more particularly to a circuit technique for reducing the offset voltage and 1 / f noise of the operational amplifier circuit.

Operational amplifier circuits are used in a wide range of applications in semiconductor integrated circuits. In particular, from the viewpoint of high speed, low power, and cost, semiconductor integrated circuits manufactured by a CMOS process are mainly used at present, so that an operational amplifier circuit is also composed of MOS transistors.

Since the offset and 1 / f noise due to the relative accuracy of the MOS transistor are generally about an order of magnitude worse than those of the bipolar transistor, it is difficult to realize a low-offset voltage and low-noise operational amplifier circuit.

In order to solve this problem, there are chopper modulation techniques shown in (Non-Patent Documents 1 and 2) and (Patent Documents 1 to 5).

FIG. 1 shows an operational amplifier circuit using a chopper modulation technique. The chopper circuits 1 and 3 are provided at the input and output of the operational amplifier circuit 2, respectively, and the modulation operation is performed at the modulation frequency FCHOP.

The input signal is modulated by an input chopper circuit, and the modulated signal is amplified by an operational amplifier circuit and demodulated by an output chopper circuit. Since the signal is amplified at a modulated high frequency, the influence of the offset voltage of the operational amplifier circuit and 1 / f noise can be removed.

On the other hand, since the offset voltage and 1 / f noise of the operational amplifier circuit are modulated by the output chopper circuit to the modulation frequency FCHOP and its odd harmonics, the offset voltage and 1 / f noise appear at the low frequency of the output. Absent.

An operational amplifier circuit using a chopper modulation technique is used for various applications by utilizing the characteristics of a low offset voltage and 1 / f noise. For example, there are delta-sigma AD converters and band gap reference circuits listed in (Patent Documents 2 to 4) and (Non-Patent Documents 1 and 2).

If the modulated offset voltage of the operational amplifier circuit or the 1 / f noise component becomes a problem in terms of characteristics, it is necessary to provide a low-pass filter to remove it.

US Patent 4947135 US Pat. No. 4,939,516 US Pat. No. 4,994,805 US Pat. No. 6,462,612 US Pat. No. 7,224,216

KC Hsieh, PR Gray, D.D. Senderowicz, and DG Messerschmidt, “A low-noise hopper-stabilized differential-switched-capacitor filtering technique,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 708-715, Dec. 1981. Sandanenu, M.M. A. T.A. , Et al. “Accurate low power bandgap voltage reference in 0.5 μm CMOS technology,” Electronic Letters, May 14, 1998, vol. 34 No. 10, p. 1025.

In the operational amplifier circuit using the chopper modulation technique, the input and output voltages of the normal phase and the reverse phase to the operational amplifier circuit 2 are alternately switched by the chopper circuits 1 and 3, so that both the frequency characteristic and the slew rate of the operational amplifier circuit 2 are obtained. High performance is required.

For example, when the input signal is a sine wave having a frequency lower than the modulation frequency FCHOP, the terminals OUTP_I and OUTM_I of the operational amplifier circuit 2 need to change from the maximum value to the minimum value of the sine wave at time 0.5 / FCHOP. . That is, the frequency characteristics and the slew rate need to be higher than necessary for the signal to be amplified. In addition, the lack of frequency characteristics and slew rate causes distortion.

(Patent Document 5) divides an operational amplifier circuit using a chopper modulation technique into two or more segments as shown by 4a and 4b in FIG. 2, and determines the number of operational amplifier circuits whose states change at a time. By reducing, the influence of the frequency characteristic and the slew rate is reduced.

For example, when the ratios of the segments 4a and 4b are made equal, it is possible to halve the effects of the frequency characteristics and the slew rate because the state changes at a time in either the segment 4a or 4b.

However, when the operational amplifier circuit using the chopper modulation technique is divided into segments, statistical variation increases for each segment after division. This may cause a slew rate mismatch between the segments and worsen the distortion. In addition, there is still room for improvement in the method of reducing the glitch-shaped noise caused by the finite frequency characteristics and the slew rate.

The operational amplifier circuit according to the present invention includes N signal amplification units (N is an even number of 4 or more) that outputs current according to an input signal, and M (M is an even number of 4 or more) current sources that output current. A unit and a circuit for limiting the total output current of the signal amplification unit; The signal amplification unit has a selector consisting of a switch for modulating a differential input signal and demodulating the differential output current, and the current source unit has a selector consisting of a switch for modulating the differential output current. Then, the offset and 1 / f noise of the signal amplification unit and the current source unit are modulated.

Of the number of combinations of states associated with the modulation operation of the signal amplifying unit and the current source unit, control is performed so that one of them is 4 patterns or more and the other is 2 patterns or more, and it occurs in one state transition. Control is performed so as to reduce the number of transitions between the signal amplification unit and the current source unit. Also, control is performed such that the state transition timing is shifted so that state transitions of the signal amplification unit and the current source unit do not occur simultaneously, and the state transition periods of the signal amplification unit and the current source unit are set to different values.

Similar to the chopper modulation technique, an operational amplifier circuit with a low offset voltage and reduced 1 / f noise can be realized. Compared with chopper modulation technology, the amount of change in signal that changes per state transition decreases, so the frequency characteristics and slew rate required for the operational amplifier circuit decrease, and the glitch caused by the finite frequency characteristics and slew rate Noise and distortion of the shape can be reduced.

Since the slew rate of the circuit is determined by the total value of the output current of the signal amplification unit, the problem of slew rate mismatch can be reduced as compared with the case where the operational amplifier circuit is segmented. For the output currents of the N signal amplification units, these additions can be easily performed by short-circuiting the N output terminals. Also for the output currents of the M current source units, these additions can be easily performed by short-circuiting the M output terminals. In addition, since the signal can be amplified by a signal amplifying means such as a current input type grounded gate amplifier after adding the output current, the voltage fluctuation at the output terminal is reduced, and the frequency characteristics and slew rate required for the circuit are reduced. Output distortion caused by frequency characteristics and slew rate can be reduced.

Since the state transition timing of the signal amplification unit and the current source unit can be controlled separately, the state transition timing can be distributed. As a result, the amount of change in signal that changes per state transition can be further reduced, so that glitch-shaped noise and distortion due to finite frequency characteristics and slew rate can be further reduced. Then, the state transition periods of the signal amplification unit and the current source unit can be set to different values. That is, it is possible to set an appropriate state transition period for each of the signal amplification and current source units.

Example 1 is shown in FIG.

The operational amplifier circuit includes switches SW11 to 14, switches SW11B to 14B, switches SW21 to 24, switches SW21B to 24B, four signal amplification units having transistors M1, M2, M1B, and M2B, and a current output from the signal amplification unit. The signal amplification means includes transistors MC1 and MC2, current sources IL_M and IL_P, and a tail current source ITAIL.

Each signal amplification unit
One circuit with the switches SW11, SW11B, SW21, SW21B and the transistor M1,
One circuit is composed of the switches SW12, SW12B, SW22, SW22B and the transistor M2.
One circuit with the switches SW13, SW13B, SW23, SW23B and the transistor M1B,
The switches SW14, SW14B, SW24, and SW24B and the transistor M2B constitute one circuit. For convenience, these signal amplification units will be named as signal amplification units 1 to 4, respectively.

The switches SW11 and SW11B do not conduct at the same time.
That is, when the switch SW11 is conductive, SW11B is in a cut-off state, and when the switch SW11B is conductive, SW11 is in a cut-off state.

The same applies to the switches SW12 to SW14B and SW12B to 14B, and the switches SW21 to 24 and SW21B to 24B. When one switch is conductive, the other switch is in the cut-off state.

Here, the operation of the first signal amplification unit will be described. The first signal amplification unit is
A state 1 in which the switch SW11 transmits a signal input to the positive-phase input terminal INP to the gate terminal of the transistor M1 and connects the drain terminal of the transistor M1 and the source terminal of the transistor MC1 via the SW21;
The switch SW11B transmits the signal input to the negative-phase input terminal INM to the gate terminal of the transistor M1, and has two states of state 2 in which the drain terminal of the transistor M1 is connected to the source terminal of the transistor MC2 via the SW21B. .

The same operation is performed for the remaining second to fourth signal amplification units.
That is, the signal input to the input terminal INP of the positive phase is amplified, the signal input to the input terminal INM opposite to the state 1 in which the output current is output to the source terminal of the transistor MC1, and the output current is amplified. Is output to the source terminal of the transistor MC2.

That is, the switches SW11 to 14 and the switches SW11B to 14B perform an operation for modulating the input signal, and the switches SW21 to 24 and the switches SW21B to 24B perform an operation for demodulating the input signal.

Since the output of the signal amplification unit is a current, the addition of the output of each signal amplification unit can be easily performed by short-circuiting the output terminals of the signal amplification unit.

Further, when the output current is input to the source terminals of the transistors MC1 and MC2 and the MC1 and MC2 are operated as a grounded gate amplifier, the impedance of the source terminals of the MC1 and MC2 becomes low. This has the effect of reducing the voltage fluctuation at the output terminal of the circuit and can reduce the frequency characteristics and slew rate required for circuit operation.

The source terminals of the transistors M1, M2, M1B, and M2B constituting the signal amplification unit are short-circuited to supply current from the tail current source ITAIL. As a result, the total output current of the signal amplification unit is limited by the amount of current of the tail current source.

According to paragraph (0032), in the present invention, it can be considered that a signal is input to one differential pair at an arbitrary time during operation, and the slew rate is substantially constant regardless of the state of each signal amplification unit. Therefore, it is possible to reduce the distortion problem caused by the slew rate mismatch between segments when the operational amplifier circuit shown in paragraph (0016) is segmented.

The ratio of the time during which each signal amplification unit is in the state 1 and the state 2 is preferably 50% to 50% from the viewpoint of the offset and 1 / f noise modulation operation. If the ratio deviates from this value, the effect of offset and 1 / f noise modulation is reduced.

The drain terminals of the transistors MC1 and MC2 are connected to OUTM and OUTP, which are output terminals of opposite phase and positive phase, respectively.

Current sources IL_M and IL_P are connected to the output terminals OUTM and OUTP as loads.

In order to control the common-mode voltage of the positive-phase output terminal OUTP and the negative-phase output terminal OUTM, a common mode feedback circuit may be provided to adjust the current amount of the current source IL_M, IL_P or the tail current ITAIL.

In the present embodiment, a case will be described in which the transistors M1, M2, M1B, and M2B are made with the same device size and designed so that the same drain current flows in the same bias state.

FIG. 4 shows a timing chart showing the state of the signal amplification unit and the output voltage when the circuit of FIG. 3 is controlled so as to obtain the same effect as the conventional chopper stabilization technique. The portion not explicitly shown as state 1 in this timing chart is state 2.

The combination of the states of the first to fourth signal amplification units in the modulation signal period TCHOP changes every TCHOP / 2. Specific combinations of states of the signal amplification units are two patterns of states 1, 1, 2, and 2 and states 2, 2, 1, 1, respectively.

When a DC signal equal to the positive phase and negative phase input terminals INP and INM is applied, an offset and 1 / f noise modulated by a signal of the modulation signal period TCHOP appear at the output terminals OUTM and OUTP. That is, the output terminals OUTP and OUTM of the positive phase and the negative phase are rectangular waves that alternately change between the two states every time TCHOP / 2.

In addition, at the timing of state transition, glitch-shaped noise caused by the finite frequency characteristics and slew rate of the signal amplification unit appears in OUTP and OUTM.

FIG. 5 is a timing chart showing the state of the signal amplification unit and the output voltage when the state transition timing of the second and fourth signal amplification units is delayed by TCHOP / 4 using the present invention. The portion not explicitly shown as state 1 in this timing chart is state 2.

The combination of the states of the first to fourth signal amplification units in the modulation signal cycle TCHOP changes every time TCHOP / 4. The specific combinations of signal amplification unit states are states 1, 2, 2, 1 and states 1, 1, 2, 2 and states 2, 1, 1, 2 and states 2, 2, 1, 1 respectively. It is a pattern.

Since the offset and the 1 / f noise are modulated into a waveform in which the four states transition in order every TCHOP / 4 time, the same effect as the chopper modulation technique can be obtained.

Since the number of signal amplification units per state transition is reduced by half compared to the conventional chopper modulation technology, the finite frequency characteristics of the signal amplification unit generated at the state transition timing and the glitch-shaped noise due to the slew rate are Decrease.

Although the example in which the timing of the state transition of the second and fourth signal amplification units is delayed by TCHOP / 4 is shown, this does not limit that the time needs to be strictly TCHOP / 4.

Further, regarding the combination pattern of the states of the signal amplification units, this does not limit the number of combinations to four. There can be a maximum of C (4,2) = 6 combinations for selecting two non-overlapping units among the four signal amplification units.

The transistors M1, M2, M1B, and M2B shown in this embodiment may be any circuit that outputs a current in accordance with an input signal. For example, an amplifier circuit may be provided in front of the transistor M1, and a gate-grounded amplifier may be further provided between the drain terminal of the transistor M1 and SW21 and SW21B. Devices constituting the circuit are not limited to MOS transistors.

The signal for controlling the switch does not need to be a periodic signal in principle, and may be a random signal. The random signal may or may not have periodicity.

FIG. 6 is a timing chart showing the switch state and output current when a pseudo-random signal is used as a signal for controlling the switch. The portion not explicitly shown as state 1 in this timing chart is state 2.

The first signal amplification unit is controlled to be in state 1 when the pseudo-random signal of period TPRBS is HI, and the third signal amplification unit is controlled to be in state 1 when the pseudo-random signal is LOW. The second and fourth signal amplifying units control the states of the first and third signal amplifying units by delaying the state of TPRBS / 16, respectively.

The number of signal amplification units shown in the first embodiment is not limited to four, and may be an even number of four or more. FIG. 7 shows a circuit diagram of the second embodiment.

In the circuit of the first embodiment, switches SW15 to 18, switches SW15B to 18B, switches SW25 to 28, switches SW25B to 28B, and four signal amplification units having transistors M3, M4, M3B, and M4B are added.

The added signal amplifying unit is composed of one switch SW15, SW15B, SW25, SW25B and a transistor M3.
One circuit is composed of the switches SW16, SW16B, SW26, SW26B and the transistor M4.
One circuit is composed of the switches SW17, SW17B, SW27, SW27B and the transistor M3B.
The switches SW18, SW18B, SW28, SW28B and the transistor M4B are one circuit. For convenience, these signal amplifying units are named as signal amplifying units Nos. 5 to 8, respectively.

These fifth to eighth signal amplification units perform the same operation as in paragraph (0027).
That is, the state 1 in which the signal input to the positive phase input terminal INP is amplified and the output current is output to the source terminal of the transistor MC1, and the signal input to the negative phase input terminal INM is amplified and the output current is increased. There are two states, state 2 which is output to the source terminal of the transistor MC2.

In the present embodiment, a case will be described in which the transistors M1 to M4 and M1B to M4B are made with the same device size and designed to allow the same drain current to flow in the same bias state.

FIG. 8 is a timing chart showing the state and output voltage of the signal amplification unit according to the second embodiment. The portion not explicitly shown as state 1 in this timing chart is state 2.

The operation timings of the second to eighth signal amplification units are sequentially delayed by TCHOP / 8 with respect to the operation state of the first signal amplification unit.

As a result, the combination of the states of the first to eighth signal amplification units in the modulation signal cycle TCHOP changes every TCHOP / 8 time. Specific combinations of signal amplification unit states are states 1, 2, 2, 2, 2, 1, 1, 1, and
States 1, 1, 2, 2, 2, 2, 1, 1, and
States 1, 1, 1, 2, 2, 2, 2, 1, and
States 1, 1, 1, 1, 2, 2, 2, 2, and
States 2, 1, 1, 1, 1, 2, 2, 2, and
States 2, 2, 1, 1, 1, 1, 2, 2, and
States 2, 2, 2, 1, 1, 1, 1, 2, and
There are 8 patterns of states 2, 2, 2, 2, 1, 1, 1, 1.

Since the offset and the 1 / f noise are modulated into a waveform that sequentially changes the eight states every time TCHOP / 8, the same effect as the chopper modulation technique can be obtained.

Since the number of signal amplification units per state transition is reduced to ¼ compared with the conventional chopper modulation technique, the ridge frequency characteristics and slew rate of the signal amplification unit generated at the state transition timing Noise is also reduced.

The example in which the operation timing of the second to eighth signal amplification units is sequentially delayed by TCHOP / 8 with respect to the operation state of the first signal amplification unit has been shown, but this time is strictly TCHOP / 8. It is not limited to need.

In addition, although the example in which the combinations of the states of the signal amplification units constituting the current IOUTM and the current IOUTP are eight patterns is shown, this does not limit the number of combinations to eight. A combination of selecting four non-overlapping four of the eight signal amplification units can be C (8,4) = 70. The maximum value of the combination when the number of signal amplification units is N is determined by C (N, N / 2).

FIG. 9 shows a third embodiment for removing the offset and 1 / f noise caused by the current sources IL_M and IL_P shown in the first and second embodiments.

Instead of the current sources IL_M and IL_P of the first embodiment, there are four current source units including switches SW31 to 34, switches SW31B to 34B, and current sources IL5, IL6, IL5B, and IL6B.

Each current source unit is
One circuit with the switches SW31 and SW31B and the current source IL5,
One circuit with the switches SW32 and SW32B and the current source IL6,
One circuit with the switches SW33 and SW33B and the current source IL5B,
The switches SW34 and SW34B and the current source IL6B are configured in one circuit. For convenience, these current amplifying units are named as current source units 1 to 4, respectively.

Here, the operation of one current source unit will be described. The first current source unit has two states: a state 3 in which the current of the current source IL5 is connected to the output terminal OUTM through the switch SW31, and a state 4 in which the current from the current source IL5 is connected to the output terminal OUTP through the switch SW31B.

The same operation is performed for the remaining second to fourth current source units. That is, there are two states: a state 3 in which the currents of the current sources IL6, IL5B, and IL6B are connected to the output terminal OUTM, and a state 4 in which the currents of the current sources IL6, IL5B, and IL6B are connected to the output terminal OUTP.

Since the output of the current source unit is a current, the output of each current source unit can be easily added by short-circuiting the output terminals of the current source unit.

The percentage of time that each current source unit is in state 3 and state 4 is preferably 50% to 50% from the viewpoint of the offset and 1 / f noise modulation operations. If the ratio deviates from this value, the effect of offset and 1 / f noise modulation is reduced.

In order to control the common-mode voltage of the positive-phase output terminal OUTP and the negative-phase output terminal OUTM, a common mode feedback circuit may be provided to adjust the current amount of the current source IL5, IL6, IL5B, IL6B or the tail current ITAIL. Good.

In this embodiment, a case will be described in which the current sources IL5, IL6, IL5B, and IL6B are made with the same device size and designed to allow the same drain current to flow in the same bias state.

FIG. 10 shows a timing chart of the state of the signal amplification unit and the current source unit.
The portion not explicitly shown as state 1 in the timing chart of the state of the signal amplification unit is state 2, and the portion not explicitly shown as state 3 in the timing chart of the state of the current source unit is state 4.

The timing at which the first to fourth signal amplification units are in states 1 and 2 is the same as the timing at which the first to fourth current source units are in states 3 and 4.
The combinations of the states of the first to fourth signal amplification units in the modulation signal period TCHOP are four patterns as shown in the paragraph (0044). Similarly, the specific combinations of the states of the first to fourth current source units are respectively There are four patterns of states 3, 4, 4, 3 and states 3, 3, 4, 4 and states 4, 3, 3, 4 and states 4, 4, 3, 3.

As in the paragraph (0045), the offsets and 1 / f noise of the current sources IL5, IL6, IL5B, and IL6B are modulated into waveforms that sequentially transition between the four states every time TCHOP / 4. The same effect as technology can be obtained.

As in the paragraph (0046), the number of current source units per state transition is reduced by half compared to the conventional chopper modulation technique, so that the finite frequency characteristics and slew rate of the signal amplification unit generated at the state transition timing are reduced. The glitch-shaped noise caused by the is reduced.

FIG. 11 shows an example of a method for controlling so that the state transition of the signal amplification unit and the state transition of the current source unit do not occur simultaneously. The portion not explicitly shown as state 1 in the timing chart of the state of the signal amplification unit is state 2, and the portion not explicitly shown as state 3 in the timing chart of the state of the current source unit is state 4.

FIG. 11 shows the operation timing of the first to fourth current source units in FIG. 10 delayed by TCHOP / 8.

This prevents the state transition of the signal amplification unit and the current source unit from occurring at the same time, so signal amplification that occurs at the state transition timing compared to the chopper modulation technique using the conventional segmented operational amplifier circuit The glitch-shaped noise caused by the finite frequency characteristics and slew rate of the unit can be reduced.

The paragraph (0079) describes that the operation timing is delayed by TCHOP / 8. However, as described in the paragraph (0080), the purpose is not to cause the state transition of the signal amplification unit and the current source unit at the same time. The amount of delay is not limited to TCHOP / 8.

In addition to FIG. 11, FIG. 12 shows an example in which the period of the state transition of the signal amplification unit and the state transition of the current source unit are different. The portion not explicitly shown as state 1 in the timing chart of the state of the signal amplification unit is state 2, and the portion not explicitly shown as state 3 in the timing chart of the state of the current source unit is state 4.

12 delays the operation timing of the first to fourth current source units in FIG. 10 by TCHOP / 8 and further sets the period of state transition to 2 TCHOP, which is twice TCHOP. Control is performed so that unit state transitions do not occur simultaneously.

The period of state transition between the signal amplifying unit and the current source unit, that is, the modulation frequency is the corner of 1 / f noise generated by the devices constituting each unit from the viewpoint of removing 1 / f noise as in the conventional chopper modulation technique. It is desirable that the frequency be higher than the frequency.
On the other hand, if the modulation frequency is high, the operation speed required for the signal amplification unit and the current source unit increases, leading to an increase in area and an increase in current consumption. Therefore, the modulation frequency is preferably as low as possible.

Here, when the corner frequency of the 1 / f noise of the signal amplification unit and the current source unit is different depending on the type and size of the device, the modulation frequency of both can be set to different values as shown in FIG. Based on the ideas of paragraphs (0080) and (0081), the modulation frequency of both can be set so that the state transition of the signal amplification unit and the current source unit does not occur simultaneously.

Although FIG. 12 shows an example in which the period of state transition of the signal amplification unit is shorter than the period of the current source unit, the magnitude relationship between these periods is not limited to the example of FIG. The period of state transition of the signal amplification unit may be longer than the period of the current source unit.

It is desirable to control so that the state transitions of the signal amplification unit and the current source unit do not occur simultaneously, and in order to realize this, it is desirable that the operation of the state transitions of the signal amplification unit and the current source unit be synchronized.
That is, in other words, it is desirable that the ratio of the period of state transition between the signal amplification unit and the current source unit is expressed as a natural number versus a natural number.

The number of current source units is not limited to four, and may be M (M is an even number of 4 or more). The number N of signal amplification units and the number M of current source units need not be the same, and may be different values.

The number of combinations of the states of the signal amplification units and the number of combinations of the states of the current source units need not be the same, and may be different.

Depending on the circuit characteristics determined by the type and size of the device, the number of combinations of the states of the signal amplification unit and the current source unit need not be more than 4 patterns. Any one of the numbers may be two patterns.
Further, when the number of combinations of the states of the signal amplification units and the current source units is two patterns, the effect of reducing the number of signal amplification units per state transition shown in paragraphs (0046) and (0077) cannot be obtained. Are the effects of shifting the operation timing so that state transitions of the signal amplification unit and the current source unit shown in paragraphs (0080) and (0081) do not occur simultaneously, and the signal amplification unit and the current source unit shown in paragraph (0085) The effect of setting the modulation frequency to a different value can be obtained.

Paragraphs (0038), (0057), and (0073) describe the case where the transistors or current sources constituting the signal amplification unit and the current source unit are made with the same device size and designed to allow the same drain current to flow in the same bias state. However, this is not limited to designing the current flowing through the signal amplification unit and the current source unit of the present invention to be equal. What is necessary is just to design so that the total value of the device size which outputs an electric current to the output terminal of a normal phase and an anti | reverse | negative phase is equal, and the equal electric current flows in the same bias state in the combination of all the states which a signal amplification unit can take. The same applies to the current source unit.
For example, in the timing chart of FIG. 5, the first and third signal amplification units do not overlap in the state 1 state, and the second and fourth signal amplification units do not overlap in the state 1 state. In this case, by setting the device size ratio of the first to fourth signal amplification units to 1: 2: 1: 2, the ratio of the device sizes of the signal amplification units in the state 1 and state 2 is always 3: 3. Thus, in the same bias state, a design can be made in which equal current flows through the output terminals of the positive phase and the negative phase. The same applies to the current source unit.

FIG. 13 shows an example in which transistors MC3 and MC4 are added as signal amplification means to the circuit shown in the third embodiment, and a cascode current source is configured in combination with a current source unit.

Transistors MC3 and MC4 are provided between the four current source units and the output terminals OUTM and OUTP, and BIAS2 is applied as the gate bias thereof.

The operations of the signal amplification unit and the current source unit are the same as those in the third embodiment.

The modification of the fourth embodiment shown in FIG. 13 has the same effect as the paragraphs (0030) and (0031) on the output terminal of the current source unit. That is, there is an effect that voltage fluctuations associated with modulation operation can be reduced, and frequency characteristics and slew rate required for circuit operation can be reduced.

Note that the transistors MC1, MC2 and MC3, MC4 used as signal amplifying means are not necessarily required because the signal amplification effect is reduced depending on the load of the operational amplifier circuit.

A folded cascode configuration can be obtained by modifying the circuit of the fourth embodiment. An embodiment is shown in FIG.

In the circuit of the fourth embodiment, current sources IL1, IL2, IL1B, and IL2B are respectively added to four signal amplification units, and the transistors MC1, MC2, MC3, and MC4 are replaced with transistors MC1B, MC2B, MC3B, and MC4B.

Each signal amplification unit
One circuit with the switches SW11, SW11B, SW21, SW21B, the transistor M1 and the current source IL1,
One circuit is composed of the switches SW12, SW12B, SW22, SW22B, the transistor M2, and the current source IL2.
One circuit with the switches SW13, SW13B, SW23, SW23B, the transistor M1B and the current source IL1B,
The switches SW14, SW14B, SW24, SW24B, the transistor M2B, and the current source IL2B are configured in one circuit.

The operations of these signal amplification units are the same as those in the first embodiment, except that the transistors MC1 and MC2 are replaced with MC1B and MC2B.

The current source unit is the same as that of the fourth embodiment except that the direction of the output current of the current source differs depending on whether it is in the power supply direction or the ground direction. The operation of these current source units is the same as that of the fourth embodiment, except that the transistors MC3 and MC4 are replaced with MC3B and MC4B.

The operational amplifier circuit of the present invention can be used in a variety of applications where the conventional operational amplifier circuit is used. FIG. 15 shows an embodiment in which a bandgap reference circuit is configured using the operational amplifier circuit of the fourth embodiment.

In this embodiment, transistors ML1, ML2, ML1B, and ML2B are used instead of the current sources IL5, IL6, IL5B, and IL6B in the circuit of FIG. The gate terminals of these transistors are connected to the OUTP terminal to convert the output from differential to single phase.

The gate of the transistor MOUT is connected to the output terminal OUTM, and the drain is connected to the terminal BGROUT.

One terminal of resistors RBGR1, RBGR2, and RLPF is connected to the terminal BGROUT.

The other terminals of resistors RBGR1 and RBGR2 are connected to input terminals INM and INP, respectively. The anode of D21 and one terminal of the resistor RBGR3 are connected to the input terminals INM and INP, respectively.

The cathode of the diode D11 and the anode of D12 are connected, and the other terminal of the resistor RBGR3 is connected to the anode of the diode D11.
The cathode of the diode D21 and the anode of D22 are connected, and the cathodes of the diodes D12 and D22 are connected to the ground terminal.

The other terminal of the resistor RLPF is connected to the capacitor CLPF, and the other terminal of the capacitor CLPF is connected to the ground terminal to constitute a low-pass filter, and its output is a terminal LPFOUT.

Feedback is applied so that the input terminals INP and INM are equalized by the circuit operation. Assume that the values of resistors RBGR1 and RBGR2 are equal, the sizes of diodes D11 and D12 are equal, the sizes of D21 and D22 are equal, and the size of D11 is A times D21. Is Vt, the voltage of the terminal BGROUT can be expressed by 2 * (VF + (RBGR1 / RBGR3) * Vt * ln (A)).

Since the offset and 1 / f noise of the transistors M11, M12, M11B, and M12B and the transistors ML1, ML2, ML1B, and ML2B are modulated, the offset voltage and 1 / f noise of the operational amplifier circuit appearing at the terminal BGROUT are reduced. .

The modulated offset voltage and 1 / f noise can be reduced by the low-pass filter.

Illustration of conventional chopper modulation technology Explanatory drawing of conventional technology with segmented operational amplifier circuit using chopper modulation technology Circuit diagram of Example 1 Timing chart showing signal amplification unit status and output voltage when using conventional chopper modulation technology The timing chart which showed the state of the signal amplification unit and output voltage of Example 1 Timing chart showing the state and output voltage of the signal amplification unit when using a pseudo-random signal as a signal to control the switch Circuit diagram of Example 2 The timing chart which showed the state of the signal amplification unit and output voltage of Example 2 Circuit diagram of Example 3 The timing chart which showed the state of the signal amplification unit and current source unit of Example 3 FIG. 10 is a timing chart showing a case where the state transition timings of the signal amplification unit and the current source unit are shifted by TCHOP / 8. FIG. 10 is a timing chart showing a case where the state transition timings of the signal amplification unit and the current source unit are shifted by TCHOP / 8 and the state transition periods of the two are different. Circuit diagram of Example 4 Circuit diagram of Example 5 Circuit diagram of Example 6 and circuit diagram of a bandgap reference using the circuit of Example 4

1, 1b input chopper circuit 2, 2b operational amplifier circuit 3, 3b output chopper circuit 4a, 4b operational amplifier circuit having function of segmented chopper modulation FCHOP modulation frequency

INP Positive-phase input terminal INM Reverse-phase input terminal SW11-18 SW-switch SW11B-18B connecting the positive-phase input terminal INP and the gates of transistors M1-4, M1B-4B, and negative-phase input terminal INM, transistor M1 -4, switches M1-4 for connecting the gates of M1B-4B, transistors M1B-4B, transistor OUTP, positive phase output terminal OUTM, reverse phase output terminal SW21-28, and switches SW21B connected to the drains of transistors M1-4, M1B-4B ~ 28B Switches connected to the drains of transistors M1-4, M1B-4B

IOUTP Current flowing in the current path of the positive phase output terminal IOUTM Current flowing in the current path of the negative phase output terminal

TCHOP modulation signal period TPRBS pseudo-random signal period

ITAIL tail current source IL_P current source IL_M current source

IL5, 6 Current source IL5B, 6B Current source

SW31-34 Switches SW31B-34B connected to current sources IL5, 6, IL5B, 6B Switches connected to current sources IL5, 6, IL5B, 6B

ML1, 2 transistor ML1B, 2B transistor

MC1-4 Transistors BIAS2 Bias terminals BIAS3 of transistors MC1 and MC2 Bias terminals of transistors MC3 and MC4

MC1B to 4B Transistor BIAS2B Bias terminal BIAS3B of transistors MC1B and MC2B Bias terminal of transistors MC3B and MC4B

BGROUT Output of band gap reference circuit LPFOUT Output of low pass filter MOUT Transistor RBGR1 whose gate terminal is connected to output terminal OUTM and drain terminal is connected to BGROUT RBGR2 which constitutes a bandgap reference circuit Resistor RBGR3 which constitutes a bandgap reference circuit Resistor D11 constituting the gap reference circuit Diode D12 constituting the band gap reference circuit Diode D21 constituting the band gap reference circuit Diode D22 constituting the band gap reference circuit Diode RLPF constituting the band gap reference circuit Resistor constituting the low pass filter CLPF Capacitor constituting low-pass filter

Claims (14)

Modulate the differential signal of the first input terminal and the second input terminal
A differential amplifier circuit that amplifies and demodulates the modulated differential signal and outputs the amplified differential signal to the first output terminal and the second output terminal;
The differential amplifier circuit selects and amplifies a signal input to the first and second input terminals by a first selector to generate an output current, and a second selector outputs the output current as a destination of the output current. 1, a circuit of N signal amplification unit to select the second output terminal (N is an even number of 4 or more) and <br/> the N signal amplification unit to limit the total value of current that can be output <br /> and a second current source for supplying a current to the first of the first supply current to the output terminal of the current source and <br/> said second output terminal,
In the N signal amplification units, the first selector selects the first input terminal, the second selector selects the first output terminal, and the first selector selects the second input terminal. The second selector has N signal amplification unit control signals for switching between the two states of the state 2 in which the second output terminal is selected,
The N signal amplification unit control signals periodically change in a first period,
The operational amplifier circuit characterized in that the number of states 1 and 2 in the N signal amplification units is four or more patterns
Modulate the differential signal of the first input terminal and the second input terminal
A differential amplifier circuit that amplifies and demodulates the modulated differential signal and outputs the amplified differential signal to the first output terminal and the second output terminal;
The differential amplifier circuit selects and amplifies the signals input to the first and second input terminals by the first selector to generate an output current, and the second selector converts the output current to the signal amplifying means 1. Alternatively, the number of signal amplifying units selected to be output to the first or second output terminal via the signal amplifying means 2 is N and the total value of currents that can be output from the N signal amplifying units is limited. and a circuit with <br/> second current source for supplying a current to the first current source and <br/> said second output terminal for supplying a current to said first output terminal,
In the N signal amplification units, the first selector selects the first input terminal, the second selector selects the first output terminal, and the first selector selects the second input terminal. The second selector has N signal amplification unit control signals for switching between the two states of the state 2 in which the second output terminal is selected,
The N signal amplification unit control signals periodically change in a first period,
The operational amplifier circuit characterized in that the number of states 1 and 2 in the N signal amplification units is four or more patterns
As the first and second current sources, there are M current source units (M is an even number of 4 or more) having a function of selecting and outputting a current to the first and second output terminals by a third selector. And
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit according to claim 1, wherein the number of combinations of the state 3 and the state 4 of the M current source units is two or more patterns. As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
Between the third selector and the first output terminal of the current source unit, there is a signal amplification means 3,
Between the third selector and the second output terminal of the current source unit, there is signal amplification means 4;
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
3. The operational amplifier circuit according to claim 1, wherein the number of combinations of the state 3 and the state 4 of the M current source units is two or more patterns. As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit according to claim 1, wherein the number of combinations of the state 3 and the state 4 of the M current source units is 4 patterns or more. As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
Between the third selector and the first output terminal of the current source unit, there is a signal amplification means 3,
Between the third selector and the second output terminal of the current source unit, there is signal amplification means 4;
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit according to claim 1, wherein the number of combinations of the state 3 and the state 4 of the M current source units is four or more patterns. Modulate the differential signal of the first input terminal and the second input terminal
A differential amplifier circuit that amplifies and demodulates the modulated differential signal and outputs the amplified differential signal to the first output terminal and the second output terminal;
The differential amplifier circuit selects and amplifies a signal input to the first and second input terminals by a first selector to generate an output current, and a second selector outputs the output current as a destination of the output current. 1, <br/> with the circuit a signal amplification unit to select the second output terminal and the N <br/> the N signal amplification unit to limit the total value of current that can be output the first output terminal and a second current source for supplying a current to the first current source and <br/> said second output terminal for supplying a current to,
In the N signal amplification units, the first selector selects the first input terminal, the second selector selects the first output terminal, and the first selector selects the second input terminal. The second selector has N signal amplification unit control signals for switching between the two states of the state 2 in which the second output terminal is selected,
The N signal amplification unit control signals periodically change in a first period,
The number of combined states 1 and 2 of the N signal amplification units is two or more patterns,

As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit characterized in that the number of combined states 3 and 4 of the M current source units is four or more patterns
Modulate the differential signal of the first input terminal and the second input terminal
A differential amplifier circuit that amplifies and demodulates the modulated differential signal and outputs the amplified differential signal to the first output terminal and the second output terminal;
The differential amplifier circuit selects and amplifies a signal input to the first and second input terminals by a first selector to generate an output current, and a second selector outputs the output current as a destination of the output current. 1, <br/> with the circuit a signal amplification unit to select the second output terminal and the N <br/> the N signal amplification unit to limit the total value of current that can be output the first output terminal and a second current source for supplying a current to the first current source and <br/> said second output terminal for supplying a current to,
In the N signal amplification units, the first selector selects the first input terminal, the second selector selects the first output terminal, and the first selector selects the second input terminal. The second selector has N signal amplification unit control signals for switching between the two states of the state 2 in which the second output terminal is selected,
The N signal amplification unit control signals periodically change in a first period,
The number of combined states 1 and 2 of the N signal amplification units is two or more patterns,

As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
Between the third selector and the first output terminal of the current source unit, there is a signal amplification means 3,
Between the third selector and the second output terminal of the current source unit, there is signal amplification means 4;
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit characterized in that the number of combined states 3 and 4 of the M current source units is four or more patterns

Modulate the differential signal of the first input terminal and the second input terminal
A differential amplifier circuit that amplifies and demodulates the modulated differential signal and outputs the amplified differential signal to the first output terminal and the second output terminal;
The differential amplifier circuit selects and amplifies the signals input to the first and second input terminals by the first selector to generate an output current, and the second selector converts the output current to the signal amplifying means 1. Alternatively, the number of signal amplifying units selected to be output to the first or second output terminal via the signal amplifying means 2 is N and the total value of currents that can be output from the N signal amplifying units is limited. and a circuit with <br/> second current source for supplying a current to the first current source and <br/> said second output terminal for supplying a current to said first output terminal,
In the N signal amplification units, the first selector selects the first input terminal, the second selector selects the first output terminal, and the first selector selects the second input terminal. The second selector has N signal amplification unit control signals for switching between the two states of the state 2 in which the second output terminal is selected,
The N signal amplification unit control signals periodically change in a first period,
The number of combined states 1 and 2 of the N signal amplification units is two or more patterns,

As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit characterized in that the number of combined states 3 and 4 of the M current source units is four or more patterns
Modulate the differential signal of the first input terminal and the second input terminal
A differential amplifier circuit that amplifies and demodulates the modulated differential signal and outputs the amplified differential signal to the first output terminal and the second output terminal;
The differential amplifier circuit selects and amplifies the signals input to the first and second input terminals by the first selector to generate an output current, and the second selector converts the output current to the signal amplifying means 1. Alternatively, the number of signal amplifying units selected to be output to the first or second output terminal via the signal amplifying means 2 is N and the total value of currents that can be output from the N signal amplifying units is limited. and a circuit with <br/> second current source for supplying a current to the first current source and <br/> said second output terminal for supplying a current to said first output terminal,
In the N signal amplification units, the first selector selects the first input terminal, the second selector selects the first output terminal, and the first selector selects the second input terminal. The second selector has N signal amplification unit control signals for switching between the two states of the state 2 in which the second output terminal is selected,
The N signal amplification unit control signals periodically change in a first period,
The number of combined states 1 and 2 of the N signal amplification units is two or more patterns,

As the first and second current sources, M current source units having a function of selecting and outputting a current to the first and second output terminals by a third selector are provided.
Between the third selector and the first output terminal of the current source unit, there is a signal amplification means 3,
Between the third selector and the second output terminal of the current source unit, there is signal amplification means 4;
In the current source unit, the third selector has M current source unit control signals for switching between the state 3 in which the first output terminal is selected and the state 4 in which the second output terminal is selected. And
The M current source unit control signals periodically change in the second period,
The operational amplifier circuit characterized in that the number of combined states 3 and 4 of the M current source units is four or more patterns


11. The operational amplifier circuit according to claim 3, wherein the first period is equal to the second period. 11. The operational amplifier circuit according to claim 3, wherein the first period and the second period are different. 11. The operational amplifier circuit according to claim 3, wherein the first period and the second period are different, and a ratio of the first period and the second period can be expressed by a natural number to a natural number. The timing of transition from state 1 to state 2 and state 2 to state 1 of the N signal amplification units differs from the timing of transition from state 3 to state 4 and state 4 to state 3 of the M current source units. The operational amplifier circuit according to claim 3, wherein no state transition occurs at the timing.

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