JP6406136B2 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nitride semiconductor device having a GaN device using a compound semiconductor containing gallium nitride (hereinafter referred to as GaN) as a main component and a manufacturing method thereof.

  Conventionally, Patent Document 1 discloses a technique for realizing normally-off and low on-resistance in a nitride semiconductor device having a plurality of channels. Specifically, a natural super junction structure (hereinafter referred to as an NSJ structure) is formed by repeatedly forming a heterojunction of an AlGaN layer and a GaN layer on the GaN layer. In addition, the first gate structure portion that reaches the lowermost AlGaN layer in the NSJ structure and the second gate structure portion that reaches the upper AlGaN layer are sandwiched between the first gate structure portion and the second gate structure portion. On both sides, a source region and a drain region composed of n-type regions are arranged.

  In the nitride semiconductor device configured as described above, the gate structure portion has a MOS structure. And, since the electrostatic potential of the first gate electrode and the gate insulating film provided in the first gate structure part is lower than the conduction band of the heterojunction of the GaN layer and the AlGaN layer, there is no carrier at the heterointerface, Normally-off operation is performed. In addition, by providing a plurality of heterojunctions, the amount of two-dimensional electron gas (hereinafter referred to as 2DEG) generated can be increased, and the on-resistance can be reduced. A desired off breakdown voltage can be obtained by the polarization effect regardless of the number of laminated heterojunctions.

JP 2013-98284 A

  However, in the nitride semiconductor device configured as described above, a MOS structure gate structure is used in order to perform a normally-off operation. However, in the MOS structure, the resistivity of a channel formed immediately below the gate structure is increased. The on-resistance cannot be sufficiently reduced. For example, the on-resistance is greater than 2 mΩ / mm.

  An object of the present invention is to provide a nitride semiconductor device capable of achieving a lower on-resistance while securing an off-breakdown voltage, and a method for manufacturing the same.

In order to achieve the above object, according to the first aspect of the present invention, a substrate (1) made of semi-insulating or semiconductor, a GaN layer (2) formed on the substrate and constituting an electron transit layer, and A channel-forming layer in which a plurality of heterojunction structure pairs composed of AlGaN layers (3) constituting the electron supply unit are stacked, and the surface of the channel-forming layer is formed so as to reach the layer closest to the substrate among the channel-forming layers. The base region composed of the p-type GaN layer (5) and the both sides sandwiching the p-type GaN layer are disposed so as to protrude from the surface of the channel formation layer to the most substrate side layer among the channel formation layers. An emitter region and a collector region composed of n-type GaN layers (9, 10) formed as described above, and at the interface between the GaN layer and the AlGaN layer constituting the channel formation layer. A lateral switching device that induces a two-dimensional electron gas carrier on the GaN layer side and applies a voltage to the base region to pass a current between the emitter region and the collector region. It is said.

  According to such a configuration, in the on state, that is, in a state where the base voltage is applied to the base region, hole injection is performed from the base region, and an electron current flows from the emitter region side to the collector region side. Therefore, conductivity modulation that increases the carrier concentration in the base region occurs and the resistance is reduced. Thereby, the on-resistance is reduced. Furthermore, since a plurality of sets of GaN layers and AlGaN layers are repeatedly formed, 2DEG carriers can be generated by the plurality of layers, and the on-resistance can be further reduced. The on-resistance can be further reduced as the number of combinations of the GaN layer and the AlGaN layer is increased. In addition, since a structure in which a plurality of sets of GaN layers and AlGaN layers are repeatedly formed is used, the breakdown voltage can be ensured by controlling the film thickness ratio to form the NSJ structure.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a cross-sectional perspective view of a nitride semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the nitride semiconductor device shown in FIG. 3 is a cross-sectional view showing a state of charges accumulated at an interface with the GaN layer 2 in the AlGaN layer 3. FIG. FIG. 6 is a cross-sectional view showing a manufacturing process of the nitride semiconductor device according to the first embodiment. It is sectional drawing of the nitride semiconductor device concerning 2nd Embodiment of this invention. It is sectional drawing of the nitride semiconductor device concerning 3rd Embodiment of this invention. It is sectional drawing of the nitride semiconductor device concerning 4th Embodiment of this invention. It is sectional drawing of the nitride semiconductor device concerning 5th Embodiment of this invention. It is sectional drawing of the nitride semiconductor device concerning 6th Embodiment of this invention. It is sectional drawing which showed the manufacturing process of the nitride semiconductor device concerning 6th Embodiment. It is sectional drawing of the nitride semiconductor device concerning 7th Embodiment of this invention. It is sectional drawing which showed the manufacturing process of the nitride semiconductor device concerning 7th Embodiment. It is sectional drawing of the nitride semiconductor device concerning the modification of 7th Embodiment. It is sectional drawing of the nitride semiconductor device concerning 8th Embodiment of this invention. It is sectional drawing of the nitride semiconductor device concerning other embodiment. It is sectional drawing of the nitride semiconductor device concerning other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, a nitride semiconductor device including a lateral switching element will be described as a nitride semiconductor device having a GaN device using a compound semiconductor containing GaN as a main component.

  As shown in FIGS. 1A and 1B, the nitride semiconductor device according to the present embodiment includes a horizontal switching element. 1 (a) and 1 (b) show only one cell of the switching element, but in actuality, for example, a layout that is symmetrically laid out with the left end of FIG. 1 (a) as the center line is shown. A plurality of switching elements are formed. This switching element is configured as follows.

  The horizontal switching element is formed by using a compound semiconductor substrate in which a plurality of sets of structures in which the GaN layer 2 and the n-type AlGaN layer 3 are stacked are repeatedly formed on the surface of the substrate 1. Then, a heterojunction structure composed of a plurality of sets of GaN layers 2 and AlGaN layers 3 is used as a channel formation layer, and 2DEG is formed on the GaN layer 2 side of the AlGaN / GaN interface by the GaN layers 2 and AlGaN layers 3 by piezoelectric and polarization effects. Induces carriers.

The substrate 1 is made of a semiconductor material such as Si (111). A GaN layer 2 and an AlGaN layer 3 are formed on the substrate 1 by, for example, heteroepitaxial growth.


The film thickness of the AlGaN layer 3 is set to 10 nm to 200 nm, preferably 20 nm to 100 nm. If the film thickness of the AlGaN layer 3 is less than 10 nm, the 2DEG surface density is less than 8 × 10 ¹² cm ⁻² , which increases the on-resistance of the device. If the thickness exceeds 200 nm, the dislocation density increases due to strain relaxation. The variation in characteristics increases and causes an extreme decrease in production yield. Typically, the defect density is 1 × 10 ¹¹ cm ⁻² or more. Further, it is preferable that the film thickness of the AlGaN layer 3 is 20 nm or more and 100 nm or less because the essential problems of the above materials do not occur and the density of 2DEG is low and the defect density is low. The thickness of the GaN layer 2 formed on the AlGaN layer 3 must also be designed in the same film thickness range as described above for the same reason. In particular, in the range of 40 nm to 100 nm, two-dimensional hole gas (2DHG) is formed in the same order as 2DEG at the Ga / AlGaN interface paired with 2DEG, so that an ideal NSJ structure is obtained, and the device has a high breakdown voltage. Is more preferable.

The film thickness ratio AlGaN / GaN between the GaN layer 2 formed on the AlGaN layer 3 and the AlGaN layer 3 is AlGaN / GaN ≦ 5, preferably AlGaN / GaN ≦ 2. . When the film thickness ratio AlGaN / GaN exceeds 5, the lattice relaxation of the AlGaN layer 3 is effectively achieved, and 2DEG and 2DHG are not effectively generated, resulting in high resistance. Further, when the film thickness ratio AlGaN / GaN is ½ or more and 2 or less, an AlGaN / GaN laminated structure is formed without taking over the lattice constant of the lowermost GaN and remarkably relaxing the strain, and the dislocation and defect density are 1 × 10 ¹¹ cm ⁻² is preferable because it can be kept low.

  About the specific resistance value of a compound semiconductor substrate, what is necessary is just to adjust arbitrarily with the impurity concentration of each layer which comprises a compound semiconductor substrate according to the characteristic of the target device. An AlGaN-GaN superlattice layer or the like may be interposed between the GaN layer 2 and the substrate 1 to improve the crystallinity of the GaN layer 2. Here, the crystallinity means defects or dislocations in the GaN layer 2 and affects the electrical and optical characteristics.

A recess 4 having a depth that does not reach the substrate 1 is formed from the surface of the compound semiconductor substrate, reaching the layer closest to the substrate 1 in the channel forming layer, that is, the lowermost GaN layer 2. A p-GaN layer 5 made of p-type GaN constituting the base region is formed in the recess 4. The impurity concentration of the p-GaN layer 5 is set to 5 × 10 ¹⁶ cm ⁻³ or more, for example. By setting the impurity concentration of the p-GaN layer 5 in this way, punch-through leakage current can be suppressed. The higher the impurity concentration at which the proper off operation is realized, the greater the effect of suppressing the punch-through current. However, if the impurity concentration is too high, the transport efficiency of the base deteriorates and the current amplification factor during the on operation decreases. Regarding the base concentration, a desired concentration may be selected for the device in consideration of the length of the base. Typically, 5 × 10 ¹⁶ cm ⁻² or more is necessary from the viewpoint of suppressing leakage current, and it is necessary to make it smaller than 5 × 10 ¹⁸ cm ⁻² from the viewpoint of base transport efficiency. In addition, as for the lateral dimension of the p-GaN layer 5, that is, the horizontal dimension in FIG. 1, in consideration of the current amplification factor of the switching element, an optimal one may be selected together with the impurity concentration described above.

A p ⁺ -GaN layer 6 having a higher impurity concentration than the p-GaN layer 5 is formed on the surface of the p-GaN layer 5. The impurity concentration of the p ⁺ -GaN layer 6 is set to, for example, 1 × 10 ¹⁹ cm ⁻³ or more, preferably 1 × 10 ²⁰ cm ⁻³ or more. By thus setting the impurity concentration of p ⁺ -GaN layer 6 is a p ⁺ -GaN layer 6 is in ohmic contact with the base electrode or base wiring is formed (not shown) thereon. In the case of 1 × 10 ¹⁹ cm ⁻³ or less, since a Schottky contact and a current barrier are formed, stable element operation cannot be realized. From the standpoint of parasitic resistance during operation, the interface resistance becomes sufficiently lower than the operating resistance by setting it to 1 × 10 ²⁰ cm ⁻³ or more, thereby improving the switching performance of the device.

In addition, on both sides of the p-GaN layer 5, recesses 7 and 8 having a depth not reaching the substrate 1 are formed while reaching the lowermost GaN layer 2 from the surface of the compound semiconductor substrate. The n ⁺ -GaN layers 9 and 10 constituting the emitter region and the collector region are formed in the recesses 7 and 8, respectively. The n ⁺ -GaN layers 9 and 10 are both formed at positions away from the p-GaN layer 5.

Note that the element breakdown voltage is determined by the distance between the p-GaN layer 5 constituting the base region and the n ⁺ -GaN layer 10 constituting the collector region, but the dimension design may be performed according to the desired element breakdown voltage. Further, n ⁺ Above the -GaN layer 9 are formed an emitter electrode and a collector electrode (not shown), each of these electrodes are brought into ohmic contact with n ⁺ -GaN layer 9,10.

  As described above, the nitride semiconductor device including the lateral switching element according to the present embodiment is configured. The horizontal switching element configured as described above operates as follows.

First, in the off state, that is, the base voltage VB = 0 V applied to the p-GaN layer 5, the electron current is blocked by the height of the electron barrier of the p-GaN layer 5. Further, the hole current is also blocked by the barrier of the n ⁺ -GaN layers 9 and 10 constituting the emitter region and the collector region. Therefore, in the off state, a normally-off type switching element in which no current flows between the emitter and the collector is obtained.

On the other hand, when the base voltage VB is applied to the p-GaN layer 5 in the ON state, holes are injected from the p-GaN layer 5, and the n ⁺ -GaN layer 9 serving as the emitter region becomes the collector region from the n ⁺ -GaN layer 9 side. ^An electron current flows to the ⁺ -GaN layer 10 side. Therefore, conductivity modulation that increases the carrier concentration in the base region occurs and the resistance is reduced. Thereby, the on-resistance is reduced. Furthermore, since a plurality of sets of the GaN layer 2 and the AlGaN layer 3 are repeatedly formed, 2DEG carriers can be generated by the plurality of layers, and the on-resistance can be further reduced. The on-resistance can be further reduced as the number of sets in which the GaN layer 2 and the AlGaN layer 3 are repeated is increased.

  In addition, since the structure is such that a plurality of sets of GaN layers 2 and AlGaN layers 3 are repeatedly formed, a breakdown voltage can be secured. More specifically, the breakdown voltage can be ensured by controlling the film thickness ratio between the GaN layer 2 and the AlGaN layer 3 to have an NSJ structure. As shown in FIG. 2, the charge accumulated at the interface between the AlGaN layer 3 and the GaN layer 2 is balanced at the top and bottom of the AlGaN layer 3. For this reason, the charge balance is in a good state and the breakdown voltage can be secured.

  Therefore, it is possible to provide a nitride semiconductor device that can achieve a lower on-resistance while ensuring an off-breakdown voltage.

  Further, as described above, in the present embodiment, the p-GaN layer 5 has a depth that does not reach the substrate 1. For this reason, it becomes possible to suppress the hole from being removed from the p-GaN layer 5 to the substrate 1 made of a semiconductor material, and the switching characteristics can be improved.

  Next, a method for manufacturing the horizontal switching element according to the present embodiment will be described with reference to FIG.

[Step shown in FIG. 3 (a)]
A compound semiconductor substrate having a structure in which a plurality of sets of GaN layers 2 and n-type AlGaN layers 3 are repeatedly stacked on the surface of a substrate 1 made of Si (111) is prepared. For example, a GaN layer 2 and an AlGaN layer 3 are formed on the surface of the substrate 1 by MOCVD (Metal Organic Chemical Vapor Deposition) method or ultra-high purity and high precision MBE (Molecular Beam Epitaxy). It is formed by the law.

[Step shown in FIG. 3B]
After a mask 20 composed of an oxide film (SiO ² ) or a nitride film (SiN) is formed on the surface of the AlGaN layer 3, the mask 20 is patterned to open a region where the p-GaN layer 5 is to be formed. For example, after forming a resist (not shown) on the surface of the mask 20 and patterning the resist through a photolithography process, the mask 20 is patterned using the resist. Thereafter, by performing a dry etching process using the mask 20, the AlGaN layer 3 and the GaN layer 2 are etched to form the recess 4 reaching the GaN layer 2 located at the lowest layer.

[Step shown in FIG. 3 (c)]
Further, the GaN layer is selectively epitaxially grown (hereinafter referred to as selective epi) with the mask 20 covering the surface of the AlGaN layer 3. As a result, first, the p-GaN layer 5 is selectively epitaxially buried so as to fill the recess 4 up to the position of the AlGaN layer 3 positioned on the outermost surface, and then the p ⁺ -GaN layer 6 is selectively epitaxially formed thereon. . Thus, since the p-GaN layer 5 and the p ⁺ -GaN layer 6 are formed by selective epi, they can be formed only in the recess 4.

[Step shown in FIG. 3 (d)]
After removing the mask 20, a new mask 21 is formed, and the masks 20 and 21 are patterned to open the masks 20 and 21 in regions where the n ⁺ -GaN layers 9 and 10 are to be formed. The mask 21 is made of, for example, the same material as the mask 20 and is patterned by the same method as the mask 20. Then, by performing a dry etching process using the masks 20 and 21, the AlGaN layer 3 and the GaN layer 2 are etched to form the recesses 7 and 8 reaching the GaN layer 2 located at the lowest layer.

[Step shown in FIG. 3 (e)]
Further, the GaN layer is selectively epitaxialized with the mask 21 covering the surface of the AlGaN layer 3. Thereby, n ⁺ -GaN layers 9 and 10 are formed so as to fill the recesses 7 and 8 up to the position of the AlGaN layer 3 located on the outermost surface. In this way, since the n ⁺ -GaN layers 9 and 10 are formed by selective epi, these can be formed only in the recesses 7 and 8.

Although the subsequent steps are not shown, an interlayer insulating film is formed so as to cover the p ⁺ -GaN layer 6 and the n ⁺ -GaN layers 9 and 10 after removing the masks 20 and 21, and then the interlayer insulation is formed. An interlayer insulating film forming step of forming a contact hole by patterning the film is performed. Further, an electrode forming process for forming a base electrode, an emitter electrode, and a collector electrode through the contact hole is performed. Thus, the nitride semiconductor device provided with the switching element according to the present embodiment is completed.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the material of the substrate 1 is changed with respect to the first embodiment, and the others are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  In the present embodiment, the substrate 1 is composed of a semi-insulating substrate such as sapphire, SiC, or AlN. Then, as shown in FIG. 4, the p-GaN layer 5 is formed so as to reach the surface of the substrate 1.

  Thus, when the substrate 1 is formed of a semi-insulating substrate, it is difficult for holes to escape from the p-GaN layer 5 to the substrate 1. Therefore, the p-GaN layer 5 may be in contact with the substrate 1. Further, since the p-GaN layer 5 may be in contact with the surface of the substrate 1 in this way, the etching time when forming the recess 4 can be easily controlled, and the manufacturing process can be simplified. Is also possible.

Although the n ⁺ -GaN layers 9 and 10 are separated from the substrate 1 here, they may be formed in contact with the substrate 1. In that case, since the etching time when forming the recesses 7 and 8 can be easily controlled, the manufacturing process can be further simplified.

(Third embodiment)
A third embodiment of the present invention will be described. This embodiment is provided with a semi-insulating layer with respect to the first embodiment, and the others are the same as those of the first embodiment, and therefore only the parts different from the first embodiment will be described.

As shown in FIG. 5, a semi-insulating layer 30 is provided below the p-GaN layer 5. The semi-insulating layer 30 is made of, for example, Al ₂ O ₃ , SiC, AlN, or the like, and is not only on the p-GaN layer 5 but also on the entire surface in the substrate plane until reaching the n ⁺ -GaN layers 9 and 10. Is formed.

  Thus, by providing the semi-insulating layer 30 below the p-GaN layer 5, it is possible to further suppress the escape of holes from the p-GaN layer 5 to the substrate 1. Thereby, a switching characteristic can be improved more.

  Such a structure is different from the nitride semiconductor device manufacturing method according to the first embodiment in that a step of forming the semi-insulating layer 30 before the GaN layer 2 is formed or during the epitaxial growth of the GaN layer 2 is performed. It can be realized by adding.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. This embodiment is provided with a cap layer with respect to the first to third embodiments, and the other parts are the same as those of the first to third embodiments, and therefore different from the first to third embodiments. Only will be described. In addition, although the case where this embodiment is applied with respect to the structure of 2nd Embodiment is demonstrated here, it is the same also about 1st, 3rd embodiment.

  As shown in FIG. 6, a cap layer 40 composed of a GaN layer is further provided on the surface of the AlGaN layer 3 located at the uppermost layer. As described above, when the cap layer 40 composed of the GaN layer is further disposed on the AlGaN layer 3 positioned at the uppermost layer, the GaN layer 2 and the cap layer 40 are disposed on the upper and lower surfaces of the AlGaN layer 3. Thus, the upper layer of the AlGaN layer 3 is also charged, and the upper and lower charge balance is achieved. As a result, the on-resistance can be further reduced.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In the present embodiment, the configurations of the GaN layer 2 and the AlGaN layer 3 are changed with respect to the first to fourth embodiments, and the others are the same as those of the first to fourth embodiments. Only parts different from the fourth embodiment will be described. In addition, although the case where this embodiment is applied with respect to the structure of 4th Embodiment is demonstrated here, it is the same also about 1st-3rd embodiment.

  As shown in FIG. 7, in the present embodiment, a structure in which an AlGaN layer 3 is stacked on a substrate 1 and then a GaN layer 2 is sequentially stacked, and a plurality of pairs of the AlGaN layer 3 and the GaN layer 2 are repeatedly stacked. It is said. As described above, the same effects as those of the above-described embodiments can be obtained even when the formation positions of the GaN layer 2 and the AlGaN layer 3 are interchanged with respect to the above-described embodiments.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. In the present embodiment, the configurations of the GaN layer 2 and the AlGaN layer 3 are changed with respect to the second, fourth, and fifth embodiments, and the others are the same as those in the second to fourth embodiments. Only portions different from the second, fourth, and fifth embodiments will be described. In addition, although the case where this embodiment is applied with respect to the structure of 4th Embodiment is demonstrated here, it is the same also about 2nd, 5th embodiment.

As shown in FIG. 8, in this embodiment, the GaN layer 2 and the AlGaN layer 3 are not laminated between the p-GaN layer 5 constituting the base region and the n ⁺ -GaN layer 9 constituting the emitter region. The n-GaN layer 50 is made of n-type GaN.

As described above, when the p-GaN layer 5 and the n ⁺ -GaN layer 9 are configured by the n-GaN layer 5, the hole diffusion length is shortened, and the current amplification factor can be improved.

In the nitride semiconductor device of this embodiment, for example, the p-GaN layer 5, the n ⁺ -GaN layer 9, and the n-GaN layer 50 can be formed by selective epi.

Specifically, as shown in FIG. 9A, after performing the same steps as in FIG. 3A, the p-GaN layer 5 and n ⁺ in the mask 20 as shown in FIG. 9B. The regions where the -GaN layer 9 and the n-GaN layer 50 are to be formed are opened. Then, the GaN layer 2 and the AlGaN layer 3 are etched using the mask 20. Subsequently, as shown in FIG. 9C, the p-GaN layer 5 and the p ⁺ − are formed in the opening of the mask 20, that is, in the portion where the GaN layer 2 and the AlGaN layer 3 are removed by selective epitaxy using the mask 20. A GaN layer 6 is formed.

Thereafter, as shown in FIG. 9D, the mask 21 is formed by removing the mask 20 or by stacking on the mask 20, and the n ⁺ -GaN layer 9 and the n-GaN layer 50 in the mask 21 are to be formed. Open the area. Then, regions where the n ⁺ -GaN layer 9 and the n-GaN layer 50 are to be formed in the p-GaN layer 5 and the p ⁺ -GaN layer 6 are removed by etching using the mask 21.

Further, as shown in FIG. 9E, the n-GaN layer is formed in the opening of the mask 21, that is, the portion where the p-GaN layer 5 and the p ⁺ -GaN layer 6 are removed by selective epitaxy using the mask 21. 50 is deposited. After that, as shown in FIG. 9F, the mask 22 is formed by removing the mask 21 or stacking it on the mask 21, and opening the regions where the n ⁺ -GaN layers 9 and 10 are to be formed in the mask 22. . Then, after forming the recesses 7 and 8 by etching using the mask 22, n ⁺ -GaN layers 9 and 10 are formed in the openings of the mask 22 by selective epitaxy using the mask 22. Thereafter, by performing the same process as in the first embodiment, the switching element of this embodiment can be manufactured.

(Seventh embodiment)
A seventh embodiment of the present invention will be described. In the present embodiment, the structures of the p-GaN layer 5, the n ⁺ -GaN layer 9 and the n-GaN layer 50 are changed with respect to the sixth embodiment. The other parts are the same as in the sixth embodiment, and therefore only the parts different from the sixth embodiment will be described.

As shown in FIG. 10, in this embodiment, the entire region where the p-GaN layer 5, the n ⁺ -GaN layer 9 and the n-GaN layer 50 are disposed is a recess 60, and the p-GaN is formed in the recess 60. The layer 5, the n ⁺ -GaN layer 9, and the n-GaN layer 50 are sequentially stacked. That is, the p-GaN layer 5 is formed on the bottom and side surfaces of the recess 60, and the n ⁺ -GaN layer 9 and the n-GaN layer 50 are sequentially formed thereon. Even with such a structure, the same effect as in the sixth embodiment can be obtained.

Note that the nitride semiconductor device of this embodiment can be formed, for example, by selective epitaxy of the p-GaN layer 5, the n ⁺ -GaN layer 9, and the n-GaN layer 50 in order. That is, in FIG. 11 (a), (b), the process similar to FIG. 9 (a), (b) is performed. Then, as shown in FIG. 11 (c), the p-GaN layer 5, the n ⁺ -GaN layer 9 and the n-GaN layer 50 are sequentially formed in the recess 60 by selective epi. Subsequently, after forming the mask 23 as shown in FIG. 11 (d), a region where the p ⁺ -GaN layer 6 is to be formed is opened in the mask 23. Then, as shown in FIG. 11E, after forming the p ⁺ -GaN layer 6 in the opening of the mask by selective epitaxy using a mask (not shown), the mask is removed. Thereafter, by performing the same process as in the first embodiment, the switching element of this embodiment can be manufactured.

(Modification of the seventh embodiment)
In the seventh embodiment, the n-GaN layer 50 is provided. However, as shown in FIG. 12, the n-GaN layer 50 is lost and the n ⁺ -GaN is directly formed on the p-GaN layer 5. A structure in which the layer 9 is formed may be used. With such a structure, since the n-GaN layer 50 is not provided, electrons are directly injected into the p-GaN layer 5 from the n ⁺ -GaN layer 9 side where the depletion layer does not extend and the electron concentration is high. Is done. Therefore, the current amplification factor can be further improved.

(Eighth embodiment)
An eighth embodiment of the present invention will be described. In the present embodiment, the configuration of the p ⁺ -GaN layer 6 is changed with respect to the first to seventh embodiments, and the others are the same as those of the first to seventh embodiments. Only parts different from the seventh embodiment will be described. In addition, although the case where this embodiment is applied with respect to the structure of 4th Embodiment is demonstrated here, it is the same also about 1st-3rd, 5th-7th embodiment.

As shown in FIG. 13, in this embodiment, the p ⁺ -GaN layer 6 is projected to the emitter region side and the collector region side to have a T-shaped cross section, thereby forming a T base. An interlayer insulating film 70 is formed on the cap layer 40, and the upper layer portion of the p ⁺ -GaN layer 6 is formed on the interlayer insulating film 70 so as to protrude from the lower layer portion.

By adopting such a structure, it becomes possible to achieve both lateral scaling of the p-GaN layer 5 and reduction of the contact resistance between the base contact, that is, the p ⁺ -GaN layer 6 and the base electrode. It becomes possible to improve.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

The dimensions of the configuration of the nitride semiconductor device described in the above embodiments, the manufacturing method, and the like are merely examples. For example, as shown in FIG. 14, in each embodiment, the n ⁺ -GaN layers 9 and 10 may be formed by ion implantation of Si. In FIG. 14, the case where the n ⁺ -GaN layers 9 and 10 are formed by ion implantation is illustrated for the structure of the second embodiment, but the same can be applied to other embodiments. As shown in FIG. 15, in the sixth embodiment, an n-GaN layer 50 can be formed by ion implantation in addition to the n ⁺ -GaN layers 9 and 10. In that case, the portion where Si is implanted into the AlGaN layer 3 becomes the n-AlGaN layer 50a. Of course, the n ⁺ -GaN layers 9 and 10 may be formed by selective epi, not ion implantation, and only the n-GaN layer 50 including the n-AlGaN layer 50a may be formed by ion implantation.

DESCRIPTION OF SYMBOLS 1 Substrate 2 GaN layer 3 AlGaN layer 5 p-GaN layer 6 p ⁺ -GaN layer 7, 8 Recess 9, 10 n ⁺ -GaN layer 30 Semi-insulating layer 40 Cap layer 50 n-GaN layer

Claims (12)

A semi-insulating or semiconductor substrate (1);
A channel forming layer formed on the substrate, in which a plurality of heterojunction structure pairs each including a GaN layer (2) constituting an electron transit layer and an AlGaN layer ( 3 ) constituting an electron supply unit are laminated;
A base region composed of a p-type GaN layer (5) formed so as to protrude from the surface of the channel forming layer to the layer closest to the substrate among the channel forming layers;
N-type GaN layers (9, 10) disposed on both sides of the p-type GaN layer and formed so as to reach the most substrate-side layer among the channel-forming layers from the surface of the channel-forming layer. An emitter region and a collector region,
A two-dimensional electron gas carrier is induced on the GaN layer side at the interface between the GaN layer and the AlGaN layer constituting the channel forming layer, and a voltage is applied to the base region, whereby the emitter region and A nitride semiconductor device comprising a lateral switching device for passing a current between the collector region and the collector region. A semi-insulating or semiconductor substrate (1);
A channel forming layer formed on the substrate, in which a plurality of heterojunction structure pairs each including a GaN layer (2) constituting an electron transit layer and an AlGaN layer ( 3 ) constituting an electron supply unit are laminated;
A base region composed of a p-type GaN layer (5) formed so as to protrude from the surface of the channel forming layer to the layer closest to the substrate among the channel forming layers;
An emitter region composed of an n-type GaN layer (9) disposed on one side with respect to the p-type GaN layer;
An n-type GaN layer disposed on the opposite side of the one side with respect to the p-type GaN layer and formed so as to reach the most substrate-side layer among the channel-forming layers from the surface of the channel-forming layer. A collector region constituted by (10);
An n-type GaN layer (50) disposed between the emitter region and the base region;
A two-dimensional electron gas carrier is induced on the GaN layer side at the interface between the GaN layer and the AlGaN layer constituting the channel forming layer, and a voltage is applied to the base region, whereby the emitter region and A nitride semiconductor device comprising a lateral switching device for passing a current between the collector region and the collector region.   A contact region formed of a p-type GaN layer (6) formed on the base region and having an impurity concentration higher than that of the p-type GaN layer constituting the base region. The nitride semiconductor device according to claim 1 or 2.   4. The nitride semiconductor device according to claim 3, wherein the base region has a T-shaped cross section projecting toward the emitter region and the collector region. 5. The substrate is made of a semiconductor material;
The nitride semiconductor device according to claim 1, wherein the base region is separated from the substrate. The substrate is made of a semi-insulating material,
The nitride semiconductor device according to claim 1, wherein the base region is in contact with the substrate.   The channel forming layer is characterized in that the GaN layer and the AlGaN layer are laminated in order, and the uppermost AlGaN layer is covered with a cap layer (40) made of GaN. The nitride semiconductor device according to any one of 1 to 6.   8. The channel forming layer according to claim 1, wherein a film thickness ratio between the GaN layer and the AlGaN layer is controlled to a value constituting a natural super junction structure by the GaN layer and the AlGaN layer. The nitride semiconductor device according to any one of the above. The substrate is made of a semi-insulating material;
In the channel forming layer, a recess (60) reaching the substrate from the outermost surface of the channel forming layer is formed, and the base region is formed on the bottom and side surfaces of the recess in the recess, and 3. The nitride semiconductor device according to claim 2, wherein the n-type GaN layer and the emitter region are sequentially formed on a base region. A semi-insulating or semiconductor substrate (1);
A channel forming layer formed on the substrate, in which a plurality of heterojunction structure pairs each including a GaN layer (2) constituting an electron transit layer and an AlGaN layer ( 3 ) constituting an electron supply unit are laminated;
A base region composed of a p-type GaN layer (5) formed so as to reach the most substrate-side layer of the channel formation layer from the surface of the channel formation layer;
N-type GaN layers (9, 10) disposed on both sides of the p-type GaN layer and formed so as to reach the most substrate-side layer among the channel-forming layers from the surface of the channel-forming layer. An emitter region and a collector region,
A two-dimensional electron gas carrier is induced on the GaN layer side at the interface between the GaN layer and the AlGaN layer constituting the channel forming layer, and a voltage is applied to the base region, whereby the emitter region and A method for manufacturing a nitride semiconductor device comprising a lateral switching device for passing a current between the collector region and the collector region,
Laminating a plurality of sets of the GaN layer and the AlGaN layer constituting the channel forming layer on the substrate;
Forming a recess (4) from the surface of the channel forming layer so as to reach the layer closest to the substrate among the channel forming layers;
Forming a base region by selectively epitaxially growing a p-type GaN layer in the recess. Forming recesses (7, 8) from the surface of the channel formation layer so as to reach the layer closest to the substrate among the channel formation layers at positions where the emitter region and the collector region are to be formed;
Forming the emitter region and the collector region by selectively epitaxially growing an n-type GaN layer (9, 10) in each of the recesses formed at the positions where the emitter region and the collector region are to be formed; The method for manufacturing a nitride semiconductor device according to claim 10, wherein: A semi-insulating or semiconductor substrate (1);
A channel forming layer formed on the substrate, in which a plurality of heterojunction structure pairs each including a GaN layer (2) constituting an electron transit layer and an AlGaN layer ( 3 ) constituting an electron supply unit are laminated;
A base region composed of a p-type GaN layer (5) formed so as to reach the most substrate-side layer of the channel formation layer from the surface of the channel formation layer;
An emitter region composed of an n-type GaN layer (9) disposed on one side with respect to the p-type GaN layer;
An n-type GaN layer disposed on the opposite side of the one side with respect to the p-type GaN layer and formed so as to reach the most substrate-side layer among the channel-forming layers from the surface of the channel-forming layer. A collector region constituted by (10);
An n-type GaN layer (50) disposed between the emitter region and the base region;
A two-dimensional electron gas carrier is induced on the GaN layer side at the interface between the GaN layer and the AlGaN layer constituting the channel forming layer, and a voltage is applied to the base region, whereby the emitter region and A method for manufacturing a nitride semiconductor device comprising a lateral switching device for passing a current between the collector region and the collector region,
Laminating a plurality of sets of the GaN layer and the AlGaN layer constituting the channel forming layer on the substrate;
After forming a recess from the surface of the channel formation layer so as to reach the substrate side layer of the channel formation layer, the base region, the n-type GaN layer, and the emitter region are selected in the recess. And a step of epitaxially growing the nitride semiconductor device.

Images