JP6410144B2 - Semiconductor device and inspection method thereof - Google Patents

Description

  The present disclosure relates to a semiconductor device formed by CSP (chip size package), WLCSP (wafer level chip size package), or FOWLP (Fan out wafer level package), and in particular, whether or not rewiring is broken. The present invention relates to a semiconductor device and an inspection method thereof.

  In recent years, with the progress of miniaturization, thinning, and weight reduction of electronic devices, semiconductor devices having a CSP (chip size package) structure that is almost the same as the outer size of a semiconductor chip are rapidly spreading. In this CSP, rewiring is formed from an electrode on a semiconductor chip to solder balls (bumps) which are external terminals arranged in a lattice pattern on the surface of the package. In the CSP, the WLCSP technology forms a through electrode and a rewiring in an assembly process in a wafer state.

  For example, Patent Document 1 discloses a semiconductor device in which an inductive element L that is patterned so that an inductance component is not generated in the conductor layer 5 on the circuit element formation area DA is formed as a rewiring.

Japanese Patent No. 3540729

  However, the above-described semiconductor device has a problem that it cannot be inspected for the disconnection of the rewiring that connects the electrode pad of the semiconductor chip and the external terminal of the semiconductor device.

  An object of the present disclosure is to solve the above problems and to provide a semiconductor device and an inspection method thereof capable of inspecting whether or not a rewiring that connects an electrode pad of a semiconductor chip and an external terminal of the semiconductor device is disconnected.

A semiconductor device according to the present disclosure is:
A semiconductor device mounting a semiconductor chip including an output transistor that converts an input voltage input to an input terminal into a first voltage and outputs the first voltage,
The semiconductor chip includes a first electrode pad connected to the output terminal of the output transistor, and a second electrode pad connected to the output terminal of the output transistor via an internal resistor,
The semiconductor device includes a first through electrode and a rewiring that connect the first electrode pad and an external terminal of the semiconductor device, and a second through that connects the second electrode pad and the rewiring. With electrodes,
The semiconductor chip is
An error amplifier that generates an error voltage between the first voltage and the negative feedback voltage, and that controls the output transistor to convert the input voltage to be input into the first voltage based on the error voltage;
And a switching unit that selectively outputs either the second voltage at the first electrode pad or the third voltage at the second electrode pad as the negative feedback voltage to the error amplifier.

  According to the semiconductor device and the inspection method thereof according to the present disclosure, it is possible to determine whether or not the rewiring is disconnected in the semiconductor device only by providing a simple switch on the wiring. Therefore, since the switch can be formed by using the empty space in the semiconductor chip, it is possible to prevent an increase in circuit scale and power consumption.

3 is a top view of the semiconductor device 2 according to the first embodiment of the present disclosure. FIG. It is the elements on larger scale of the area | region A enclosed with the broken line of FIG. FIG. 3 is a longitudinal sectional view of the semiconductor device 2 taken along the line B-B ′ of FIG. 2. FIG. 4 is a circuit diagram of the semiconductor chip 1 of FIG. 3. FIG. 5 is a schematic diagram for explaining the operation of the semiconductor device 2 of FIG. 4.

  Embodiments according to the present disclosure will be described below with reference to the drawings. In the following embodiments, the same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.

First embodiment.
A low dropout (LDO) linear regulator formed on a semiconductor chip is mounted on a CSP (chip size package), WLCSP (wafer level chip size package) or FOWLP (Fan out wafer level package) (fan out wafer level package), There is a technique for reducing internal resistance due to wiring in a semiconductor chip by using rewiring in CSP, WLCSP, or FOWLP. On the other hand, the first embodiment of the present disclosure is characterized in that the presence or absence of disconnection of the rewiring in the CSP, WLCSP, or FOWLP can be easily inspected.

  FIG. 1 is a top view of the semiconductor device 2 according to the first embodiment of the present disclosure. In FIG. 1, a solder ball 11 is an input terminal, and a solder ball 12 is an output terminal. Here, the input voltage input to the input terminal is converted into a predetermined voltage by a constant voltage circuit 15 (described later) mounted in the semiconductor device 2 and output from the output terminal.

  2 is a partially enlarged view of a region A surrounded by a broken line in FIG. 1, and FIG. 3 is a longitudinal sectional view of the semiconductor device 2 taken along line B-B ′ in FIG. 1 and 2, the semiconductor device 2 is an individual CSP that is cut out from a wafer-state CSP by dicing. 1 and 2, each CSP has a rectangular shape, and a solder ball 11 as an external terminal and an electrode pad P1 of a semiconductor chip 1 described later are electrically connected through a through electrode TH1 and a rewiring 10. The Also, the solder balls 12 that are external terminals and the electrode pads P2 of the semiconductor chip 1 are electrically connected via the rewiring 20 and the through-hole electrodes TH2. Furthermore, the solder balls 12 that are external terminals and the electrode pads P3 of the semiconductor chip 1 are electrically connected via the rewiring 20 and the through-hole electrodes TH3. That is, the rewiring 20 and the electrode pad P3 are electrically connected through the through electrode TH3. Here, the rewiring 20 has a resistance of about 0.1 ohm.

  In FIG. 3, a manufacturing process until the solder ball 12 which is an external terminal of the semiconductor device 2 is formed will be described below.

(1) On the semiconductor chip 1, electrode pads P1 to P3 formed of a conductive material such as aluminum are patterned and formed.
(2) The first insulating layer 7 is deposited on the semiconductor chip 1 and the electrode pads P1 to P3.
(3) Openings are respectively formed on the electrode pads P1 to P3 in the deposited first insulating layer 7 using a photolithography process and a dry etching method.
(4) Metals such as platinum, rhodium, ruthenium, and iridium are deposited in the openings on the electrode pads P1 to P3 by using a sputtering method, a vacuum deposition method, or the like to form the through electrodes TH1 to TH3, respectively.
(5) For example, a metal material such as copper or nickel is deposited on the through electrodes TH1 to TH3 and the first insulating layer 7, and the deposited metal material is patterned using a photolithography process, a dry etching method, and the like. Wirings 10 and 20 are formed, respectively.
(6) A second insulating layer is deposited on the rewirings 10 and 20 and the first insulating layer 7.
(7) In the second insulating layer 8, openings are provided on the rewirings 10 and 20, and solder balls 11 and 12 are formed in the openings.

  FIG. 4 is a circuit diagram of the semiconductor chip 1 of FIG. In FIG. 4, the semiconductor chip 1 includes a constant voltage circuit 15 such as a low dropout (LDO) linear regulator, a switch SW, an internal resistance R having a resistance of about 4 ohms, and electrode pads P1 to P3. Configured. The constant voltage circuit 15 includes a power supply 6 having a reference voltage Vref, an output transistor 4 that converts an input voltage input to the electrode pad P1 via the solder ball 11 into a reference voltage Vref, and outputs the reference voltage Vref. An error amplifier 3 that generates an error voltage with respect to the feedback voltage and controls the output transistor 4 to convert the input voltage to the reference voltage Vref based on the error voltage is provided. Here, the internal resistance R means the resistance of the wiring connected from the drain of the output transistor 4 to the electrode pad P3 connected to the solder ball 12 as the output terminal. Therefore, in the present embodiment, this wiring resistance is illustrated as an internal resistance R connected between the electrode pad P2 and the drain of the output transistor 4 and the electrode pad P3.

  The electrode pad P 1 is connected to the source of the output transistor 4, and the electrode pad P 2 is connected to the drain of the output transistor 4. The non-inverting input terminal of the error amplifier 3 is connected to the positive side of the power source 6 and the negative side of the power source 4 is grounded. A switch SW is connected to the inverting input terminal of the error amplifier 3, and the switch SW is switched to the contact point a or the contact point b based on the switching signal CS from the external device. Here, when the switch SW is switched to the contact point b, the drain voltage of the output transistor 4 is input to the inverting input terminal of the error amplifier 3, and when the switch SW is switched to the contact point a, the voltage at the electrode pad P3 is changed to the error amplifier. 3 input to the inverting input terminal. That is, the switch SW is a switching unit that selectively outputs either the voltage at the electrode pad P2 or the voltage at the electrode pad P3 to the error amplifier 3 as a negative feedback voltage. Here, the switch SW is configured using a CMOS (complementary metal oxide semiconductor). Therefore, since the switch SW can be configured with a small transistor size, current consumption by the switch SW can be reduced.

  The operation of the semiconductor device 2 configured as described above will be described below.

  FIG. 5 is a schematic diagram for explaining the operation of the semiconductor device 2 of FIG. Here, the reference voltage Vref of the power source 6 is described as 1.2 volts (V). In FIG. 5, when the switch SW is switched to the contact a, the error amplifier 3 controls the output transistor 4 so that the voltage at the electrode pad P3 (the voltage at the point D) becomes 1.2 volts. In this case, even if a disconnection occurs in the through electrode TH2 or the rewiring 20, the error amplifier 3 outputs the output transistor so that the voltage at the electrode pad P3 (the voltage at the point D) becomes 1.2 volts. 4 is controlled, the voltage detected by the solder ball 12 is always about 1.2 volts. Therefore, it cannot be determined whether or not a disconnection has occurred in the through electrode TH2 or the rewiring 20.

  When the switch SW is switched to the contact point b, the error amplifier 3 controls the output transistor 4 so that the drain voltage (voltage at the point C) of the output transistor 4 becomes 1.2 volts. Accordingly, when no disconnection occurs in the through electrode TH2 or the rewiring 20, the resistance of the rewiring 20 (about 0.1 ohm) is smaller than the internal resistance R (about 4 ohm), and therefore the solder ball 12 The voltage detected at is the voltage at point C, which is about 1.2 volts. On the other hand, when a disconnection occurs in the through electrode TH2 or the rewiring 20, the load current I_load output from the output transistor 4 does not pass through the rewiring 20 but passes through the internal resistance R. Flows to 5. Therefore, the voltage at the point D detected by the solder ball 12 is smaller than the voltage at the point C (1.2 volts) by the voltage drop due to the internal resistance R (= load current I_load × 4 ohms).

  Next, the inspection method of the semiconductor device 2 described above will be described below.

  Using an external device, a switching signal CS indicating that the switch SW is switched to the contact a is input to the switch SW. In this case, the voltage of the electrode pad P3 is input to the inverting input terminal of the error amplifier 3 as a negative feedback voltage. With the switch SW connected to the contact a, the voltage at the solder ball 12 that is the output terminal of the semiconductor device 2 is measured.

  Next, using an external device, a switching signal CS indicating that the switch SW is switched to the contact b is input to the switch SW. In this case, the drain voltage (voltage at the point C) of the output transistor 4 is input to the inverting input terminal of the error amplifier 3 as a negative feedback voltage. With the switch SW connected to the contact b, the voltage at the solder ball 12 that is the output terminal of the semiconductor device 2 is measured.

  Next, the voltage at the solder ball 12 with the switch SW connected to the contact a is compared with the voltage at the solder ball 12 with the switch SW connected to the contact b, so that the second through electrode It is determined whether or not a disconnection has occurred in any of TH2 and rewiring 20. Here, when the voltage at the solder ball 12 with the switch SW connected to the contact b is lower than the voltage at the solder ball 12 with the switch SW connected to the contact a, the second through electrode TH2 And the rewiring 20 are determined to be defective products in which disconnection occurs. When the voltage at the solder ball 12 with the switch SW connected to the contact b and the voltage at the solder ball 12 with the switch SW connected to the contact a are the same, the second through electrode It is determined that the product is a non-defective product in which no disconnection occurs in TH2 and the rewiring 20

As described above, the semiconductor device according to the first aspect is
A semiconductor device mounting a semiconductor chip including an output transistor that converts an input voltage input to an input terminal into a first voltage and outputs the first voltage,
The semiconductor chip includes a first electrode pad connected to the output terminal of the output transistor, and a second electrode pad connected to the output terminal of the output transistor via an internal resistor,
The semiconductor device includes a first through electrode and a rewiring that connect the first electrode pad and an external terminal of the semiconductor device, and a second through that connects the second electrode pad and the rewiring. With electrodes,
The semiconductor chip is
An error amplifier that generates an error voltage between the first voltage and the negative feedback voltage, and that controls the output transistor to convert the input voltage to be input into the first voltage based on the error voltage;
And a switching unit that selectively outputs either the second voltage at the first electrode pad or the third voltage at the second electrode pad as the negative feedback voltage to the error amplifier.

  According to the semiconductor device of the first aspect, either the drain voltage of the output transistor or the voltage at the output terminal of the semiconductor device can be selectively output to the error amplifier as a negative feedback voltage. Therefore, when a disconnection occurs in the first route that is output from the output terminal via the rewiring having a low resistance, the voltage converted by the output transistor, the voltage converted by the output transistor is output via the internal resistance. Output from the terminal (second route). Therefore, the disconnection in the first route described above can be detected by monitoring the voltage at the output terminal and measuring the voltage drop due to the internal resistance.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
The switching unit connects either the first electrode pad or the second electrode pad to the error amplifier based on a switching signal input from the outside of the semiconductor device.

  According to the semiconductor device according to the second aspect, it is possible to easily determine the presence or absence of disconnection based on the switching signal input from the outside of the semiconductor device, and when there is no abnormality, input the signal from the outside again. Thus, the wiring state in the product state can be restored. Accordingly, since it is possible to inspect for disconnection without spending time, the throughput in the manufacturing process can be improved.

A semiconductor device according to a third aspect is the semiconductor device according to the first or second aspect,
The semiconductor device is formed of a chip size package or a wafer level chip size package.

A semiconductor device according to a fourth aspect is the semiconductor device according to the first to third aspects,
The switching unit is a switch configured using a complementary metal oxide semiconductor.

  According to the semiconductor device according to the fourth aspect, it is possible to determine whether or not the rewiring is disconnected in the semiconductor device only by providing a simple switch on the wiring. Therefore, since the switch can be formed by using the empty space in the semiconductor chip, it is possible to prevent an increase in circuit scale and power consumption.

A semiconductor device inspection method according to a fifth aspect is the semiconductor device inspection method according to the first aspect, wherein:
Switching the second voltage to be output to the error amplifier as the negative feedback voltage and measuring a fourth voltage at the external terminal;
Switching to output the third voltage as the negative feedback voltage to the error amplifier and measuring a fifth voltage at the external terminal;
Comparing the fourth voltage with the fifth voltage and determining whether or not a break has occurred in any of the second through electrode and the rewiring.

A semiconductor device inspection method according to a sixth aspect is the semiconductor device inspection method according to the fifth aspect,
When the fourth voltage is lower than the fifth voltage, it is determined as a defective product in which disconnection has occurred in any of the second through electrode and the rewiring, and the fourth voltage When the first voltage and the fifth voltage are the same, it is determined that the product is a non-defective product in which no disconnection occurs in any of the second through electrode and the rewiring.

  In the embodiment described above, switching of the negative feedback voltage input to the error amplifier 3 has been described using the switch SW, but the present disclosure is not limited to this. For example, the negative feedback voltage input to the error amplifier 3 may be switched using a fuse instead of the switch SW. Even in this case, the same effect as the present embodiment can be obtained.

  As described above in detail, according to the semiconductor device according to the present disclosure, it is possible to determine disconnection of rewiring in the semiconductor device only by providing a switch in the semiconductor chip. Accordingly, the wiring area in the semiconductor chip can be reduced.

1 ... Semiconductor chip,
2 ... Semiconductor device,
3 ... error amplifier,
4 ... Output transistor,
5 ... Load,
6 ... Power supply,
7 ... 1st insulating layer,
8 ... the second insulating layer,
10, 20 ... rewiring,
11, 12 ... solder balls,
15 ... Constant voltage circuit.

Claims (6)

A semiconductor device mounting a semiconductor chip including an output transistor that converts an input voltage input to an input terminal into a first voltage and outputs the first voltage,
The semiconductor chip includes a first electrode pad connected to the output terminal of the output transistor, and a second electrode pad connected to the output terminal of the output transistor via an internal resistor,
The semiconductor device includes a first through electrode and a rewiring that connect the first electrode pad and an external terminal of the semiconductor device, and a second through that connects the second electrode pad and the rewiring. With electrodes,
The semiconductor chip is
An error amplifier that generates an error voltage between the first voltage and the negative feedback voltage, and that controls the output transistor to convert the input voltage to be input into the first voltage based on the error voltage;
A switching device that selectively outputs either the second voltage at the first electrode pad or the third voltage at the second electrode pad as the negative feedback voltage to the error amplifier. .   The semiconductor device according to claim 1, wherein the switching unit connects either the first electrode pad or the second electrode pad to the error amplifier based on a switching signal input from the outside of the semiconductor device. .   3. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a chip size package or a wafer level chip size package. The semiconductor device according to claim 1 , wherein the switching unit is a switch configured using a complementary metal oxide semiconductor. An inspection method for a semiconductor device according to claim 1,
Switching the second voltage to be output to the error amplifier as the negative feedback voltage and measuring a fourth voltage at the external terminal;
Switching to output the third voltage as the negative feedback voltage to the error amplifier and measuring a fifth voltage at the external terminal;
A step of comparing the fourth voltage with the fifth voltage to determine whether or not a break has occurred in any of the second through electrode and the rewiring. Inspection method. When the fourth voltage is lower than the fifth voltage, it is determined as a defective product in which disconnection has occurred in any of the second through electrode and the rewiring, and the fourth voltage 6. The semiconductor according to claim 5 , wherein when the voltage of the second and the fifth voltage are the same, the semiconductor device is determined to be a non-defective product in which no disconnection occurs in any of the second through electrode and the rewiring. Device inspection method.

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