JP6424570B2 - Electronic component built-in substrate and method of manufacturing the same - Google Patents

Description

  The present invention relates to an electronic component built-in substrate including a core substrate, an electronic component mounted on one main surface of the core substrate, and a buried layer provided by embedding the electronic component, and a method of manufacturing the same. .

  In recent years, in response to the thinning of portable electronic devices, an electronic component built-in substrate in which the thinning of the substrate is achieved by embedding the electronic components inside the substrate as disclosed in International Publication No. 2011/135926 (Patent Document 1). Has been proposed.

  FIG. 8 is a cross-sectional view of the electronic component built-in substrate 100 described in Patent Document 1. As shown in FIG. In the electronic component built-in substrate 100 described in FIG. 8, the electronic components 101 and 102 are mounted on the core substrate 108, and the embedded layer 109 is formed so that the electronic components 101 and 102 are embedded.

  Such an electronic component built-in substrate 100 is light in weight and does not involve high-temperature firing like a ceramic substrate, so that there is an advantage that the built-in electronic components are less restricted.

  Here, a multilayer ceramic capacitor is considered as the electronic components 101 and 102 embedded in the embedded layer 109 of the electronic component embedded substrate 100 described in Patent Document 1. FIG. 9 shows a cross-sectional view of the laminated ceramic capacitor 201. As shown in FIG.

  The multilayer ceramic capacitor 201 includes a ceramic laminate 202, and a first outer electrode 203 and a second outer electrode 204 provided on the surface of the ceramic laminate 202. The ceramic laminate 202 is formed by connecting in parallel capacitor elements formed by inserting the ceramic dielectric layer 205 between the first inner electrode 206 and the second inner electrode 207 in parallel. Such a multilayer ceramic capacitor 201 is excellent in reliability and durability, and can realize small size and large capacity.

  The small-sized large-capacitance multilayer ceramic capacitor 201 often uses a ceramic material having a high dielectric constant, which is mainly composed of barium titanate, as a material of the ceramic dielectric layer 205 constituting the ceramic laminate 202. When a voltage is applied to the laminated ceramic capacitor 201 including such a ceramic laminate 202, distortion corresponding to the magnitude of the applied voltage is generated in the ceramic laminate 202 due to the electrostrictive effect and the reverse piezoelectric effect. Accordingly, the ceramic laminate 202 repeats expansion in the stacking direction and contraction in the plane direction orthogonal to the stacking direction.

  In recent years, with the progress of miniaturization and thinning of the multilayer ceramic capacitor 201, the strength of the electric field applied to the dielectric has become high, so the degree of distortion of the above-mentioned ceramic laminate 202 is also increasing.

  Here, as shown to FIG. 10 (A), the case where the laminated ceramic capacitor 201 is mounted in the board | substrate B by the solder S is considered. When a voltage is applied to the laminated ceramic capacitor 201, distortion generated in the ceramic laminated body 202 vibrates the substrate B fixed to the laminated ceramic capacitor 201 via the solder S, as shown in FIG. 10B. Let

  Such vibration of the substrate B may cause a malfunction of the acceleration sensor when an acceleration sensor such as a shock sensor is mounted on the substrate B, for example.

  Also, when the frequency is in the audible range of 20 Hz to 20 kHz, it is recognized as an audible sound by the human ear. This phenomenon is also referred to as "acoustic noise", and has become a design issue in power supply circuits of various applications such as laptop computers, mobile phones, digital cameras, etc., along with the quietness of electronic devices.

International Publication No. 2011/135926

  When the multilayer ceramic capacitor 201 is mounted on the substrate B by the solder S as described above and is further embedded in the embedded layer as described in Patent Document 1, the solder S and the embedded layer both cause distortion of the ceramic laminate 202. It is conceivable to transmit to B. In that case, there is a concern that the above-mentioned vibration of the substrate B becomes large and the audible sound becomes large.

  Therefore, it is an object of the present invention to reduce vibration even if distortion occurs due to the application of a voltage to an electronic component embedded in the embedded layer including the resin material portion, and further prevent or reduce the generation of audible sound due to the vibration. An electronic component built-in substrate and a method of manufacturing the same.

  In the present invention, even if distortion occurs due to the application of a voltage to the electronic component embedded in the embedded layer, the vibration of the electronic component built-in substrate is reduced, and the generation of audible sound due to the vibration is prevented or reduced. An improvement in the layer thickness is achieved.

  The present invention is first directed to an electronic component built-in substrate.

  An electronic component built-in substrate according to the present invention comprises a core substrate having parallel one main surface and the other main surface, at least one electronic component mounted on one main surface of the core substrate, and a buried layer. .

  The electronic component described above is a multilayer capacitor including a multilayer body, and a first external electrode and a second external electrode provided on the surface of the multilayer body.

  The laminate includes a capacitance developing portion on which a capacitor element in which a dielectric layer is inserted between the first internal electrode and the second internal electrode is stacked, and a first portion sandwiching the capacitance developing portion. And a second protection portion. The first outer electrode is connected to the first inner electrode. The second outer electrode is connected to the second inner electrode.

  The material of the dielectric in the multilayer capacitor described above is not particularly limited as long as distortion can be generated by the application of a voltage.

  The buried layer described above is provided on the one main surface of the core substrate such that the electronic component is buried, and the outer surface is parallel to the one main surface of the core substrate.

And, when the thickness T _R of the buried layer, the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, the elastic modulus E _B of the core substrate, and the one main surface of the core substrate as a reference plane the height T _C of the center of the capacity expression unit, thereby satisfying the expression (1).

In the electronic component built-in substrate described above, and the thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, the core substrate and the elastic modulus E _B, the center of the electrostatic capacity developing unit The height T _C satisfies the relationship represented by equation (1).

Electronic-part built-in substrate is embedded by subtracting the core substrate, a first portion of the buried layer having a respective thickness T _C from the center to the upper and lower capacitance expression unit of the electronic component, the first portion from the buried layer total thickness And the second part of the layer.

  Here, the first part of the buried layer is substantially symmetrical in the vertical direction of the central surface of the capacitance developing portion, and even if distortion occurs in the electronic component, the upper portion of the central surface of the capacitance developing portion The layer and the lower layer are considered to vibrate so as to cancel each other's vibration.

  The relationship represented by the above equation (1) is that the core substrate and the second portion of the buried layer, including the interaction with the first portion of the buried layer, are viewed from the center plane of the capacitance developing portion, It is inferred that it represents a condition that vibrates so as to cancel each other's vibration.

  Therefore, the vibration of the electronic component built-in substrate can be reduced and the generation of the audible sound due to the vibration can be prevented or reduced by satisfying the relationship expressed by the equation (1) for each component in the electronic component built-in substrate. it can.

A first preferred embodiment of the electronic component-embedded board according to the present invention, the thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, and the elastic modulus of the core board E _B , the height T _C of the center of the electrostatic capacity developing unit when the one main surface of the core substrate as a reference plane, in addition to the above (1), further (2) to (4) I am satisfied.

In the electronic component built-in substrate described above, and the thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, the core substrate and the elastic modulus E _B, the center of the electrostatic capacity developing unit The height T _C satisfies the relationship represented by the equations (1) to (4).

  By defining each component in the electronic component built-in substrate as represented by the above equations (2) to (4), the core substrate and the second portion of the buried layer are the first portion of the buried layer It is surmised that, as seen from the center plane of the capacitance developing portion, including the interaction with the above, it vibrates so as to cancel each other's vibration reliably.

  Therefore, when each component in the electronic component built-in substrate satisfies the relationship represented by the equations (1) to (4), the vibration of the electronic component built-in substrate is reliably reduced, and further the generation of an audible sound due to the vibration Can be reliably prevented or reduced.

  In the second preferred embodiment of the electronic component built-in substrate according to the present invention, the thickness of the first protective portion of the electronic component is larger than the thickness of the second protective portion. Furthermore, the electronic component is mounted such that the first protective portion is on the one main surface side of the core substrate.

  In the electronic component built-in substrate described above, the center of the capacitance developing portion of the electronic component is closer to the one main surface of the core substrate than in the case where the first protective portion and the second protective portion have the same thickness. It is in a high position.

  It has been separately confirmed that the vibration of the electronic component built-in substrate can be effectively reduced by mounting the electronic component having the above structure on the core substrate.

  Therefore, the size of each component in the electronic component built-in substrate satisfies the relationship between the above-described embodiment and the first preferred embodiment, whereby the electronic component built-in substrate has already been reduced to some extent even in the absence of the buried layer. Can be further reduced, and the generation of audible sound due to the vibration can be further reliably prevented or reduced.

  The present invention is also directed to a method of manufacturing an electronic component built-in substrate.

  A method of manufacturing an electronic component built-in substrate according to the present invention includes: a core substrate having parallel one main surface and the other main surface; at least one electronic component mounted on one main surface of the core substrate; . A method of manufacturing an electronic component built-in substrate comprising:

  The electronic component described above is a multilayer capacitor including a multilayer body, and a first external electrode and a second external electrode provided on the surface of the multilayer body.

  The laminate includes a capacitance developing portion on which a capacitor element in which a dielectric layer is inserted between the first internal electrode and the second internal electrode is stacked, and a first portion sandwiching the capacitance developing portion. And a second protection portion. The first outer electrode is connected to the first inner electrode. The second outer electrode is connected to the second inner electrode.

  The buried layer described above is provided on the one main surface of the core substrate such that the electronic component is buried, and the outer surface is parallel to the one main surface of the core substrate.

  A method of manufacturing an electronic component built-in substrate according to the present invention includes a mounting step and a buried layer forming step.

  The mounting step is a step of mounting the electronic component on one main surface of the core substrate.

The buried layer forming step is a step of providing a buried layer in which the electronic component is buried on one main surface of the core substrate. In the buried layer forming step, the buried layer R has a thickness T _R of the buried layer, a modulus E _R of the buried layer, a thickness T _B of the core substrate, a modulus E _B of the core substrate, and one of the core substrates. and height T _C of the center of the electrostatic capacity developing unit upon a reference plane surface is provided so as to satisfy the expression (1).

  In the method of manufacturing an electronic component built-in substrate described above, in the embedded layer forming step, the embedded layer is formed such that each component in the electronic component built-in substrate satisfies the relationship represented by the formula (1).

  Therefore, it is possible to efficiently manufacture the electronic component-embedded substrate in which the vibration in the above-mentioned audible frequency range is small and the generation of the audible sound is prevented or reduced.

A first preferred embodiment of the method of manufacturing an electronic component-embedded substrate according to the present invention, the buried layer forming step, the buried layer R has a thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the core substrate of the thickness T _B, and the elastic modulus E _B of the core substrate, the height T _C of the center of the electrostatic capacity developing unit when the one main surface of the core substrate as a reference plane, the above formula (1) In addition, it is provided to further satisfy the expressions (2) to (4).

  In the method of manufacturing an electronic component-embedded substrate described above, in the embedded layer forming step, the embedded layer is formed such that each component in the electronic component-embedded substrate satisfies the relationship represented by the equations (1) to (4). .

  Therefore, it is possible to efficiently manufacture the electronic component-embedded substrate in which the vibration in the above-mentioned audible frequency range is smaller and the generation of the audible sound is reliably prevented or reduced.

The electronic-part built-in substrate according to the present invention, the thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the core substrate and the thickness T _B of the core substrate and the elastic modulus E _B, the capacitance expression of The center height T _c satisfies the relationship represented by the above-mentioned equation (1).

  Therefore, even if distortion occurs due to the application of voltage to the electronic component embedded in the embedded layer, the vibration of the electronic component built-in substrate can be reduced, and the generation of audible sound due to the vibration can be prevented or reduced.

  Further, in the method of manufacturing an electronic component built-in substrate according to the present invention, in the embedded layer forming step, the embedded layer is formed such that each component in the electronic component built-in substrate satisfies the relationship represented by the above equation (1). Do.

  Therefore, it is possible to efficiently manufacture the electronic component-embedded substrate in which the vibration in the above-mentioned audible frequency range is small and the generation of the audible sound is prevented or reduced.

FIG. 1 is a top view of an electronic component built-in substrate 1 according to an embodiment of the present invention. FIG. 1 is a cross-sectional view of an electronic component built-in substrate 1 according to an embodiment of the present invention. (A) is arrow sectional drawing of the surface containing the Y1-Y1 line | wire of FIG. (B) is arrow sectional drawing of the surface containing the X1-X1 line | wire of FIG. It is an appearance perspective view for explaining deflection amount h when external force F acts on plate-like member PM. It is a graph which shows the result of having calculated | required the relationship between the thickness of the embedding layer R provided in the electronic component built-in substrate 1, and sound pressure by simulation. It is sectional drawing corresponded in FIG. 1 of the modification 1A of the electronic component built-in substrate concerning an embodiment of this invention. FIG. 3 is a view for schematically illustrating an example of a mounting process, for explaining an example of a method of manufacturing the electronic component built-in substrate 1 shown in FIG. 1 and FIG. 2. FIG. 3 is a view for schematically illustrating an embedded layer forming step, for explaining an example of a method of manufacturing the electronic component built-in substrate 1 shown in FIG. 1 and FIG. 2. It is sectional drawing of the electronic component built-in board | substrate 100 of background art. It is sectional drawing of a laminated ceramic capacitor for demonstrating the subject which this invention tends to solve. It is sectional drawing of the state which mounted the laminated ceramic capacitor in the board | substrate for demonstrating the subject which this invention tends to solve. (A) is a state where no voltage is applied. (B) is a schematic sectional drawing explaining the state of distortion when a voltage is applied.

  Hereinafter, the features of the present invention will be described in more detail by showing embodiments of the present invention.

-Embodiment of electronic component built-in substrate-
An electronic component built-in substrate 1 according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG.

<Structure of Electronic Component Built-in Substrate>
FIG. 1 is a top view of an electronic component built-in substrate 1 according to an embodiment of the present invention. FIG. 2A is an arrow sectional view of a plane including the Y1-Y1 line of FIG. FIG. 2 (B) is an arrow sectional view of a plane including line X1-X1 of FIG.

  The electronic component built-in substrate 1 according to the embodiment of the present invention includes a core substrate B, an electronic component 10, and a buried layer R. The electronic component 10 is mounted on one main surface of the core substrate B having one main surface and the other main surface parallel to each other in the error range. The buried layer R embeds the electronic component 10 on one main surface of the core substrate B, and the outer surface is parallel to the one main surface of the core substrate B in the error range.

  In the electronic component built-in substrate 1 according to the embodiment of the present invention, the embedded layer R includes a resin material portion. The resin material portion is formed using a resin material in which a glass material, silica or the like is dispersed as a filler as described later. In addition to the resin material portion, the buried layer R may further include a conductive material portion provided on the surface of the resin material portion (not shown in FIGS. 1 and 2).

  The core substrate B is a multilayer substrate corresponding to FIG. 6 described above, and is illustrated in a simplified manner with internal electrodes, vias, etc. not shown. Further, in the embodiment of the present invention, in order to emphasize the electronic component 10, the relationship in size between the core substrate B and the electronic component 10 is different from the actual one.

  The electronic component 10 is a multilayer ceramic capacitor including the ceramic laminate 11 and the first external electrode 12 and the second external electrode 13. The ceramic laminate 11 has a first capacitance developing portion CP in which a capacitor element in which the ceramic dielectric layer 14 is inserted between the first internal electrode 15 and the second internal electrode 16 is stacked. It is the structure pinched | interposed by the ceramic protection part P1 and the 2nd ceramic protection part P2.

  The ceramic laminate 11 has two end surfaces facing each other, and a side surface connecting the two end surfaces. The first outer electrode 12 is connected to the first inner electrode 15, and the second outer electrode 13 is connected to the second inner electrode 16. The first external electrode 12 and the second external electrode 13 are provided on the surface of the ceramic laminate 11, respectively.

  In the above embodiment, although the case where the electronic component 10 is a multilayer ceramic capacitor has been described, as described above, the material of the dielectric is a ceramic material if distortion can be generated by the application of a voltage. It is not limited. For example, the present invention can be applied to a laminated metallized film capacitor which is a laminated capacitor using a resin material as a dielectric material other than a ceramic material.

  In FIGS. 2A and 2B, the electronic component 10 is mounted on the mounting lands L11 and L12 using the solder S. The material of the mounting lands L11 and L12 and the material of the solder S can be appropriately selected from existing ones and used. The mounting lands L11 and L12 are on the wiring including the conductive pattern not shown. A voltage is applied to the electronic component 10 through the wiring.

  A plurality of electronic components 10 may be mounted on the electronic component built-in substrate 1 according to the embodiment of the present invention. Similarly, electronic components other than the multilayer ceramic capacitor may be mounted on the electronic component built-in substrate 1.

  The electronic component 10, which is a multilayer ceramic capacitor, often uses a ceramic material having a high dielectric constant and having barium titanate as a basic material, and may vibrate due to distortion when a voltage is applied. This vibration is transmitted to the substrate B fixed to the electronic component 10 through the solder S, but in the case where the electronic component 10 is embedded in the embedded layer R, the substrate B is also interposed through the embedded layer R Transmitted to

The buried layer R has a thickness T _R of the buried layer, an elastic modulus E _R of the buried layer, a thickness T _B of the core substrate, an elastic modulus E _B of the core substrate, and one main surface of the core substrate B as a reference surface. and height T _C of the center of the electrostatic capacity developing unit when the satisfies the equation (1), preferably formed so as to further satisfy the expression (2) to (4) below.

As described above, the electronic component built-in substrate 1 includes the core substrate B and the first portion R ₁ of the buried layer having the thickness T _C from the center of the capacitance developing portion CP of the electronic component 10 respectively and the buried layer a second portion R ₂ of the buried layer from the total thickness minus a first portion configured to include three parts.

Here, the first portion R ₁ because it contains the solder and the mounting land L11 and L12 S, more precisely, at the vertical symmetry with respect to the center plane of the capacitance expression unit CP of the electronic component 10 Absent. However, the mounting lands L11 and L12 and the solder S are thinner than the thickness of the buried layer R and can be neglected in order to simplify the structure.

That is, in the first part R _1, and the upper layer and lower layer of the central plane of the electrostatic capacity developing unit CP, is considered to be substantially symmetrical. In that case, even if the distortion due to the application of a voltage to the internal electronic components 10 of the first portion R ₁ has occurred, the upper layer and lower layer of the central plane of the electrostatic capacity developing unit CP, the vibration of each other It will vibrate so as to cancel each other.

Thus, since the vibration of the electronic component-embedded substrate 1 is reduced, the second portion of the buried layer R ₂ and the core substrate B is viewed from the center plane of the capacitance expression unit CP, cancel the vibration of each other It should be vibrated to fit.

  Generally, a single plate-like member PM having a distance L between fulcrums as shown in FIG. 3A, a width W, a thickness T and an elastic modulus E by the action of an external force F as shown in FIG. When deflection occurs, the deflection amount h is expressed by equation (5).

The deflection amount h of the second portion R ₂ and the core substrate B becomes when applied as a reverse direction at the same size (5) and (6).

The length L _R of length L _B and buried layer R of the core substrate B, and as the width W _B of the core substrate and the width W _R of the buried layer R and is equal to, and solving for T _R (6) Equation (7 It becomes an equation.

(7), the deflection of the second portion R ₂ of the core substrate B and buried layer when a reverse direction at the same size, that is, the second portion R ₂ of the core substrate B and buried layer, of each other It shows the case where it vibrates so as to cancel the vibration.

However, in practice, the second portion R ₂ is a first portion overlying layers of R _1, when vibration, mutually affect one another due to factors that are not taken into account. Similarly, the core substrate B and the lower layer of the first portion R1 mutually influence each other due to factors not considered when vibrating. Therefore, the second portion R ₂ and the core substrate B, can not be treated as that vibrates alone respectively.

Therefore, in consideration of the above interaction, the thickness T _{R of the} buried layer and the thickness T _{B of the} core substrate are variables, and the ratio E _B / elastic modulus E _B of the core substrate to the elastic modulus E _R of the buried layer A linear equation was assumed in which the center height T _{C of} E _R and the capacity development portion is a constant. Then, using the index m of the power of the ratio E _B / E _R between the elastic modulus E _{B of the} core substrate and the elastic modulus E _R of the buried layer, which is 1⁄3 in the equation (7), the actual vibration Based on the conditions, vibrational conditional expressions were obtained. That is, the above linear equation is expressed by equation (8).

Here, the vibration parameter VP indicating the vibration of the electronic component-embedded substrate 1 is represented by equation (8) on the right side was divided by the thickness T _R of the buried layer (9).

  When the vibration parameter VP is 1, the vibration of the electronic component built-in substrate 1 is minimized. On the other hand, the more the vibration parameter VP is away from 1, the larger the vibration of the electronic component built-in substrate 1.

  As a result of intensive studies, the present inventor has found that by controlling the vibration parameter VP, it is possible to control the vibration of the electronic component built-in substrate and the generation of an audible sound based thereon, and have made the present invention. At that time, the magnitude of the sound pressure corresponding to the vibration of the substrate in the state where the electronic component 10 is not embedded in the buried layer R is the reference sound pressure, and the range of the vibration parameter VP corresponding to the range smaller than the reference sound pressure Defined. The sound pressure is obtained by converting the largest amplitude of the vibrations generated in the audible range into the size of the sound.

  That is, in the present invention, based on the above technical idea, the inventor of the present invention has specified the upper limit value A and the lower limit value B of the vibration parameter VP smaller than the reference sound pressure and the exponent m of the power.

  The manner of defining the upper limit value A and the lower limit value B of the vibration parameter VP and the value of the exponent m of the power will be specifically described below.

The relationship between the thickness T _{R of the} buried layer provided on one main surface of the electronic component-embedded substrate 1 and the sound pressure corresponding to the magnitude of vibration is based on the finite element method for the elastic modulus E _R of various buried layers. Obtained by simulation. Then, by comparing with the simulation result, the upper limit value A and the lower limit value B of the vibration parameter VP, and the exponent m of the exponent are determined.

4, the thickness T _R of the electronic components provided on one main surface of the built-in substrate 1 buried layer, the relationship between the sound pressure corresponding to the magnitude of the vibration, the results obtained by simulation based on the finite element method FIG.

  The sound pressure represents the magnitude of the sound (so-called "squeal") generated in the L direction of the electronic component 10 (the direction parallel to the core substrate B in FIG. 2B). In the simulation, it is assumed that the electronic component 10 is mounted such that the internal electrodes 15 and 16 are parallel to the core substrate B.

The thickness T _B of the core substrate is 0.8 mm, elasticity modulus E _B of the core substrate 20 GPa, high T _C of the center of the electrostatic capacity developing unit is set to 0.315 mm. Modulus E _B of the core substrate B uses a value plausible as the elastic modulus generally glass epoxy substrate used (flexural modulus). Electronic component 10, as the length of the L direction is embedded in the buried layer R of 24 mm, and calculating the change in sound pressure due to the change of the thickness T _R of the buried layer.

FIG. 4 shows three simulation results when the elastic modulus E _R of the buried layer is 15 GPa, 25 GPa and 35 GPa. First, in order to determine the value of the exponent m of the vibration parameter VP, buried layer and the second portion R ₂ of the buried layer and the core substrate B has a minimum sound pressure cancel each other a vibration of one another attention is paid to the thickness T _R. When the elastic modulus E _R of the buried layer is each value described above, the thickness T _{R of the} buried layer at which the sound pressure is a minimum value is about 1.6 mm, about 1.3 mm and about 1.15 mm, respectively.

Here, assuming that the exponent m of the exponent is 3/4 and the elastic modulus E _R of the buried layer is 15 GPa, 25 GPa and 35 GPa, the thickness T _R of the buried layer is calculated by the equation (9) to be 1.62 mm and 1.31 mm, respectively. And 1.16 mm, which reproduces the simulation results very well.

Moreover, even without not cancel completely the vibration of each other, the magnitude of the vibration of the electronic component-embedded substrate 1 (loudness associated with it), by burying layer R of the thickness T _R is formed, buried layer It should be smaller than the state without R.

The range of thickness T _R of such buried layer obtained from the simulation results shown in FIG. As a result, when the elastic modulus E _R of the buried layer is 15 GPa, when T _R is 1.3 to 2.1, the magnitude of the vibration of the electronic component built-in substrate 1 is smaller than that in the state without the buried layer R. It turned out that it became. Similarly, when the elastic modulus E _R of the buried layer is 25 GPa and 35 GPa, and the T _R is 1.1 to 1.55 and 1.0 to 1.3, respectively, the magnitude of the vibration of the electronic component built-in substrate 1 However, it turned out that it becomes smaller than the state without the embedding layer R.

  As described above, when the vibration parameter VP is matched with the simulation result of FIG. 4, the exponent m of the exponent is 3/4, the upper limit A of the vibration parameter VP is 1.2, and the lower limit B is 0.8. I understand.

These values, in simplified structure, and a second portion R ₂ of the core substrate B and buried layer, including the interaction of the first portion R ₁ of the aforementioned buried layer, the capacitance expression unit CP Seeing from the center plane of, it is considered to represent a condition that vibrates so as to cancel each other's vibration.

That is, when the thickness T _R of the buried layer, the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, the elastic modulus E _B of the core substrate, and one main surface of the core substrate B as a reference surface relationship between the height T _C of the center of the electrostatic capacity developing unit, when satisfying the expression (1), is reduced vibration of the electronic component-embedded substrate 1, occurrence of audible sound is prevented or reduced by further vibration Ru. Therefore, the sound pressure of the audible sound due to the vibration of the electronic component built-in substrate 1 becomes smaller than the reference sound pressure.

Further, from the above-mentioned ranges of T _R and E _R and the values of T _B , T _C and E _B , the thickness T _R of the buried layer, the elastic modulus E _R of the buried layer, and the thickness T _{B of the} core substrate The elastic modulus E _B of the core substrate and the height T _C of the center of the capacitance developing portion when one main surface of the core substrate is a reference surface are added to the above equation (1), (2) When the equations (4) are further satisfied, the vibration of the electronic component built-in substrate 1 is reliably reduced, and the generation of an audible sound due to the vibration is reliably prevented or reduced.

<Modification of Embodiment>
A modification 1A of the electronic component built-in substrate according to the embodiment of the present invention will be described with reference to FIG.

  FIG. 5 is a cross-sectional view of a modification 1A of the electronic component built-in substrate according to the embodiment of the present invention. 5A corresponds to an arrow sectional view (FIG. 2A) of a plane including the Y1-Y1 line in FIG. FIG. 5B corresponds to an arrow sectional view (FIG. 2B) of a plane including the X1-X1 line in FIG.

  In the modification 1A of the electronic component built-in substrate according to the embodiment of the present invention, the thickness of the first ceramic protective portion P1 of the electronic component 10 is larger than the thickness of the second ceramic protective portion P2. Furthermore, the electronic component 10 is mounted such that the first ceramic protective portion P1 is on the one main surface side of the core substrate B. The core substrate B is illustrated in a simplified manner as in the above-described embodiment.

  In the modification 1A of the electronic component built-in substrate according to the embodiment of the present invention, the center of the capacitance developing portion CP of the electronic component 10 has the same thickness as the first ceramic protective portion P1 and the second ceramic protective portion P2. The position from the one main surface of the core substrate B is higher than that in the case of having the

  For example, JP-A-2013-65820 describes that by mounting the electronic component 10 having the above structure on the core substrate B, the vibration of the electronic component built-in substrate can be effectively reduced.

  Therefore, when the dimensions of each component in the electronic component built-in substrate 1A satisfy the above relationship, the vibration of the electronic component built-in substrate, which has already been reduced to a certain degree, is further reduced even when the embedded layer R is not present. Generation of an audible sound can be further reliably prevented or reduced.

<Method of manufacturing electronic component built-in substrate>
An example of a method of manufacturing the electronic component built-in substrate 1 according to the embodiment of the present invention will be described with reference to FIGS. 6 and 7. 6 and 7 schematically show the mounting step and the buried layer forming step sequentially performed in an example of the method of manufacturing the electronic component built-in substrate 1. 6 and 7 correspond to an arrow sectional view (FIG. 2 (A)) of a plane including the Y1-Y1 line of FIG.

<Mounting process>
FIGS. 6A and 6B schematically show the mounting process of the method of manufacturing the electronic component built-in substrate 1. By the mounting step, the electronic component 10 is mounted on the one main surface of the core substrate B.

  FIG. 6A shows a stage of preparing the electronic component 10 and the core substrate B on which the electronic component 10 is mounted. The electronic component 10 is a laminated ceramic capacitor having the above-described structure and in which distortion occurs when a voltage is applied. The core substrate 10 includes mounting lands L11 and L12 (L12 is not shown) for joining the electronic components 10 on one main surface.

  FIG. 6B shows a stage in which the electronic component 10 is mounted on one main surface of the core substrate 10 by bonding the mounting lands L11 and L12 with the solder S.

At this time, the center plane of the capacitance expression unit CP, when taken as a reference plane to the main surface of the core substrate B, and a height T _C.

<Burying layer formation process>
FIGS. 7A and 7B are diagrams schematically showing a buried layer forming step of the method of manufacturing the electronic component built-in substrate 1. In the embedded layer forming step, the embedded layer R is provided on the one main surface of the core substrate B so that the electronic component 10 is embedded.

  FIG. 7A shows a step of applying a liquid resin LR to one main surface of the core substrate B on which the electronic component 10 is mounted by, for example, a dispenser D so as to have a predetermined thickness represented by an alternate long and short dash line. Indicates

  The apparatus used for application | coating can use not only said dispenser D but the existing application apparatus. For example, various coaters such as a curtain coater and a spin coater may be used.

  Further, the liquid resin LR is not limited to one made of a single resin material, and a resin material containing a filler such as a glass material or silica as a filler can be used.

  Further, the embedded layer R is not limited to the method of applying the liquid resin LR as shown in FIG. 7A, but a sheet-like prepreg in a semi-cured state is mounted on one main surface of the core substrate B 10 may be formed by pressing so as to be embedded.

  FIG. 7B shows a stage in which the liquid resin LR in which the electronic component 10 is embedded is heated and cured to form the embedded layer R after curing.

At this time, the embedded layer R after curing has a thickness T _R , an elastic modulus E _R of the embedded layer, a thickness T _B of the core substrate, an elastic modulus E _B of the core substrate, and a center of the capacitance developing portion. of the height T _C is formed so as to satisfy the expression (1).

Relationship expressed by the above equation (1), as described above, including the interaction of the second portion R ₂ of the core substrate B and buried layer, a first portion R ₁ of the buried layer, electrostatic When viewed from the center plane of the capacity expression portion CP, it is considered to represent a condition that vibrates so as to cancel each other's vibration.

  That is, when each component in the electronic component built-in substrate 1 satisfies the relationship represented by the equation (1), the vibration of the electronic component built-in substrate 1 is reduced, and the generation of the audible sound due to the vibration is prevented or reduced. Ru.

  Therefore, in the embedded layer forming step, by forming the embedded layer R so that each component in the electronic component built-in substrate 1 satisfies the relationship represented by the equation (1), the vibration in the above-mentioned audio frequency range It is possible to efficiently manufacture a smaller electronic component-embedded substrate in which generation of an audible sound is reliably prevented or reduced.

  In the embedded layer formation step, the embedded layer R is provided such that each component in the electronic component built-in substrate 1 further satisfies the expressions (2) to (4) in addition to the expression (1) above. Being preferred.

  In the embedded layer forming step, by forming the embedded layer R so that each component in the electronic component built-in substrate 1 satisfies the relationship represented by the equations (1) to (4), the above-mentioned audible frequency range can be obtained. The electronic component-embedded substrate can be efficiently manufactured, in which the vibration of the electronic component is smaller and the generation of the audible sound is reliably prevented or reduced.

Adjustment of the thickness T _R of the buried layer, in anticipation of volume change upon curing of the resin LR liquid, after curing the resin LR liquid may be applied to a thickness of T _R. Further, the resin LR liquid was coated in advance larger amount, by removing the excess resin after curing, the thickness T _R of the buried layer may be a desired value.

  The present invention is not limited to the above embodiment, and various applications and modifications can be made within the scope of the present invention.

1 Electronic Component Built-in Substrate 10 Electronic Component (Multilayer Ceramic Capacitor)
11 ceramic laminated body 12 first external electrode 13 second external electrode 14 ceramic dielectric layer 15 first internal electrode 16 second internal electrode B core substrate CP electrostatic capacity developing portion P1 first ceramic protective portion P2 modulus of elasticity of the second ceramic protective part R buried layer T _C electrostatic modulus of the center of the height T _B core substrate having a thickness E _B core substrate of capacity developing unit T _R buried layer thickness E _R buried layer

Claims (5)

A core substrate having parallel one main surface and the other main surface,
At least one electronic component mounted on one main surface of the core substrate;
An electronic component built-in substrate comprising: an embedding layer on the one main surface of the core substrate, wherein the electronic component is embedded and an outer surface is provided parallel to the one main surface of the core substrate;
The electronic component includes: a capacitance developing portion in which a capacitor element in which a dielectric layer is inserted between a first internal electrode and a second internal electrode is stacked; A laminate including the first protective portion and the second protective portion, and a first external electrode provided on the surface of the laminate and connected to the first internal electrode and connected to the second internal electrode A second external electrode to be
Electrostatic when the thickness T _R of the buried layer, the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, the elastic modulus E _B of the core substrate, and one main surface of the core substrate as a reference plane The center height T _C of the capacity expression portion is

An electronic component built-in substrate characterized by satisfying the above. And the thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, and the elastic modulus E _B of the core substrate, and the one main surface of the core substrate as a reference surface When the center height T _C of the capacitance developing portion,

The electronic component built-in substrate according to claim 1, further satisfying: The thickness of the first protective portion of the electronic component is thicker than the thickness of the second protective portion,
The electronic component built-in substrate according to claim 1, wherein the electronic component is mounted such that the first protective portion is on the one main surface side of the core substrate. A core substrate having parallel one main surface and the other main surface, at least one electronic component mounted on one main surface of the core substrate, and the electronic component embedded in one main surface of the core substrate And a buried layer provided in such a manner that the outer surface is parallel to one main surface of the core substrate.
The electronic component includes: a capacitance developing portion in which a capacitor element in which a dielectric layer is inserted between a first internal electrode and a second internal electrode is stacked; A laminate including the first protective portion and the second protective portion, and a first external electrode provided on the surface of the laminate and connected to the first internal electrode and connected to the second internal electrode A second external electrode to be
A mounting step of mounting the electronic component on one main surface of the core substrate;
Electrostatic when the thickness T _R of the buried layer, the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, the elastic modulus E _B of the core substrate, and one main surface of the core substrate as a reference plane The center height T _C of the capacity expression portion is

A buried layer forming step of providing a buried layer for burying the electronic component on one main surface of the core substrate so as to satisfy
A method of manufacturing an electronic component built-in substrate, comprising: In the buried layer forming step, the buried layer, the thickness T _R of the buried layer, and the elastic modulus E _R of the buried layer, the thickness T _B of the core substrate, and the elastic modulus E _B of the core substrate, The height T _C of the center of the capacitance developing portion when the one main surface of the core substrate is a reference surface,

The method according to claim 4, wherein the method further comprises:

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